JP2012100432A - Gate drive device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate drive device capable of preventing malfunction of a gate drive circuit, which is caused by noises, at a low cost, with the gate drive circuit being integrated at high density, and reducing possibility of short circuit destruction of a semiconductor switching element which is caused when a noise is superposed on a normal control signal.SOLUTION: A gate drive circuit 6 and a gate drive circuit 9 for driving a module 2 for U-phase, a gate drive circuit 7 and a gate driving circuit 10 for driving a module 3 for V-phase, and a gate drive circuit 8 and a gate drive circuit 11 for driving a module 4 for W-shape are arranged not to approach each other in closest manner. By this configuration, it is prevented that the noise generated from a control circuit for upper and lower arms in the same phase are superposed on each other for malfunction, otherwise, semiconductor elements constituting the upper and lower arms in the same phase come to be ON to cause short-circuit destruction.

Description

  The present invention relates to a gate driving device for driving a semiconductor switching element, and more particularly to an arrangement of a gate driving circuit capable of switching a semiconductor switching element with high reliability.

In recent years, there has been a strong demand for downsizing of devices, and the installation space for circuit boards mounted on the devices has also been reduced. As a result, the circuits are integrated with high density.
For example, a semiconductor switching element is used for an inverter that is a power converter, but a plurality of elements are often provided in one package (module).
When two elements (upper arm and lower arm) are encapsulated in one module, the circuits that drive these elements are often arranged close to each other while ensuring mutual insulation. As many as the number of modules are arranged. As a result, it becomes easy to integrate the module and the drive circuit as a set, and it is possible to reduce the size of the entire device (see, for example, Patent Document 1).

Japanese Patent Laying-Open No. 2006-81309 (page 17, FIG. 3)

In power converters such as inverters, high-speed (high-frequency) switching of semiconductor switching elements constituting the converter is being promoted.
The tendency becomes remarkable by using not only IGBT (Insulated Gate Bipolar Transistor) but also MOSFET (Metal Oxide Field Effect Transistor) for semiconductor switching elements.

Among these, SiC-MOSFETs (Silicon Carbide-MOSFETs) are capable of high-speed (high-frequency) switching in a large power region and are being put into practical use.
Generally, when a circuit is operated, electromagnetic noise accompanying the operation is generated from the circuit. This noise is propagated from the source to the periphery in the form of conduction noise propagated through the circuit and radiation (radiation) noise propagated through the space.

Noise generation tends to become more noticeable as the circuit operates at higher speed (high frequency). Other circuits and devices are more susceptible to noise as they are closer to the noise source.
The miniaturized power converter is one of typical applications in which internal circuits are densely packed and these circuits are operated at high speed (high frequency).

  Due to the above characteristics, the noise generated in a plurality of circuits of the power converter propagates to other circuits in the vicinity and malfunctions, or the noise is superimposed on the normal control signal. There has been a problem that erroneous ON occurs, resulting in short circuit breakdown of the semiconductor switching element.

In particular, when a SiC-MOSFET is used as a semiconductor switching element, there is a problem that the possibility of erroneous turn-on due to noise is further increased because of its element characteristics as compared with a conventional Si-MOSFET.
Further, in order to reduce noise, an additional configuration such as a filter or a shield is necessary, and there is a problem that the countermeasure is accompanied by an increase in cost.

  The present invention has been made to solve such a problem, and prevents malfunction of the gate drive circuit due to noise at a low cost while integrating a high-density gate drive circuit, or is normal. It is an object of the present invention to obtain a gate drive device that can reduce the probability that a semiconductor switching element will be short-circuited and destroyed by superimposing noise on a control signal.

  A gate drive device according to the present invention is a gate drive device having a plurality of gate drive circuits for driving a plurality of semiconductor switching elements on a substrate, and an arbitrary gate drive circuit among the plurality of gate drive circuits, Another gate drive circuit closest to the gate drive circuit is characterized in that the phases to be controlled are different from each other.

  The gate driving device according to the present invention is characterized in that an arbitrary gate driving circuit and another gate driving circuit closest to the gate driving circuit are controlled in different phases. Arranging the gate drive circuits that control the upper and lower arms so as not to be adjacent to each other prevents the malfunction of the semiconductor switching element due to noise without increasing the size and cost of the gate drive device, resulting in short circuit breakdown Can be reduced.

It is a schematic block diagram of the gate drive device concerning Embodiment 1 of the present invention. It is the schematic diagram which showed the example of the control signal in FIG. It is the schematic diagram which replaced and showed arrangement | positioning of the control signal in FIG. It is a schematic block diagram of the gate drive device concerning Embodiment 2 of this invention. It is a schematic block diagram of the modification of the gate drive device which concerns on Embodiment 2 of this invention. It is a schematic block diagram of the gate drive device concerning Embodiment 3 of this invention. It is the schematic block diagram which showed the example of the circuit of the conventional gate drive device. It is a schematic block diagram of the conventional gate drive device. FIG. 9 is a schematic diagram illustrating an example of a control signal in each gate drive circuit of FIG. 8.

Embodiment 1 FIG.
Prior to the description of the invention of the gate driving device according to the present embodiment, the arrangement of a general conventional gate driving circuit and the influence of noise generated from the gate driving circuit will be described.
FIG. 7 shows an example of a general three-phase inverter circuit. Here, an IGBT is used as the semiconductor switching element, and a PWM (Pulse Width Modulation) control signal generated by the control circuit is input to the control terminals (UP, UN, VP, VN, WP, WN).

FIG. 8 is a schematic configuration diagram of a gate driving apparatus 1 including three modules 2 to 4 in which IGBTs are sealed and a gate driving circuit 6 to a gate driving circuit 11 disposed on a substrate 5. Two modules of IGBT are enclosed in modules 2 to 4 to form upper and lower arms for one phase, and gate drive circuits 6 to 11 are configured for each IGBT.
Here, the module 2 is for U phase, the module 3 is for V phase, and the module 4 is for W phase (the same applies hereinafter).
The gate drive circuit 6 to the gate drive circuit 11 are arranged as a set for the upper and lower arms for each module. Here, the gate drive circuit 6 is a high-side gate drive circuit for the module 2, and the gate drive circuit 9 is a low-side gate drive circuit for the module 2.
The gate drive circuit 7 is a high-side gate drive circuit for the module 3, and the gate drive circuit 10 is a low-side gate drive circuit for the module 3. Similarly, the gate drive circuit 8 is a high-side gate drive circuit for the module 4, and the gate drive circuit 11 is a low-side gate drive circuit for the module 4. (The same shall apply in the following description.)

In general, noise generated in the control circuit is likely to occur when the amount of change in the current flowing through the control circuit or the applied voltage is large. This corresponds to the timing at which the control signal switches from low to high and from high to low. That is, noise is generated at this timing, and this noise is also superimposed on the control signal.
In addition, the noise is superposed as it gets closer to the noise source.
FIG. 9 schematically shows a control signal transmitted to the control terminal of the IGBT, and is a diagram focused on when the control signal is likely to be hard-switched.
The control signals of the in-phase control circuits arranged close to each other generate noise generated when the signal changes.

  The U phase will be described as an example. When the noise superimposed on the control signal of the control terminal UN exceeds the IGBT threshold voltage due to the control signal change of the control terminal UP (U-phase high side), the IGBT of the lower arm, which is originally in the off state, malfunctions and is turned on. (Part shown by an ellipse in FIG. 9). At this time, since the IGBT of the upper arm is on, both the upper and lower arms are turned on and short-circuited, and both IGBTs are destroyed. The same applies to the signal change of the control terminal UN, and the same applies to the V phase and the W phase.

As described above, in the conventional arrangement of the general gate drive circuit, every time the control signal changes, noise may be superimposed on the control signal in the same phase and the arm may be short-circuited. Therefore, the control circuit is physically separated. The measures such as were adopted.
Therefore, there has been a need for a gate drive device that reduces the probability of noise short-circuiting to arm short-circuiting without increasing the mounting area.

FIG. 1 is a schematic configuration diagram showing a gate driving apparatus according to Embodiment 1 of the present invention. In FIG. 1, the gate drive device 101 includes a gate drive circuit 6 to a gate drive circuit 11 provided on a substrate 5 that drives the modules 2 to 4. Each module incorporates two semiconductor switching elements to form a one-phase upper and lower arm.
Here, the U-phase module 2 is driven by the gate drive circuit 6 and the gate drive circuit 9, and the V-phase module 3 is driven by the gate drive circuit 7 and the gate drive circuit 10, and the W-phase module. 4 is driven by the gate drive circuit 8 and the gate drive circuit 11. That is, the W-phase low-side gate drive circuit 11 is closest to the U-phase high-side gate drive circuit 6, and the U-phase low-side gate drive circuit 9 is closest to the V-phase high-side gate drive circuit 7. The V-phase low-side gate drive circuit 10 is located closest to the W-phase high-side gate drive circuit 8.

When the general three-phase inverter circuit shown in FIG. 7 is driven by PWM control under such a gate drive circuit configuration, the control signal for each semiconductor element is closest to the control signal as shown in FIG. The noise from the gate driving circuit arranged in the circuit is greatly superimposed.
FIG. 3 shows the waveforms of the control signals shown in FIG. 2 rearranged for each phase.

The following situation can be read from FIG. (In the following, U, V, and W represent “phase”, and P and N represent “high side” and “low side”)
At time t1, noise due to the rise of the control signal of WN is superimposed on the control signal of UP, and there is a possibility that the upper and lower arms are short-circuited depending on the state of UN.
At time t2, noise due to the rise of the UP control signal is superimposed on the WN control signal, but the upper arm WP of the same phase is off and the upper and lower arms are not short-circuited.
At time t3, noise due to the rise of the VN control signal is superimposed on the WP control signal, and there is a possibility that the upper and lower arms are short-circuited depending on the state of WN.
At time t4, noise due to the rise of the WP control signal is superimposed on the VN control signal, but the upper arm VP of the same phase is off and the upper and lower arms are not short-circuited.
At time t5, noise due to the rise of the UN control signal is superimposed on the VP control signal, and there is a possibility that the upper and lower arms are short-circuited depending on the state of VN.
At time t6, noise due to the rise of the VP control signal is superimposed on the UN control signal, but the upper arm UP of the same phase is off and the upper and lower arms are not short-circuited.
This has the effect of halving the probability that the in-phase high side and low side are simultaneously turned on and the arm is short-circuited as compared with the case of the control signal waveform in the conventional gate driving device shown in FIG.

  In this way, by arranging on the board so that the in-phase high-side and low-side gate drive circuits are not located closest to each other, it is possible to perform semiconductor switching due to noise without adding parts or expanding board dimensions. A gate driving device having a function of reducing the probability of element destruction can be obtained.

Embodiment 2. FIG.
Hereinafter, a gate driving apparatus according to the second embodiment of the present invention will be described focusing on differences from the first embodiment.
When a device is downsized, it is necessary to reduce the size of a built-in substrate. At this time, it is effective to mount the components on both sides of the substrate together with means for improving the mounting density of the components on the substrate or reducing the size of the components. Here, a configuration in which the gate drive circuit is mounted on both sides of the substrate is referred to as a second embodiment of the present invention.
FIG. 4 is a schematic configuration diagram of the gate driving apparatus according to the second embodiment. In FIG. 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here, and only differences from FIG. 1 are described.
4 is different from FIG. 1 in that a plurality of gate driving circuits are distributedly mounted on both surfaces of the substrate.

Even in such a configuration with the substrate sandwiched therebetween, the gate drive circuits are arranged in the same manner as in the first embodiment in consideration of the distance between the gate drive circuits.
The gate driving device 102 according to the second embodiment has the same effect as that of the first embodiment by being mounted so that the high-side and low-side gate driving circuits are not located closest to each other. Is mounted on both the front and back surfaces of the substrate, the surface area of the substrate can be reduced, and the entire gate driving device can be reduced in size and cost.

  In this way, by arranging on both sides of the substrate so that the in-phase high-side and low-side gate drive circuits are not located closest to each other, the probability that the semiconductor switching element will be destroyed due to noise is reduced, and the device is A gate driving device having a function of downsizing can be obtained.

  In the second embodiment, the gate drive circuit is mounted on either side of the substrate in element units controlled by the circuit. However, as shown in FIG. 5, one gate drive circuit 7 is divided into 7a and 7b. Even if they are mounted on both sides of the substrate, the same effects as in the first embodiment can be obtained.

Embodiment 3 FIG.
Hereinafter, a gate driving device according to a third embodiment of the present invention will be described focusing on differences from the first embodiment.
Since the high-side and low-side gate drive circuits have different reference potentials, they must be insulated from each other. Therefore, in the first embodiment and the second embodiment described above, the gate driving circuits are arranged with a certain interval.
In addition, the withstand voltage between the circuits is determined by the creepage distance between the substrates between the circuits, but in general, the withstand voltage along the substrate creepage is smaller than that of air. That is, if air insulation is used, the circuit can be arranged at a higher density, and the size can be reduced.
Therefore, a configuration in which the substrate on which the gate driving circuit is mounted is divided into a third embodiment.

FIG. 6 is a schematic configuration diagram of the gate driving apparatus according to the third embodiment. In FIG. 6, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here, and only differences from FIG. 1 are described.
6 differs from FIG. 1 in that the substrate on which the gate drive circuit is mounted is divided. As shown in FIG. 6, the gate driving device 104 has six gate driving circuits mounted on the front and back of the three divided substrates 15 to 17 one by one.
In such a configuration, the gate drive circuits facing each other with each substrate interposed therebetween are positioned closest to each other. Therefore, the rules described in the first embodiment, that is, the in-phase high side and low side gate drive circuits are closest to each other. Mount so that it is not located.
As a result, the gate drive device 104 has the same effect as that of the first embodiment, and can also reduce the insulation distance and reduce the substrate area by dividing the gate drive circuit and mounting it on both sides of the substrate. The gate driving device can be reduced in size and cost.

In addition, it is possible to obtain a gate driving device having a function of reducing the size of the device while reducing the probability that the semiconductor switching element is destroyed due to noise.
In Embodiment 3, by using the high dielectric strength of air, slits are provided between the circuits to increase the creepage distance on the substrate without dividing the substrate, and to reduce the distance between the gate drive circuits accordingly. Needless to say, it is possible to downsize the apparatus.
In addition, the gate drive circuit may be mounted on one side of the substrate as in the first embodiment.

In the first to third embodiments, the noise source is a gate drive circuit for simplifying the description, and the arrangement of the gate drive circuit is determined from the distance between the circuits, but the noise source is clearly shown. In some cases, it goes without saying that the reference for determining the arrangement of the gate drive circuit is the distance from the noise source.
Moreover, the module which comprises each phase may be one package, The shape etc. are not limited. In addition, a two-level three-phase inverter is shown as a circuit example. However, the present invention can be applied to a power converter such as a multi-level such as a three-level, a multi-phase such as a single-phase or a six-phase, and a chopper circuit. Needless to say.

The semiconductor switching element may be formed of conventional silicon or may be formed of a wide band gap semiconductor having a larger band gap than silicon. Examples of the wide gap semiconductor include silicon carbide, a gallium nitride-based material, and diamond.
In particular, when a SiC-MOSFET is used as a semiconductor switching element, there is a possibility that the possibility of erroneous turn-on due to noise is further increased compared to a conventional Si-MOSFET due to its element characteristics. By applying the above, it is possible to reduce the probability that the semiconductor switching element is short-circuited and destroyed by superimposing noise on a normal control signal.

  A semiconductor switching element formed of such a wide band gap semiconductor has a high voltage resistance and a high allowable current density, so that the semiconductor switching element can be miniaturized, and a semiconductor module incorporating these elements can be further reduced. Can be reduced in size.

  In addition, since the heat resistance is high, it is possible to reduce the size of the heat dissipating fins of the heat sink and the air cooling of the water cooling portion, thereby further reducing the size of the semiconductor module.

  Furthermore, since the power loss is low, the switching element can be highly efficient, and the semiconductor module can be highly efficient.

101, 102, 104 gate drive unit, 2, 3, 4 module,
5, 15, 16, 17 substrate,
6, 7, 7a, 7b, 8, 9, 10, 11 Gate drive circuit.

Claims (8)

A gate driving device having a plurality of gate driving circuits for driving a plurality of semiconductor switching elements on a substrate, the gate driving circuit being the closest to the gate driving circuit among the plurality of gate driving circuits The gate drive circuit of this is a gate drive device in which the phases to be controlled are different. The gate driving device according to claim 1, wherein the plurality of gate driving circuits are mounted on one side of the substrate. The gate driving device according to claim 1, wherein the plurality of gate driving circuits are mounted on both surfaces of the substrate. The gate driving device according to claim 2, wherein the substrate is provided with a slit between gate driving circuits to be mounted. The gate driving apparatus according to claim 1, wherein the substrate is divided into a plurality of parts. The gate drive device according to claim 1, wherein the gate drive circuit is configured for each of the semiconductor switching elements. The gate driving device according to claim 1, wherein the semiconductor switching element is formed of a wide band gap semiconductor. The gate driving device according to claim 7, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

Images