JP2012099841A - Method for manufacturing photoelectric conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a solid-state imaging device in which the difference of the dark current difference between adjoining photoelectric conversion elements is zero or small, and high sensitivity and low dark current are ensured even during a high-speed read operation.SOLUTION: A photodiode is configured by providing a well 302 on a wafer substrate 301, and forming diffusion layers 101a, 101b in the well. A well contact 306 is formed between the diffusion layers 101a, 101b. Element isolation regions 303b, 303a are provided between the well contact and the diffusion layers, and channel stop layers 307b, 307a are provided under the element isolation regions 303b, 303a. A conductive layer 304 is provided on the element isolation region 303b, and a sidewall 308 is provided on the side surface of the conductive layer 304. A relation of c>a≥b is satisfied, where a is the distance between the end of the element isolation region 303b and the conductive layer 304, b is the width of the sidewall 308, and c is the element isolation width.

Description

  The present invention relates to a photoelectric conversion device, and a solid-state imaging device and system using the photoelectric conversion device, and to an imaging device and system such as a digital camera, a video camera, a copying machine, and a facsimile.

  Many solid-state imaging devices in which photoelectric conversion elements such as photodiodes are arranged one-dimensionally or two-dimensionally are mounted on digital cameras, video cameras, copying machines, facsimiles, and the like. Solid-state imaging devices include, for example, a CCD imaging device and an amplification type solid-state imaging device represented by a CMOS sensor in which peripheral circuits are integrally formed by a CMOS process.

  These solid-state imaging devices tend to have a larger number of pixels, and the photodiode area also tends to decrease as the area of one pixel is reduced. Therefore, it is necessary to handle a smaller amount of signal charge, and there is a need to reduce the dark current as a noise component or to effectively increase the photodiode area. As one means for this purpose, as disclosed in Patent Document 1, floating diffusion regions (floating diffusion regions) formed for each pixel are connected by a conductor, and amplified by a common amplification MOS transistor and read out. There is a method of keeping the photodiode area large by reducing the number of transistors per unit pixel.

  Further, when the area of the solid-state imaging device is increased, as disclosed in Patent Document 2 or Patent Document 3, it is necessary to make a well contact in order to firmly hold the substrate potential of the photodiode or transistor and suppress shading.

  Further, since miniaturization of MOS transistors to be used is indispensable in the image sensor or in the peripheral circuit portion, transistor structures having a so-called LDD (Lightly-Doped-Drain) structure are widely used.

Japanese Patent Laid-Open No. 2000-232216 (FIG. 4) JP 2001-332714 A (FIGS. 7 and 10) JP 2001-230400 A (FIGS. 1 and 16)

  By the way, when the well contact is formed between the photodiodes in the imaging device, an element isolation region is arranged for element isolation between the well contact and the photodiode, and a conductive layer such as polysilicon is formed thereon. In some cases, a side wall accompanying formation of a transistor having an LDD (Lightly-Doped-Drain) structure is formed in the conductive layer.

  The present inventor has found that there is a problem that the dark current of the photodiode increases depending on the arrangement of the sidewalls.

The photoelectric conversion device of the present invention includes a first conductive type first semiconductor region, a photoelectric conversion element having a second conductive type second semiconductor region formed in the first semiconductor region, and the first conductive type. A third semiconductor region of a first conductivity type formed in one semiconductor region and electrically connected to the first semiconductor region, and between the third semiconductor region and the second semiconductor region An element isolation region provided; a conductive layer provided on the element isolation region; and a fourth semiconductor region of a first conductivity type provided below the element isolation region; Have side walls on the sides,
The width of the element isolation region is c, the width of the sidewall is b, and the distance between the end of the element isolation region on the third semiconductor region side and the end of the conductive layer on the third semiconductor region side Is a
The relationship is c> a ≧ b.

According to another aspect of the present invention, there is provided a photoelectric conversion device including a first conductivity type first semiconductor region and a second conductivity type second semiconductor region formed in the first semiconductor region; A third semiconductor region of a first conductivity type formed in one semiconductor region and electrically connected to the first semiconductor region, and between the third semiconductor region and the second semiconductor region An element isolation region provided; a conductive layer provided on the element isolation region; and a fourth semiconductor region of a first conductivity type provided below the element isolation region; Have side walls on the sides,
The sidewall is on the element isolation region, and an outer end portion of the sidewall is arranged so as not to exceed an end portion of the element isolation region.

  The solid-state imaging device of the present invention uses the photoelectric conversion device of the present invention.

  The solid-state imaging system of the present invention uses the solid-state imaging device of the present invention.

  According to the present invention, it is possible to provide a photoelectric conversion device and a solid-state imaging device that have high sensitivity and low dark current even when high-speed reading is performed by arranging the sidewalls that generate little dark current.

It is sectional drawing of Embodiment 1 of the photoelectric conversion apparatus of this invention, and 1st Example of a solid-state imaging device. It is sectional drawing of the comparative example of the photoelectric conversion apparatus of this invention, and a solid-state imaging device. It is a top view of an embodiment of a solid imaging device of the present invention. 1 is a plan view of a first embodiment of a solid-state imaging device of the present invention. FIG. 5 is an equivalent circuit diagram of a pixel unit surrounded by a dotted line in FIG. 4. It is a top view of the comparative example of the photoelectric conversion apparatus and solid-state imaging device of this invention. It is a block diagram when the solid-state imaging device using the photoelectric conversion device of the embodiment or the solid-state imaging device of Example 1 is used as the solid-state imaging system of the present invention. It is a top view of an embodiment of a solid imaging device of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a sectional view showing an embodiment of a photoelectric conversion device according to the present invention. FIG. 2 is a cross-sectional view showing a comparative example related to the present invention.

In FIG. 1, for example, 301 is an N-type wafer substrate (semiconductor substrate), 302 is a P-type well (semiconductor region), 101 a and 101 b are N-type diffusion layers (semiconductor regions), and are bonded to the well 302. A photodiode is formed by forming a portion. 303b and 303a are element isolation regions, for example, LOCOS (local oxidation of silicon) films. Under the element isolation regions 303b and 303a, 307b and 307a made of P ⁺ type semiconductor regions serving as channel stop layers are formed, respectively. 304 is a conductive layer provided on the element isolation region 303b, and is formed of, for example, polysilicon. Reference numeral 308 denotes a so-called sidewall made of a silicon oxide film or the like formed on the side surface of the conductive layer. The well contact defines the potential of the P-type well 302 via the P ⁺⁺ diffusion layer 306.

  Although the contact is a well contact, it becomes a substrate contact when the N type diffusion layers 101a and 101b are directly provided on the wafer.

In FIG. 2, a p-type well 1102 is formed on an n-type substrate 1101, photodiodes (N-type diffusion layers) 1001 and 1002, and a high concentration p ⁺⁺ type well contact between them. The diffusion layer (P ⁺⁺ layer) 1003 is formed so as to be sandwiched between the element isolation regions 1103 and 1104. Under each element isolation region, p ⁺ type semiconductor regions 1105 and 1106 are formed as channel stop layers, respectively. In addition, sidewall layers 1107 and 1108 are formed on both sides of the polysilicon wiring 1004 on the element isolation region 1103.

As is clear from a comparison between FIG. 2 showing the comparative example and FIG. 1 showing the embodiment according to the present invention, the well contact diffusion layer (P ⁺⁺ layer) 1003 and the channel stop layer 1105 are separated from each other in FIG. In contrast, in FIG. 1, the well contact diffusion layer 306 and the channel stop layer 307b are connected.

As shown in FIG. 2, a thin P well layer is interposed between the high concentration P ⁺⁺ layer 1003 and the channel stop layer 1105 to reach the N-type photodiode region 1001. As shown in the conceptual diagram of the potential between the two XX's, in this part, electrons that are minority carriers are present in a higher concentration than in other regions, so some of them are taken into the photodiode with low potential and darkened. This leads to an increase in current.

On the other hand, as shown in FIG. 1, a high-concentration P ⁺ layer is formed from the high-concentration P ⁺⁺ layer 306 to the N-type photodiode region 101b through the channel stop layer 307b. As shown in the conceptual diagram of the potential between 1 and XX ′, the concentration of electrons which are minority carriers is kept low, and the dark current can be reduced.

In order to not to cause the pocket of potential as shown in FIG. 2, as shown in FIG. 1, P of the P ⁺⁺ layer 306 side end and the polysilicon conductive layer 304 of the isolation region 303b ⁺⁺ The distance a between the end portions on the layer 306 side may be the same as the width b of the sidewall 308 or larger than the width b. Cause since the pocket of the potential is generated in the process of forming a diffusion layer (P ⁺⁺ layer) 1003 in the well of FIG. 2, the side wall formed in the preceding P ⁺⁺ layer to portions of the potential pocket This is because ion implantation was not performed. If the element isolation width is c, the distance a is required to be smaller than the element isolation width c in order to form the conductive layer 304 thereon. From the above points, the relationship between a, b, and c may be c> a ≧ b. This configuration is also a configuration in which the sidewall is on the element isolation region and the outer end portion of the sidewall does not exceed the end portion of the element isolation region.

  On the other hand, in FIG. 2, although the distance a is smaller than the element isolation width c and is formed on the element isolation region, it becomes smaller than the sidewall width b, so that a potential pocket is generated and dark current increases. The embodiment of the present invention is particularly effective in the case of a solid-state imaging device in which a plurality of pixels are arranged one-dimensionally or two-dimensionally. This is because a pixel with increased dark current due to the existence of one well contact for a plurality of pixels and a pixel that is not so are generated periodically (every other row if two pixels are common, every third row if four pixels are common). This is because the image quality is significantly deteriorated. As described above, by setting c> a ≧ b, it is possible to provide a high S / N solid-state imaging device with little dark current.

  Note that although FIG. 1 illustrates a mode in which the conductive layer 304 is provided only on the element isolation region 303b, the present invention can be applied to a case where a conductive layer is provided on the element isolation region 303a in addition to the element isolation region 303b. In other words, c> a ≧ b, in other words, the side wall may be on the element isolation region and the outer end of the side wall may be arranged not to exceed the end of the element isolation region.

As shown in FIG. 3, diffusion layers 101a and 101b constituting a pixel photodiode are arranged two-dimensionally, and two pixels are grouped into one group (101a and 101b, 101a 'and 101b' are grouped as one group, respectively. In a solid-state imaging device in which one well contact is arranged between two pixels (for each group) and between pixels (within a group), the structure shown in FIG. The amount of minority carrier Ib flowing into the photodiodes 101b and 101b 'of the pixels in the second and fourth rows from the well contact is larger than the amount of minority carrier Ia flowing into the photodiodes 101a and 101a' of the pixels in the third row. Become more. When the minority carrier diffusion is different as described above, the amount of minority carrier Ia is different from the amount of minority carrier Ib, and dark current unevenness occurs between odd and even rows. When such a difference occurs, striped noise occurs every other line, and the image quality deteriorates. In particular, this phenomenon becomes more prominent when long seconds are accumulated. According to the configuration of the present embodiment, the generation of potential pockets can be suppressed and the dark current difference can be reduced. Although FIG. 3 shows an example in which two pixels are grouped, three or more pixels may be grouped. In this case, a plurality of well contacts may be provided in the grape in accordance with the number of pixels constituting the group.

  In the configuration of the embodiment of the present invention, signal charges from a plurality of photodiodes are amplified and read by a common amplification MOS transistor via floating diffusions formed independently for each photoelectric conversion element. It can be suitably applied to a solid-state imaging device.

  For example, as seen in Patent Document 1, when considering a layout in which two pixels share an amplifying MOS transistor, if the well contact is not taken, the potential of the substrate is increased when trying to increase the driving speed at the time of reading. It takes a long time to stabilize, making high-speed reading difficult.

  Further, if a well contact is made for each pixel, the area of the photodiode is reduced by that amount, so that the common effect of the pixel is reduced.

  Therefore, by adopting the configuration of this embodiment for the problem that a well contact is taken for each of a plurality of pixels, and the layout of the well contact causes a difference in dark current between pixel rows (photodiode rows). Can be dealt with.

As shown in FIG. 8, when the pixels 101a and 101b having the common amplification MOS transistor are the first group, and the pixels 101a 'and 101b' having the common amplification MOS transistor are the second group, The contact is different from the first group between the first group of pixels and the second group of pixels adjacent to the pixel, that is, the second semiconductor region in the first group. Formed in a first semiconductor region (well region) disposed in the second group and between the second semiconductor region in the first group and the adjacent second semiconductor region. It may be. In particular, as shown in FIG. 4, in the case of a configuration in which the amplification MOS transistor is shared by a plurality of pixels, it is preferable to form between the pixels 101b and 101a 'between adjacent groups because the layout is easy. FIG. 4 shows an example in which the amplification MOS transistors are shared by two pixels and the two pixels are made into one group. However, the amplification MOS transistors are shared by three or more pixels, and three or more pixels are made into one group. It is good. In that case, well contacts may be provided not only between the groups but also between the pixels in the group.

  As described above, the present invention reduces or eliminates the dark current difference between adjacent photoelectric conversion elements, and is applied to a photoelectric conversion apparatus in which a well contact or a substrate contact is provided between two photoelectric conversion elements. Specifically, the present invention is applied to a solid-state imaging device which is a line sensor in which photoelectric conversion elements are arranged one-dimensionally or an area sensor in which two-dimensionally arranged photoelectric conversion elements are arranged.

  Examples of the present invention will be described below.

  FIG. 4 shows a plan view of the first embodiment of the present invention. In FIG. 4, PD is a photodiode (diffusion layer), ACT is an active region, POL is a polysilicon layer, CNT is a contact hole, AL1 is a first metal layer such as aluminum, and TH is a through hole.

  In FIG. 4, 101a, 101b, and 101a 'are N-type diffusion layers that serve as carrier storage layers of photodiodes for photoelectric conversion, and 102a and 102b read signal charges from the photodiodes (N-type diffusion layers) 101a and 101b. The transfer MOS transistor has a gate electrode, 103a and 103b are the drain region of the transfer MOS transistor (becomes a floating diffusion (FD) region), and 104 is a photodiode (N-type diffusion layer) and a floating diffusion (FD) region. A gate electrode of a reset MOS transistor for resetting, 106 is a gate electrode of an amplifying MOS transistor serving as a source follower amplifier for voltage conversion of the read charge, and the gate electrode of the amplifying MOS transistor and the FD region 103a and 103b is connected by wiring 105. Reference numeral 107 denotes a gate electrode of the row selection MOS transistor, which selectively outputs the output of the amplification MOS transistor serving as a source follower amplifier to the signal line 108. Reference numeral 109 denotes a well contact in the pixel region, which is fixed to a fixed potential, for example, a ground potential via the power supply wiring 110 (connected to a fixed voltage source (including the case of grounding)).

  In FIG. 4, the region surrounded by the alternate long and short dash line includes two photodiodes (N-type diffusion layer), two transfer MOS transistors, two floating diffusions, one amplification MOS transistor, one reset MOS transistor, This is a pixel unit composed of one selection MOS transistor. Here, two photodiodes form one group, and when there are 2m photodiodes arranged in the column direction (m is a natural number of 1 or more), m groups are formed. When one group is configured by four photodiodes, m / 2 groups are configured when there are 2m photodiodes (m is a natural number of 2 or more) arranged in the column direction. A transfer MOS transistor is provided for each photodiode, and a reset MOS transistor and a selection MOS transistor are provided for each photodiode group to constitute a pixel unit. One pixel unit is provided with a plurality of photodiodes (N-type diffusion layers), and one pixel unit constitutes a plurality of pixels.

  FIG. 5 shows an equivalent circuit diagram of the pixel unit surrounded by a dotted line in FIG. In FIG. 5, 101a and 101b indicate not the diffusion layers but photodiodes themselves, and 102a, 102b, 104, 106 and 107 are not gate electrodes, but transfer MOS transistors, reset MOS transistors, amplification MOS transistors, and selection MOS transistors themselves, respectively. Is shown. The photodiodes 101a and 101b are connected to the FD region 103 via transfer MOS transistors 102a and 102b, respectively. The back gate potentials of all the transistors and the anode electrodes of the photodiodes are fixed to a fixed potential such as a ground potential via the well contact 109. Further, the drain end of the reset transistor 104 and the drain end of the source follower amplifier are fixed to the power supply voltage via a via hole.

1 corresponds to a cross-sectional view taken along the line AA ′ of FIG. The section taken along the line AA ′ in FIG. 4 is the same as the sectional configuration of the first embodiment already described, and will be described with reference to FIG. In FIG. 1, 301 is, for example, an N-type wafer substrate, 302 is a P-type well, 101a, 101b and 101a ′ are adjacent N-type diffusion layers, and a junction is formed with the well 302 to constitute a photodiode. is doing. 303b and 303a are element isolation regions, for example, LOCOS (local oxidation of silicon) films.
P ⁺ channel stop layers 307b and 307a are formed under the element isolation regions 303b and 303a, respectively. Reference numeral 304 denotes a gate electrode of the transfer transistor 102b, which is made of, for example, polysilicon. Reference numeral 308 denotes a so-called sidewall formed on the side surface of the gate electrode 304. Here, the case where the gate electrode of the transfer transistor 102b is used as the conductive layer is described. However, the conductive layer includes the gate electrode 107 of the selection MOS transistor, the gate electrode 104 of the reset MOS transistor, the gate electrode of the amplification MOS transistor, and the like. Sometimes it is arranged.

The sidewall 308 is formed before ion implantation of a high-concentration diffusion layer (N ⁺⁺ or P ⁺⁺ ) that forms the source / drain of the MOS transistor in the formation process. The well contact 109 takes the potential of the P-type well 302 via the P ⁺⁺ diffusion layer 306.

As already described in the embodiment of the present invention, as shown in FIG. 2, the P is thin while reaching the N-type photodiode region 1001 through the high-concentration P ⁺⁺ layer 1003 and the channel stop layer 1105. When the well layer is interposed, as shown in the conceptual diagram of the potential between XX ′ in FIG. 2, electrons in the minority carriers are present in a higher concentration in this portion than in other regions, so a part thereof The dark current is increased by being taken into the photodiode having a low potential.

On the other hand, in this embodiment, as shown in FIG. 1, a well contact diffusion layer 306 and a channel stop layer 307b are connected, and an N-type photo is connected from the high-concentration P ⁺⁺ layer 306 to the channel stop layer 307b. By forming the P ⁺ layer with a high concentration up to the diode region 101b, the concentration of electrons which are minority carriers is kept low, and the dark current can be reduced.

In order to not to cause the pocket of potential as shown in FIG. 2, as previously described, P ⁺⁺ layer of the conductive layer 304 of the end portion and the polysilicon P ⁺⁺ layer 306 side of the element isolation region 303b The distance a between the end portions on the 306 side may be the same as or larger than the width b of the sidewall 308, and the distance a may be smaller than the element isolation width c. Therefore, in this embodiment, the relationship of a, b, c is set so that c> a ≧ b. This configuration is also a configuration in which the sidewall is on the element isolation region and the outer end portion of the sidewall does not exceed the end portion of the element isolation region.

  Here, FIG. 6 shows a plan view of a solid-state imaging device corresponding to the comparative example of FIG. FIG. 2 corresponds to the AA ′ cross section of FIG. In FIG. 6, a well contact layer 1003 is disposed between two photodiodes 1001 and 1002. Further, a polysilicon wiring 1004 is provided between 1001 and 1003.

As shown in FIG. 2, the cross-sectional structure includes a p-type well 1102 formed on an n-type substrate 1101, photodiodes (diffusion layers) 1001 and 1002, and a high-concentration p ⁺ therebetween. ^{A +} -type well contact region 1003 is formed so as to sandwich the element isolation regions 1103 and 1104. Under the respective element isolation regions 1103 and 1104, p ⁺ type channel stop layers 1105 and 1106 are formed, respectively.

  Further, sidewall layers 1107 and 1108 are formed on both sides of the polysilicon wiring 1004. This sidewall layer is formed as a secondary when the MOS transistor in the solid-state imaging device is formed.

  A pixel having a photodiode (N-type diffusion layer), a transfer MOS transistor, an amplification MOS transistor, a reset MOS transistor, and a selection MOS transistor (here, common to a plurality of photodiodes and a plurality of transfer MOS transistors) In the present invention, each transistor is not limited to a MOS transistor, but is a VMIS (Threshold Voltage Modulation Image Sensor), BCAST (Buried Charge Accumulator and Sensing transistor arrays) and LBCAST (Lateral Buried Charge Accumulator and Sensing Transistor arrays) are also applicable. In particular, BCAST and LBCAST can be realized without substantial change by replacing the amplification MOS transistor with a JFET transistor. In addition, a sensor of a type that guides signal charges accumulated in the photoelectric conversion unit to a control electrode of a transistor provided in the pixel and outputs an amplified signal from the main electrode can be used for the pixel of this embodiment. SIT type image sensor using SIT as an amplifying transistor (A. Yusa, J. Nishizawa et al., “SIT image sensor: Design consideration and characteristics,”. IEEE trans. Vol. ED-33, pp.735-742, June 1986), BASIS using bipolar transistors (N. Tanaka et al., “A 310K pixel bipolar imager (BASIS),”. IEEETrans. Electron Devices, vol.35, pp. 646-652, may 1990) CMD using a JFET with a depleted control electrode (Nakamura et al. “Gate Storage MOS Phototransistor Image Sensor”, TV Society Journal, 41, 11, pp. 1075-1082 Nov., 1987).

In this embodiment, the amplification MOS transistor is shared by a plurality of pixels, and the selection MOS transistor and the reset MOS transistor are also shared by a plurality of pixels. However, the amplification MOS transistor is provided for each pixel. , the select MOS transistors, can also be used similarly present invention in the case of providing the MOS transistor for resetting, P of the P ⁺⁺ layer 306 side end and the polysilicon conductive layer 304 of the isolation region 303b ⁺⁺ The distance a between the end portions on the layer 306 side is set to be equal to or larger than the width b of the sidewall 308, and the distance a is made smaller than the element isolation width c (c> a ≧ b). . This configuration is also a configuration in which the sidewall is on the element isolation region and the outer end portion of the sidewall does not exceed the end portion of the element isolation region. Similarly, the gate electrode 102a of the transfer transistor 102b, the gate electrode 107 of the selection MOS transistor, the gate electrode 104 of the reset MOS transistor, the gate electrode 106 of the amplification MOS transistor, and the like can be used as the conductive layer.

  FIG. 7 is a configuration diagram of an imaging system using the solid-state imaging device using the photoelectric conversion device of the above-described embodiment or the solid-state imaging device of Example 1 as the imaging device of the present invention. The imaging system includes a barrier 2001 that serves as a lens switch and a main switch, a lens 2002 that forms an optical image of a subject on the solid-state imaging device 2004, an aperture 2003 that changes the amount of light passing through the lens 2002, and an image formed by the lens 2002. Output from the solid-state imaging device 2004 (corresponding to the solid-state imaging device including the photoelectric conversion device described in the above embodiment or the solid-state imaging device of Example 1) for capturing the captured subject as an image signal An image signal processing circuit 2005 that performs various corrections, clamps, and the like on the image signal to be processed, an A / D converter 2006 that performs analog-digital conversion of the image signal output from the solid-state image sensor 2004, and an A / D converter 2006. A signal processing unit 2 that performs various corrections on the output image data and compresses the data. 07, composed of a solid-state image sensor 2004 and an imaging signal processing circuit 2005 and A / D converter 2006 and the signal processor timing generator 2008 outputs various timing signals to the 2007. Each circuit of 2005 to 2008 may be formed on the same chip as the solid-state imaging device 2004. Also, an overall control / arithmetic unit 2009 for controlling various computations and the entire still video camera, a memory unit 2010 for temporarily storing image data, a recording medium control interface unit 2011 for recording or reading on a recording medium, A solid-state imaging system includes a removable recording medium 2012 such as a semiconductor memory for recording or reading image data, and an external interface (I / F) unit 2013 for communicating with an external computer or the like.

  Next, the operation of FIG. 7 will be described. When the barrier 2001 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 2006 is turned on. Then, in order to control the exposure amount, the overall control / arithmetic unit 2009 opens the aperture 2003, and the signal output from the solid-state imaging device 2004 passes through the imaging signal processing circuit 2005 to the A / D converter 2006. Is output. The A / D converter 2006 performs A / D conversion on the signal and outputs the signal to the signal processing unit 2007. Based on the data, the signal processing unit 2007 performs exposure calculation by the overall control / calculation unit 2009.

  Brightness is determined based on the result of this photometry, and the overall control / calculation unit 2009 controls the aperture according to the result. Next, based on the signal output from the solid-state imaging device 2004, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 2009. Thereafter, the lens 2002 is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens 2002 is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 2004 is corrected and the like in the imaging signal processing circuit 2005, further A / D converted by the A / D converter 2006, and totally controlled through the signal processing unit 2007. Accumulated in the memory unit 2010 by the operation 2009. Thereafter, the data stored in the memory unit 2010 is recorded on a removable recording medium 2012 such as a semiconductor memory through the recording medium control I / F unit 2011 under the control of the overall control / arithmetic unit 2009. Further, the image may be processed by directly inputting to a computer or the like through the external I / F unit 2013.

  The present invention can be used in a solid-state imaging device and a solid-state imaging system such as a digital camera, a video camera, a copying machine, and a facsimile using the same.

101a, 101b photodiode
102a, 102b Transfer transistor gate electrode
103a, 103b Drain electrode of transfer transistor
104 Reset transistor
105 Floating diffusion (FD) area
106 Source follower amplifier
107 row select transistor
108 signal lines
109 Well contact
110 Power supply wiring
301 Silicon N substrate
302 P-well
303b, 303a´ element isolation layer
304 Gate electrode of transfer transistor
305 Reset transistor gate electrode
306 P + diffusion layer
307 channel stop layer
308 sidewall
1001,1002 photodiode
1003 Well contact
1004 Polysilicon wiring
1101 n-type substrate
1102 p-type well
1103,1104 isolation region
1105,1106 p-type channel stop layer
1107,1108 Sidewall 2001 Barrier 2002 Lens 2003 Aperture 2004 Solid-state imaging device 2005 Imaging signal processing circuit 2006 A / D converter 2007 Signal processing unit 2008 Timing generation unit 2009 Overall control / calculation unit 2010 Memory unit 2011 Recording medium control interface (I / F) section 2012 recording medium 2013 external interface (I / F) section

  The present invention relates to a method for manufacturing a photoelectric conversion device.

Claims (11)

A photoelectric conversion element having a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type formed in the first semiconductor region, and formed in the first semiconductor region. A third semiconductor region of a first conductivity type electrically connected to the first semiconductor region, an element isolation region provided between the third semiconductor region and the second semiconductor region, A conductive layer provided on the element isolation region; a first conductivity type fourth semiconductor region provided below the element isolation region; and a sidewall on a side surface of the conductive layer;
The width of the element isolation region is c, the width of the sidewall is b, and the distance between the end of the element isolation region on the third semiconductor region side and the end of the conductive layer on the third semiconductor region side Is a
A photoelectric conversion device having a relationship of c> a ≧ b. A photoelectric conversion element having a first conductivity type first semiconductor region and a second conductivity type second semiconductor region formed in the first semiconductor region; and formed in the first semiconductor region; A third semiconductor region of a first conductivity type electrically connected to the first semiconductor region; an element isolation region provided between the third semiconductor region and the second semiconductor region; A conductive layer provided on the element isolation region; a first conductivity type fourth semiconductor region provided below the element isolation region; and a side wall on the side of the conductive layer,
The photoelectric conversion device, wherein the sidewall is on the element isolation region, and an outer end portion of the sidewall is arranged not to exceed an end portion of the element isolation region. 3. The photoelectric conversion device according to claim 1, wherein the third semiconductor region is in contact with the fourth semiconductor region. 4. The photoelectric conversion device according to claim 1, further comprising: a transfer transistor for transferring carriers accumulated in the second semiconductor region, wherein the conductive layer includes the transfer transistor. A photoelectric conversion device comprising a part of the gate electrode. 4. The photoelectric conversion device according to claim 1, further comprising: a floating diffusion region and a carrier that is provided for each of the second semiconductor regions and accumulates in the second semiconductor region. A transfer transistor for transferring to the diffusion region, an amplifying transistor connected to the floating diffusion region and the gate electrode, a selection transistor connected to the amplifying transistor, and a reset transistor for resetting at least the floating diffusion region Have
The conductive layer is a part of any one of a gate electrode of the transfer transistor, a gate electrode of the amplification transistor, a gate electrode of the selection transistor, and a gate electrode of the reset transistor. A photoelectric conversion device. A solid-state imaging device using the photoelectric conversion device according to claim 1,
The second semiconductor regions are arranged one-dimensionally or two-dimensionally in the first semiconductor region, and a plurality of second semiconductor regions arranged in one direction constitute a group every predetermined number, Each group has the third semiconductor region,
The third semiconductor region is formed in the first semiconductor region between at least one adjacent second semiconductor region in the group;
The element isolation region is provided between the third semiconductor region and the adjacent second semiconductor region, the fourth semiconductor region is provided under each element isolation region, and the conductive layer is at least one of the A solid-state image pickup device provided on an element isolation region. A solid-state imaging device using the photoelectric conversion device according to claim 1,
The second semiconductor regions are arranged one-dimensionally or two-dimensionally in the first semiconductor region, and a plurality of second semiconductor regions arranged in one direction constitute a group every predetermined number,
The third semiconductor region includes a second semiconductor region in the first group and a second group different from the first group adjacent to the second semiconductor region in the first group. Formed in the first semiconductor region between the second semiconductor region disposed inside,
The element isolation region is provided between the third semiconductor region and the first and second groups of second semiconductor regions adjacent to the third semiconductor region, and the fourth semiconductor region is A solid-state imaging device provided under each element isolation region, wherein the conductive layer is provided on at least one of the element isolation regions. 8. The solid-state imaging device according to claim 6, further comprising: a transfer transistor for transferring carriers accumulated in the second semiconductor region, wherein the conductive layer is a gate electrode of the transfer transistor. A solid-state imaging device characterized by comprising a part. 8. The solid-state imaging device according to claim 6, further comprising: a floating diffusion region provided for each photoelectric conversion element; and a second diffusion region provided for each second semiconductor region, and accumulated in the second semiconductor region. A transfer transistor for transferring carriers to the floating diffusion region, an amplifying transistor connected to the floating diffusion region and a gate electrode, a selection transistor connected to the amplifying transistor, and at least resetting the floating diffusion region A resetting transistor,
The conductive layer is a part of any one of a gate electrode of the transfer transistor, a gate electrode of the amplification transistor, a gate electrode of the selection transistor, and a gate electrode of the reset transistor. Solid-state imaging device. 10. The solid-state imaging device according to claim 9, wherein the amplification transistor is provided in common for each group. A solid-state imaging device according to any one of claims 6 to 10,
An optical system for imaging light onto the solid-state imaging device;
And a signal processing circuit for processing an output signal from the solid-state imaging device.