JP2012099539A - Semiconductor wafer and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor wafer allowing a compound semiconductor layer to be thickly formed on a substrate, and capable of reducing parasitic capacitance generated in a buffer region.SOLUTION: In the semiconductor wafer comprising a substrate 2, a buffer region 3 and a main semiconductor region 4, the buffer region consists of a plurality of multilayer structure buffer regions 5 in which a plurality of first layers 6 and a plurality of second layers 7 are alternately arranged; and an intermediate buffer region 8 interposed between a plurality of multilayer structure buffer regions. The first layer consists of a compound semiconductor having a lattice constant smaller than that of a material configuring the substrate, the second layer consists of a compound semiconductor having a lattice constant between the lattice constant of the material configuring the substrate and that of the first layer, and the intermediate buffer region is formed thicker than the first layer and the second layer, and has a lattice constant between the lattice constant of the material configuring the first layer and that of the second layer.

Description

The present invention relates to a semiconductor wafer obtained by epitaxially growing a compound semiconductor on a substrate, and a semiconductor element such as HEMT, MESFET, SBD (Schottky Barrier Diode), LED (Light Emitting Diode), etc. formed from the semiconductor wafer.

A semiconductor wafer obtained by epitaxially growing a nitride semiconductor on a substrate made of silicon (hereinafter referred to as a silicon substrate) is disclosed in Japanese Patent Application Laid-Open No. 2003-59948 (Patent Document 1) and the like. A silicon substrate has a feature that the cost is lower than that of a sapphire substrate. However, the linear expansion coefficient of the silicon substrate is about 4.70 × 10 ⁻⁶ / K, and the linear expansion coefficient of GaN as a nitride semiconductor is about 5.59 × 10 ⁻⁶ / K. There is a large difference in linear expansion coefficient. Silicon and nitride semiconductors have different lattice constants. Note that nitride semiconductors other than GaN also differ from the silicon substrate in terms of linear expansion coefficient and lattice constant. For this reason, when a nitride semiconductor is formed on a silicon substrate, stress is applied to the nitride semiconductor, and cracks and dislocations are likely to occur here. In order to solve this problem, in the technology of the above-mentioned patent publication, a multilayer structure buffer region in which first layers made of AlN and second layers made of GaN are alternately arranged on a silicon substrate is provided. A nitride semiconductor region for forming a semiconductor element is epitaxially grown on the buffer region. Since the multilayer buffer region has a good stress relaxation effect, cracks and dislocations in the nitride semiconductor region for forming a semiconductor element disposed on the buffer region are reduced.

Further, when a nitride semiconductor is epitaxially grown thickly on a substrate, stress is generated in the buffer region and the nitride semiconductor for forming a semiconductor element. Reference 2 is disclosed as an example for reducing warpage generated in the semiconductor wafer due to the stress. ing.

In the semiconductor wafer of Cited Document 2, the buffer area of Cited Document 1 is composed of a plurality of multilayer structure buffer areas and an intermediate buffer area disposed between the plurality of multilayer structure buffer areas.

Specifically, a plurality of multilayer structure buffer regions in which a first layer made of AlN and a second layer made of GaN are alternately arranged are arranged, and the second layer is interposed between the plurality of multilayer structure buffer regions. An example of disposing an intermediate buffer region made of GaN formed to be thicker is disclosed.

JP 2003-59948 A JP 2008-205117 A

However, in the cited document 2, the stress due to the difference between the lattice constant of the material constituting the first layer made of AlN and the lattice constant constituting the intermediate buffer region made of GaN causes piezo polarization in the intermediate buffer region, Lowering the resistance of the intermediate buffer region. Further, the resistance of the intermediate buffer region is reduced by defects due to nitrogen vacancies generated in the intermediate buffer region. As a result, current flows easily in the lateral direction in the thick intermediate buffer region, and there is a problem that the parasitic capacitance generated in the buffer region increases.

ADVANTAGE OF THE INVENTION According to this invention, the compound semiconductor layer can be formed thickly on a board | substrate, and the semiconductor wafer and semiconductor element which can reduce the parasitic capacitance which arises in a buffer area | region are provided.

In order to solve the above problems, a semiconductor wafer of the present invention includes a substrate, a buffer region disposed on one main surface of the substrate and formed of a compound semiconductor, and a compound semiconductor disposed on the buffer region. The buffer wafer includes a plurality of multi-layered buffer regions in which a plurality of first layers and second layers are alternately arranged, and the plurality of multi-layered semiconductor wafers. An intermediate buffer region disposed between the structure buffer regions, and the first layer is made of a compound semiconductor having a lattice constant smaller than a lattice constant of a material constituting the substrate, and the second layer Is made of a compound semiconductor having a lattice constant between the lattice constant of the material constituting the substrate and the lattice constant of the first layer, and the intermediate buffer region is formed of the first and second layers. Also thick, and characterized in that it consists of a compound semiconductor having a lattice constant between the lattice constant of the said lattice constant of the first material constituting the layer a second layer.

In order to solve the above problems, a semiconductor element of the present invention includes a substrate, a buffer region disposed on one main surface of the substrate and formed of a compound semiconductor, and disposed on the buffer region. A semiconductor element having a main semiconductor region formed of a compound semiconductor and an electrode disposed on the main semiconductor region, wherein the buffer region includes a plurality of first layers and second layers alternately arranged. A plurality of multilayered buffer regions and an intermediate buffer region disposed between the plurality of multilayered buffer regions, wherein the first layer is smaller than a lattice constant of a material constituting the substrate The second layer is made of a compound semiconductor having a lattice constant between a lattice constant of a material constituting the substrate and a lattice constant of the first layer, and the intermediate layer is made of a compound semiconductor having a lattice constant. The compound region is formed thicker than the first and second layers, and has a lattice constant between the lattice constant of the material constituting the first layer and the lattice constant of the second layer. A semiconductor device comprising:

According to the semiconductor wafer and the semiconductor device of the present invention, the first layer and the second layer constituting the multilayer structure buffer region between the multilayer structure buffer regions in which a plurality of first layers and second layers are alternately stacked. By forming an intermediate buffer region made of a compound semiconductor formed thicker than the layer and having a lattice constant between the lattice constant of the material forming the first layer and the lattice constant of the material forming the second layer Reduce the stress generated in the intermediate buffer area, or relax the stress relaxation effect of the buffer area to suppress the piezoelectric polarization due to the stress generated in the intermediate buffer area, and suppress the lateral current component generated in the intermediate buffer area By doing so, the parasitic capacitance in the buffer region can be reduced.

It is sectional drawing which shows roughly the semiconductor wafer according to Example 1 of this invention. It is sectional drawing which shows the semiconductor wafer of FIG. 1 in detail. It is a top view which shows the detailed structure of the buffer layer which concerns on Example 1 of this invention. It is sectional drawing which shows schematically HEMT formed based on the semiconductor wafer of FIG. It is a figure which shows the relationship between the thickness and curvature of the main semiconductor region and buffer region for demonstrating curvature. It is sectional drawing which shows roughly the semiconductor wafer according to Example 2 of this invention. It is a figure which shows the thickness and composition change of a buffer area | region according to Example 2 of this invention. It is a figure which shows the thickness and composition change of a buffer area | region according to Example 2 of this invention.

Next, a semiconductor wafer and a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

A semiconductor wafer 1 for forming a high electron mobility transistor (HEMT) as a semiconductor device according to Example 1 of the present invention includes a substrate 2 made of silicon as schematically shown in FIG. A buffer region 3 disposed on one main surface of the substrate 2 and formed of a nitride semiconductor, and a main semiconductor region 4 for forming a semiconductor element disposed on the buffer region 3 and formed of a nitride semiconductor. And have. The semiconductor wafer 1 has an area where a plurality of HEMTs can be formed.

The substrate 2 has a thickness of, for example, 350 to 1000 μm, a lattice constant (for example, 0.543 nm) larger than that of the buffer region 3 and the main semiconductor region 4, and a linear expansion coefficient of the buffer region 3 (for example, 5.60 × 10). ⁻⁶ / K) and a single-crystal silicon having a linear expansion coefficient (for example, 4.70 × 10 ⁻⁶ / K) smaller than that of the main semiconductor region 4 (for example, 5.59 × 10 ⁻⁶ / K). The buffer region 3 and the main semiconductor region 4 have a function as a growth substrate and a function as a mechanical support substrate. Note that a conductivity determining impurity can be added to the substrate 2 as necessary. The substrate 2 can also be formed of a silicon compound such as SiC or sapphire.

FIG. 2 shows a semiconductor wafer 1 in which the semiconductor wafer 1 of FIG. 1 is enlarged in the thickness direction and the buffer region 3 and the main semiconductor region 4 are shown in detail. Note that the thicknesses of the substrate 2 and the regions 3 and 4 in FIGS. 1 and 2 are shown in an explanatory manner, and are different from the actual thicknesses.

The buffer area 3 has first and second multilayer structure buffer areas 5 and 5 'shown in FIG. Each of the first and second multilayer structure buffer regions 5 and 5 ′ is composed of an alternating laminate of the first layer 6 and the second layer 7 indicated by hatching in FIG. 2. In FIG. 2, the first multilayer structure buffer region 5 is formed by stacking four pairs of the first layer 6 and the second layer 7, and the second multilayer structure buffer region 5 ′ is the first layer. 6 and two pairs of the second layer 7 are laminated. However, the number of pairs of the first layer 6 and the second layer 7 in the first multilayer buffer region 5, and the first layer 6 and the second layer 7 in the second multilayer buffer region 5 ′ The number of pairs can be arbitrarily changed. For example, the number of pairs of the first layer 6 and the second layer 7 in the second multilayer structure buffer region 5 ′ may be the same as the number of pairs in the first multilayer structure buffer region 5. However, in order to reduce the maximum value of warpage, the number of pairs of the first layer 6 and the second layer 7 in the second multilayer structure buffer region 5 ′ is set to the number of pairs in the first multilayer structure buffer region 5. Is desirable.

The preferred number of pairs of the first layer 6 and the second layer 7 in the first multilayer structure buffer region 5 is 4 to 50, and the first layer 6 and the second layer in the second multilayer structure buffer region 5 ′. The preferred number of pairs with 2 layers 7 is 2-30. When the number of pairs of the first layer 6 and the second layer 7 in the first multilayer structure buffer region 5 is less than 4, or the first layer 6 and the second layer in the second multilayer structure buffer region 5 ′ When the number of pairs with the layer 7 is less than 2, or when the number of pairs between the first layer 6 and the second layer 7 in the first multilayer buffer region 5 is greater than 50, or In any case where the number of pairs of the first layer 6 and the second layer 7 in the multilayer buffer region 5 'is larger than 30, it is impossible to improve the warp of the semiconductor wafer satisfactorily.

In FIG. 2, the thickness Ta of the first multilayer buffer region 5 is larger than the thickness Ta ′ of the second multilayer buffer region 5 ′. However, the thicknesses Ta and Ta ′ can be adjusted to be the same or arbitrary according to the change in the number of pairs.

The first layer 6 is a material that is smaller than the lattice constant of the material constituting the substrate 2 and has a relatively high insulating property.
_{Al x M y Ga 1-x} -y N
Here, the M is at least one element selected from In (indium) and B (boron),
X and y are 0 <x ≦ 1,

0 ≦ y <1,

x + y ≦ 1
It consists of a nitride semiconductor material represented by a numerical value satisfying That is, the first layer 6 is made of, for example, a nitride semiconductor material selected from AlN (aluminum nitride), AlInN (indium aluminum nitride), AlGaN (gallium aluminum nitride), and AlInGaN (gallium indium aluminum nitride). The first layer 6 can be doped with n-type or p-type conductivity determining impurities as necessary. The thickness Td of the first layer 6 is desirably 0.5 to 20 nm. When the thickness Td of the first layer 6 is thinner than 0.5 nm and thicker than 20 nm, the effect of improving the warpage of the semiconductor wafer 1 and the crystallinity of the main semiconductor region 4 is lowered. In this embodiment, the first layer 6 is made of AlN, and the thickness Td is set to 5 nm.

In FIG. 2, all the first layers 6 are formed of the same material (AlN), but the plurality of first layers 6 can be formed of different materials. In FIG. 2, all the first layers 6 are formed to have the same thickness, but the plurality of first layers 6 may be formed to have different thicknesses. The lattice constants of the crystal axes a and c of the first layer 6 are smaller than the lattice constant of the substrate 2 made of silicon (for example, 0.311 nm for the a axis and 0.498 nm for the c axis). Further, the linear expansion coefficient of the first layer 6 is larger than the linear expansion coefficient of the substrate 2 (for example, 5.64 × 10 ⁻⁶ / K).

The second layer 7 disposed on the first layer 6 has a lattice constant between the lattice constant of the material constituting the substrate 2 and the lattice constant of the material constituting the first layer 6. For example, the nitride content ratio is a second ratio (including zero) of a nitride semiconductor,
Chemical formula
Al _{a Mb} Ga _1-ab N
Here, the M is at least one element selected from In (indium) and B (boron),
A and b are 0 ≦ a ≦ 1,

0 ≦ b <1,

a + b ≦ 1

a <x
It is made of a nitride semiconductor material represented by a numerical value satisfying That is, the second layer 7 is, for example, a lattice constant between the lattice constant of the material constituting the substrate 2 and the lattice constant of the material constituting the first layer 6 or the material constituting the first layer 6. A material having a smaller band gap than the first layer 6 and having a relatively low insulating property, such as GaN (gallium nitride), InGaN (gallium indium nitride), AlInN (indium aluminum nitride), It is made of a nitride semiconductor material selected from AlGaN (gallium aluminum nitride) and AlInGaN (gallium indium aluminum nitride) having a lower Al content than the first layer. The second layer 7 can be doped with n-type or p-type conductivity determining impurities as necessary. The thickness Te of the second layer 7 is preferably 1 to 50 nm. When the thickness Te of the second layer 7 is thinner than 1 and thicker than 50 nm, the effect of improving the warpage of the semiconductor wafer and the crystallinity of the main semiconductor region 4 is lowered. In this embodiment, the second layer 7 is made of GaN having a band gap energy narrower than that of the first layer 6 and a resistance value lower than that of the first layer 6, and the thickness Te is set to 3.5 nm.

In FIG. 2, all the second layers 7 are made of the same material (GaN), but a plurality of second layers 7 can be made of different materials. In FIG. 2, all the second layers 7 are formed to have the same thickness, but a plurality of the second layers 7 can be formed to have different thicknesses. The second layer 7 does not contain aluminum as an essential component and may not contain aluminum. Therefore, the second proportion of aluminum in the second layer 7 is a predetermined value including zero. However, since the resistance value of the second layer 7 can be increased by containing aluminum in the second layer 7, it is desirable that aluminum be also contained in the second layer 7. The lattice constants of the crystal axes a and c of the second layer 7 are larger than the lattice constant of the first layer 6 and smaller than the lattice constant of the substrate 2 (for example, 0.318 nm for the a axis and 0 for the c axis). .518 nm). Further, the linear expansion coefficient of the second layer 7 is larger than the linear expansion coefficient of the substrate 2 (for example, 5.59 × 10 ⁻⁶ / K).

The intermediate buffer region 8 is disposed between the first multilayer structure buffer region 5 and the second multilayer structure buffer region 5 ′. The intermediate buffer region 8 is made of a material having a lattice constant smaller than that of the material constituting the first layer 6 macroscopically, for example, a nitride semiconductor containing aluminum at a third ratio smaller than the first ratio. Consists of
Chemical formula
Al _h M _k Ga _1-hk N
Here, the M is at least one element selected from In (indium) and B (boron),
H and k are 0 ≦ h <1,


0 ≦ k <1,

h + k ≦ 1

a ≦ h <x
It is formed of a nitride semiconductor material indicated by a numerical value satisfying
FIG. 3 shows a detailed structure of the intermediate buffer area 8 according to the first embodiment of the present invention. The intermediate buffer region 8 includes a first intermediate buffer layer 81, a second intermediate buffer layer 82, and a third intermediate buffer layer 83.

The first intermediate buffer layer 81 is disposed at the bottom of the intermediate buffer region 8, that is, between the first multilayer buffer region 5 and the second intermediate buffer layer 82. The first intermediate buffer layer 81 is made of aluminum at a fourth ratio that is smaller than the first ratio and larger than the second ratio so as to have a lattice constant larger than that of the material constituting the first layer 6. Containing nitride semiconductor,
Chemical formula
_{Al m M n Ga 1-m} -n N
Here, the M is at least one element selected from In (indium) and B (boron),
M and n are 0 <m <1,

0 ≦ n <1,

m + n ≦ 1

a <m <x
It is formed of a nitride semiconductor material indicated by a numerical value satisfying That is, the first intermediate buffer layer 81 is made of, for example, a nitride semiconductor material selected from AlGaN, AlInGaN, and AlInN having a lower Al content than the first layer 6. The aluminum content m in the first intermediate buffer layer 81 is preferably 0.5 or less.

The second intermediate buffer layer 82 is disposed between the first intermediate buffer layer 81 and the third intermediate buffer layer 83. The second intermediate buffer layer 82 is made of a nitride semiconductor material containing aluminum at the same second ratio (including zero) as the second layer 7. That is, the second intermediate buffer layer 82 includes, for example, GaN (gallium nitride), InGaN (gallium indium nitride), AlInN (indium aluminum nitride), the first layer 6 and the first intermediate buffer layer 81. It consists of a nitride semiconductor material selected from AlGaN (gallium aluminum nitride) and AlInGaN (gallium indium aluminum nitride) with a low content.

The third intermediate buffer layer 83 is disposed above the intermediate buffer region 8 and between the second intermediate buffer layer 82, that is, the second multilayer buffer region 5 ′. The third intermediate buffer layer 83 is made of a nitride semiconductor containing aluminum at a fifth ratio smaller than the first ratio and larger than the second ratio,
Chemical formula
Al _p M _q Ga _1-pq N
Here, the M is at least one element selected from In (indium) and B (boron),
M and n are 0 <p <1,

0 ≦ q <1,

p + q ≦ 1

a <p <x
It is formed of a nitride semiconductor material indicated by a numerical value satisfying That is, the third intermediate buffer layer 83 is made of, for example, a nitride semiconductor material selected from AlGaN, AlInGaN, and AlInN having a lower Al content than the first layer 6. The aluminum content m in the third intermediate buffer layer 83 is preferably 0.5 or less. The third intermediate buffer layer 83 may have the same composition as the first intermediate buffer layer 81 or may have different compositions.

In addition, each layer 81, 82, 83 constituting the intermediate buffer region 8 can be doped with n-type or p-type conductivity determining impurities as necessary. In addition, each of the layers 81, 82, and 83 constituting the intermediate buffer region 8 may be composed of a plurality of layers. For example, the first intermediate buffer layer 81 may have a structure in which a GaN layer of several nm and an AlGaN layer of several nm are repeatedly stacked, and the first intermediate buffer layer 81 is average (or macroscopic). ), The aluminum content m should satisfy the above relationship.

Further, the first and second multilayer buffer regions 5 and 5 ′ are obtained by further laminating the first layer 6 on the alternate laminated body of the first layer 6 and the second layer 7, An intermediate buffer region 8 may be formed thereon. Thus, when the first layer 6 on the top of the first and second multilayer structure buffer regions 5 and 5 ′ is included in the first and second multilayer structure buffer regions 5 and 5 ′, the first layer 6 is shown. The sum of the first layers 6 included in the first and second multilayer structure buffer regions 5, 5 ′ is one more than the sum of the second layers 7.

The intermediate buffer region 8 has a thickness Tb larger than the thickness Td of the first layer 6 and the thickness Te of the second layer 6. The intermediate buffer region 8 is desirably formed thicker than the sum of the thickness Td of the first layer 6 and the thickness Te of the second layer 7, and the thickness of the intermediate buffer region 8 is preferably 20 to 400 nm. desirable. When the thickness of the intermediate buffer region 8 is thinner than 20 nm and thicker than 400 nm, the effect of improving the warpage of the semiconductor wafer and the crystallinity of the main semiconductor region 4 is lowered.

In the present embodiment, the first and third intermediate buffer layers 81 and 83 are made of AlGaN having a thickness of 50 nm, the second intermediate buffer layer 82 is made of GaN having a thickness of 200 nm, and the thickness Tb of the intermediate buffer region 8 is It is set to 300 nm.

Note that the lattice constants of the crystal axes a and c of the intermediate buffer region 8 are lattice constants seen on average (or macroscopic). Further, when the first multilayer 6 is further laminated on the alternate laminated body of the first layer 6 and the second layer 7 as the first multilayer structure buffer region 5, the intermediate buffer region 8 As the distance from the substrate 2 increases (in the direction in which the thickness of the buffer region 3 on the substrate 2 increases), the lattice constant of the material constituting the first intermediate buffer layer 81 gradually approaches the second layer 7 from the first layer 6. You may do it. For example, when the first intermediate buffer layer 81 is made of AlGaN, the Al content rate may be gradually reduced as the distance from the substrate 2 increases. In this case, the relaxation of stress due to the arrangement of the intermediate buffer region 8 can be realized more gently, and the semiconductor wafer 1 can be made thicker.

Furthermore, by suppressing the piezo polarization due to the stress generated in the intermediate buffer region 8 and suppressing the lateral current component generated in the intermediate buffer region 8, the parasitic capacitance in the buffer region 3 can be reduced.

The second multilayer structure buffer area 5 ′ arranged on the intermediate buffer area 8 is formed of a stacked body of sub multilayer structure buffer areas 6 like the first multilayer structure buffer area 5. The second multilayer structure buffer region 5 'is different from the first multilayer structure buffer region 5 in the number of pairs of the first layer 6 and the second layer 7, and the thickness Ta' is the first multilayer structure buffer. The structure is the same as that of the first multilayer buffer area 5 except for the differences from the area 5.

It should be noted that the first multilayered buffer region 5 ′ in the second multilayered buffer region 5 ′ satisfies the condition that the average Al content in the second multilayered buffer region 5 ′ is larger than that of the intermediate buffer region 8. The material constituting either one or both of the layer 6 and the second layer 7 can be modified. Further, the second multilayer structure buffer region 5 ′ can have the same number of pairs of the first layer 6 and the second layer 7 as the first multilayer structure buffer region 5.

The main semiconductor region 4 according to Example 1 of FIG. 1 includes an electron transit layer 41 made of GaN that is not doped with impurities and an electron supply layer that is made of Al _0.2 Ga _0.8 N that is not doped with impurities in order to form a HEMT. 42. The electron supply layer 42 can be doped with n-type impurities. The electron transit layer 41 disposed on the buffer region 3 can also be called a channel layer, and has a thickness of 1800 nm, for example. The electron supply layer 42 disposed on the electron transit layer 41 causes the electron transit layer 41 to form a known two-dimensional carrier gas layer (two-dimensional electron gas layer) by piezoelectric polarization based on a heterojunction with the electron transit layer 41. For example, it has a thickness of 30 nm.

The electron supply layer 42 containing Al is extremely thinner than the electron transit layer 41 not containing Al. Therefore, the average aluminum ratio in the main semiconductor region 4 is substantially the same as the Al ratio in the electron transit layer 41, and is smaller than the first and second multilayer buffer regions 5, 5 ′. The average lattice constant of the main semiconductor region 4 is substantially the same as the lattice constant of the electron transit layer 41, and is larger than the first and second multilayer structure buffer regions 5, 5 ′ and smaller than the substrate 2. .

The lattice constants in the crystal axes a and c of the electron transit layer 41 occupying most of the main semiconductor region 4 are, for example, 0.318 nm on the a axis and 0.518 nm on the c axis, which is larger than the lattice constant of the first layer 6. large.

The linear expansion coefficient of the thickest electron transit layer 41 in the main semiconductor region 4, the linear expansion coefficient of the next thickest electron supply layer 42, and the macroscopic linear expansion coefficient of the main semiconductor region 4 are all the substrate. The linear expansion coefficient of 2 and the linear expansion coefficient of the first layer 6 are larger. Therefore, when the substrate 2 is not taken into consideration, that is, when the stress of the main semiconductor region 4 is observed ignoring the substrate 2, a compressive stress is generated in the main semiconductor region 4 in the same manner as the intermediate buffer region 8 when viewed macroscopically.

FIG. 4 shows a HEMT manufactured using the semiconductor wafer 1 shown in FIGS. In order to simplify the description, the same reference numerals in FIG. 4 denote the same parts as in FIG. 1, and a description thereof will be omitted. The source electrode 91 as the first electrode and the drain electrode 92 as the second electrode are in ohmic (low resistance) contact with the electron supply layer 42, and the gate electrode 93 as the control electrode is in Schottky contact with the electron supply layer 42. ing. Note that a contact layer having a high n-type impurity concentration can be provided between the source electrode 91 and the drain electrode 92 and the electron supply layer 42. The gate electrode 92 may have a MIS structure. In order to stabilize the operation of the HEMT, an auxiliary electrode 94 is provided on the lower surface of the substrate 2, and this is connected to the source electrode 91 by a conductor 95. Therefore, the withstand voltage between the drain electrode 92 and the auxiliary electrode 94 provided on the lower surface of the substrate 2 is important in the HEMT of FIG. Since the substrate 2 is a silicon semiconductor, a high breakdown voltage cannot be expected here. Therefore, in this embodiment, the buffer region 3 and the main semiconductor region 4 are formed relatively thick in order to improve the breakdown voltage.

Next, an example of a method for manufacturing the semiconductor wafer 1 in FIG. 1 and the HEMT in FIG. 4 will be described.
First, a silicon substrate 2 having a main surface which is a (111) plane in the crystal plane orientation indicated by the Miller index is prepared.

Next, the substrate 2 is put into a reaction chamber of a well-known MOCVD (Metal Organic Chemical Vapor Deposition), that is, an organic metal vapor phase growth apparatus, the oxide film on the surface of the substrate 2 is removed, and TMA (trimethylaluminum) is put into the reaction chamber. The first layer 6 made of AlN (aluminum nitride) is epitaxially grown on the silicon substrate 2 by flowing ammonia and ammonia. Thereafter, the supply of TMA is stopped, and the supply of ammonia is continued. At the same time, TMG (trimethylgallium) is flowed to epitaxially grow the second layer 7 made of GaN. The first multilayer buffer region 5 is obtained by repeating the steps of forming the first and second layers 6 and 7 a desired number of times.

Next, ammonia and less TMA (trimethylaluminum) than in the formation of the first layer 6 are allowed to flow in the reaction chamber longer than in the formation of the first layer 6 so as to flow from the first layer 6 and the second layer 7. The intermediate buffer region 8 made of thicker AlGaN is epitaxially grown.

Next, a second multilayer structure buffer region 5 ′ is formed by the same method as the first multilayer structure buffer region 5, and the buffer region 3 is completed.

Thereafter, the main semiconductor region 4 is formed by a known epitaxial growth method. This completes the semiconductor wafer.

Further, when the HEMT is manufactured using the semiconductor wafer 1, the source electrode 91 made of, for example, titanium (Ti) / gold (Au) is used as the first electrode, and the titanium (Ti) / gold (Au) is used as the second electrode. A drain electrode 92 made of is deposited on the main semiconductor region 4, and a gate electrode 93 in Schottky contact is formed on the electron supply layer 42 between the source electrode 91 and the drain electrode 92 to complete.

FIG. 5 schematically shows stress (strain force) generated in each of the regions 5, 8, 5 ′, and 4 of the semiconductor wafer 1 when the substrate 2 is not considered (when the substrate 2 is ignored). As shown in FIG. 2, the first and second multilayer structure buffer regions 5 and 5 'include a plurality of first layers 6 and second layers 7, but on average, the ratio of Al is an intermediate buffer. Since the lattice constant is larger than that of the region 8 and, on average, smaller than that of the intermediate buffer region 8, a tensile stress is generated as shown by the outward arrow in FIG. In contrast, the intermediate buffer region 8 and the main semiconductor region 4 having a lattice constant larger than that of the first and second multilayer buffer regions 5 and 5 ′ on the average are shown in FIG. As shown in FIG. If the stresses in the respective regions 4, 5, 5 ′ and 8 are adjusted, the tensile stress and the compressive stress are offset, and the warpage of the semiconductor wafer 1 can be reduced. The intermediate buffer region 8 is formed of a material (for example, AlGaN) having a lattice constant between the lattice constant constituting the first layer 6 and the lattice constant constituting the second layer 7. Compared with the case where the intermediate buffer region 8 is formed of GaN, the stress is small, and further, the stress relaxation effect of the buffer region 3 can be moderated.

Further, when considering the substrate 2 (when the substrate 2 is not ignored), it is necessary to consider the influence of the substrate 2 on the buffer region 3 and the main semiconductor region 4, and this is not necessarily as shown in FIG. The stress (strain force) generated in each of the regions 5, 8, 5 'and 4 of the semiconductor wafer 1 of Example 1 can be relaxed, and the film thickness of the semiconductor wafer 1 can be increased.

As is apparent from the above, the first embodiment has the following effects.
(1) Disposing first and third intermediate buffer layers 81 and 83 made of a compound semiconductor having a lattice constant between the lattice constant of the material constituting the first layer 6 and the lattice constant of the second layer 7 As a result, the stress generated in the second intermediate buffer layer 82 is suppressed, thereby suppressing the piezoelectric polarization in the intermediate buffer region 8 and suppressing the current component in the lateral direction of the intermediate buffer region 8, thereby The parasitic capacitance in the region 3 can be reduced. Therefore, if a switching element is formed using the semiconductor wafer 1 of the present invention, the switching speed can be improved.
(2) The intermediate buffer region 8 made of a material having a lattice constant between the lattice constant of the material constituting the first layer 6 and the lattice constant constituting the second layer 7 is changed from the first multilayer structure buffer region 5 to the first multilayer buffer region 5. By disposing it between the two multilayer structure buffer regions 5 ', the stress of the entire buffer region 3 can be relaxed gradually, and the semiconductor wafer 1 can be made thicker. Therefore, the vertical breakdown voltage of the semiconductor wafer 1 can be improved.
(3) By using a material having a lattice constant between the lattice constant of the material constituting the first layer 6 and the lattice constant of the material constituting the second layer 7 in the intermediate buffer region 8, the semiconductor wafer 1 In addition to improving the warpage, the buffer region 3 and the main semiconductor region 4 can be made thicker. As a result, the breakdown voltage in the thickness direction of the semiconductor wafer 1 can be improved.
(4) By providing the intermediate buffer region 8, the compressive stress applied to the main semiconductor region 4 can be reduced, and cracks in the main semiconductor region 4 can be reduced.
(5) By adjusting at least one of the composition and thickness of the second layer 7, the stress in the first and second multilayer structure buffer regions 5, 5 ′ can be finely adjusted. Further, by including aluminum in the second layer 7, the resistance value of the second layer 7 can be increased and the parasitic capacitance in the buffer region 3 can be reduced.
(6) Since each of the first and second multilayer structure buffer regions 5 and 5 'has a structure in which the relatively thin first and second layers 6 and 7 are alternately laminated, it is composed of only one layer. Compared with the buffer region, cracks can be suppressed, and the buffer region 3 can be formed thicker.
(7) Disposing the first intermediate buffer layer 81 made of a material having a lattice constant between the lattice constant of the material constituting the first layer 6 and the lattice constant of the material constituting the second layer 7. Thus, the stress generated in the second intermediate buffer layer 82 can be relaxed. Further, the warpage of the wafer 1 can be controlled by adjusting the aluminum content ratio or the film thickness of the second intermediate buffer layer 82.

Next, a semiconductor wafer 1a according to the second embodiment will be described with reference to FIG. 6 that are substantially the same as those in FIG. 2 are assigned the same reference numerals, and descriptions thereof are omitted.

The semiconductor wafer 1a shown in FIG. 6 has a second intermediate buffer region 8 ′ and a third multilayer buffer region 5 ″ added between the second multilayer buffer region 5 ′ and the main semiconductor region 4 shown in FIG. The rest of the configuration is the same as that in Fig. 2. The added second intermediate buffer region 8 'included in the modified buffer region 3a in Fig. 6 is the second and third multilayer buffer regions 5'. 5 ″, formed of the same material as the intermediate buffer region (first intermediate buffer region) 8 and having a thickness Tb ′ substantially the same as the thickness Tb of the intermediate buffer region 8.

In the semiconductor wafer 1a of FIG. 6, the number of pairs of the first layer 6 and the first second layer 7 in the second multilayer buffer region 5 ′ is equal to the number of pairs in the multilayer buffer region 5 ′ of the first embodiment. The number of pairs of the first layer 6 and the second layer 7 in the third multilayer buffer region 5 ″ is 2, which is one more than the number 3. Accordingly, the first, second and third The number of pairs of the first layer 6 and the second layer 7 in the multilayer structure buffer regions 5, 5 ′ and 5 ″ decreases as the distance from the substrate 2 increases.

Further, in the semiconductor wafer 1a of FIG. 6, when a plurality of intermediate buffer regions 8, 8 ′ sandwiched between the multilayer buffer regions 5, 5 ′, 5 ″ are arranged, the lattice constants of the plurality of intermediate buffer regions 8, 8 ′. Is preferably smaller as the distance from the substrate 2 becomes smaller and approaches the lattice constant of the second layer 7. For example, the second intermediate buffer region 8 'is compared with the aluminum content of the material constituting the intermediate buffer region 8. By reducing the aluminum content ratio (sixth ratio), the stress can be relaxed more gently, and the buffer region 3a can be made thicker more easily. As shown in FIG. 7, the second intermediate buffer is compared with the aluminum content in the material of the first and third intermediate buffer layers 81 and 83 constituting the intermediate buffer region 8. The first and third intermediate buffer layer 81 'constituting the § area 8', by reducing the content of aluminum material 83 ', the structure as described above can be obtained.

Further, the first and third intermediate buffer layers 81, 81 ′, 83, 83 ′ in the intermediate buffer regions 8, 8 ′ may change the Al content in each of the first and third intermediate buffer layers 81, 81 ′, 83, 83 ′. For example, as shown in FIG. 8, the lattice constant of the first intermediate buffer layers 81 and 81 ′ approaches the lattice constant of the second intermediate buffer layers 82 and 82 ′ as the distance from the substrate 2 increases (in the thickness direction). Is preferred. Furthermore, it is preferable that the lattice constants of the third intermediate buffer layers 83 and 83 ′ approach the lattice constants of the second intermediate buffer layers 82 and 82 ′ as they approach the substrate 2 (in the direction opposite to the thickness direction). Further, the composition (Al content ratio) of at least a part of the first intermediate buffer layers 81 and 81 ′ and the third intermediate buffer layers 83 and 83 ′ is the same as the composition of the second intermediate buffer layers 82 and 82 ′. It may be the same. With such a structure, the interface between the first intermediate buffer layer 81, 81 ′ and the second intermediate buffer layer 82, 82 ′ and the third intermediate buffer layer 83, 83 ′ and the second intermediate buffer layer 82, The change in the band gap at the interface with 82 'becomes relatively moderate. Therefore, the accumulation of carriers in the intermediate buffer region 8 is suppressed, and the generation of channels (two-dimensional electron gas, two-dimensional hole gas) in the intermediate buffer layers 82 and 82 'is suppressed, and the buffer region 3a Parasitic capacitance is reduced.

The present invention is not limited to the first and second embodiments described above, and can be modified as shown below, including combinations of the embodiments.
(1) The main semiconductor region 4 is made of another semiconductor such as MESFET, SBD, LED, etc. other than HEMT.
It can be transformed into a semiconductor region for constituting an element.
(2) The third multilayer structure buffer region 5 ″ is formed of a material having substantially the same composition as the first and second multilayer structure buffer regions 5, 5 ′, and the first and second multilayer structure buffers. It has a thickness Ta ″ that is thinner than the regions 5, 5 ′. However, the thicknesses of the first, second, and third multilayer structure buffer regions 5, 5 ′, 5 ″ can be the same.
(3) The number of pairs of the first layer 6 and the second layer 7 constituting the first, second and third multilayer structure buffer regions 5, 5 ′ and 5 ″ may be the same.
(4) The effect of the present invention can be obtained without forming the plurality of sub multilayer buffer regions 6 constituting the first, second and third multilayer buffer regions 5, 5 ', 5 "with the same material. Can be formed of different materials within the range of possible.
(5) The effects of the present invention can be obtained without forming the plurality of second layers 7 constituting the first, second and third multilayer structure buffer regions 5, 5 ′, 5 ″ with the same material or thickness. Different materials or thicknesses can be used within the possible range.
(6) On the third multilayer buffer area 5 ″ in FIG. 6, the same thing as the second intermediate buffer area 8 ′ and the third multilayer buffer area 5 ″ is repeated once or a plurality of times. Can be provided.

DESCRIPTION OF SYMBOLS 1, 1a Semiconductor wafer 2 Silicon substrate 3, 3a Buffer layer 4 Main semiconductor region 5, 5 ', 5 "1st, 2nd and 3rd multilayer structure buffer region 6 1st layer 7 2nd layer 8, 8 ', 8' Intermediate buffer region 81, 81 'First intermediate buffer layer 82, 82' Second intermediate buffer layer 83, 83 'Third intermediate buffer layer

Claims (4)

A semiconductor wafer having a substrate, a buffer region disposed on one main surface of the substrate and formed of a compound semiconductor, and a main semiconductor region disposed on the buffer region and formed of a compound semiconductor. ,
The buffer area includes a plurality of multilayer buffer areas in which a plurality of first layers and second layers are alternately arranged, and an intermediate buffer area arranged between the plurality of multilayer buffer areas. ,
The first layer is made of a compound semiconductor having a lattice constant smaller than that of the material constituting the substrate,
The second layer is composed of a compound semiconductor having a lattice constant between the lattice constant of the material constituting the substrate and the lattice constant of the first layer,
The intermediate buffer region is formed thicker than the first and second layers, and has a lattice constant between a lattice constant of a material constituting the first layer and a lattice constant of the second layer. A semiconductor wafer comprising a compound semiconductor. The intermediate buffer region has a first intermediate buffer layer, a second intermediate buffer layer, and a third intermediate buffer layer, and the first intermediate buffer layer is made of a material that constitutes the first layer. The second intermediate buffer layer is made of the same material as that of the second layer, and the third intermediate buffer layer is made of the same material as that of the second layer. A semiconductor wafer comprising a material having a lattice constant larger than a material constituting the first layer and smaller than a material constituting the second layer. The substrate is made of silicon or a silicon-based material,
The first layer is made of a nitride semiconductor containing aluminum,
The second layer is made of a nitride semiconductor containing less or less aluminum than the first layer;
3. The semiconductor wafer according to claim 1, wherein the intermediate buffer region is made of a nitride-based semiconductor containing aluminum at a rate smaller than that of the first layer on average. A substrate, a buffer region disposed on one main surface of the substrate and formed of a compound semiconductor, a main semiconductor region disposed on the buffer region and formed of a compound semiconductor, and on the main semiconductor region A semiconductor element having an electrode disposed thereon,
The buffer area includes a plurality of multilayer buffer areas in which a plurality of first layers and second layers are alternately arranged, and an intermediate buffer area arranged between the plurality of multilayer buffer areas. ,
The first layer is made of a compound semiconductor having a lattice constant smaller than that of the material constituting the substrate,
The second layer is composed of a compound semiconductor having a lattice constant between the lattice constant of the material constituting the substrate and the lattice constant of the first layer,
The intermediate buffer region is formed thicker than the first and second layers, and has a lattice constant between a lattice constant of a material constituting the first layer and a lattice constant of the second layer. A semiconductor device comprising a compound semiconductor.