JP2012099213A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption of a display device and increase the size and definition of the display device, by suppressing the variation in threshold voltage of a transistor and reducing the number of contacts of a driver IC mounted on a display panel.SOLUTION: A gate electrode of a transistor which easily deteriorates is connected to a wire to which a high potential is supplied via a first switching transistor and to a wire to which a low potential is supplied via a second switching transistor. By inputting a clock signal to a gate electrode of the first switching transistor and inputting an inversion clock signal to a gate electrode of the second switching transistor, the high potential and the low potential are alternately supplied to the gate electrode of the transistor which easily deteriorates.

Description

The present invention relates to a display device having a circuit formed using a transistor. In particular, the present invention relates to a display device using an electro-optic element such as liquid crystal or a light emitting element as a display medium, and a driving method thereof.

In recent years, display devices have been actively developed due to an increase in large display devices such as liquid crystal televisions. In particular, a technique for integrally forming a driver circuit (hereinafter also referred to as an internal circuit) including a pixel circuit and a shift register using a transistor formed of an amorphous semiconductor (hereinafter also referred to as amorphous silicon) on an insulating substrate is described. In order to greatly contribute to the reduction of power consumption and cost, development is being actively promoted. An internal circuit formed on the insulator is connected to a controller IC or the like (hereinafter also referred to as an external circuit) via an FPC or the like, and its operation is controlled.

Among the internal circuits shown above, a shift register using a transistor formed of an amorphous semiconductor (hereinafter also referred to as an amorphous silicon transistor) has been devised. A structure of a flip-flop included in a conventional shift register is illustrated in FIG. The flip-flop in FIG. 30A includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, a transistor 15, and a transistor 17, and includes a signal line 21, a signal line 22, a wiring 23, a signal line 24, a power supply line 25, The power supply line 26 is connected. A start signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input to the signal line 21, the signal line 22, the signal line 24, the power supply line 25, and the power supply line 26, respectively. The operation period of the flip-flop in FIG. 30A is divided into a set period, a selection period, a reset period, and a non-selection period as shown in the timing chart of FIG. Selection period.

Here, the transistor 12 and the transistor 16 are on in the non-selection period. Therefore, since amorphous silicon is used for the semiconductor layers of the transistors 12 and 16, the threshold voltage (Vth) varies due to deterioration or the like. More specifically, the threshold voltage increases. That is, the conventional shift register cannot be turned on because the threshold voltages of the transistors 12 and 16 are increased, so that VSS cannot be supplied to the node 41 and the wiring 23 and malfunction occurs.

In order to solve this problem, Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3 devise shift registers that can suppress the shift of the threshold voltage of the transistor 12. In Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3, a new transistor (referred to as a first transistor) is arranged in parallel with a transistor 12 (referred to as a second transistor). By inputting inverted signals to the gate electrode of the first transistor and the gate electrode of the second transistor, the threshold voltage shift of the first transistor and the second transistor is suppressed.

Further, Non-Patent Document 4 devises a shift register that can suppress the shift of the threshold voltage of the transistor 16 as well as the transistor 12. In Non-Patent Document 4, a new transistor (referred to as a first transistor) is arranged in parallel with a transistor 12 (referred to as a second transistor), and another new transistor (referred to as a third transistor) is provided as a transistor. 16 (referred to as a fourth transistor) is arranged in parallel. In the non-selection period, inverted signals are input to the gate electrode of the first transistor and the gate electrode of the second transistor, respectively, and inverted to the gate electrode of the third transistor and the gate electrode of the fourth transistor, respectively. By inputting a signal, a shift in threshold voltage of the first transistor, the second transistor, the third transistor, and the fourth transistor is suppressed.

Further, in Non-Patent Document 5, the shift of the threshold voltage of the transistor 12 is suppressed by applying an AC pulse to the gate electrode of the transistor 12.

Note that the display devices of Non-Patent Document 6 and Non-Patent Document 7 use a shift register formed of an amorphous silicon transistor as a scanning line driving circuit, and further video from one signal line to R, G, and B subpixels. By inputting signals, the number of signal lines is reduced to 1/3. Thus, the display devices of Non-Patent Document 6 and Non-Patent Document 7 reduce the number of connections between the display panel and the driver IC.

JP 2004-157508 A

Soo Young Yoon, et al. , "Highly Stable Integrated Gate Driver A-Si TFT with Dual Pull-down STRUCTURE", SICIETY FOR INFORMATION DISPLAY. 348-351 Binn Kim, et al. , "A-Si Gate Driver Integration with Time Shared Data Driving", Proceedings of The 12th International Display Workshops in Conjunction. 1073-1076 Mindoo Chun, et al. , "Integrated Gate Driver Using Highly Stable a-Si TFT's", Proceedings of The 12th International Display Workshops in junction with Asp. 1077-1080 Chun-Ching, et al. , “Integrated Gate Driver Using a-Si TFT”, Processeds of The 12th International Display Workshops in junction with Asia Disp. 5, 1023-1026 Yong Ho Jang, et al. , “A-Si TFT Integrated Gate Driver with AC-Driving Single Pull-Down Structure X, SOCIETY FOR INFORMATION DISPLAY TECHNO TECHNO TECHNO TECHN 208-211 Jin Young Choi, et al. , “A Compact and Cost-Efficient TFT-LCD through the Triple-Gate Pixel Structure II XOPIC TECHN TECHN TECHNO TECHN TECHN 274-276 Yong Soon Lee, et al. , "Advanced TFT-LCD Data Line Reduction Method", SOCIETY FOR INFORMATION DISPLAY 2006 INTERNIONAL SYMPOSIUM DIGITAL OF TECHNICAL PAPERS, X. 1083-1086

According to the conventional technique, the shift of the threshold voltage of the transistor is suppressed by applying an AC pulse to the gate of the transistor that is easily deteriorated. However, when amorphous silicon is used as the semiconductor layer of the transistor, it is a problem that the transistor constituting the circuit that generates the AC pulse also causes a threshold voltage shift.

In addition, it has been proposed to reduce the number of contact points between the display panel and the driver IC by reducing the number of signal lines to 1/3 (Non-Patent Document 6 and Non-Patent Document 7). There is a need to further reduce the number of IC contacts.

That is, as a problem that cannot be solved by the conventional technique, a circuit technique that suppresses the fluctuation of the threshold voltage of the transistor remains as a problem. A technique for reducing the number of contact points of a driver IC mounted on a display panel remains as a problem. Lowering power consumption of display devices remains a problem. There remains a problem of enlargement or high definition of the display device.

An object of the invention disclosed in this specification is to provide an industrially useful technique by solving one or more of the above problems.

The display device according to the present invention can suppress a shift in threshold voltage of a transistor by alternately applying a positive power source and a negative power source to a gate electrode of a transistor that is likely to deteriorate.

Further, the display device according to the present invention alternately supplies a high potential (VDD) or a low potential (VSS) through a switch to a gate electrode of a transistor that is likely to deteriorate, whereby the transistor The threshold voltage shift can be suppressed.

Specifically, the gate electrode of the transistor that is easily deteriorated is connected to a wiring to which a high potential is supplied via the first switching transistor and a wiring to which a low potential is supplied via the second switching transistor, By inputting a clock signal to the gate electrode of the first switching transistor and inputting an inverted clock signal to the gate electrode of the second switching transistor, a high potential or a low potential is alternately applied to the gate electrode of the transistor that is likely to deteriorate. Supply.

Note that a variety of switches can be used as a switch described in this document (specification, claims, drawings, or the like). Examples include electrical switches and mechanical switches. That is, it is only necessary to be able to control the current flow, and is not limited to a specific one. For example, as a switch, a transistor (for example, a bipolar transistor, a MOS transistor, etc.), a diode (for example, a PN diode, a PIN diode, a Schottky diode, a MIM (Metal Insulator Semiconductor) diode, a MIS (Metal Insulator Semiconductor) diode, a diode-connected transistor, etc.), A thyristor or the like can be used. Alternatively, a logic circuit combining these can be used as a switch.

In the case where a transistor is used as a switch, the transistor operates as a mere switch, and thus the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desired to suppress off-state current, it is desirable to use a transistor having a polarity with smaller off-state current. As a transistor with low off-state current, a transistor having an LDD region, a transistor having a multi-gate structure, and the like can be given. Alternatively, an N-channel transistor is preferably used in the case where the transistor operates as a switch when the potential of the source terminal of the transistor is close to a low potential power source (Vss, GND, 0 V, or the like). On the other hand, it is desirable to use a P-channel transistor when operating in a state where the potential of the source terminal is close to a high potential side power supply (Vdd or the like). This is because when the N-channel transistor operates with the source terminal close to the low-potential side power supply, and the P-channel transistor operates with the source terminal close to the high-potential side power supply, the absolute value of the gate-source voltage is This is because it can be made larger, so that it operates more reliably as a switch. Moreover, since the source follower operation is rarely performed, the output voltage is rarely reduced.

Note that a CMOS switch may be used as a switch by using both an N-channel transistor and a P-channel transistor. When a CMOS switch is used, a current flows when one of the P-channel transistor and the N-channel transistor is turned on, so that the switch can easily function as a switch. For example, the voltage can be appropriately output regardless of whether the voltage of the input signal to the switch is high or low. Furthermore, since the voltage amplitude value of the signal for turning on / off the switch can be reduced, the power consumption can be reduced.

Note that when a transistor is used as a switch, the switch has an input terminal (one of a source terminal or a drain terminal), an output terminal (the other of the source terminal or the drain terminal), and a terminal for controlling conduction (a gate terminal). is doing. On the other hand, when a diode is used as the switch, the switch may not have a terminal for controlling conduction. Therefore, the use of a diode as a switch rather than a transistor can reduce the wiring for controlling the terminal.

In this specification, when A and B are explicitly described as being connected, A and B are electrically connected and A and B are functionally connected. And the case where A and B are directly connected. Here, A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, the configuration disclosed in this specification is not limited to a predetermined connection relationship, for example, the connection relationship illustrated in the drawing or text, and includes other than the connection relationship illustrated in the drawing or text.

For example, when A and B are electrically connected, an element (for example, a switch, a transistor, a capacitor, an inductor, a resistance element, a diode, or the like) that enables electrical connection between A and B is provided. 1 or more may be arranged between A and B. Alternatively, when A and B are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.), a signal conversion circuit that enables functional connection between A and B (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching circuit , Amplifier circuits (circuits that can increase signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) between A and B One or more of them may be arranged. Alternatively, when A and B are directly connected, A and B without interposing other elements or other circuits between A and B.
And may be directly connected.

Note that in the case where it is explicitly described that A and B are directly connected, when A and B are directly connected (that is, another element or other circuit between A and B). And A and B are electrically connected (that is, they are connected with another element or circuit between A and B). ).

Note that in the case where it is explicitly described that A and B are electrically connected, another element is connected between A and B (that is, between A and B). Or when A and B are functionally connected (that is, they are functionally connected with another circuit between A and B). And a case where A and B are directly connected (that is, a case where another element or another circuit is not connected between A and B). That is, when it is explicitly described that it is electrically connected, it is the same as when it is explicitly only described that it is connected.

Note that a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element can have various modes or have various elements. For example, as a display element, a display device, a light-emitting element, or a light-emitting device, an EL element (an organic EL element, an inorganic EL element, or an EL element including an organic substance and an inorganic substance), an electron-emitting element, a liquid crystal element, electronic ink, an electrophoretic element, Grating light valve (GLV), plasma display (PDP), digital micromirror device (DMD), piezoelectric ceramic display, carbon nanotube, and other displays that change contrast, brightness, reflectivity, transmittance, etc. due to electromagnetic action Media can be used. Note that an EL display is used as a display device using an EL element, and a liquid crystal device such as a field emission display (FED) or an SED type flat display (SED: Surface-conduction Electron-emitter Display) is used as a display device using an electron-emitting device. The display device used is a liquid crystal display (transmission type liquid crystal display, transflective type liquid crystal display, reflection type liquid crystal display, direct view type liquid crystal display, projection type liquid crystal display), and a display device using electronic ink or electrophoretic elements is an electronic device. There is paper.

Note that various types of transistors can be used as the transistor described in this document (the specification, the claims, the drawings, or the like). Thus, there is no limitation on the type of transistor used. For example, a thin film transistor (TFT) including a non-single-crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as semi-amorphous) silicon, or the like can be used. When using TFT, there are various advantages. For example, since manufacturing can be performed at a lower temperature than that of single crystal silicon, manufacturing cost can be reduced or a manufacturing apparatus can be increased in size. Since the manufacturing apparatus can be enlarged, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, it can be manufactured at low cost. Furthermore, since the manufacturing temperature is low, a substrate with low heat resistance can be used. Therefore, a transistor can be manufactured on a transparent substrate. Then, light transmission through the display element can be controlled using a transistor over a transparent substrate. Alternatively, since the thickness of the transistor is small, part of the film included in the transistor can transmit light. Therefore, the aperture ratio can be improved.

Note that by using a catalyst (such as nickel) when manufacturing polycrystalline silicon, it is possible to further improve crystallinity and to manufacture a transistor with favorable electrical characteristics. As a result, a gate driver circuit (scanning line driving circuit), a source driver circuit (signal line driving circuit), and a signal processing circuit (signal generation circuit, gamma correction circuit, DA conversion circuit, etc.) can be integrally formed on the substrate. .

Note that when a microcrystalline silicon is manufactured, by using a catalyst (such as nickel), crystallinity can be further improved and a transistor with favorable electrical characteristics can be manufactured. At this time, crystallinity can be improved only by applying heat treatment without using a laser. As a result, part of the gate driver circuit (scanning line driver circuit) and the source driver circuit (analog switch, etc.) can be formed integrally on the substrate. Further, when a laser is not used for crystallization, unevenness in crystallinity of silicon can be suppressed. Therefore, a beautiful image can be displayed.

However, it is possible to produce polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel).

Alternatively, a transistor can be formed using a semiconductor substrate, an SOI substrate, or the like. In that case, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used as the transistor described in this specification. Accordingly, a transistor with small variations in characteristics, size, shape, and the like, high current supply capability, and small size can be manufactured. When these transistors are used, low power consumption of the circuit or high integration of the circuit can be achieved.

Alternatively, a transistor having a compound semiconductor or an oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, or SnO, or a thin film transistor in which these compound semiconductor or oxide semiconductor is thinned can be used. I can do it. Accordingly, the manufacturing temperature can be lowered, and for example, the transistor can be manufactured at room temperature. As a result, the transistor can be formed directly on a substrate having low heat resistance, such as a plastic substrate or a film substrate. Note that these compound semiconductors or oxide semiconductors can be used not only for a channel portion of a transistor but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistance elements, pixel electrodes, and transparent electrodes. Furthermore, since these can be formed or formed simultaneously with the transistor, cost can be reduced.

Alternatively, a transistor formed using an inkjet method or a printing method can be used. By these, it can manufacture at room temperature, manufacture at a low vacuum degree, or can manufacture on a large sized board | substrate. Further, since the transistor can be manufactured without using a mask (reticle), the layout of the transistor can be easily changed. Furthermore, since it is not necessary to use a resist, the material cost is reduced and the number of processes can be reduced. Further, since a film is formed only on a necessary portion, the material is not wasted and cost can be reduced as compared with a manufacturing method in which etching is performed after film formation on the entire surface.

Alternatively, a transistor including an organic semiconductor or a carbon nanotube can be used. Thus, a transistor can be formed over a substrate that can be bent. Therefore, it can be strong against impact.

In addition, various transistors can be used.

Note that various types of substrates on which transistors are formed can be used and are not limited to specific types. As a substrate on which a transistor is formed, for example, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber (silk, cotton, hemp) ), Synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, stainless steel substrates, substrates with stainless steel foil, etc. Can be used. Alternatively, the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used as the substrate. Alternatively, a transistor may be formed over a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed over another substrate. The substrate to which the transistor is transferred is a single crystal substrate, SOI substrate, glass substrate, quartz substrate, plastic substrate, paper substrate, cellophane substrate, stone substrate, wood substrate, cloth substrate (natural fiber (silk, cotton, hemp) , Synthetic fibers (including nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, stainless steel substrates, substrates with stainless steel foil, etc. be able to. Alternatively, the skin (skin surface, dermis) or subcutaneous tissue of an animal such as a human may be used as the substrate. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, or reduce weight.

Note that the structure of the transistor can take a variety of forms. It is not limited to a specific configuration. For example, a multi-gate structure having two or more gate electrodes may be used. When the multi-gate structure is employed, the channel regions are connected in series, so that a plurality of transistors are connected in series. With the multi-gate structure, the off-state current can be reduced and the reliability can be improved by improving the withstand voltage of the transistor. Or, when operating in the saturation region, the drain-source current does not change much even when the drain-source voltage changes, and the slope of the voltage / current characteristic is flat due to the multi-gate structure. it can. By using the characteristic that the slope of the voltage / current characteristic is flat, an ideal current source circuit and an active load having a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized. Alternatively, a structure in which gate electrodes are arranged above and below the channel may be employed. With the structure in which the gate electrodes are arranged above and below the channel, the channel region increases, so that the current value can be increased or the S value can be reduced due to the easy formation of a depletion layer. When gate electrodes are provided above and below a channel, a structure in which a plurality of transistors are connected in parallel is obtained.

Alternatively, a structure in which a gate electrode is disposed over a channel region may be employed, or a structure in which a gate electrode is disposed under a channel region may be employed. Alternatively, a normal stagger structure or an inverted stagger structure may be used, the channel region may be divided into a plurality of regions, the channel regions may be connected in parallel, or the channel regions may be connected in series. Good. In addition, a source electrode or a drain electrode may overlap with the channel region (or a part thereof). With the structure in which the source electrode or the drain electrode overlaps with the channel region (or part thereof), it is possible to prevent electric charges from being accumulated in part of the channel region and unstable operation. Further, an LDD region may be provided. By providing the LDD region, the off-state current can be reduced or the reliability can be improved by improving the withstand voltage of the transistor. Alternatively, by providing the LDD region, when operating in the saturation region, even if the drain-source voltage changes, the drain-source current does not change so much, and the slope of the voltage / current characteristic is flat. can do.

Note that various types of transistors can be used in this specification, and the transistor can be formed over various substrates. Therefore, all of the circuits necessary for realizing a predetermined function may be formed on the same substrate. For example, all circuits necessary for realizing a predetermined function may be formed over a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate, or may be formed over various substrates. . Since all the circuits necessary to realize a given function are formed on the same board, the number of parts can be reduced to reduce costs, and the number of connection points with circuit parts can be reduced to improve reliability. can do. Alternatively, a part of the circuit necessary for realizing the predetermined function is formed on a certain substrate, and another part of the circuit necessary for realizing the predetermined function is formed on another substrate. It may be. That is, not all of the circuits necessary for realizing a predetermined function may be formed on the same substrate. For example, a part of a circuit necessary for realizing a predetermined function is formed using a transistor over a glass substrate, and another part of a circuit required for realizing a predetermined function is a single crystal substrate. The IC chip formed on the single crystal substrate and formed of a transistor may be connected to the glass substrate by COG (Chip On Glass), and the IC chip may be arranged on the glass substrate. Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed board. As described above, since a part of the circuit is formed on the same substrate, the number of parts can be reduced to reduce the cost, and the number of connection points with the circuit parts can be reduced to improve the reliability. In addition, since the power consumption of a circuit having a high driving voltage or a high driving frequency is large, such a circuit is not formed on the same substrate. Instead, for example, on a single crystal substrate. If the circuit of that portion is formed and an IC chip constituted by the circuit is used, an increase in power consumption can be prevented.

Note that in this specification, one pixel represents one element whose brightness can be controlled. Therefore, as an example, one pixel represents one color element, and brightness is expressed by one color element. Therefore, at that time, in the case of a color display device composed of R (red), G (green), and B (blue) color elements, the minimum unit of an image is an R pixel, a G pixel, and a B pixel. It is assumed to be composed of three pixels. Note that the color elements are not limited to three colors, and three or more colors may be used, or colors other than RGB may be used. For example, RGBW (W is white) may be added by adding white. Further, one or more colors such as yellow, cyan, magenta, emerald green, vermilion, and the like may be added to RGB. Further, for example, a color similar to at least one of RGB may be added to RGB. For example, R, G, B1, and B2 may be used. B1 and B2 are both blue, but have slightly different frequencies. Similarly, R1, R2, G, and B may be used. By using such color elements, it is possible to perform display closer to the real thing or to reduce power consumption. As another example, when brightness is controlled using a plurality of areas for one color element, one area may be used as one pixel. Therefore, as an example, when area gradation is performed or when sub-pixels (sub-pixels) are provided, there are a plurality of brightness control areas for one color element, and the gradation is expressed as a whole. However, one pixel for controlling the brightness may be one pixel. Therefore, in that case, one color element is composed of a plurality of pixels. Alternatively, even if there are a plurality of areas for controlling the brightness in one color element, they may be combined into one pixel. Therefore, in that case, one color element is composed of one pixel. When brightness is controlled using a plurality of areas for one color element, the size of the area contributing to display may be different depending on the pixel. In addition, in a plurality of brightness control areas for one color element, a signal supplied to each may be slightly different to widen the viewing angle. That is, for one color element, the potentials of the pixel electrodes in each of a plurality of regions may be different from each other. As a result, the voltage applied to the liquid crystal molecules is different for each pixel electrode. Therefore, the viewing angle can be widened.

In addition, when it is explicitly described as one pixel (for three colors), it is assumed that three pixels of R, G, and B are considered as one pixel. When it is explicitly described as one pixel (for one color), it is assumed that when there are a plurality of areas for one color element, they are considered as one pixel.

Note that in this document (the specification, the claims, the drawings, or the like), the pixels may be arranged (arranged) in a matrix. Here, the pixel being arranged (arranged) in the matrix includes a case where the pixels are arranged in a straight line or a jagged line in the vertical direction or the horizontal direction. Therefore, for example, when full color display is performed with three color elements (for example, RGB), the case where stripes are arranged and the case where dots of three color elements are arranged in delta are included. Furthermore, the case where a Bayer is arranged is included. Note that the color elements are not limited to three colors, and may be more than that, for example, RGBW (W is white) or RGB in which one or more colors of yellow, cyan, magenta, etc. are added. Further, the size of the display area may be different for each dot of the color element. Thereby, it is possible to reduce power consumption or extend the life of the display element.

Note that in this document (the specification, the claims, the drawings, or the like), an active matrix method in which an active element is included in a pixel or a passive matrix method in which an active element is not included in a pixel can be used.

In the active matrix system, not only transistors but also various active elements (active elements and nonlinear elements) can be used as active elements (active elements and nonlinear elements). For example, MIM (Metal Insulator Metal) or TFD (Thin Film Diode) can be used. Since these elements have few manufacturing steps, manufacturing cost can be reduced or yield can be improved. Furthermore, since the size of the element is small, the aperture ratio can be improved, and low power consumption and high luminance can be achieved.

Note that as a method other than the active matrix method, a passive matrix type that does not use active elements (active elements, nonlinear elements) can be used. Since no active element (active element or nonlinear element) is used, the number of manufacturing steps is small, and manufacturing cost can be reduced or yield can be improved. In addition, since an active element (an active element or a non-linear element) is not used, the aperture ratio can be improved, and low power consumption and high luminance can be achieved.

Note that a transistor is an element having at least three terminals including a gate, a drain, and a source. The transistor has a channel region between the drain region and the source region, and the drain region, the channel region, and the source region. A current can be passed through. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, in this specification, a region functioning as a source and a drain may not be referred to as a source or a drain. In that case, as an example, there are cases where they are referred to as a first terminal and a second terminal, respectively. Alternatively, they may be referred to as a first electrode and a second electrode, respectively. Alternatively, they may be referred to as a source region and a drain region.

Note that the transistor may be an element having at least three terminals including a base, an emitter, and a collector. Similarly in this case, the emitter and the collector may be referred to as a first terminal and a second terminal.

Note that a gate refers to the whole or part of a gate electrode and a gate wiring (also referred to as a gate line, a gate signal line, a scan line, a scan signal line, or the like). A gate electrode refers to a portion of a conductive film that overlaps with a semiconductor forming a channel region with a gate insulating film interposed therebetween. Note that a part of the gate electrode may overlap an LDD (Lightly Doped Drain) region or a source region and a drain region with a gate insulating film interposed therebetween. A gate wiring is a wiring for connecting the gate electrodes of each transistor, a wiring for connecting the gate electrodes of each pixel, or a wiring for connecting the gate electrode to another wiring. Say.

However, there are portions (regions, conductive films, wirings, etc.) that also function as gate electrodes and function as gate wirings. Such a portion (region, conductive film, wiring, or the like) may be called a gate electrode or a gate wiring. That is, there is a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when a part of the gate wiring extended and the channel region overlap, the portion (region, conductive film, wiring, etc.) functions as the gate wiring, but also as the gate electrode It is functioning. Therefore, such a portion (region, conductive film, wiring, or the like) may be called a gate electrode or a gate wiring.

Note that a portion (a region, a conductive film, a wiring, or the like) formed using the same material as the gate electrode and connected to form the same island (island) as the gate electrode may be called a gate electrode. Similarly, a portion (a region, a conductive film, a wiring, or the like) formed using the same material as the gate wiring and connected by forming the same island (island) as the gate wiring may be referred to as a gate wiring. In a strict sense, such a portion (region, conductive film, wiring, or the like) may not overlap with the channel region or may not have a function of being connected to another gate electrode. However, due to conditions in the manufacturing process, etc., a portion (region, conductive film, wiring, etc.) that is formed of the same material as the gate electrode or gate wiring and forms the same island (island) as the gate electrode or gate wiring. ) Therefore, such a portion (region, conductive film, wiring, or the like) may also be referred to as a gate electrode or a gate wiring.

Note that, for example, in a multi-gate transistor, one gate electrode and another gate electrode are often connected to each other with a conductive film formed using the same material as the gate electrode. Such a portion (region, conductive film, wiring, or the like) is a portion (region, conductive film, wiring, or the like) for connecting the gate electrode to the gate electrode, and may be called a gate wiring. These transistors can be regarded as a single transistor, and may be referred to as a gate electrode. That is, a portion (region, conductive film, wiring, or the like) that is formed using the same material as the gate electrode or gate wiring and is connected to form the same island (island) as the gate electrode or gate wiring is connected to the gate electrode or gate wiring. You can call it. Further, for example, a conductive film in a portion where the gate electrode and the gate wiring are connected and formed of a material different from the gate electrode or the gate wiring may be referred to as a gate electrode. You may call it.

Note that a gate terminal means a part of a part of a gate electrode (a region, a conductive film, a wiring, or the like) or a part electrically connected to the gate electrode (a region, a conductive film, a wiring, or the like). .

Note that in the case of calling a gate wiring, a gate line, a gate signal line, a scanning line, a scanning signal line, or the like, the gate of the transistor may not be connected to the wiring. In this case, the gate wiring, the gate line, the gate signal line, the scanning line, and the scanning signal line are formed at the same time as the wiring formed in the same layer as the gate of the transistor, the wiring formed of the same material as the gate of the transistor, or the gate of the transistor. It may mean a deposited wiring. Examples include a storage capacitor wiring, a power supply line, a reference potential supply wiring, and the like.

Note that a source refers to the whole or part of a source region, a source electrode, and a source wiring (also referred to as a source line, a source signal line, a data line, a data signal line, or the like). The source region refers to a semiconductor region containing a large amount of P-type impurities (such as boron and gallium) and N-type impurities (such as phosphorus and arsenic). Therefore, a region containing a little P-type impurity or N-type impurity, that is, a so-called LDD (Lightly Doped Drain) region is not included in the source region. A source electrode refers to a portion of a conductive layer which is formed using a material different from that of a source region and is electrically connected to the source region. However, the source electrode may be referred to as a source electrode including the source region. The source wiring is a wiring for connecting the source electrodes of the transistors, a wiring for connecting the source electrodes of each pixel, or a wiring for connecting the source electrode to another wiring. Say.

However, there are portions (regions, conductive films, wirings, and the like) that also function as source electrodes and function as source wirings. Such a portion (region, conductive film, wiring, or the like) may be called a source electrode or a source wiring. That is, there is a region where the source electrode and the source wiring cannot be clearly distinguished. For example, in the case where a part of a source wiring that is extended and the source region overlap with each other, the portion (region, conductive film, wiring, etc.) functions as a source wiring, but as a source electrode Will also work. Thus, such a portion (region, conductive film, wiring, or the like) may be called a source electrode or a source wiring.

Note that a portion (region, conductive film, wiring, or the like) that is formed using the same material as the source electrode and forms the same island (island) as the source electrode, or a portion (region) that connects the source electrode and the source electrode , Conductive film, wiring, etc.) may also be referred to as source electrodes. Further, a portion overlapping with the source region may be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected by forming the same island as the source wiring may be called a source wiring. Such a portion (region, conductive film, wiring, or the like) may not have a function of connecting to another source electrode in a strict sense. However, there is a portion (a region, a conductive film, a wiring, or the like) that is formed using the same material as the source electrode or the source wiring and connected to the source electrode or the source wiring because of conditions such as manufacturing conditions. Therefore, such a portion (region, conductive film, wiring, or the like) may also be referred to as a source electrode or a source wiring.

Note that, for example, a conductive film in a portion where the source electrode and the source wiring are connected and formed using a material different from that of the source electrode or the source wiring may be referred to as a source electrode or a source wiring. You may call it.

Note that a source terminal refers to a part of a source region, a source electrode, or a portion (region, conductive film, wiring, or the like) electrically connected to the source electrode.

Note that in the case of calling a source wiring, a source line, a source signal line, a data line, a data signal line, or the like, the source (drain) of the transistor may not be connected to the wiring. In this case, the source wiring, the source line, the source signal line, the data line, and the data signal line are the wiring formed in the same layer as the source (drain) of the transistor and the wiring formed of the same material as the source (drain) of the transistor. Alternatively, it may mean a wiring formed simultaneously with the source (drain) of the transistor. Examples include a storage capacitor wiring, a power supply line, a reference potential supply wiring, and the like.

The drain is the same as the source.

Note that a semiconductor device refers to a device having a circuit including a semiconductor element (a transistor, a diode, a thyristor, or the like). Furthermore, a device that can function by utilizing semiconductor characteristics may be called a semiconductor device.

Note that a display element means an optical modulation element, a liquid crystal element, a light emitting element, an EL element (an organic EL element, an inorganic EL element or an EL element containing an organic substance and an inorganic substance), an electron-emitting element, an electrophoretic element, a discharge element, and a light reflection element. An element, a light diffraction element, a digital micromirror device (DMD), etc. are said. However, it is not limited to this.

Note that a display device refers to a device having a display element. Note that the display device may be a display panel body in which a plurality of pixels including display elements or a peripheral drive circuit for driving the pixels is formed over the same substrate. Note that the display device includes a peripheral drive circuit arranged on the substrate by wire bonding or bumps, an IC chip connected by so-called chip on glass (COG), or an IC chip connected by TAB or the like. May be. Note that the display device may include a flexible printed circuit (FPC) to which an IC chip, a resistor element, a capacitor element, an inductor, a transistor, and the like are attached. Note that the display device may include a printed wiring board (PWB) connected via a flexible printed circuit (FPC) or the like to which an IC chip, a resistor element, a capacitor element, an inductor, a transistor, or the like is attached. Note that the display device may include an optical sheet such as a polarizing plate or a retardation plate. Note that the display device may include a lighting device, a housing, a voice input / output device, an optical sensor, and the like. Here, the illumination device such as the backlight unit may include a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water cooling type, air cooling type) and the like. good.

Note that the lighting device refers to a device including a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflective sheet, a light source (such as an LED, a cold cathode tube, a hot cathode tube), a cooling device, and the like.

Note that a light-emitting device refers to a device having a light-emitting element or the like.

In addition, a reflection apparatus means the apparatus which has a light reflection element, a light diffraction element, a light reflection electrode, etc.

Note that a liquid crystal display device refers to a display device having a liquid crystal element. Liquid crystal display devices include direct view type, projection type, transmission type, reflection type, and transflective type.

Note that a driving device refers to a device having a semiconductor element, an electric circuit, and an electronic circuit. For example, a transistor that controls input of a signal from a source signal line into a pixel (sometimes referred to as a selection transistor or a switching transistor), a transistor that supplies voltage or current to a pixel electrode, or a voltage or current to a light-emitting element A transistor that supplies the voltage is an example of a driving device. Further, a circuit for supplying a signal to the gate signal line (sometimes referred to as a gate driver or a gate line driver circuit) and a circuit for supplying a signal to the source signal line (sometimes referred to as a source driver or source line driver circuit). ) Is an example of a driving device.

Note that a display device, a semiconductor device, a lighting device, a cooling device, a light-emitting device, a reflecting device, a driving device, and the like may overlap with each other. For example, the display device may include a semiconductor device and a light-emitting device. Alternatively, the semiconductor device may include a display device and a driving device.

In addition, in this document (specifications, claims or drawings, etc.), if it is explicitly stated that B is formed on A or B is formed on A, It is not limited that B is formed in direct contact with A. The case where it is not in direct contact, that is, the case where another object is interposed between A and B is also included. Here, A and B are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

Therefore, for example, when it is explicitly described that the layer B is formed on the layer A (or on the layer A), the layer B is formed in direct contact with the layer A. And the case where another layer (for example, layer C or layer D) is formed in direct contact with the layer A, and the layer B is formed in direct contact therewith. Note that another layer (for example, the layer C or the layer D) may be a single layer or a multilayer.

Furthermore, the same applies to the case where B is explicitly described as being formed above A, and is not limited to the direct contact of B on A. This includes the case where another object is interposed in. Therefore, for example, when the layer B is formed above the layer A, the case where the layer B is formed in direct contact with the layer A and the case where another layer is formed in direct contact with the layer A. (For example, the layer C or the layer D) is formed, and the layer B is formed in direct contact therewith. Note that another layer (for example, the layer C or the layer D) may be a single layer or a multilayer.

In addition, when it is explicitly described that B is formed in direct contact with A, it includes a case in which B is formed in direct contact with A. It shall not be included when an object is present.

The same applies to the case where B is below A or B is below A.

According to this specification, deterioration of characteristics of all transistors included in the shift register can be suppressed. Therefore, malfunction of a semiconductor device to which the shift register such as a liquid crystal display device is applied can be suppressed.

3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 2 is a timing chart illustrating the operation of the flip-flop illustrated in FIG. 1. 3A and 3B illustrate operation of the flip-flop illustrated in FIG. 1. 3A and 3B illustrate operation of the flip-flop illustrated in FIG. 1. 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3 is a timing chart illustrating operation of the flip-flop described in Embodiment 1; 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3A and 3B illustrate a structure of a flip-flop described in Embodiment 1. 3A and 3B illustrate a structure of a shift register described in Embodiment 1. 12 is a timing chart illustrating operation of the shift register illustrated in FIG. 11. 12 is a timing chart illustrating operation of the shift register illustrated in FIG. 11. 3A and 3B illustrate a structure of a shift register described in Embodiment 1. FIG. 15 is a diagram illustrating the configuration of the buffer illustrated in FIG. 14. FIG. 15 is a diagram illustrating the configuration of the buffer illustrated in FIG. 14. 3A and 3B illustrate a structure of a display device described in Embodiment 1. 18 is a timing chart illustrating a writing operation of the display device illustrated in FIG. 3A and 3B illustrate a structure of a display device described in Embodiment 1. 3A and 3B illustrate a structure of a display device described in Embodiment 1. FIG. 21 is a timing chart illustrating a writing operation of the display device illustrated in FIG. 20. 6 is a timing chart illustrating operation of the flip-flop described in Embodiment 2. 6 is a timing chart illustrating operation of the flip-flop described in Embodiment 2. FIG. 5 illustrates a structure of a shift register shown in Embodiment 2; 25 is a timing chart illustrating operation of the shift register illustrated in FIG. 25 is a timing chart illustrating operation of the shift register illustrated in FIG. 3A and 3B illustrate a structure of a display device described in Embodiment 2. 3A and 3B illustrate a structure of a display device described in Embodiment 2. FIG. 8 is a top view of the flip-flop in FIG. The figure which shows the structure of the conventional flip-flop. 7A and 7B illustrate a structure of a signal line driver circuit described in Embodiment 5. FIG. 32 is a timing chart illustrating operation of the signal line driver circuit illustrated in FIG. 31. FIG. 7A and 7B illustrate a structure of a signal line driver circuit described in Embodiment 5. 34 is a timing chart illustrating operation of the signal line driver circuit illustrated in FIG. 7A and 7B illustrate a structure of a signal line driver circuit described in Embodiment 5. 7A and 7B illustrate a structure of a protection diode described in Embodiment 6. 7A and 7B illustrate a structure of a protection diode described in Embodiment 6. 7A and 7B illustrate a structure of a protection diode described in Embodiment 6. 8A and 8B illustrate a structure of a display device described in Embodiment 7. FIG. 5 illustrates a structure of a flip-flop shown in Embodiment 3; 41 is a timing chart illustrating operation of the flip-flop illustrated in FIG. FIG. 5 illustrates a structure of a shift register shown in Embodiment 3; 43 is a timing chart illustrating operation of the shift register illustrated in FIG. FIG. 5 illustrates a structure of a flip-flop shown in Embodiment 4; 45 is a timing chart illustrating operation of the flip-flop illustrated in FIG. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. FIG. 6 is a top view of a display element of a semiconductor device according to the present invention. FIG. 6 is a top view of a display element of a semiconductor device according to the present invention. FIG. 6 is a top view of a display element of a semiconductor device according to the present invention. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device according to the present invention. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device according to the present invention. 4A and 4B illustrate a panel circuit configuration of a semiconductor device according to the invention. 4A and 4B illustrate a panel circuit configuration of a semiconductor device according to the invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. 8A and 8B illustrate a peripheral component member of a semiconductor device according to the present invention. FIG. 6 illustrates a peripheral circuit configuration of a semiconductor device according to the present invention. 8A and 8B illustrate a peripheral component member of a semiconductor device according to the present invention. 8A and 8B illustrate a peripheral component member of a semiconductor device according to the present invention. 8A and 8B illustrate a peripheral component member of a semiconductor device according to the present invention. 6A and 6B illustrate a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. 4A and 4B are a pixel layout example and a cross-sectional view of a semiconductor device according to the invention. Sectional drawing of the display element of the semiconductor device which concerns on this invention. 8A and 8B illustrate a device for forming a display element of a semiconductor device according to the present invention. 8A and 8B illustrate a device for forming a display element of a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 8A and 8B illustrate one method for driving a semiconductor device according to the present invention. 6A and 6B illustrate one pixel circuit of a semiconductor device according to the present invention. 6A and 6B illustrate one pixel circuit of a semiconductor device according to the present invention. 8A and 8B illustrate a process for manufacturing a semiconductor device according to the present invention. 8A and 8B illustrate a display element of a semiconductor device according to the present invention. 8A and 8B illustrate a display element of a semiconductor device according to the present invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 6A and 6B illustrate a structure of a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention. 4A and 4B each illustrate an electronic device including a semiconductor device according to the invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

(Embodiment 1)
In this embodiment, a structure and a driving method of a flip-flop, a driver circuit including the flip-flop, and a display device including the driver circuit are described.

A basic structure of the flip-flop of this embodiment is described with reference to FIG. The flip-flop illustrated in FIG. 1A includes a first transistor 101, a second transistor 102, a third transistor 103, a fourth transistor 104, a fifth transistor 105, a sixth transistor 106, and a seventh transistor. A transistor 107 and an eighth transistor 108 are included. In this embodiment, the first transistor 101 to the eighth transistor 108 are N-channel transistors and are turned on when a gate-source voltage (Vgs) exceeds a threshold voltage (Vth). And

Note that the flip-flop of this embodiment is characterized in that the first transistor 101 to the eighth transistor 108 are all N-channel transistors. Therefore, in the flip-flop of this embodiment, amorphous silicon can be used as a semiconductor layer of a transistor, so that a manufacturing process can be simplified, and manufacturing cost can be reduced and yield can be improved. . However, the manufacturing process can be simplified even if polysilicon or polycrystalline silicon is used for the semiconductor layer of the transistor.

A connection relation of the flip-flop of FIG. The first electrode (one of the source electrode and the drain electrode) of the first transistor 101 is connected to the fifth wiring 125, and the second electrode (the other of the source electrode and the drain electrode) of the first transistor 101 is the first electrode. 3 wiring 123. The first electrode of the second transistor 102 is connected to the fourth wiring 124, the second electrode of the second transistor 102 is connected to the third wiring 123, and the gate electrode of the second transistor 102 is the eighth wiring. The wiring 128 is connected. The first electrode of the third transistor 103 is connected to the sixth wiring 126, the second electrode of the third transistor 103 is connected to the gate electrode of the sixth transistor 106, and the gate of the third transistor 103 The electrode is connected to the seventh wiring 127. The first electrode of the fourth transistor 104 is connected to the tenth wiring 130, the second electrode of the fourth transistor 104 is connected to the gate electrode of the sixth transistor 106, and the gate of the fourth transistor 104 The electrode is connected to the eighth wiring 128. The first electrode of the fifth transistor 105 is connected to the ninth wiring 129, the second electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101, and the gate of the fifth transistor 105 The electrode is connected to the first wiring 121. The first electrode of the sixth transistor 106 is connected to the twelfth wiring 132, and the second electrode of the sixth transistor 106 is connected to the gate electrode of the first transistor 101. The first electrode of the seventh transistor 107 is connected to the thirteenth wiring 133, the second electrode of the seventh transistor 107 is connected to the gate electrode of the first transistor 101, and the gate of the seventh transistor 107 The electrode is connected to the second wiring 122. The first electrode of the eighth transistor 108 is connected to the eleventh wiring 131, the second electrode of the eighth transistor 108 is connected to the gate electrode of the sixth transistor 106, and the gate of the eighth transistor 108 The electrode is connected to the gate electrode of the first transistor 101.

Note that a connection position of the gate electrode of the first transistor 101, the second electrode of the sixth transistor 106, the second electrode of the seventh transistor 107, and the gate electrode of the eighth transistor 108 is a node 141. Further, a connection portion of the second electrode of the third transistor 103, the second electrode of the fourth transistor 104, the gate electrode of the sixth transistor 106, and the second electrode of the eighth transistor 108 is connected to the node 142. To do.

Note that the first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, the seventh wiring 127, and the eighth wiring 128 are respectively connected to the first signal line and the second signal 128. May be called a line, a third signal line, a fourth signal line, a fifth signal line, or a sixth signal line. Further, the fourth wiring 124, the sixth wiring 126, the ninth wiring 129, the tenth wiring 130, the eleventh wiring 131, the twelfth wiring 132, and the thirteenth wiring 133 are respectively connected to the first power supply. May be referred to as a line, a second power line, a third power line, a fourth power line, a fifth power line, a sixth power line, and a seventh power line.

Next, operation of the flip-flop illustrated in FIG. 1A is described with reference to a timing chart of FIG. 2 and FIGS. 3 and 4. Further, the timing chart of FIG. 2 will be described by being divided into a set period, a selection period, a reset period, a first non-selection period, and a second non-selection period. However, the set period, the reset period, the first non-selection period, and the second non-selection period may be collectively referred to as a non-selection period.

Note that the potential of V1 is supplied to the sixth wiring 126 and the ninth wiring 129, and the fourth wiring 124, the tenth wiring 130, the eleventh wiring 131, the twelfth wiring 132, and the thirteenth wiring. 133 is supplied with the potential of V2. Here, V1> V2.

Note that the first wiring 121, the fifth wiring 125, the eighth wiring 128, the seventh wiring 127, and the second wiring 122 are respectively provided with a signal 221, a signal 225, a signal 228, and a signal 227 shown in FIG. , A signal 222 is input. A signal 223 shown in FIG. 2 is output from the third wiring 123. Here, in the signal 221, the signal 225, the signal 228, the signal 227, the signal 222, and the signal 223, the potential of the H signal is V1 (hereinafter also referred to as H level) and the potential of the L signal is V2 (hereinafter also referred to as L level). ) Digital signal. Further, the signal 221, the signal 225, the signal 228, the signal 227, the signal 222, and the signal 223 are respectively converted into a start signal, a power clock signal (PCK), a first control clock signal (CCK1), and a second control clock signal (CCK2). ), May be called a reset signal or an output signal.

Note that various signals, potentials, and currents may be input to the first wiring 121, the second wiring 122, and the fourth wiring 124 to the thirteenth wiring 133, respectively.

First, in the set period shown in FIGS. 2A and 3A, the signal 221 becomes H level, the fifth transistor 105 is turned on, and the signal 222 is L level, so that the seventh transistor 107 is turned off. 228 becomes H level, the second transistor 102 and the fourth transistor 104 are turned on, the signal 227 becomes L level, and the third transistor 103 is turned off. At this time, the potential of the node 141 (the potential 241) is obtained by subtracting the threshold voltage of the fifth transistor 105 from the potential of the ninth wiring 129 with the second electrode of the fifth transistor 105 serving as a source electrode. Therefore, V1−Vth105 (Vth105: threshold voltage of the fifth transistor 105). Accordingly, the first transistor 101 and the eighth transistor 108 are turned on, and the fifth transistor 105 is turned off. At this time, the potential of the node 142 (the potential 242) is V2, and the sixth transistor 106 is turned off. In this manner, in the set period, the third wiring 123 is electrically connected to the fifth wiring 125 to which the L signal is input and the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 is V2. It becomes. Therefore, the L signal is output from the third wiring 123. Further, the node 141 is in a floating state with the potential maintained at V1−Vth105.

Note that in the flip-flop of this embodiment, as shown in FIG. 5A, even when the first electrode of the fifth transistor 105 is connected to the first wiring 121, the flip-flop is similar to the set period described above. Operation can be performed. In the flip-flop in FIG. 5A, the ninth wiring 129 is unnecessary, so that the yield can be improved. Further, the flip-flop in FIG. 5A can reduce the layout area.

Note that in the flip-flop of this embodiment, a transistor 501 may be newly provided as illustrated in FIG. The transistor 501 has a first electrode connected to the wiring 511 to which V 2 is supplied, a second electrode connected to the node 141, and a gate electrode connected to the first wiring 121. In the flip-flop in FIG. 5C, the time during which the potential of the node 142 is decreased by the transistor 501 can be shortened, so that the sixth transistor 106 can be quickly turned off. Therefore, the flip-flop in FIG. 5C can shorten the time until the potential of the node 141 becomes V1-Vth105, and thus can operate at high speed and is applied to a larger display device or a higher definition display device. it can.

In the selection period shown in FIGS. 2B and 3B, the signal 221 becomes L level, the fifth transistor 105 is turned off, and the signal 222 remains L level, so that the seventh transistor 107 remains off. The signal 228 becomes L level, the second transistor 102 and the fourth transistor 104 are turned off, the signal 227 becomes H level, and the third transistor 103 is turned on. At this time, the node 141 maintains the potential at V1−Vth105. Therefore, the first transistor 101 and the eighth transistor 108 are kept on. At this time, the potential of the node 142 is such that the potential difference (V1−V2) between the potential (V2) of the eleventh wiring 131 and the potential (V1) of the sixth wiring 126 is the third transistor 103 and the eighth transistor 108. Is divided into V2 + β (β: an arbitrary positive number). Further, β <Vth106 (the threshold voltage of the sixth transistor 106). Accordingly, the sixth transistor 106 remains off. Here, since the H signal is input to the fifth wiring 125, the potential of the third wiring 123 starts to increase. Then, the potential of the node 141 rises from V1−Vth105 by the bootstrap operation, and becomes V1 + Vth101 + α (Vth101: threshold voltage of the first transistor 101, α: any positive number). Therefore, the potential of the third wiring 123 is equal to that of the fifth wiring 125 and thus becomes V1. In this manner, in the selection period, the third wiring 123 is electrically connected to the fifth wiring 125 to which the H signal is input, so that the potential of the third wiring 123 is V1. Therefore, the H signal is output from the third wiring 123.

Note that this bootstrap operation is performed by capacitive coupling of parasitic capacitance between the gate electrode and the second electrode of the first transistor 101. However, as shown in FIG. 1B, by disposing the capacitor 151 between the gate electrode and the second electrode of the first transistor 101, a bootstrap operation can be stably performed. The parasitic capacitance of the first transistor 101 can be reduced. Here, the capacitor 151 may use a gate insulating film as an insulating layer and a gate electrode layer and a wiring layer as a conductive layer, or use a gate insulating film as an insulating layer and a gate electrode layer and an impurity as a conductive layer. May be used, or an interlayer film (insulating film) may be used as an insulating layer, and a wiring layer and a transparent electrode layer may be used as a conductive layer. However, in the capacitor 151, when a gate electrode layer and a wiring layer are used as the conductive film, the gate electrode layer is connected to the gate electrode of the first transistor 101, and the wiring layer is connected to the second electrode of the first transistor 101. It is good to connect. More preferably, when a gate electrode layer and a wiring layer are used as the conductive film, the gate electrode layer is directly connected to the gate electrode of the first transistor 101, and the wiring layer is directly connected to the second electrode of the first transistor 101. Good. This is because the increase in the layout area of the flip-flop due to the arrangement of the capacitor 151 is reduced.

Further, a transistor 152 may be used as the capacitor 151 as illustrated in FIG. The transistor 152 can function as a capacitor having a large capacitance component by connecting the gate electrode to the node 141 and connecting the first electrode and the second electrode to the third wiring 123. Note that the transistor 152 can function as a capacitor even when one of the first electrode and the second electrode is floating.

Note that the first transistor 101 must supply an H signal to the third wiring 123. Therefore, in order to shorten the fall time and the rise time of the signal 223, the W / L value of the first transistor 101 is set to the W / L value of each of the first transistor 101 to the eighth transistor 108. It is desirable to maximize it.

Further, in the fifth transistor 105, the potential of the node 142 (the gate electrode of the first transistor 101) must be V1−Vth105 in the set period. Therefore, the value of W / L of the fifth transistor 105 is The W / L value of the first transistor 101 is ½ times to ５ times, more preferably １ ／ times to ¼ times.

Note that in order to set the potential of the node 142 to V2 + β, the ratio W / L of the channel width W to the channel length L of the eighth transistor 108 is larger than the value of W / L of the third transistor 103. It is preferable to make it at least 10 times or more. Therefore, the transistor size (W × L) of the eighth transistor 108 is increased. Here, the value of the channel length L of the third transistor 103 is larger than the value of the channel length L of the eighth transistor 108, more preferably 2 to 3 times, so that the transistor of the eighth transistor 108 Since the size can be reduced, the layout area can be reduced.

In the reset period illustrated in FIGS. 2C and 3C, since the signal 221 remains at the L level, the fifth transistor 105 remains off, the signal 222 becomes the H level, and the seventh transistor 107 is turned on. Then, the signal 228 becomes H level, the second transistor 102 and the fourth transistor 104 are turned on, the signal 227 becomes L level, and the third transistor 103 is turned off. The potential of the node 141 at this time is V 2 because the potential (V 2) of the thirteenth wiring 133 is supplied through the seventh transistor 107. Accordingly, the first transistor 101 and the eighth transistor 108 are turned off. The potential of the node 142 at this time is V2 because the fourth transistor 104 is turned on. Accordingly, the sixth transistor 106 is turned off. Thus, in the reset period, the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 becomes V2. Therefore, the L signal is output from the third wiring 123.

Note that the fall time of the signal 223 can be shortened by delaying the timing at which the seventh transistor 107 is turned on. This is because the L signal input to the fifth wiring 125 can be supplied to the third wiring 123 through the first transistor 101 having a large W / L value.

Alternatively, even if the W / L value of the seventh transistor 107 is reduced and the fall time until the potential of the node 141 becomes V2 is increased, the fall time of the signal 223 can be shortened. In this case, the value of the seventh transistor W / L is set to 1/10 to 1/40 times, more preferably 1/20 to 1/30 times the value of W / L of the first transistor 101.

Note that as shown in FIG. 5B, the operation similar to that in the set period described above can be performed without the seventh transistor 107. In the flip-flop in FIG. 5B, the number of transistors and wirings can be reduced, so that the layout area can be reduced.

In the first non-selection period shown in FIGS. 2D and 4D, since the signal 221 remains at the L level, the fifth transistor 105 remains off, and the signal 222 becomes the L level. The transistor 107 is turned off, the signal 228 becomes L level, the second transistor 102 and the fourth transistor 104 are turned off, the signal 227 becomes H level, and the third transistor 103 is turned on. The potential of the node 142 at this time is obtained by subtracting the threshold voltage of the third transistor 103 from the potential (V1) of the seventh wiring 127 with the second electrode of the third transistor 103 serving as a source electrode. Therefore, V1−Vth103 (Vth103: threshold voltage of the third transistor 103). Accordingly, the sixth transistor 106 is turned on. At this time, the potential of the node 141 is V2 because the sixth transistor 106 is turned on. Accordingly, the first transistor 101 and the eighth transistor 108 remain off. Thus, in the first non-selection period, the third wiring 123 is in a floating state and maintains the potential at V2.

Note that the flip-flop of this embodiment can suppress a shift in threshold voltage of the second transistor 102 by turning off the second transistor 102.

Note that the threshold voltage shift of the third transistor 103 can be suppressed by setting the potential of the signal 227 to be equal to or lower than V1 and decreasing the potential of the gate electrode of the third transistor 103. Further, the threshold voltage of the fourth transistor 104 and the second transistor 102 is shifted by applying a reverse bias to the fourth transistor 104 and the second transistor 102 by setting the potential of the signal 228 to V2 or less. Can be suppressed.

Note that as illustrated in FIG. 9A, V2 can be supplied to the third wiring 123 by newly arranging the transistor 901. Since the transistor 901 has a first electrode connected to the fourth wiring 124, a second electrode of the transistor 901 connected to the third wiring 123, and a gate electrode connected to the node 142, the sixth transistor On / off is controlled at the same timing as 106. Therefore, the flip-flop in FIG. 9A can be resistant to noise because the third wiring 123 does not enter a floating state. Further, as illustrated in FIG. 9B, a transistor 901 can be provided instead of the second transistor 102.

In the second non-selection period shown in FIGS. 2E and 4E, since the signal 221 remains at the L level, the fifth transistor 105 remains off and the signal 222 remains at the L level. 7 transistor 107 remains off, the signal 228 becomes H level, the second transistor 102 and the fourth transistor 104 are turned on, the signal 227 becomes L level, and the third transistor 103 is turned off. At this time, the potential of the node 142 is V2 because the fourth transistor 104 is turned on. Accordingly, the sixth transistor 106 is turned off. Since the node 141 at this time is in a floating state, the potential is maintained at V2. Accordingly, the first transistor 101 and the eighth transistor 108 remain off. In this manner, in the second non-selection period, the third wiring 123 is electrically connected to the fourth wiring 124 to which V2 is supplied, so that the potential of the third wiring 123 becomes V2. Therefore, the L signal is output from the third wiring 123.

Note that the flip-flop in this embodiment can suppress a shift in threshold voltage of the sixth transistor 106 by turning off the sixth transistor 106.

Note that the flip-flop of this embodiment can set the potential of the third wiring 123 to V2 even if the potential of the third wiring 123 fluctuates due to noise in the second non-selection period. Further, in the flip-flop of this embodiment, even when the potential of the node 141 varies due to noise, the potential of the node 141 can be set to V2 in the first non-selection period.

Note that the threshold voltage shift of the third transistor 103 can be suppressed by setting the potential of the signal 227 to V2 or less and applying a reverse bias to the third transistor 103. Further, the threshold value of the fourth transistor 104 and the second transistor 102 is reduced by setting the potential of the signal 228 to V1 or less and lowering the potential of the gate electrode of the fourth transistor 104 and the electrode of the second transistor 102. Voltage shift can be suppressed.

From the above, the flip-flop of this embodiment can suppress a threshold shift of the second transistor 102 and the sixth transistor 106, and thus can have a long lifetime. Further, the flip-flop of this embodiment can suppress a shift in threshold voltage of all transistors, so that the lifetime can be extended. Further, since the flip-flop of this embodiment is resistant to noise, reliability can be improved.

Here, functions of the first transistor 101 to the eighth transistor 108 are described. The first transistor 101 has a function of selecting the timing at which the potential of the fifth wiring 125 is supplied to the third wiring 123 and increasing the potential of the node 141 by a bootstrap operation, and functions as a bootstrap transistor. To do. The second transistor 102 has a function of selecting timing for supplying the potential of the fourth wiring 124 to the third wiring 123 and functions as a switching transistor. The third transistor 103 has a function of selecting timing for supplying the potential of the sixth wiring 126 to the node 142 and functions as a switching transistor. The fourth transistor 104 has a function of selecting timing for supplying the potential of the tenth wiring 130 to the node 124 and functions as a switching transistor. The fifth transistor 105 has a function of selecting timing for supplying the potential of the ninth wiring 129 to the node 141 and functions as an input transistor. The sixth transistor 106 has a function of selecting timing for supplying the potential of the twelfth wiring 132 to the node 141 and functions as a switching transistor. The seventh transistor 107 has a function of selecting timing for supplying the potential of the thirteenth wiring 133 to the node 141 and functions as a switching transistor. The eighth transistor 108 has a function of selecting timing for supplying the potential of the eleventh wiring 131 to the node 142 and functions as a switching transistor.

Note that the first transistor 101 to the eighth transistor 108 are not limited to transistors as long as they have the functions described above. For example, the second transistor 102, the fourth transistor 104, the third transistor 103, the fourth transistor 104, the sixth transistor 106, the seventh transistor 107, and the eighth transistor 108 that function as switching transistors are: As long as the element has a switching function, a diode, a CMOS analog switch, or various logic circuits may be applied. Further, the fifth transistor 105 functioning as an input transistor only needs to have a function of selecting the timing at which the node 141 is turned off by increasing the potential of the node 141. Also good.

Note that the arrangement and the number of the transistors are not limited to those in FIG. 1 as long as the operation similar to that in FIG. 1 is performed. As can be seen from FIGS. 3 and 4 describing the operation of the flip-flop of FIG. 1, in this embodiment, the set period, the selection period, the reset period, the first non-selection period, and the second non-selection period are: It suffices that the continuity is taken as indicated by the solid lines in FIGS. 3A to 3C, 4D, and 4E, respectively. Therefore, transistors, other elements (resistive elements, capacitive elements, etc.), diodes, switches, various logic circuits, etc. are newly arranged if the transistor can be arranged and operated to satisfy this requirement. Also good.

For example, the potential of the node 142 is determined depending on whether the third transistor 103 is turned on or the fourth transistor 104 is turned on. However, as shown in FIG. 10A, even when the resistance element 1011 and the resistance element 1012 are connected between the seventh wiring 127 and the eighth wiring 128, the same operation as that in FIG. Is possible. The flip-flop in FIG. 10A can reduce the number of transistors and the number of wirings, so that the layout area can be reduced, the yield can be improved, and the like.

Further, as shown in FIG. 10B, a diode-connected transistor 1021 and a diode-connected transistor 1022 are arranged between the seventh wiring 127 and the node 142 instead of the resistance element 1011, and the eighth wiring 128. Instead of the resistance element 1012, a diode-connected transistor 1023 and a diode-connected transistor 1024 may be provided between the node 142 and the node 142. The seventh wiring 127 is connected to the first electrode of the transistor 1021, the gate electrode of the transistor 1021, and the first electrode of the transistor 1022. The eighth wiring 128 is connected to the first electrode of the transistor 1023 and the transistor 1024. And the gate electrode of the transistor 1024 are connected to each other. The node 142 has a second electrode of the transistor 1021, a second electrode of the transistor 1022, a gate electrode of the transistor 1022, a second electrode of the transistor 1023, and a transistor The gate electrode of 1023 and the second electrode of the transistor 1024 are connected. That is, two diodes are connected in reverse and in parallel between the seventh wiring 127 and the node 142 and between the eighth wiring 128 and the node 142, respectively.

Note that as long as the operation similar to that in FIG. 1 is performed, the driving timing of the flip-flop of this embodiment is not limited to the timing chart in FIG.

For example, as illustrated in the timing chart of FIG. 6, the period during which an H signal is input to the first wiring 121, the second wiring 122, the fifth wiring 125, the seventh wiring 127, and the eighth wiring 128 is shortened. May be. In FIG. 6, the timing at which the signal switches from the L level to the H level is delayed by the period Ta1, and the timing at which the signal switches from the H level to the L level is advanced by the period Ta2, as compared with the timing chart of FIG. Therefore, in the flip-flop to which the timing chart of FIG. 6 is applied, the instantaneous current of each wiring becomes small, so that it is possible to save power, suppress malfunction, improve the range of operating conditions, and the like. Further, the flip-flop to which the timing chart of FIG. 6 is applied can shorten the fall time of the signal output from the third wiring 123 in the reset period. This is because the timing at which the potential of the node 141 becomes the L level is delayed by the period Ta1 + the period Ta2, so that the L signal input to the fifth wiring 125 has a large current capability (a channel width is large). This is because the voltage is supplied to the third wiring 123 via the. Note that portions common to the timing chart of FIG. 2 are denoted by common reference numerals, and description thereof is omitted.

Note that the relationship between the period Ta1, the period Ta2, and the period Tb is preferably ((Ta1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 <10 [%]. More desirably, ((Ta1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 <5 [%] is desirable. Further, it is desirable that the period Ta1≈the period Ta2.

Note that the first wiring 121 to the thirteenth wiring 131 can be freely connected as long as the operation similar to that in FIG. 1 is performed. For example, as illustrated in FIG. 7A, the first electrode of the second transistor 102, the first electrode of the fourth transistor 104, the first electrode of the sixth transistor 106, and the seventh transistor 107 The first electrode of the eighth transistor 108 and the first electrode of the eighth transistor 108 may be connected to the seventh wiring 707. Further, the first electrode of the fifth transistor 105 and the first electrode of the third transistor 103 may be connected to the sixth wiring 706. Further, the first electrode of the first transistor 101 and the gate electrode of the third transistor 103 may be connected to the fourth wiring 704. Note that the first electrode of the first transistor 101 may be connected to the eighth wiring 708 as illustrated in FIG. Further, as illustrated in FIG. 8A, the first electrode of the third transistor 103 may be connected to the ninth wiring 709. Further, as illustrated in FIG. 8B, the first electrode of the fourth transistor 104 may be connected to the tenth wiring 710. Note that portions common to the configuration in FIG. 1 are denoted by common reference numerals and description thereof is omitted.

In the flip-flop in FIG. 7A, the number of wirings can be reduced; thus, yield, reduction in layout area, improvement in reliability, or improvement in a range of operating conditions can be achieved. Further, since the flip-flop in FIG. 7B can reduce the potential applied to the third transistor 103 and apply a reverse bias, the shift of the threshold voltage of the third transistor 103 can be further suppressed. Further, since the potential supplied to the ninth wiring 709 can be reduced in the flip-flop in FIG. 8A, the shift of the threshold voltage of the seventh transistor 107 can be further suppressed. Further, since the flip-flop in FIG. 8B can prevent the current flowing through the third transistor 103 and the fourth transistor 104 from operating as other transistors, the range of operating conditions can be improved. it can.

FIG. 29 illustrates an example of a top view of the flip-flop illustrated in FIG. The conductive layer 2901 includes a portion functioning as the first electrode of the first transistor 101 and is connected to the fourth wiring 704 through the wiring 2951. The conductive layer 2902 functions as the second electrode of the first transistor 101 and is connected to the third wiring 703 through the wiring 2952. The conductive layer 2903 includes a function as a gate electrode of the first transistor 101 and a gate electrode of the eighth transistor 108. The conductive layer 2904 includes a portion functioning as the second electrode of the second transistor 102 and is connected to the third wiring 703 through the wiring 2952. The conductive layer 2905 functions as the first electrode of the second transistor 102, the first electrode of the fourth transistor 104, and the first electrode of the eighth transistor 108, and the seventh wiring 707 Connected. The conductive layer 2906 functions as the gate electrode of the second transistor 102 and the gate electrode of the fourth transistor 104 and is connected to the fifth wiring 705 through the wiring 2953. The conductive layer 2907 functions as the first electrode of the third transistor 103 and is connected to the sixth wiring 706 through the wiring 2954. The conductive layer 2908 functions as the second electrode of the third transistor 103, the second electrode of the fourth transistor 104, and the second electrode of the eighth transistor 108. The conductive layer 2909 includes a function as a gate electrode of the third transistor 103 and is connected to the fourth wiring 704 through the wiring 2955. The conductive layer 2910 functions as the first electrode of the fifth transistor 105 and is connected to the sixth wiring 706 through the wiring 2956. The conductive layer 2911 functions as the second electrode of the fifth transistor 105 and the second electrode of the seventh transistor 107 and is connected to the conductive layer 2903 through the wiring 2957. The conductive layer 2912 includes a function as a gate electrode of the fifth transistor 105 and is connected to the first wiring 701 through the wiring 2958. The conductive layer 2913 includes a function as the second electrode of the sixth transistor 106 and is connected to the conductive layer 2903 through the wiring 2595. The conductive layer 2914 includes a function as a gate electrode of the sixth transistor 106 and is connected to the conductive layer 2908 through a wiring 2954. The conductive layer 2915 has a function as the second electrode of the seventh transistor 107 and is connected to the wiring 707. The conductive layer 2916 includes a function as the gate electrode of the seventh transistor 107 and is connected to the second wiring 702 through the wiring 2960.

Note that portions functioning as the gate electrode, the first electrode, and the second electrode of the first transistor 101 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2981. The portions functioning as the gate electrode, the first electrode, and the second electrode of the second transistor 102 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2982. The portions functioning as the gate electrode, the first electrode, and the second electrode of the third transistor 103 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2983. The portions functioning as the gate electrode, the first electrode, and the second electrode of the fourth transistor 104 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2984. The portion functioning as the gate electrode, the first electrode, and the second electrode of the fifth transistor 105 is a portion where the conductive layer including each of them overlaps with the semiconductor layer 2985. The portion functioning as the gate electrode, the first electrode, and the second electrode of the sixth transistor 106 is a portion where the conductive layer including each of them overlaps with the semiconductor layer 2986. The portions functioning as the gate electrode, the first electrode, and the second electrode of the seventh transistor 107 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2987. The portions functioning as the gate electrode, the first electrode, and the second electrode of the eighth transistor 108 are portions where a conductive layer including each of them overlaps with the semiconductor layer 2988.

Next, a structure and driving method of the shift register including the flip-flop of this embodiment described above will be described.

A structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 11 includes n flip-flops (flip-flops 1101_1 to 1101_n).

Connection relations of the shift register in FIG. 11 are described. In the shift register in FIG. 11, the i-th flip-flop 1101_i (any one of the flip-flops 1101_1 to 1101_n) has the first wiring 121 illustrated in FIG. The second wiring 122 illustrated in FIG. 1A is connected to the seventh wiring 1117_i + 1, and the third wiring 123 illustrated in FIG. 1A is connected to the seventh wiring 1117_i. 1A, the fourth wiring 124, the tenth wiring 130, the eleventh wiring 131, the twelfth wiring 132, and the thirteenth wiring 133 are connected to the fifth wiring 1115, and FIG. ) Are connected to the second wiring 1112 in the odd-numbered flip-flops, and are connected to the third wiring 1113 in the even-numbered flip-flops. The eighth wiring 128 illustrated in FIG. 1A is connected to the third wiring 1113 in the odd-numbered flip-flops, and is connected to the second wiring 1112 in the even-numbered flip-flops. The sixth wiring 126 and the ninth wiring 129 shown in A) are connected to the fourth wiring 1114. Note that the first wiring 121 illustrated in FIG. 1A of the first-stage flip-flop 1101_1 is connected to the first wiring 1111 and the second-stage flip-flop 1101_n illustrated in FIG. The wiring 122 is connected to the sixth wiring 1116.

Note that the first wiring 1111, the second wiring 1112, the third wiring 1113, and the sixth wiring 1116 are respectively connected to the first signal line, the second signal line, the third signal line, and the fourth signal. You may call it a line. Further, the fourth wiring 1114 and the fifth wiring 1115 may be referred to as a first power supply line and a second power supply line, respectively.

Next, operation of the shift register illustrated in FIG. 11 is described with reference to a timing chart of FIG. 12 and a timing chart of FIG. Here, the timing chart of FIG. 12 is divided into a scanning period and a blanking period. The scan period is a period from when the selection signal is output from the seventh wiring 1117_1 to when the selection signal is output from the seventh wiring 1117_n. The blanking period is a period from when the output of the selection signal from the seventh wiring 1117 — n is finished until the output of the selection signal from the seventh wiring 1117 — 1 is started.

Note that the potential of V 1 is supplied to the fourth wiring 1114 and the potential of V 2 is supplied to the fifth wiring 1115.

Note that the signals 1211, 1212, 1213, and 1216 illustrated in FIG. 12 are input to the first wiring 1111, the second wiring 1112, the third wiring 1113, and the sixth wiring 1116, respectively. Here, the signal 1211, the signal 1212, the signal 1213, and the signal 1216 are digital signals in which the potential of the H signal is V1 (hereinafter also referred to as H level) and the potential of the L signal is V2 (hereinafter also referred to as L level). . Further, the signal 1211, the signal 1212, the signal 1213, and the signal 1216 may be referred to as a start signal, a first clock signal, a second clock signal (inverted clock signal), and a reset signal, respectively.

Note that various signals, potentials, and currents may be input to the first wiring 1111 to the sixth wiring 1116, respectively.

Note that from the seventh wiring 1117_1 to the seventh wiring 1117_n, digital signals having an H signal potential of V1 (hereinafter also referred to as H level) and an L signal potential of V2 (hereinafter also referred to as L level) are received. Is output. However, as shown in FIG. 14, signals are output from the seventh wiring 1117_1 to the seventh wiring 1117_n through the buffers 1401_1 to 1401_n, respectively, and the output signal of the shift register and the transfer signal of each flip-flop are divided. As a result, the range of operating conditions can be increased.

Here, an example of the buffers 1401_1 to 1401_n included in the shift register illustrated in FIG. 14 is described with reference to FIGS. In the buffer 8000 illustrated in FIG. 15A, an inverter 8001a, an inverter 8001b, and an inverter 8001c are connected between the wiring 8011 and the wiring 8012, so that an inverted signal of the signal input to the wiring 8011 is output from the wiring 8012. The However, the number of inverters connected between the wiring 8011 and the wiring 8012 is not limited. For example, when an even number of inverters are connected between the wiring 8011 and the wiring 8012, the same signal as the signal input to the wiring 8011 is used. A polarity signal is output from the wiring 8012. Further, as shown in a buffer 8100 in FIG. 15B, an inverter 8002a, an inverter 8002b, and an inverter 8002c connected in series, and an inverter 8003a, an inverter 8003b, and an inverter 8003c arranged in series are connected in parallel. Also good. The buffer 8100 in FIG. 15B can average variation in transistor characteristics, so that delay and rounding of a signal output from the wiring 8012 can be reduced. Further, the outputs of the inverter 8002a and the inverter 8002a and the outputs of the inverter 8002b and the inverter 8002b may be connected.

Note that in FIG. 15A, it is preferable that W of a transistor included in the inverter 8001a <W of a transistor included in the inverter 8001b <W of a transistor included in the inverter 8001c. This is because when the inverter 8001a has a small W, the driving capability of the flip-flop (specifically, the W / L value of the transistor 101 in FIG. 1) can be reduced, so that the shift register of the present invention can reduce the layout area. . Similarly, in FIG. 15B, it is preferable that W of the transistor included in the inverter 8002a <W of the transistor included in the inverter 8002b <W of the transistor included in the inverter 8002c. Similarly, in FIG. 15B, it is preferable that W of the transistor included in the inverter 8003a <W of the transistor included in the inverter 8003b <W of the transistor included in the inverter 8003c. Further, W of the transistor included in the inverter 8002a = W of the transistor included in the inverter 8003a, W of the transistor included in the inverter 8002b = W of the transistor included in the inverter 8003b, W of the transistor included in the inverter 8002c = W of the transistor included in the inverter 8003c It is preferable to do.

Note that there is no particular limitation on the inverter illustrated in FIGS. 15A and 15B as long as it can output an inverted signal. For example, an inverter may be formed using the first transistor 8201 and the second transistor 8202 as illustrated in FIG. Further, a signal is input to the first wiring, a signal is output from the second wiring 8212, V 1 is supplied to the third wiring 8213, and V 2 is supplied to the fourth wiring 8214. In the inverter illustrated in FIG. 15C, when an H signal is input to the first wiring 8211, a potential obtained by dividing V 1 −V 2 by the first transistor 8201 and the second transistor 8202 (first
(W / L of the transistor 8201 <W / L of the second transistor 8202) is output from the second wiring 8212. Further, when the L signal is input to the first wiring 8211, the inverter in FIG. 15C outputs V1−Vth8201 (Vth8201: the threshold voltage of the first transistor 8201) from the second wiring 8212. Further, the first transistor 8201 may be a PN junction diode as long as it is an element having a resistance component, or may simply be a resistance element.

Further, as illustrated in FIG. 15D, an inverter may be formed using the first transistor 8301, the second transistor 8302, the third transistor 8303, and the fourth transistor 8304. Further, a signal is input to the first wiring 8311, a signal is output from the second wiring 8312, V1 is supplied to the third wiring 8313 and the fifth wiring 8315, and the fourth wiring 8314 and V2 is supplied to the sixth wiring 8316. The inverter in FIG. 15D outputs V 2 from the second wiring 8312 when an H signal is input to the first wiring 8311. At this time, since the potential of the node 8341 is set to the L level, the first transistor 8301 is turned off. Further, when the L signal is input to the first wiring 8311, the inverter in FIG. 15D outputs V1 from the second wiring 8312. At this time, when the potential of the node 8341 becomes V1−Vth8303 (Vth8303: threshold voltage of the third transistor 8303), the node 8341 is in a floating state, and the potential of the node 8341 is V1 + Vth8301 (Vth8301: first) by the bootstrap operation. The first transistor 8301 is turned on. Further, since the first transistor 8301 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode.

Further, as illustrated in FIG. 16A, an inverter may be formed using the first transistor 8401, the second transistor 8402, the third transistor 8403, and the fourth transistor 8404. The inverter in FIG. 16A is a two-input inverter and can perform a bootstrap operation. Further, a signal is input to the first wiring 8411, an inverted signal is input to the second wiring 8412, a signal is output from the third wiring 8413, and the fourth wiring 8414 and the sixth wiring 8416 are output. Is supplied with V1, and V5 is supplied to the fifth wiring 8415 and the seventh wiring 8417. When an L signal is input to the first wiring 8411 and an H signal is input to the second wiring 8412, the inverter in FIG. 16A outputs V 2 from the third wiring 8413. At this time, since the potential of the node 8441 is V2, the first transistor 8401 is turned off. Further, when the H signal is input to the first wiring 8411 and the L signal is input to the second wiring 8412, the inverter in FIG. 16A outputs V1 from the third wiring 8413. At this time, when the potential of the node 8441 becomes V1−Vth8403 (Vth8403: threshold voltage of the third transistor 8403), the node 8441 is in a floating state, and the potential of the node 8441 is V1 + Vth8401 (Vth8401: first) by the bootstrap operation. , The first transistor 8401 is turned on. Further, since the first transistor 8401 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, when one of the first wiring 8411 and the second wiring 8412 is connected to the third wiring 123 illustrated in FIG. 1A and the other is connected to the node 142 illustrated in FIG. Good.

Further, as illustrated in FIG. 16B, an inverter may be formed using the first transistor 8501, the second transistor 8502, and the third transistor 8503. The inverter in FIG. 16B is a two-input inverter and can perform a bootstrap operation. Further, a signal is input to the first wiring 8511, an inverted signal is input to the second wiring 8512, a signal is output from the third wiring 8513, and the fourth wiring 8514 and the sixth wiring 8516 are output. Is supplied with V2, and the fifth wiring 8515 is supplied with V2. FIG.
When an L signal is input to the first wiring 8511 and an H signal is input to the second wiring 8512, the inverter of FIG. 5B outputs V2 from the third wiring 8513. At this time, since the potential of the node 8541 is V2, the first transistor 8501 is turned off. Further, when the H signal is input to the first wiring 8511 and the L signal is input to the second wiring 8512, the inverter in FIG. 16B outputs V1 from the third wiring 8513. At this time, when the potential of the node 8541 becomes V1−Vth8503 (Vth8503: the threshold voltage of the third transistor 8503), the node 8541 enters a floating state, and the potential of the node 8541 becomes V1 + Vth8501 (Vth8501: first) by the bootstrap operation. The first transistor 8501 is turned on. Further, since the first transistor 8501 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, when one of the first wiring 8511 and the second wiring 8512 is connected to the third wiring 123 illustrated in FIG. 1A and the other is connected to the node 142 illustrated in FIG. Good.

Further, as illustrated in FIG. 16C, an inverter may be formed using the first transistor 8601, the second transistor 8602, the third transistor 8603, and the fourth transistor 8604. The inverter in FIG. 16C is a two-input inverter and can perform a bootstrap operation. Further, a signal is input to the first wiring 8611, an inverted signal is input to the second wiring 8612, a signal is output from the third wiring 8613, and V1 is supplied to the fourth wiring 8614. The fifth wiring 8615 and the sixth wiring 8616 are supplied with V2. When an L signal is input to the first wiring 8611 and an H signal is input to the second wiring 8612, the inverter in FIG. 16A outputs V2 from the third wiring 8613. At this time, since the potential of the node 8641 becomes V2, the first transistor 8601 is turned off. Further, when an H signal is input to the first wiring 8611 and an L signal is input to the second wiring 8612, the inverter in FIG. 16C outputs V 1 from the third wiring 8613. At this time, when the potential of the node 8641 becomes V1−Vth8603 (Vth8603: the threshold voltage of the third transistor 8603), the node 8641 becomes in a floating state, and the potential of the node 8641 becomes V1 + Vth8601 (Vth8601: first) by the bootstrap operation. , The first transistor 8601 is turned on. Further, since the first transistor 8601 functions as a bootstrap transistor, a capacitor may be provided between the second electrode and the gate electrode. Further, when one of the first wiring 8611 and the second wiring 8612 is connected to the third wiring 123 illustrated in FIG. 1A and the other is connected to the node 142 illustrated in FIG. Good.

Note that a signal output from the seventh wiring 1117_i-1 is used as a start signal of the flip-flop 1101_i, and a signal output from the seventh wiring 1117_i + 1 is used as a reset signal. Here, a start signal of the flip-flop 1101_1 is input from the first wiring 1111 and a reset signal of the flip-flop 1101_n is input from the sixth wiring 1116. Note that as the reset signal of the flip-flop 1101_n, a signal output from the seventh wiring 1117_1 or a signal output from the seventh wiring 1117_2 may be used. Alternatively, a dummy flip-flop may be newly disposed and the output signal of the dummy flip-flop may be used. By doing so, the number of wirings and the number of signals can be reduced.

As illustrated in FIG. 13, for example, when the flip-flop 1101_i enters a selection period, an H signal (selection signal) is output from the seventh wiring 1117_i. At this time, the flip-flop 1101_i + 1 is in the set period. After that, the flip-flop 1101_i enters a reset period, and an L signal is output from the seventh wiring 1117_i. At this time, the flip-flop 1101_i + 1 is in a selection period. After that, the flip-flop 1101_i enters the first non-selection period, the seventh wiring 1117_i becomes floating, and the potential is maintained at V2. At this time, the flip-flop 1101_i + 1 is in the reset period. After that, the flip-flop 1101_i enters the second non-selection period, and the L signal is output from the seventh wiring 1117_i. At this time, the flip-flop 1101_i + 1 is in the first non-selection period.

In this manner, the shift register in FIG. 11 can output a selection signal from the seventh wiring 1117_1 to the seventh wiring 1117_n in order. That is, the shift register in FIG. 11 can scan the seventh wiring 1117_1 to the seventh wiring 717_n.

Further, the shift register to which the flip-flop of this embodiment is applied can suppress a shift in threshold voltage of the transistor, so that the lifetime can be extended. Further, the shift register to which the flip-flop of this embodiment is applied can improve reliability. Further, the shift register to which the flip-flop of this embodiment is applied can suppress malfunction.

Further, the shift register to which the flip-flop of this embodiment is applied can operate at high speed, and thus can be applied to a higher-definition display device or a larger display device. Further, the shift register to which the flip-flop of this embodiment is applied can simplify the process. Further, a shift register to which the flip-flop of this embodiment is applied can reduce manufacturing costs. Further, the shift register to which the flip-flop of this embodiment is applied can improve yield.

Next, a structure and driving method of the display device including the shift register of this embodiment described above will be described. Note that the display device of this embodiment mode includes at least the flip-flop of this embodiment mode.

The structure of the display device of this embodiment will be described with reference to FIG. The display device in FIG. 17 includes a signal line driver circuit 1701, a scan line driver circuit 1702, and a pixel portion 1704, and the pixel portion 1704 includes a plurality of signals that extend from the signal line driver circuit 1701 in the column direction. A plurality of scanning lines G1 to Gn, signal lines S1 to Sm, and a plurality of scanning lines G1 to Gn arranged in a matrix corresponding to the lines S1 to Sm and the scanning line driving circuit 1702 extending in the row direction. Pixels 1703. Each pixel 1703 is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scanning line Gi (any one of the scanning lines G1 to Gn). Further, the scan line driver circuit 1702 may be referred to as a driver circuit.

Note that as the scan line driver circuit 1702, the shift register of this embodiment can be used. Needless to say, the shift register of this embodiment may also be used for the signal line driver circuit 1701.

Note that the scan lines G1 to Gn are connected to the seventh wiring 1117_1 to the seventh wiring 1117_n illustrated in FIGS.

Note that the signal line and the scanning line may be simply referred to as wiring. Further, each of the signal line driver circuit 1701 and the scan line driver circuit 1702 may be referred to as a driver circuit.

Note that the pixel 1703 includes at least one switching element, one capacitor element, and a pixel electrode. Note that the pixel 1703 may include a plurality of switching elements or a plurality of capacitor elements. Furthermore, a capacitive element is not always necessary. Further, the pixel 1703 may further include a transistor that operates in a saturation region. Further, the pixel 1703 may include a display element such as a liquid crystal element or an EL element. Here, a transistor and a PN junction diode can be used as the switching element. However, when a transistor is used as the switching element, it is preferable that the transistor operates in a linear region. Further, in the case where the scan line driver circuit 1702 includes only N-channel transistors, it is preferable to use N-channel transistors as switching elements. Further, in the case where the scan line driver circuit 1702 includes only P-channel transistors, it is preferable to use P-channel transistors as switching elements.

Note that the scan line driver circuit 1702 and the pixel portion 1704 are formed over the insulating substrate 1705, and the signal line driver circuit 1701 is not formed over the insulating substrate 1705. The signal line driver circuit 1701 is formed over a single crystal substrate, an SOI substrate, or an insulating substrate different from the insulating substrate 1705. The signal line driver circuit 1701 is connected to the signal lines S1 to Sm via a printed circuit board such as an FPC. Note that the signal line driver circuit 1701 may be formed over the insulating substrate 1705, or a circuit that constitutes part of the function of the signal line driver circuit 1701 may be formed over the insulating substrate 1705.
Note that wiring, electrodes, conductive layers, conductive films, terminals, etc. are made of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr). Nickel (Ni), Platinum (Pt), Gold (Au), Silver (Ag), Copper (Cu), Magnesium (Mg), Scandium (Sc), Cobalt (Co), Zinc (Zn), Niobium (Nb) , Silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), and oxygen (O). One or a plurality of elements, or a compound, an alloy material (for example, indium tin oxide (ITO), indium zinc oxide (IZO), silicon oxide) containing one or more elements selected from the above group as a component Including Indium tin oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), tin cadmium oxide (CTO), aluminum neodymium (Al-Nd), magnesium silver (Mg-Ag), molybdenum niobium (Mo-Nb) Etc.). Alternatively, the wiring, the electrode, the conductive layer, the conductive film, the terminal, and the like are preferably formed using a substance in which these compounds are combined. Or one or more elements selected from the group and a silicon compound (silicide) (for example, aluminum silicon, molybdenum silicon, nickel silicide, etc.), one or more elements selected from the group and nitrogen It is desirable to form with a compound (eg, titanium nitride, tantalum nitride, molybdenum nitride, or the like).

Note that silicon (Si) may contain an n-type impurity (such as phosphorus) or a p-type impurity (such as boron). When silicon contains impurities, the conductivity is improved and the same behavior as a normal conductor can be achieved. Therefore, it becomes easy to use as wiring, electrodes, and the like.

Note that silicon having various crystallinity such as single crystal, polycrystal (polysilicon), amorphous (amorphous silicon), and microcrystal (microcrystal silicon) can be used. By using single crystal silicon or polycrystalline silicon, resistance of a wiring, an electrode, a conductive layer, a conductive film, a terminal, or the like can be reduced. By using amorphous silicon or microcrystalline silicon, a wiring or the like can be formed by a simple process.

Note that since aluminum or silver has high conductivity, signal delay can be reduced. Further, since etching is easy, patterning is easy and fine processing can be performed.

Note that since copper has high conductivity, signal delay can be reduced. When copper is used, it is desirable to have a laminated structure in order to improve adhesion.

Molybdenum or titanium is preferable because it has advantages such as no defects, easy etching, and high heat resistance even when in contact with an oxide semiconductor (ITO, IZO, or the like) or silicon.

Tungsten is desirable because it has advantages such as high heat resistance.

Neodymium is desirable because it has advantages such as high heat resistance. In particular, when an alloy of neodymium and aluminum is used, the heat resistance is improved, and aluminum does not easily cause hillocks.

Silicon is preferable because it can be formed at the same time as a semiconductor layer included in a transistor and has high heat resistance.

Note that ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (SnO), and tin cadmium oxide (CTO) have a light-transmitting property and are used for a portion that transmits light. be able to. For example, it can be used as a pixel electrode or a common electrode.

Note that IZO is desirable because it is easy to etch and process. It is difficult for IZO to leave a residue when it is etched. Therefore, when IZO is used as the pixel electrode, it is possible to reduce the occurrence of defects (short circuit, alignment disorder, etc.) in the liquid crystal element and the light emitting element.

Note that a wiring, an electrode, a conductive layer, a conductive film, a terminal, or the like may have a single-layer structure or a multilayer structure. With a single-layer structure, a manufacturing process of wiring, electrodes, conductive layers, conductive films, terminals, and the like can be simplified, the number of process days can be reduced, and cost can be reduced. Alternatively, by using a multilayer structure, it is possible to reduce the demerits while making use of the merits of each material, and to form wirings, electrodes, and the like with good performance. For example, by including a low resistance material (such as aluminum) in the multilayer structure, the resistance of the wiring can be reduced. In addition, by using a laminated structure in which a low heat resistant material is sandwiched between high heat resistant materials, the heat resistance of a wiring, an electrode, or the like can be increased while taking advantage of the low heat resistant material. For example, a layered structure in which a layer containing aluminum is sandwiched between layers containing molybdenum, titanium, neodymium, or the like is preferable.

In addition, when wires, electrodes, etc. are in direct contact with each other, they may adversely affect each other. For example, one wiring, electrode, etc. is contained in the other wiring, electrode, etc. material, changing its properties, making it impossible to achieve its original purpose, forming a high resistance part, and manufacturing Occasionally, problems may occur that prevent successful manufacture. In such a case, it is preferable to sandwich or cover a material that reacts more easily by a laminated structure with a material that does not react easily. For example, when ITO and aluminum are connected, it is desirable to sandwich titanium, molybdenum, or a neodymium alloy between ITO and aluminum. When silicon and aluminum are connected, it is desirable to sandwich titanium, molybdenum, or a neodymium alloy between ITO and aluminum.

In addition, wiring means what the conductor is arrange | positioned. It may extend linearly or may be arranged short without extending. Therefore, the electrode is included in the wiring.

Note that the wirings and electrodes described above can also be applied to other display devices, shift registers, and pixels.

Note that the signal line driver circuit 1701 inputs voltage or current as video signals to the signal lines S1 to Sm. However, the video signal may be a digital signal or an analog signal. Further, the positive / negative polarity of the video signal may be inverted every frame (frame inversion driving), or the positive / negative polarity may be inverted every row (gate line inversion driving). The positive and negative electrodes may be inverted (source line inversion driving), and the positive and negative electrodes may be inverted every row and column (dot line inversion driving). Further, the video signal may be input to the signal lines S1 to Sm by dot sequential driving or may be input by line sequential driving. Further, the signal line driver circuit 1701 may input not only a video signal but also a constant voltage such as a precharge voltage to the signal lines S1 to Sm. It is desirable to input a constant voltage such as a precharge voltage for each gate selection period and for each frame.

Note that the scanning line driver circuit 1702 inputs signals to the scanning lines G1 to Gn, and selects the scanning lines G1 to Gn in order from the first row (hereinafter also referred to as scanning). Then, the scan line driver circuit 1702 selects a plurality of pixels 1703 connected to the selected scan line. Here, a period in which one scanning line is selected is referred to as one gate selection period, and a period in which the scanning line is not selected is referred to as a non-selection period. Further, a signal output from the scanning line driver circuit 1702 to the scanning line is referred to as a scanning signal. Further, the maximum value of the scanning signal is larger than the maximum value of the video signal or the maximum voltage of the signal line, and the minimum value of the scanning signal is smaller than the minimum value of the video signal or the minimum voltage of the signal line.

Note that when the pixel 1703 is selected, a video signal is input from the signal line driver circuit 1701 to the pixel 1703 through the signal line. Further, when the pixel 1703 is not selected, the pixel 1703 holds a video signal (a potential corresponding to the video signal) input in the selection period.

Note that although not illustrated, the signal line driver circuit 1701 and the scan line driver circuit 1702 are supplied with a plurality of potentials and a plurality of signals.

Next, operation of the display device illustrated in FIG. 17 will be described with reference to a timing chart of FIG. Further, FIG. 18 shows one frame period corresponding to a period for displaying an image for one screen. However, the period of one frame is not particularly limited, but is preferably set to at least 1/60 second or less so that a person viewing the image does not feel flicker.

The timing chart of FIG. 18 shows the timing at which the first scanning line G1, the i-th scanning line Gi, the i + 1-th scanning line Gi + 1, and the n-th scanning line Gn are selected. .

In FIG. 18, for example, the i-th scanning line Gi is selected, and a plurality of pixels 1703 connected to the scanning line Gi are selected. The plurality of pixels 1703 connected to the scanning line Gi each input a video signal and hold a potential corresponding to the video signal. Thereafter, the i-th scanning line Gi is deselected, the i + 1-th scanning line Gi + 1 is selected, and the plurality of pixels 1703 connected to the scanning line Gi + 1 are selected. The plurality of pixels 1703 connected to the scanning line Gi + 1 each input a video signal and hold a potential corresponding to the video signal. Thus, in one frame period, the scanning lines G1 to Gn are sequentially selected, and the pixels 1703 connected to the respective scanning lines are also selected in order. A plurality of pixels 1703 connected to each scanning line each input a video signal and hold a potential corresponding to the video signal.

Further, a display device using the shift register of this embodiment as the scan line driver circuit 1702 can operate at high speed, and thus can have higher definition or larger size. Further, the display device of this embodiment can simplify the process. Furthermore, the display device of this embodiment can reduce manufacturing costs. Further, the display device in this embodiment can improve yield.

Further, in the display device in FIG. 17, since the signal line driver circuit 1701 that requires high-speed operation, the scan line driver circuit 1702, and the pixel portion 1703 are formed over different substrates, transistors of the scan line driver circuit 1702 are included. As the semiconductor layer and the semiconductor layer of the transistor included in the pixel 1703, amorphous silicon can be used. Accordingly, the display device of FIG. 17 can simplify the manufacturing process. Further, the display device of FIG. 17 can reduce the manufacturing cost. Further, the display device in FIG. 17 can improve yield. Furthermore, the display device in FIG. 17 can be increased in size. Alternatively, the display device in FIG. 17 can simplify the manufacturing process even when polysilicon or polycrystalline silicon is used for the semiconductor layer of the transistor.

Note that in the case where the signal line driver circuit 1701, the scan line driver circuit 1702, and the pixel 1703 are formed over the same substrate, a semiconductor layer of a transistor included in the scan line driver circuit 1702 and a semiconductor layer of a transistor included in the pixel 1703 are used as a polycrystal. Silicon or polycrystalline silicon may be used.

Note that as shown in FIG. 17, the number and arrangement of the driver circuits are not limited to those in FIG. 17 as long as a pixel can be selected and a video signal can be written to the pixel independently.

For example, as shown in FIG. 19, the scanning lines G1 to Gn may be scanned by the first scanning line driving circuit 1902a and the second scanning line driving circuit 1902b. The first scan line driver circuit 1902a and the second drive circuit 1902b have the same configuration as the scan line driver circuit 1702 shown in FIG. 17, and scan the scan lines G1 to Gn at the same timing. Further, the first scan line driver circuit 1902a and the second driver circuit 1902b may be referred to as a first driver circuit and a second driver circuit, respectively.

In the display device in FIG. 19, even when one of the first scan line driver circuit 1902a and the second scan line driver circuit 1902b is defective, the scan line driver circuit 1902a and the second scan line driver circuit 1902b Since the other can scan the scanning lines G1 to Gn, it can have redundancy. Further, in the display device of FIG. 19, the load of the first scan line driver circuit 1902a (the wiring resistance of the scan line and the parasitic capacitance of the scan line) and the load of the second scan line driver circuit 1902b are about half that of FIG. Therefore, the delay and rounding of signals (output signals of the first scan line driver circuit 1902a and the second drive circuit 1902b) input to the scan lines G1 to Gn can be reduced. Further, since the load on the first scan line driver circuit 1902a and the load on the second scan line driver circuit 1902b are reduced, the display device in FIG. 19 can scan the scan lines G1 to Gn at high speed. it can. Furthermore, since the scanning lines G1 to Gn can be scanned at high speed, the panel can be enlarged or the panel can be made high definition. Note that portions common to the configuration in FIG.

As another example, FIG. 20 illustrates a display device capable of writing video signals to pixels at high speed. In the display device of FIG. 20, a video signal is input to the odd-numbered pixel 1703 from the odd-numbered signal line, and a video signal is input to the even-numbered pixel 1703 from the even-numbered signal line. Further, in the display device of FIG. 20, the odd-numbered scanning lines among the scanning lines G1 to Gn are scanned by the first scanning line drive circuit 2002a, and the even-numbered scanning lines G1 to Gn. The scan line is scanned by the second scan line driver circuit 2002b. Further, the start signal input to the first scan line driver circuit 2002b is input with a delay of ¼ period of the clock signal from the start signal input to the first scan line driver circuit 2002a.

Note that the display device in FIG. 20 can perform dot inversion driving only by inputting a positive video signal and a negative video signal for each column to each signal line in one frame period. Furthermore, the display device in FIG. 20 can perform frame inversion driving by inverting the polarity of a video signal input to each signal line for each frame period.

The operation of the display device in FIG. 20 will be described with reference to the timing chart in FIG. In the timing chart of FIG. 21, the first scanning line G1, the i-1th scanning line Gi-1, the ith scanning line Gi, the i + 1th scanning line Gi + 1, and the nth scanning line Gn. Indicates the timing of selection. Furthermore, in the timing chart of FIG. 21, one selection period is divided into a selection period a and a selection period b. Further, in the timing chart of FIG. 21, a case where the display device of FIG. 20 performs dot inversion driving and frame inversion driving will be described.

In FIG. 21, for example, the selection period a of the i-th scanning line Gi overlaps the selection period b of the i-1th scanning line Gi-1, and the selection period Tb of the i-th scanning line Gi is , The selection period a of the scanning line Gi + 1 in the (i + 1) th row overlaps. Therefore, in the selection period a, the same video signal input to the pixel 1703 in the i−1 row and j + 1 column is input to the pixel 1703 in the i row j column. Further, in the selection period b, the same video signal input to the pixel 1703 in the i row and j column is input to the pixel 1703 in the i + 1 row and j + 1 column. Note that a video signal input to the pixel 1703 in the selection period b is an original video signal, and a video signal input to the pixel 1703 in the selection period a is a video signal for precharging the pixel 1703. Accordingly, each pixel 1703 is precharged by the video signal input to the pixel 1703 in the (i−1) th row and the (j + 1) th column in the selection period “a”, and then the original (i th row and the jth column) video in the selection period “b”. Input the signal.

From the above, the display device in FIG. 20 can write a video signal to the pixel 1703 at high speed, and thus can easily be increased in size or increased in definition. Furthermore, since the video signal having the same polarity is input to each of the signal lines in one frame period, the display device in FIG. 20 can realize low power consumption with less charge / discharge of each signal line. Further, in the display device of FIG. 20, since the load on the IC for inputting the video signal is significantly reduced, the heat generation of the IC and the power consumption of the IC can be reduced. Further, the display device in FIG. 20 can reduce the driving frequency of the first scan line driver circuit 2002a and the second scan line driver circuit 2002b by about half, so that power saving can be achieved.

Note that the display device of this embodiment can perform various driving methods depending on the structure and driving method of the pixel 1703. For example, in one frame period, the scan line driver circuit may scan the scan line a plurality of times.

17, 19, and 20, another wiring or the like may be added depending on the configuration of the pixel 1703. For example, a power supply line, a capacitor line, a new scanning line, or the like maintained at a constant potential may be added. However, when a scan line is newly added, a scan line driver circuit to which the shift register of this embodiment is applied may be newly added. As another example, dummy scanning lines, signal lines, power supply lines, or capacitor lines may be arranged in the pixel portion.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination, or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 2)
In this embodiment, a structure and a driving method of a flip-flop different from that in Embodiment 1, a driver circuit including the flip-flop, and a display device including the driver circuit will be described. Note that components similar to those in Embodiment 1 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

As the structure of the flip-flop in this embodiment, the same flip-flop structure as in Embodiment 1 can be used. However, the timing for driving the flip-flop is different from that of the first embodiment. Therefore, in this embodiment mode, description of the structure of the flip-flop is omitted.

Note that the case where the drive timing of this embodiment is applied to FIG. 1A will be described; however, the drive timing of this embodiment is illustrated in FIG. 1B, FIG. 1C, FIG. 5B, FIG. 5C, FIG. 7A, FIG. 7B, FIG. 8A, FIG. 8B, FIG. 9A, FIG. 9B, FIG. It can also be implemented by freely combining with the flip-flops of (A) and FIG. 10 (B). Furthermore, the drive timing of this embodiment can be implemented by freely combining with the drive timing described in Embodiment 1.

The operation of the flip-flop of this embodiment is described with reference to the flip-flop in FIG. 1A and the timing chart in FIG. Further, the timing chart of FIG. 22 will be described by being divided into a set period, a selection period, a reset period, a first non-selection period, and a second non-selection period. However, the set period is divided into a first set period and a second set period, and the selection period is divided into a first selection period and a second selection period.

Note that the first wiring 121, the fifth wiring 125, the eighth wiring 128, the seventh wiring 127, and the second wiring 122 are respectively provided with a signal 2221, a signal 2225, a signal 2228, and a signal 2227 shown in FIG. , A signal 2222 is input. A signal 2223 shown in FIG. 22 is output from the third wiring 123. Here, in the signal 2221, the signal 2225, the signal 2228, the signal 2227, the signal 2222, and the signal 2223, the potential of the H signal is V 1 (hereinafter also referred to as H level) and the potential of the L signal is V 2 (hereinafter also referred to as L level). ) Digital signal. Further, the signal 2221, the signal 2225, the signal 2228, the signal 2227, the signal 2222, and the signal 2223 are respectively converted into a start signal, a power clock signal (PCK), a first control clock signal (CCK1), and a second control clock signal (CCK2). ), May be called a reset signal or an output signal.

Note that the flip-flop of this embodiment basically performs the same operation as the flip-flop described in Embodiment 1. However, the flip-flop of this embodiment is different from the flip-flop of Embodiment 1 in that the timing at which the H signal is input to the first wiring 121 is delayed by ¼ period of the clock signal.

Note that the flip-flop of this embodiment includes the first set period (A1), the second set period (A2), the reset period (C), the first non-selection period (D), and the first In the two non-selection periods, the second non-selection period (E), the set period (A), the reset period (C), the first non-selection period (D), and the second non-selection shown in FIG. Since the same operation as that of the period is performed, the description is omitted.

In the flip-flop of this embodiment, the potential of the node 141 becomes V1 + Vth101 + α by the bootstrap operation while the H signal is input to the first wiring 121 in the first selection period illustrated in FIG. , H signals are output from the third wiring 123. In the flip-flop of this embodiment, the signal input to the first wiring 121 is in an L level in the second selection period illustrated in FIG. 22B2, but the potential of the node 141 is maintained at V1 + Vth101 + α. However, the H signal is still output from the third wiring 123.

Note that as shown in FIG. 23, in the flip-flop of this embodiment, the timing of inputting the H signal to the second wiring 122 is delayed by ¼ period of the clock signal, so that the fall time of the output signal Can be significantly shortened. That is, in the flip-flop of this embodiment to which FIG. 22 is applied, the L signal is input to the fifth wiring 125 in the first reset period illustrated in FIG. 22C1, and the potential of the node 141 is approximately V1 + Vth101. Go down. Accordingly, the first transistor 101 remains on and the L signal is output from the third wiring 123. Since the L signal is input to the third 123 through the first transistor 101 having a large W / L value, the time until the potential of the third wiring 123 changes from the H level to the L level is significantly increased. Can be shortened. After that, in the flip-flop of this embodiment to which FIG. 22 is applied, the seventh transistor 107 is turned on and the potential of the node 141 becomes V2 in the second reset period illustrated in FIG. 22C2. At this time, the potential of the node 142 is V 1 −Vth 103 and the third transistor 103 is turned on, so that the L signal is output from the third wiring 103.

Note that the flip-flop of this embodiment can suppress a shift in threshold voltage of a transistor as in the flip-flop described in Embodiment 1, and thus can have a long lifetime. Further, since the flip-flop of this embodiment is resistant to noise, reliability can be improved or malfunction can be suppressed.

Furthermore, since the flip-flop of this embodiment can operate at high speed, it can be applied to a higher-definition display device or a larger display device. Further, the flip-flop of this embodiment can simplify the process. Further, the flip-flop of this embodiment can reduce manufacturing costs. Further, the flip-flop of this embodiment can improve yield.

Next, a structure and driving method of the shift register including the flip-flop of this embodiment described above will be described.

A structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 24 includes n flip-flops (flip-flops 2401_1 to 2401_n).

Connection relations of the shift register in FIG. 24 are described. In the shift register in FIG. 24, the i-th flip-flop 2401_i (any one of the flip-flops 2401_1 to 2401_n) has the first wiring 121 illustrated in FIG. 1A as the tenth wiring 2420_i-1. 1A, the second wiring 122 illustrated in FIG. 1A is connected to the tenth wiring 2420_i + 2, and the third wiring 123 illustrated in FIG. 1A is connected to the tenth wiring 2420_i. The fourth wiring 124, the tenth wiring 130, the eleventh wiring 131, the twelfth wiring 132, and the thirteenth wiring 133 illustrated in FIG. 1A are connected to the seventh wiring 2417, and FIG. ) Is connected to the second wiring 2412 in the 4N-3 (N is a natural number of 1 or more) stage flip-flop, and the 4N-2 stage flip-flop is connected to the second wiring 2412. Is connected to the third wiring 2413, the 4N-1 flip-flop is connected to the fourth wiring 2414, and the 4N-stage flip-flop is connected to the fifth wiring 2415. FIG. ) Is connected to the fourth wiring 2414 in the 4N-3 stage flip-flop, and is connected to the fifth wiring 2415 in the 4N-2 stage flip-flop. The flip-flop of the eye is connected to the second wiring 2412, the flip-flop of the 4Nth stage is connected to the third wiring 2413, and the sixth wiring 126 and the ninth wiring 129 shown in FIG. 6 wiring 2416. Note that the first wiring 121 illustrated in FIG. 1A of the first-stage flip-flop 2401_1 is connected to the first wiring 2411, and the first-stage flip-flop 2401_n−1 illustrated in FIG. The second wiring 122 illustrated in FIG. 1A is connected to the ninth wiring 2419, and the second wiring 122 illustrated in FIG. 1A of the n-th flip-flop 2401_n is connected to the eighth wiring 2418.

Note that in the case where the timing chart in FIG. 23 is applied to the flip-flop of this embodiment, the second wiring 122 illustrated in FIG. 1A of the i-th flip-flop 2401_i is connected to the tenth wiring 2420_i + 3. Is done. Therefore, the second wiring 122 illustrated in FIG. 1A of the n-3th flip-flop 1801_n-3 is connected to the newly added wiring.

Note that the first wiring 2411, the second wiring 2412, the third wiring 2413, the fourth wiring 1914, the fifth wiring 2415, the eighth wiring 2424, and the ninth wiring 2419 are respectively connected to the first signal. May be called a line, a second signal line, a third signal line, a fourth signal line, a fifth signal line, a sixth signal line, or a seventh wiring. Further, the sixth wiring 2416 and the seventh wiring 2417 may be referred to as a first power supply line and a second power supply line, respectively.

Next, operation of the shift register illustrated in FIG. 18 is described with reference to a timing chart in FIG. 25 and a timing chart in FIG. Here, the timing chart of FIG. 25 is divided into a scanning period and a blanking period.

Note that the potential of V 1 is supplied to the fourth wiring 2416 and the potential of V 2 is supplied to the fifth wiring 2417.

Note that the first wiring 2411, the second wiring 2412, the third wiring 2413, the fourth wiring 2514, the fifth wiring 2415, the eighth wiring 2418, and the ninth wiring 2419 are illustrated in FIG. A signal 2511, a signal 2512, a signal 2513, a signal 2514, a signal 2515, a signal 2518, and a signal 2519 are input. Here, in the signal 2511, the signal 2512, the signal 2513, the signal 2514, the signal 2515, the signal 2518, and the signal 2519, the potential of the H signal is V1 (hereinafter also referred to as H level), and the potential of the L signal is V2 (hereinafter referred to as L). Digital signal). Further, the signal 2511, the signal 2512, the signal 2513, the signal 2514, the signal 2515, the signal 2518, and the signal 2519 are respectively converted into a start signal, a first clock signal, a second clock signal, a third clock signal, and a fourth clock. You may call a signal, a 1st reset signal, and a 2nd reset signal.

Note that various signals, potentials, and currents may be input to the first wiring 2411 to the ninth wiring 2419, respectively.

Note that the tenth wiring 2420_1 to the tenth wiring 2420_n each receive a digital signal with an H signal potential of V1 (hereinafter also referred to as an H level) and an L signal potential of V2 (hereinafter also referred to as an L level). Is output. Further, as in Embodiment 1, the range of operating conditions can be increased by buffer connection to the tenth wiring 2420_1 to the tenth wiring 2420_n.

Note that a signal output from the tenth wiring 2420_i-1 is used as a start signal of the flip-flop 2401_i, and a signal output from the tenth wiring 2420_i + 2 is used as a reset signal. Here, the start signal of the flip-flop 2401_1 is input from the first wiring 2411, the second reset signal of the flip-flop 2401_n−1 is input from the ninth wiring 2419, and the first reset signal of the flip-flop 2401_n is Input from the eighth wiring 2418. Note that a signal output from the tenth wiring 2420_1 is used as the second reset signal of the flip-flop 2401_n-1, and a signal output from the tenth wiring 2420_2 is used as the first reset signal of the flip-flop 2401_n. It may be used. Alternatively, a signal output from the tenth wiring 2420_2 is used as the second reset signal of the flip-flop 2401_n-1, and a signal output from the tenth wiring 2420_3 is used as the first reset signal of the flip-flop 2401_n. It may be used. Alternatively, a first dummy flip-flop and a second dummy flip-flop are newly arranged, and an output signal of the first dummy flip-flop and an output signal of the second dummy flip-flop are respectively set to the first dummy flip-flop and the second dummy flip-flop. The reset signal and the second reset signal may be used. By doing so, the number of wirings and the number of signals can be reduced.

As illustrated in FIG. 26, for example, when the flip-flop 2401_i enters the first selection period, an H signal (selection signal) is output from the tenth wiring 2420_i. At this time, the flip-flop 2401_i + 1 is in the second set period. After that, when the flip-flop 2401_i enters the second selection period, the H signal is still output from the wiring 2420_i of the wiring 10. At this time, the flip-flop 2401_i + 1 is in the first selection period. After that, when the flip-flop 2401_i enters a reset period, an L signal is output from the tenth wiring 2420_i. At this time, the flip-flop 2401_i + 1 is in the second selection period. After that, when the flip-flop 2401_i enters the first non-selection period, the tenth wiring 2420_i enters a floating state and maintains the potential at V2. At this time, the flip-flop 2401_i + 1 is in a reset period. After that, when the flip-flop 2401_i enters the second non-selection period, an L signal is output from the tenth wiring 2420_i. At this time, the flip-flop 2401_i + 1 is in the second non-selection period.

In this manner, the shift register in FIG. 24 can output selection signals from the tenth wiring 2420_1 to the tenth wiring 2420_n in order. Further, in the shift register in FIG. 24, the second selection period of the flip-flop 2401_i and the first selection period of the flip-flop 2402_i + 1 are the same period; therefore, the tenth wiring 2420_i and the tenth selection period are the same. A selection signal can be output from the wiring 2420 — i + 1.

Further, the shift register to which the flip-flop of this embodiment is applied can suppress a shift in threshold voltage of the transistor, so that the lifetime can be extended. Furthermore, since the shift register to which the flip-flop of this embodiment is applied is resistant to noise, reliability can be improved. Further, the shift register to which the flip-flop of this embodiment is applied can suppress malfunction.

Further, the shift register to which the flip-flop of this embodiment is applied can operate at high speed, and thus can be applied to a higher-definition display device or a larger display device. Further, the process of the flip-flop of this embodiment can be simplified. Further, a shift register to which the flip-flop of this embodiment is applied can reduce manufacturing costs. Further, the shift register to which the flip-flop of this embodiment is applied can improve yield.

Next, a structure and driving method of the display device including the shift register of this embodiment described above will be described. Note that the display device of this embodiment mode includes at least the flip-flop of this embodiment mode.

A structure of the display device of this embodiment is described with reference to FIG. In the display device of FIG. 27, the scanning lines G1 to Gn are scanned by the scanning line driving circuit 2702. Further, in the display device in FIG. 27, video signals are input from odd-numbered signal lines to odd-numbered pixels 1703, and video signals are input to even-numbered pixels 1703 from even-numbered signal lines. . Note that portions common to the configuration in FIG.

Note that the display device in FIG. 27 can perform the same operation as the display device in FIG. 20 with one scan line driver circuit by applying the shift register of this embodiment to the scan line driver circuit 2702. Therefore, the display device in FIG. 27 can write a video signal to a pixel at high speed. Further, the display device in FIG. 27 can have a long lifetime. Further, the display device in FIG. 27 can be increased in size. Further, the display device in FIG. 27 can achieve higher definition. Further, the display device in FIG. 27 can save power. Further, the display device of FIG. 27 can suppress the heat generation of the IC. Further, the display device in FIG. 27 can save power in the IC.

Note that as shown in FIG. 28, the scanning lines G1 to Gn may be scanned by the first scanning line driving circuit 2802a and the second scanning line driving circuit 2802b. The first scan line driver circuit 2802a and the second drive circuit 2802b have the same configuration as the scan line driver circuit 2702 shown in FIG. 27, and scan the scan lines G1 to Gn at the same timing. Further, the first scan line driver circuit 2802a and the second driver circuit 2802b may be referred to as a first driver circuit and a second driver circuit, respectively.

In the display device in FIG. 28, even if one of the first scan line driver circuit 2802a and the second scan line driver circuit 2802b is defective, the scan line driver circuit 2802a and the second scan line driver circuit 2802b are Since the other can scan the scanning lines G1 to Gn, it can have redundancy. Further, in the display device in FIG. 28, since the first scan line driver circuit 2802a and the second scan line driver circuit 2802b scan the scan lines G1 to Gn, the load on the first scan line driver circuit 2802a ( The wiring resistance of the scanning line and the parasitic capacitance of the scanning line) and the load of the second scanning line driver circuit 2802b can be halved compared to FIG. Accordingly, in the display device in FIG. 28, the load on the first scan line driver circuit 2802a and the load on the second scan line driver circuit 2802b are reduced, and thus signals (first signals) input to the scan lines G1 to Gn. Delay and rounding of output signals of one scan line driver circuit 2802a and second driver circuit 2802b can be reduced. Further, since the load on the first scan line driver circuit 2802a and the load on the second scan line driver circuit 2802b are reduced, the display device in FIG. 28 can scan the scan lines G1 to Gn at high speed. it can. Furthermore, since the scanning lines G1 to Gn can be scanned at high speed, the panel can be enlarged or the panel can be made high definition. Note that portions common to the configuration in FIG.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination, or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 3)
In this embodiment, a structure and a driving method of a flip-flop different from those in Embodiments 1 and 2, a driving circuit including the flip-flop, and a display device including the driving circuit will be described. The flip-flop of this embodiment is characterized in that the output signal of the flip-flop and the transfer signal of the flip-flop are output from different wirings by different transistors. Note that components similar to those in Embodiments 1 and 2 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

A basic structure of the flip-flop of this embodiment is described with reference to FIG. 40 includes a first transistor 101, a second transistor 102, a third transistor 103, a fourth transistor 104, a fifth transistor 105, a sixth transistor 106, a seventh transistor 107, An eighth transistor 108, a ninth transistor 109, and a tenth transistor 110 are included. In this embodiment, the ninth transistor 109 and the tenth transistor 110 are N-channel transistors and are turned on when a gate-source voltage (Vgs) exceeds a threshold voltage (Vth). And

Note that the flip-flop in FIG. 40 is similar to the flip-flop in FIG. 1A in which a ninth transistor 109 and a tenth transistor 110 are added. Therefore, the first transistor 101, the second transistor 102, the third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, the transistor 107 of the seventh transistor, and the eighth transistor 108 are The thing similar to FIG. 1 can be used.

Connection relations of the flip-flop of FIG. 40 will be described. The first electrode (one of the source electrode and the drain electrode) of the first transistor 101 is connected to the fifth wiring 125, and the second electrode (the other of the source electrode and the drain electrode) of the first transistor 101 is the first electrode. 3 wiring 123. The first electrode of the second transistor 102 is connected to the fourth wiring 124, the second electrode of the second transistor 102 is connected to the third wiring 123, and the gate electrode of the second transistor 102 is connected to the first wiring 124. 8 wiring 128. The first electrode of the third transistor 103 is connected to the sixth wiring 126, the second electrode of the third transistor 103 is connected to the gate electrode of the sixth transistor 106, and the gate of the third transistor 103 The electrode is connected to the seventh wiring 127. The first electrode of the fourth transistor 104 is connected to the tenth wiring 130, the second electrode of the fourth transistor 104 is connected to the gate electrode of the sixth transistor 106, and the gate of the fourth transistor 104 The electrode is connected to the eighth wiring 128. The first electrode of the fifth transistor 105 is connected to the ninth wiring 129, and the second electrode of the fifth transistor 105 is connected to the first transistor 101.
The gate electrode of the fifth transistor 105 is connected to the first wiring 121. The first electrode of the sixth transistor 106 is connected to the twelfth wiring 132, and the second electrode of the sixth transistor 106 is connected to the gate electrode of the first transistor 101. The first electrode of the seventh transistor 107 is connected to the thirteenth wiring 133, the second electrode of the seventh transistor 107 is connected to the gate electrode of the first transistor 101, and the gate of the seventh transistor 107 The electrode is connected to the second wiring 122. The first electrode of the eighth transistor 108 is connected to the eleventh wiring 131, the second electrode of the eighth transistor 108 is connected to the gate electrode of the sixth transistor 106, and the gate of the eighth transistor 108 The electrode is connected to the gate electrode of the first transistor 101. The first electrode of the ninth transistor 109 is connected to the fifteenth wiring 135, the second electrode of the ninth transistor 109 is connected to the fourteenth wiring 134, and the gate electrode of the ninth transistor 109 is connected to the first wiring 135. 1 is connected to the gate electrode of one transistor 101. The first electrode of the tenth transistor 110 is connected to the sixteenth wiring 136, the second electrode of the tenth transistor 110 is connected to the fourteenth wiring 134, and the gate electrode of the tenth transistor 110 is connected to the first wiring 136. 8 wiring 128.

Note that the first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, the seventh wiring 127, the eighth wiring 128, the fourteenth wiring 134, and the fifteenth wiring 135 are connected. , Called a first signal line, a second signal, a third signal line, a fourth signal line, a fifth signal line, a sixth signal line, a seventh signal line, and an eighth signal line, respectively. But you can. Further, the fourth wiring 124, the sixth wiring 126, the ninth wiring 129, the tenth wiring 130, the wiring 131, the twelfth wiring 132, the thirteenth wiring 133, and the sixteenth wiring 136, These are called a first power line, a second power line, a third power line, a fourth power line, a fifth power line, a sixth power line, a seventh power line, and an eighth power line, respectively. But you can.

Next, the operation of the flip-flop shown in FIG. 40 will be described with reference to the timing chart of FIG. Further, the timing chart of FIG. 41 will be described by being divided into a set period, a selection period, a reset period, a first non-selection period, and a second non-selection period. However, the set period, the reset period, the first non-selection period, and the second non-selection period may be collectively referred to as a non-selection period.

Note that the potential of V1 is supplied to the sixth wiring 126 and the ninth wiring 129, and the fourth wiring 124, the tenth wiring 130, the eleventh wiring 131, the twelfth wiring 132, and the thirteenth wiring. The potential of V2 is supplied to the 133th and 16th wirings 136. Here, V1> V2.

Note that the first wiring 121, the fifth wiring 125, the eighth wiring 128, the seventh wiring 127, and the second wiring 122 are respectively provided with a signal 221, a signal 225, a signal 228, and a signal 227 illustrated in FIG. , A signal 222 is input. Further, a signal 225 shown in FIG. 24 is input to the fifteenth wiring 135. Here, as the signal 221, the signal 225, the signal 228, the signal 227, and the signal 222, the same signals as in FIG. 2 or FIG. 6 can be used.

However, various signals, potentials, and currents are input to the first wiring 121, the second wiring 122, the fourth wiring 124 to the thirteenth wiring 133, the fifteenth wiring 135, and the sixteenth wiring 136, respectively. May be.

Note that a signal 223 and a signal 234 are output from the third wiring 123 and the fourteenth wiring 134, respectively. Signal 234 is an output signal of the flip-flop, and signal 223 is a transfer signal of the flip-flop. However, the signal 223 may be the output signal of the flip-flop, and the signal 234 may be the transfer signal of the flip-flop.

Therefore, when the signal 234 is used as an output signal of the flip-flop and the signal 223 is used as a transfer signal of the flip-flop, the value of W / L of the ninth transistor 109 is set to W / L of the first transistor 101 to the tenth transistor 110. It is good to make it the maximum in L. However, in the case where the signal 223 is used as an output signal of the flip-flop and the signal 234 is used as a transfer signal of the flip-flop, the value of W / L of the first transistor 101 is set to W / L of the first transistor 101 to the tenth transistor 110. The largest among L.

In this embodiment mode, as described above, the output signal of the flip-flop and the transfer signal of the flip-flop are output from different wirings by different transistors. That is, the flip-flop in FIG. 40 outputs a signal from the third wiring 123 by the first transistor 101 and the second transistor 102, and from the fourteenth wiring 134 by the ninth transistor 109 and the tenth transistor 110. Output a signal. Further, since the ninth transistor 109 and the tenth transistor 110 are connected in the same manner as the first transistor 101 and the second transistor 102, a signal output from the fourteenth wiring 134 as shown in FIG. (Signal 234) has substantially the same waveform as the signal (signal 223) output from the third wiring 123.

Note that the first transistor 101 only needs to supply electric charge to the gate electrode of the fifth transistor 105 in the next stage. Therefore, the value of W / L of the first transistor 101 is set to W / L of the fifth transistor 105. It is preferable that the value be equal to or less than twice the value of L, and more preferably, be equal to or less than the value of W / L of the fifth transistor 105.

Note that the ninth transistor 109 and the tenth transistor 110 have functions similar to those of the first transistor 101 and the second transistor 102, respectively. Further, the ninth transistor 109 and the tenth transistor 110 may be referred to as a buffer portion.

As described above, the flip-flop in FIG. 40 can prevent malfunction even when a large load is connected to the fourteenth wiring 134 and a delay or a rounding occurs in the signal 234. This is because the flip-flop in FIG. 40 is not affected by delay or rounding of the output signal by outputting the output signal of the flip-flop and the transfer signal of the flip-flop from different wirings by different transistors. It is.

Furthermore, since the flip-flop of this embodiment can operate at high speed, it can be applied to a higher-definition display device or a larger display device. Further, the flip-flop of this embodiment can simplify the process. Further, the flip-flop of this embodiment can reduce manufacturing costs. Further, the flip-flop of this embodiment can improve yield.

Note that the flip-flop of this embodiment includes the flip-flops illustrated in FIGS. 1B, 1C, 5A, 5B, 5C, 7A, and 7C. B), FIG. 8A, FIG. 8B, FIG. 9A, FIG. 9B, FIG. 10A, and FIG. 10B can be freely combined. Further, the flip-flop of this embodiment can be implemented by being freely combined with the driving timing described in Embodiment 1 and the driving timing described in Embodiment 2.

Next, a structure and driving method of the shift register including the flip-flop of this embodiment described above will be described.

The structure of the shift register of this embodiment is described with reference to FIG. The shift register in FIG. 42 includes n flip-flops (flip-flop 4201_1 to flip-flop 4201_n).

Connection relations of the shift register in FIG. 42 are described. In the shift register in FIG. 42, the i-th flip-flop 4201_i (any one of the flip-flops 4201_1 to 4201_n) has the first wiring 121 illustrated in FIG. 40 connected to the seventh wiring 4217_i−1. The second wiring 122 illustrated in FIG. 40 is connected to the seventh wiring 4217_i + 1, the third wiring 123 illustrated in FIG. 40 is connected to the seventh wiring 4217_i, and the fourth wiring 124 illustrated in FIG. The tenth wiring 130, the eleventh wiring 131, the twelfth wiring 132, the thirteenth wiring 133, and the sixteenth wiring 136 are connected to the fifth wiring 4215, and the fifth wiring 125 shown in FIG. The seventh wiring 127 and the fifteenth wiring 135 are connected to the second wiring 4212 in the odd-numbered flip-flop, and the third wiring in the even-numbered flip-flop. The eighth wiring 128 shown in FIG. 40 is connected to the third wiring 4213 in the odd-numbered flip-flops, and is connected to the second wiring 4212 in the even-numbered flip-flops. The sixth wiring 126 and the ninth wiring 129 shown in FIG. 40 are connected to the fourth wiring 4214, and the fourteenth wiring 134 shown in FIG. 40 is connected to the eighth wiring 4218_i. Note that the first wiring 121 illustrated in FIG. 40 of the first flip-flop 4201_1 is connected to the first wiring 4211, and the second wiring 122 illustrated in FIG. 40 of the n-th flip-flop 4201_n is the sixth wiring. Connected to the wiring 4216.

Note that the first wiring 4211, the second wiring 4212, the third wiring 4213, and the sixth wiring 4216 are respectively connected to the first signal line, the second signal line, the third signal line, and the fourth signal. You may call it a line. Further, the fourth wiring 4214 and the fifth wiring 4215 may be referred to as a first power supply line and a second power supply line, respectively.

Next, operation of the shift register illustrated in FIG. 42 is described with reference to a timing chart in FIG.

Note that the first wiring 4211, the second wiring 4212, the third wiring 4213, the fourth wiring 4214, the fifth wiring 4215, and the sixth wiring 4216 include a signal 4311, a signal 4312, a signal 4313, and a signal. 4314, a signal 4315, and a signal 4216 are input. The signal 4311, the signal 4312, the signal 4313, the signal 4314, the signal 4315, and the signal 4216 correspond to the signal 211, the signal 212, the signal 213, the signal 214, the signal 215, and the signal 216, respectively.

Note that the potential of the H signal is V1 (hereinafter also referred to as H level) and the potential of the L signal is V2 from the seventh wiring 4217_1 to the seventh wiring 4217_n and the eighth wiring 4218_1 to the eighth wiring 4218_n, respectively. A digital signal (hereinafter also referred to as L level) is output.

As illustrated in FIG. 43, for example, when the flip-flop 4201_i enters the selection period, an H signal (selection signal) is output from the seventh wiring 4217_i and the eighth wiring 4218_i. At this time, the flip-flop 4201_i + 1 is in the set period. After that, the flip-flop 4201_i enters a reset period, and an L signal is output from the seventh wiring 4217_i and the eighth wiring 4218_i. At this time, the flip-flop 4201_i + 1 is in a selection period. After that, the flip-flop 4201_i enters the first non-selection period, and the seventh wiring 4217_i and the eighth wiring 4218_i are in a floating state and maintain the potential at V2. At this time, the flip-flop 4201_i + 1 is in a reset period. After that, the flip-flop 4201_i enters the second non-selection period, and an L signal is output from the seventh wiring 4217_i and the eighth wiring 4218_i. At this time, the flip-flop 4201_i + 1 is in the first non-selection period.

In this manner, the shift register in FIG. 42 transmits transfer signals to the seventh wiring 4217_1 in order from the seventh wiring 4217_1.
The wiring 4217_n can be output. Further, the shift register in FIG. 42 can output selection signals from the eighth wiring 4218_1 to the eighth wiring 4218_n in order. That is, the shift register in FIG. 42 can scan the eighth wiring 4218_1 to the eighth wiring 4218_n. Therefore, the shift register in FIG. 42 can sufficiently obtain a function as a shift register.

Further, the shift register in FIG. 42 can operate without being affected by the load even when a large load (such as a resistor or a capacitor) is connected to the eighth wiring 4218_1 to the eighth wiring 4218_n. Further, the shift register in FIG. 42 can continue normal operation even when any of the eighth wiring 4218_1 to the eighth wiring 4218_n is short-circuited to a power supply line or a signal line. Therefore, the shift register of FIG. 42 can improve the range of operating conditions. Further, the shift register in FIG. 42 can improve reliability. Further, the shift register in FIG. 42 can improve yield. This is because the shift register of FIG. 42 divides the transfer signal of each flip-flop and the output signal of each flip-flop.

Further, the shift register to which the flip-flop of this embodiment is applied can suppress a shift in threshold voltage of the transistor. Further, the life of the shift register to which the flip-flop of this embodiment is applied can be extended. Further, the shift register to which the flip-flop of this embodiment is applied can improve reliability. Further, the shift register to which the flip-flop of this embodiment is applied can suppress malfunction. Further, the shift register to which the flip-flop of this embodiment is applied can be applied to a higher-definition display device or a larger display device. Further, the shift register to which the flip-flop of this embodiment is applied can simplify the process. Further, a shift register to which the flip-flop of this embodiment is applied can reduce manufacturing costs. Further, the shift register to which the flip-flop of this embodiment is applied can improve yield.

As the display device in this embodiment, the display devices in FIGS. 17, 19, 20, 27, and 28 can be used. Therefore, the display device using the shift register of this embodiment as the scan line driver circuit can suppress a shift in the threshold voltage of the transistor. Furthermore, the display device of this embodiment can have a long lifetime. Furthermore, the display device of this embodiment can improve reliability. Furthermore, the display device in this embodiment can suppress malfunction. Furthermore, the display device in this embodiment can have higher definition or larger size. Further, the display device of this embodiment can simplify the process. Furthermore, the display device of this embodiment can reduce manufacturing costs. Further, the display device in this embodiment can improve yield. Furthermore, the display device of this embodiment can save power in the driver IC. Furthermore, the display device of this embodiment can suppress the heat generation of the driver IC.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination, or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 4)
In this embodiment, the case where a p-channel transistor is used as a transistor included in the flip-flop of this specification will be described. Further, a structure and a driving method of a driver circuit including the flip-flop and a display device including the driver circuit are described.

In the flip-flop of this embodiment, the case where the polarity of the transistor included in the flip-flop in FIG. However, FIG. 1 (B), FIG. 1 (C), FIG. 5 (A), FIG. 5 (B), FIG. 5 (C), FIG. 7 (A), FIG. 7 (B), FIG. The polarity of the transistor included in the flip-flop illustrated in FIG. 8B, FIG. 9A, FIG. 9B, FIG. 10A, FIG. 10B, or FIG. You can also. Further, the flip-flop of this embodiment can be implemented by being freely combined with the description in Embodiments 1 to 3.

A basic structure of the flip-flop of this embodiment is described with reference to FIG. 44 includes a first transistor 4401, a second transistor 4402, a third transistor 4403, a fourth transistor 4404, a fifth transistor 4405, a sixth transistor 4406, a seventh transistor 4407, and the like. An eighth transistor 4408 is included. In this embodiment, the first transistor 4401, the second transistor 4402, the third transistor 4403, the fourth transistor 4404, the fifth transistor 4405, the sixth transistor 4406, the seventh transistor 4407, and the transistor 4408 are used. Is a P-channel transistor, and becomes conductive when the absolute value of the gate-source voltage (| Vgs |) exceeds the absolute value of the threshold voltage (| Vth |) (when Vgs falls below Vth). Shall be.

Note that the flip-flop of this embodiment is characterized in that the first transistor 4401 to the eighth transistor 4408 are all P-channel transistors. Therefore, the flip-flop of this embodiment can simplify the manufacturing process. Further, the flip-flop of this embodiment can reduce manufacturing costs. Further, the flip-flop of this embodiment can improve yield.

A connection relation of the flip-flop of FIG. 44 will be described. A first electrode (one of a source electrode and a drain electrode) of the first transistor 4401 is connected to a fifth wiring 4425, and a second electrode (the other of the source electrode and the drain electrode) of the first transistor 4401 is connected to a first wiring. 3 wiring 4423. A second electrode of the second transistor 4402 is connected to the fourth wiring 4424, a second electrode of the second transistor 4402 is connected to the third wiring 4423, and a gate electrode of the second transistor 4402 is connected to the eighth wiring 4423. Is connected to the wiring 4428. The first electrode of the third transistor 4403 is connected to the sixth wiring 4426, the second electrode of the third transistor 4403 is connected to the gate electrode of the sixth transistor 4406, and the gate of the third transistor 4403 The electrode is connected to the seventh wiring 4427. The first electrode of the fourth transistor 4404 is connected to the tenth wiring 4430, the second electrode of the fourth transistor 4404 is connected to the gate electrode of the sixth transistor 4406, and the gate of the fourth transistor 4404 The electrode is connected to the eighth wiring 4428. A first electrode of the fifth transistor 4405 is connected to the ninth wiring 4429, a second electrode of the fifth transistor 4405 is connected to a gate electrode of the first transistor 4401, and a gate of the fifth transistor 4405 The electrode is connected to the first wiring 4421. A first electrode of the sixth transistor 4406 is connected to the twelfth wiring 4432, and a second electrode of the sixth transistor 4406 is connected to a gate electrode of the first transistor 4401. The first electrode of the seventh transistor 4407 is connected to the thirteenth wiring 4433, the second electrode of the seventh transistor 4407 is connected to the gate electrode of the first transistor 4401, and the gate of the seventh transistor 4407 The electrode is connected to the second wiring 4422. The first electrode of the eighth transistor 4408 is connected to the eleventh wiring 4431, the second electrode of the eighth transistor 4408 is connected to the gate electrode of the sixth transistor 4406, and the gate of the eighth transistor 4408 The electrode is connected to the gate electrode of the first transistor 4401.

Note that the gate electrode of the first transistor 4401, the second electrode of the fifth transistor 4405, the second electrode of the sixth transistor 4406, the second electrode of the seventh transistor 4407, and the eighth transistor 4408 A connection position of the gate electrode is a node 4441. Further, a connection position of the second electrode of the third transistor 4403, the second electrode of the fourth transistor 4404, the gate electrode of the sixth transistor 4406, and the second electrode of the eighth transistor 4408 is connected to the node 4442. To do.

Note that the first wiring 4421, the second wiring 4422, the third wiring 4423, the fifth wiring 4425, the seventh wiring 4427, and the eighth wiring 4428 are respectively connected to the first signal line and the second signal 4428. , A third signal line, a fourth signal line, a fifth signal line, and a sixth signal line. Further, the fourth wiring 4424, the sixth wiring 4426, the ninth wiring 4429, the tenth wiring 4430, the wiring 4431 of the eleventh, the twelfth wiring 4432, and the thirteenth wiring 4433 are respectively connected to the first power supply line. , The second power line, the third power line, the fourth power line, the fifth power line, the sixth power line, and the seventh power line.

Next, the operation of the flip-flop shown in FIG. 44 will be described with reference to the timing chart of FIG. Further, the timing chart of FIG. 45 will be described by being divided into a set period, a selection period, a reset period, a first non-selection period, and a second non-selection period. However, the set period, the reset period, the first non-selection period, and the second non-selection period may be collectively referred to as a non-selection period.

Note that the timing chart of FIG. 45 is the same as that obtained by inverting the H level and L level of the timing chart of FIG.

Note that the potential of V2 is supplied to the sixth wiring 4426 and the ninth wiring 4429, and the fourth wiring 4424, the tenth wiring 4430, the eleventh wiring 4431, the twelfth wiring 4432, and the thirteenth wiring. 4433 is supplied with the potential of V1. Here, V1> V2.

Note that the first wiring 4421, the fifth wiring 4425, the eighth wiring 4428, the seventh wiring 4427, and the second wiring 4422 are a signal 4521, a signal 4525, a signal 4528, and a signal 4527 shown in FIG. , A signal 4522 is input. A signal 4423 shown in FIG. 45 is output from the third wiring 4423. Here, in the signal 4421, the signal 4425, the signal 4428, the signal 4427, the signal 4422, and the signal 4423, the potential of the H signal is V1 (hereinafter also referred to as H level) and the potential of the L signal is V2 (hereinafter also referred to as L level). ) Digital signal. Further, the signal 4421, the signal 4425, the signal 4428, the signal 4427, the signal 4422, and the signal 4423 are respectively converted into a start signal, a power clock signal (PCK), a first control clock signal (CCK1), and a second control clock signal (CCK2). ), May be called a reset signal or an output signal.

Note that various signals, potentials, and currents may be input to the first wiring 4421, the second wiring 4422, and the fourth wiring 4424 to the thirteenth wiring 4433, respectively.

First, in the set period illustrated in FIG. 45A, the signal 4521 is L level and the fifth transistor 4405 is turned on. Since the signal 4422 is H level, the seventh transistor 4407 is turned off and the signal 4528 is L level. The second transistor 4402 and the fourth transistor 4404 are turned on, so that the signal 4527 becomes an H level and the third transistor 4403 is turned off. At this time, the potential of the node 4441 (the potential 4541) is the absolute value of the potential of the ninth wiring 4429 and the threshold voltage of the fifth transistor 4405 with the second electrode of the fifth transistor 4405 serving as a source electrode. Therefore, V2 + | Vth4405 | (Vth4405: threshold voltage of the fifth transistor 4405) is obtained. Accordingly, the first transistor 4401 and the eighth transistor 4408 are turned on, and the fifth transistor 4405 is turned off. At this time, the potential of the node 4442 (the potential 4542) is V1, and the sixth transistor 4406 is turned off. In this manner, in the set period, the third wiring 4423 is electrically connected to the fifth wiring 4425 and the fourth wiring 4424 to which the H signal is input, so that the potential of the third wiring 4423 becomes V1. Accordingly, the H signal is output from the third wiring 4423. Further, the node 4441 is in a floating state with the potential maintained at V2 + | Vth4405 |.

In the selection period shown in FIG. 45B, the signal 4521 is at the H level, the fifth transistor 4405 is turned off, and the signal 4522 remains at the H level, so the seventh transistor 4407 is kept off and the signal 4528 is at the H level. The second transistor 4402 and the fourth transistor 4404 are turned off, and the signal 4527 becomes the L level, and the third transistor 4503 is turned on. At this time, the potential of the node 4441 is maintained at V1 + | Vth4405 |. Accordingly, the first transistor 4401 and the eighth transistor 4408 remain on. At this time, the potential of the node 4442 is such that the potential difference (V1−V2) between the potential (V1) of the eleventh wiring 4431 and the potential (V2) of the sixth wiring 4426 is the third transistor 4403 and the eighth transistor 4408. Is divided into V1−θ (θ is an arbitrary positive number). Further, θ <| Vth4406 | (the threshold voltage of the sixth transistor 4406). Accordingly, the sixth transistor 4406 remains off. Here, since an L signal is input to the fifth wiring 4425, the potential of the third wiring 4423 starts to decrease. Then, the potential of the node 4441 decreases from V2 + | Vth4405 | by the bootstrap operation, and becomes V2− | Vth4401 | −γ (Vth4401: threshold voltage of the first transistor 4401, γ: any positive number). . Accordingly, the potential of the third wiring 4423 is equal to that of the fifth wiring 4425 and thus becomes V2. In this manner, in the selection period, the third wiring 4423 is electrically connected to the fifth wiring 4425 to which the L signal is input, so that the potential of the third wiring 4423 becomes V2. Accordingly, the L signal is output from the third wiring 4423.

In the reset period illustrated in FIG. 45C, since the signal 4521 remains at H level, the fifth transistor 4405 remains off, the signal 4522 becomes L level, the seventh transistor 4407 turns on, and the signal 4528 becomes L The second transistor 4402 and the fourth transistor 4404 are turned on, and the signal 4527 becomes the H level, and the third transistor 4403 is turned off. The potential of the node 4441 at this time is V1 because the potential (V1) of the thirteenth wiring 4433 is supplied through the seventh transistor 4407. Accordingly, the first transistor 4401 and the eighth transistor 4408 are turned off. At this time, the potential of the node 4442 becomes V1 because the fourth transistor 4404 is turned on. Accordingly, the sixth transistor 4406 is turned off. In this manner, in the reset period, the third wiring 4423 is electrically connected to the fourth wiring 4424 to which V1 is supplied, so that the potential of the third wiring 4423 becomes V1. Accordingly, the H signal is output from the third wiring 4423.

In the first non-selection period illustrated in FIG. 45D, since the signal 4521 remains at the H level, the fifth transistor 4405 remains off, the signal 4522 becomes the H level, and the seventh transistor 4407 is turned off. The signal 4528 becomes H level, the second transistor 4402 and the fourth transistor 4404 are turned off, the signal 4527 becomes L level, and the third transistor 4403 is turned on. At this time, the potential of the node 4442 is the absolute value of the potential (V2) of the seventh wiring 4427 and the threshold voltage of the third transistor 4403 with the second electrode of the third transistor 4403 serving as a source electrode. Therefore, V2 + | Vth4403 | (Vth4403: threshold voltage of the third transistor 4403). Accordingly, the sixth transistor 4406 is turned on. At this time, the potential of the node 4441 becomes V1 because the sixth transistor 4406 is turned on. Accordingly, the first transistor 4401 and the eighth transistor 4408 remain off. As described above, in the first non-selection period, the third wiring 4423 is in a floating state, and the potential is maintained at V1.

Note that the flip-flop of this embodiment can suppress a shift in threshold voltage of the second transistor 4402 by turning off the second transistor 4402.

In the second non-selection period shown in FIG. 45E, since the signal 4521 remains at the H level, the fifth transistor 4405 remains off, and since the signal 4522 remains at the H level, the seventh transistor 4407 is off. Thus, the signal 4528 becomes L level, the second transistor 4402 and the fourth transistor 4404 are turned on, the signal 4527 becomes H level, and the third transistor 4403 is turned off. At this time, the potential of the node 4442 becomes V1 and the sixth transistor 4406 is turned off. Since the node 4441 at this time is in a floating state, the potential is maintained at V1. Accordingly, the first transistor 4401 and the eighth transistor 4408 remain off. In this manner, in the second non-selection period, the third wiring 4423 is electrically connected to the fourth wiring 4424 to which V1 is supplied, so that the potential of the third wiring 4423 becomes V1. Accordingly, the H signal is output from the third wiring 4423.

Note that the flip-flop of this embodiment can suppress a shift in threshold voltage of the sixth transistor 4406 by turning off the sixth transistor 4406.

From the above, the flip-flop of this embodiment can suppress a shift in threshold voltage of the second transistor 4402 and the sixth transistor 4406, and thus can have a long lifetime. Further, the flip-flop of this embodiment can suppress a shift in threshold voltage of all transistors, so that the lifetime can be extended. Further, the flip-flop of this embodiment can improve reliability. Further, the flip-flop of this embodiment can suppress malfunction.

Note that the shift register of this embodiment can be implemented by freely combining the flip-flop of this embodiment with the shift register described in any of Embodiments 1 to 3. For example, the shift register of this embodiment mode can be implemented by freely combining the flip-flops of this embodiment mode with the shift registers of FIGS. 11, 14, 24, and 42. However, in the shift register of this embodiment, the H level and the L level are inverted as compared with the shift register described in any of Embodiments 1 to 3.

Note that the display device of this embodiment can be implemented by freely combining the shift register of this embodiment with the display device described in any of Embodiments 1 to 3. For example, the display device of this embodiment mode can be implemented in combination with the display devices of FIGS. 17, 19, 20, 27, and 28 freely. However, in the display device of this embodiment, the H level and the L level are inverted as compared with the display devices described in Embodiments 1 to 3.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination, or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 5)
In this embodiment, a signal line driver circuit included in the display device described in any of Embodiments 1 to 4 is described.

The signal line driver circuit of FIG. 31 will be described. The signal line driver circuit illustrated in FIG. 31 includes a driver IC 5601, switch groups 5602_1 to 5602_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first switch 5603a, a second switch 5603b, and a third switch 5603c.

The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M is connected to any of the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M corresponding to the switch groups 5602_1 to 5602_M. Each of the wirings 5621_1 to 5621_M is connected to three signal lines through the first switch 5603a, the second switch 5603b, and the third switch 5603c. For example, the wiring 5621_J (any one of the wirings 5621_1 to 5621_M) in the J-th column is connected to the signal line through the first switch 5603a, the second switch 5603b, and the third switch 5603c included in the switch group 5602_J. Sj−1, signal line Sj, and signal line Sj + 1 are connected.

Note that a signal is input to each of the first wiring 5611, the second wiring 5612, and the third wiring 5613.

Note that the driver IC 5601 is preferably formed over a single crystal substrate or a glass substrate using a polycrystalline semiconductor. Further, the switch group 5602 is preferably formed over the same substrate as the pixel portion described in Embodiments 1 to 4. Therefore, the driver IC 5601 and the switch group 5602 are preferably connected via an FPC or the like.

Next, operation of the signal line driver circuit illustrated in FIG. 31 is described with reference to a timing chart of FIG. Note that the timing chart of FIG. 32 shows the timing chart when the i-th scanning line Gi is selected. Further, the selection period of the i-th scanning line Gi is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line driver circuit in FIG. 31 operates in the same manner as in FIG. 32 even when a scan line in another row is selected.

Note that in the timing chart of FIG. 32, the wiring 5621_J in the J-th column is connected to the signal line Sj−1, the signal line Sj, and the signal line Sj + 1 through the first switch 5603a, the second switch 5603b, and the third switch 5603c. It shows the case of being connected to.

Note that in the timing chart of FIG. 32, the timing at which the i-th scanning line Gi is selected, the on / off timing 5703a of the first switch 5603a, the on / off timing 5703b of the second switch 5603b, The on / off timing 5703c of the switch 5603c and the signal 5721_J input to the wiring 5621_J in the J-th column are shown.

Note that different video signals are input to the wirings 5621_1 to 5621_M in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3. For example, a video signal input to the wiring 5621_J in the first sub-selection period T1 is input to the signal line Sj-1, and a video signal input to the wiring 5621_J in the second sub-selection period T2 is input to the signal line Sj. Then, the video signal input to the wiring 5621_J in the third sub-selection period T3 is input to the signal line Sj + 1. Further, in the selection period T1, the second sub-selection period T2, and the third sub-selection period T3, video signals input to the wiring 5621_J are Dataj-1, Dataj, and Dataj + 1, respectively.

As shown in FIG. 32, in the first sub-selection period T1, the first switch 5603a is turned on, and the second switch 5603b and the third switch 5603c are turned off. At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on, and the first switch 5603a and the third switch 5603c are turned off. At this time, Dataj input to the wiring 5621_J is input to the signal line Sj through the second switch 5603b. In the third sub-selection period T3, the third switch 5603c is turned on, and the first switch 5603a and the second switch 5603b are turned off. At this time, Dataj + 1 input to the wiring 5621_J is input to the signal line Sj + 1 through the third switch 5603c.

From the above, the signal line driver circuit in FIG. 31 can divide one gate selection period into three to input video signals from one wiring 5621 to three signal lines during one gate selection period. it can. Therefore, the signal line driver circuit in FIG. 31 can reduce the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed to about 1/3 of the number of signal lines. When the number of connections is about ３, the signal line driver circuit in FIG. 31 can improve reliability, yield, and the like.

Note that the number of connections between the substrate on which the pixel portion is formed and the external substrate can be further reduced by applying the signal line driver circuit of this embodiment to the display device described in Embodiments 1 to 4. . Therefore, the display device of the present invention can improve reliability. Furthermore, the display device of the present invention can increase the yield.

Next, the case where N-channel transistors are used for the first switch 5603a, the second switch 5603b, and the third switch 5603c will be described with reference to FIGS. Note that components similar to those in FIG. 31 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

The first transistor 5903a corresponds to the first switch 5603a, the second transistor 5903b corresponds to the second switch 5603b, and the third transistor 5903c corresponds to the third switch 5603c.

For example, in the case of the switch group 5602_J, the first transistor 5903a includes a first electrode connected to the wiring 5621_J, a second electrode connected to the signal line Sj-1, and a gate electrode connected to the first wiring 5611. Is done. In the second transistor 5903b, the first electrode is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj, and the gate electrode is connected to the second wiring 5612. In the third transistor 5903c, the first electrode is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj + 1, and the gate electrode is connected to the third wiring 5613.

Note that the first transistor 5903a, the second transistor 5903b, and the third transistor 5903c each function as a switching transistor. Further, the first transistor 5903a, the second transistor 5903b, and the third transistor 5903c are turned on when a signal input to the gate electrode is at an H level, and when the signal input to the gate electrode is at an L level. Turned off.

Note that by using N-channel transistors as the first switch 5603a, the second switch 5603b, and the third switch 5603c, amorphous silicon can be used as a semiconductor layer of the transistor, so that the manufacturing process is simplified. This is because the manufacturing cost can be reduced and the yield can be improved. Further, it is possible to manufacture a semiconductor device such as a large display panel. In addition, the manufacturing process can be simplified even if polysilicon or polycrystalline silicon is used as the semiconductor layer of the transistor.

In the signal line driver circuit in FIG. 33, the case where N-channel transistors are used as the first transistor 5903a, the second transistor 5903b, and the third transistor 5903c has been described; however, the first transistor 5903a, P-channel transistors may be used as the transistor 5903b and the third transistor 5903c. At this time, the transistor is turned on when the signal input to the gate electrode is at L level, and is turned off when the signal input to the gate electrode is at H level.

As shown in FIG. 31, if one gate selection period is divided into a plurality of sub-selection periods and a video signal can be input to each of a plurality of signal lines from one wiring in each of the plurality of sub-selection periods, There are no restrictions on the arrangement, number, or driving method.

For example, when a video signal is input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, a switch and a wiring for controlling the switch may be added. However, if one gate selection period is divided into four or more sub selection periods, one sub selection period is shortened. Therefore, it is desirable that one gate selection period is divided into two or three sub selection periods.

As another example, as shown in the timing chart of FIG. 34, one selection period is divided into a precharge period Tp, a first sub selection period T1, a second sub selection period T2, and a third selection period T3. May be. Further, in the timing chart of FIG. 34, the timing at which the i-th scanning line Gi is selected, the on / off timing 5803a of the first switch 5603a, the on / off timing 5803b of the second switch 5603b, ON / OFF timing 5803c of the switch 5603c and signal 5 input to the wiring 5621_J of the J-th column
821_J is shown. As shown in FIG. 34, the first switch 5603a, the second switch 5603b, and the third switch 5603c are turned on in the precharge period Tp. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal line Sj−1, the signal line Sj, and the signal line Sj + 1 through the first switch 5603a, the second switch 5603b, and the third switch 5603c, respectively. Is done. In the first sub-selection period T1, the first switch 5603a is turned on, and the second switch 5603b and the third switch 5603c are turned off. At this time, Dataj-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first switch 5603a. In the second sub-selection period T2, the second switch 5603b is turned on, and the first switch 5603a and the third switch 5603c are turned off. At this time, Dataj input to the wiring 5621_J is input to the signal line Sj through the second switch 5603b. In the third sub-selection period T3, the third switch 5603c is turned on, and the first switch 5603a and the second switch 5603b are turned off. At this time, Dataj + 1 input to the wiring 5621_J is input to the signal line Sj + 1 through the third switch 5603c.

From the above, the signal line driver circuit in FIG. 31 to which the timing chart in FIG. 34 is applied can precharge the signal line by providing the precharge selection period before the sub selection period. Can be written at high speed. Note that components similar to those in FIG. 32 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

Also in FIG. 35, as shown in FIG. 31, one gate selection period is divided into a plurality of sub-selection periods, and a video signal is input to each of a plurality of signal lines from one wiring in each of the plurality of sub-selection periods. it can. Note that FIG. 35 illustrates only the switch group 6022 </ b> _J in the J column in the signal line driver circuit. The switch group 6022_J includes a first transistor 6001, a second transistor 6002, a third transistor 6003, a fourth transistor 6004, a fifth transistor 6005, and a sixth transistor 6006. The first transistor 6001, the second transistor 6002, the third transistor 6003, the fourth transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 are N-channel transistors. The switch group 6022_J includes a first wiring 6011, a second wiring 6012, a third wiring 6013, a fourth wiring 6014, a fifth wiring 6015, a sixth wiring 6016, a wiring 5621_J, a signal line Sj-1, The signal line Sj is connected to the signal line Sj + 1.

The first electrode of the first transistor 6001 is connected to the wiring 5621_J, the second electrode is connected to the signal line Sj-1, and the gate electrode is connected to the first wiring 6011. A first electrode of the second transistor 6002 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj-1, and a gate electrode is connected to the second wiring 6012. A first electrode of the third transistor 6003 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj, and a gate electrode is connected to the third wiring 6013. A first electrode of the fourth transistor 6004 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj, and a gate electrode is connected to the fourth wiring 6014. A first electrode of the fifth transistor 6005 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj + 1, and a gate electrode is connected to the fifth wiring 6015. A first electrode of the sixth transistor 6006 is connected to the wiring 5621_J, a second electrode is connected to the signal line Sj + 1, and a gate electrode is connected to the sixth wiring 6016.

Note that the first transistor 6001, the second transistor 6002, the third transistor 6003, the fourth transistor 6004, the fifth transistor 6005, and the sixth transistor 6006 each function as a switching transistor. Further, in each of the first transistor 6001, the second transistor 6002, the third transistor 6003, the fourth transistor 6004, the fifth transistor 6005, and the sixth transistor 6006, a signal input to the gate electrode is H level. Is turned on when the signal is input, and is turned off when the signal input to the gate electrode is at the L level.

Note that the first wiring 6011 and the second wiring 6012 correspond to the first wiring 5911 in FIG. The third wiring 6013 and the fourth wiring 6014 correspond to the second wiring 5912 in FIG. The fifth wiring 6015 and the sixth wiring 6016 correspond to the third wiring 5913 in FIG. Note that the first transistor 6001 and the second transistor 6002 correspond to the first transistor 5903a in FIG. The third transistor 6003 and the fourth transistor 6004 correspond to the second transistor 5903b in FIG. The fifth transistor 6005 and the sixth transistor 6006 correspond to the third transistor 5903c in FIG.

35, either the first transistor 6001 or the second transistor 6002 is turned on in the first sub-selection period T1 shown in FIG. In the second sub-selection period T2, either the third transistor 6003 or the fourth transistor 6004 is turned on. In the third sub-selection period T3, either the fifth transistor 6005 or the sixth transistor 6006 is turned on. Further, any of the first transistor 6001, the third transistor 6003, and the fifth transistor 6005, the second transistor 6002, the fourth transistor 6004, and the sixth transistor 6006 in the precharge period Tp shown in FIG. Turns on.

Therefore, in FIG. 35, since the on-time of each transistor can be shortened, deterioration of characteristics of each transistor can be suppressed. This is because, for example, in the first sub-selection period T1 shown in FIG. 32, if either the first transistor 6001 or the second transistor 6002 is on, a video signal is input to the signal line Sj-1. Because you can. Note that, for example, in the first sub-selection period T1 illustrated in FIG. 32, the first transistor 6001 and the second transistor 6002 are simultaneously turned on, so that a video signal can be input to the signal line Sj-1 at high speed. it can.

Note that FIG. 35 illustrates the case where two transistors are connected in parallel between the wiring 5621 and the signal line. However, the invention is not limited to this, and three or more transistors may be connected in parallel between the wiring 5621 and the signal line. By doing so, it is possible to further suppress the characteristic deterioration of each transistor.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or they can be combined. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents or part of the contents described in each drawing in this embodiment mode can be applied to the contents or a part of the contents described in the drawing in another embodiment mode. Or they can be combined. . Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that this embodiment is an example in which the content described in the other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, an example in which the content is improved, and details An example of the case described, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Or they can be combined. .

(Embodiment 6)
In this embodiment, a structure for preventing a defect due to electrostatic breakdown of the display device described in any of Embodiments 1 to 4 will be described.

Note that electrostatic breakdown means that when a positive or negative charge accumulated in a human body or object is instantaneously discharged through the input / output terminals of the device when a semiconductor device is touched, a large current is generated inside the device. It is the destruction that occurs by flowing.

FIG. 36A shows a structure for preventing electrostatic breakdown generated in the scanning line by the protective diode. FIG. 36A illustrates a structure in which the protective diode is provided between the wiring 6111 and the scan line. Although not shown, a plurality of pixels are connected to the i-th scanning line Gi. Note that a transistor 6101 is used as the protective diode. Note that the transistor 6101 is an N-channel transistor. Note that a p-channel transistor may be used, and the transistor 6101 may have a polarity similar to that of the transistor included in the scan line driver circuit or the pixel.

Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel.

The transistor 6101 has a first electrode connected to the i-th scanning line Gi, a second electrode connected to the wiring 6111, and a gate electrode connected to the i-th scanning line Gi.

The operation of FIG. 36A will be described. A certain potential is input to the wiring 6111, and the potential is lower than the L level of the signal input to the i-th scanning line Gi. When positive or negative charges are not discharged to the i-th scanning line Gi, the transistor 6101 is off because the potential of the i-th scanning line Gi is at the H level or the L level. On the other hand, when negative charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi drops instantaneously. At this time, when the potential of the i-th scanning line Gi becomes lower than the value obtained by subtracting the threshold voltage of the transistor 6101 from the potential of the wiring 6111, the transistor 6101 is turned on and current flows through the transistor 6101. Flowing into. Therefore, with the structure illustrated in FIG. 36A, a large current can be prevented from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented.

Note that FIG. 36B illustrates a structure for preventing electrostatic breakdown when positive charges are discharged to the i-th scanning line Gi. A transistor 6102 functioning as a protective diode is provided between the scan line and the wiring 6112. Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel. Note that the transistor 6102 is an N-channel transistor. Note that a p-channel transistor may be used, and the transistor 6102 may have a polarity similar to that of the transistor included in the scan line driver circuit or the pixel. The transistor 6102 has a first electrode connected to the i-th scanning line Gi, a second electrode connected to the wiring 6112, and a gate electrode connected to the wiring 6112. Note that a potential higher than the H level of the signal input to the i-th scanning line Gi is input to the wiring 6112. Accordingly, the transistor 6102 is off when the electric charge is not discharged to the i-th scanning line Gi. On the other hand, when positive charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi rises instantaneously. At this time, when the potential of the i-th scanning line Gi becomes higher than the sum of the potential of the wiring 6112 and the threshold voltage of the transistor 6102, the transistor 6102 is turned on, and current flows to the wiring 6112 through the transistor 6102. Flowing. Therefore, the structure illustrated in FIG. 36B can prevent a large current from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented.

Note that as shown in FIG. 36C, by combining FIGS. 36A and 36B, even when positive charges are discharged to the i-th scanning line Gi. Even when negative charges are discharged to the i-th scanning line Gi, electrostatic breakdown of the pixels can be prevented. Note that components similar to those in FIGS. 36A and 36B are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

FIG. 37A illustrates a structure in the case where a transistor 6201 functioning as a protection diode is connected between a scan line and a storage capacitor line. Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel. Note that the transistor 6201 is an N-channel transistor. Note that a p-channel transistor may be used, and the transistor 6201 may have a polarity similar to that of the transistor included in the scan line driver circuit or the pixel. Note that the wiring 6211 functions as a storage capacitor line. A first electrode of the transistor 6201 is connected to the i-th scanning line Gi, a second electrode is connected to the wiring 6211, and a gate electrode is connected to the i-th scanning line Gi. Note that a potential lower than an L level of a signal input to the i-th scanning line Gi is input to the wiring 6211. Accordingly, the transistor 6201 is turned off when the electric charge is not discharged to the i-th scanning line Gi. On the other hand, when negative charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi drops instantaneously. At this time, when the potential of the i-th scanning line Gi is lower than a value obtained by subtracting the threshold voltage of the transistor 6201 from the potential of the wiring 6211, the transistor 6201 is turned on and current flows through the transistor 6201. Flowing into. Therefore, the structure illustrated in FIG. 37A can prevent a large current from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented. Further, in the structure illustrated in FIG. 37A, since the storage capacitor line is used as a wiring for releasing charge, it is not necessary to add a new wiring.

Note that FIG. 37B illustrates a structure for preventing electrostatic breakdown when positive charges are discharged to the i-th scanning line Gi. Here, a potential higher than the H level of the signal input to the i-th scanning line Gi is input to the wiring 6211. Accordingly, the transistor 6201 is turned off when the electric charge is not discharged to the i-th scanning line Gi. On the other hand, when positive charges are discharged to the i-th scanning line Gi, the potential of the i-th scanning line Gi rises instantaneously. At this time, when the potential of the i-th scanning line Gi becomes higher than the sum of the potential of the wiring 6211 and the threshold voltage of the transistor 6201, the transistor 6201 is turned on and current flows to the wiring 6211 through the transistor 6201. Flowing. Therefore, the structure illustrated in FIG. 37B can prevent a large current from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented. Further, in the structure illustrated in FIG. 37B, since the storage capacitor line is used as a wiring for releasing charge, it is not necessary to add a new wiring. Note that components similar to those in FIG. 37B are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

Next, FIG. 38A shows a structure for preventing electrostatic breakdown generated in the signal line by the protective diode. FIG. 38A illustrates a structure in the case where a protective diode is provided between the wiring 6411 and the signal line. Although not shown, a plurality of pixels are connected to the signal line Sj in the j-th column. Note that a transistor 6401 is used as the protective diode. Note that the transistor 6401 is an N-channel transistor. Note that a p-channel transistor may be used, and the transistor 6401 may have a polarity similar to that of the signal line driver circuit or the transistor included in the pixel.

Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel.

The transistor 6401 has a first electrode connected to the j-th signal line Sj, a second electrode connected to the wiring 6411, and a gate electrode connected to the j-th signal line Sj.

The operation of FIG. 38A will be described. A certain potential is input to the wiring 6411, and the potential is also a potential at which the minimum value of the video signal input to the signal line Sj in the j-th row is low. When positive or negative charges are not discharged to the j-th signal line Sj, the potential of the j-th signal line Sj is the same as that of the video signal, so that the transistor 6401 is off. On the other hand, when negative charges are discharged to the j-th signal line Sj, the potential of the j-th signal line Sj drops instantaneously. At this time, when the potential of the signal line Sj in the j-th row is lower than a value obtained by subtracting the threshold voltage of the transistor 6401 from the potential of the wiring 6411, the transistor 6401 is turned on and current flows through the transistor 6401. Flowing into. Therefore, with the structure illustrated in FIG. 38A, a large current can be prevented from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented.

Note that FIG. 38B illustrates a structure for preventing electrostatic breakdown when positive charges are discharged to the signal line Sj in the j-th row. A transistor 6402 functioning as a protective diode is provided between the scan line and the wiring 6412. Although only one protective diode is arranged, a plurality of protective diodes may be arranged in series, may be arranged in parallel, or may be arranged in series-parallel. Note that the transistor 6402 is an N-channel transistor. Note that a p-channel transistor may be used, and the transistor 6402 may have a polarity similar to that of the transistor included in the scan line driver circuit or the pixel. The transistor 6402 has a first electrode connected to the signal line Sj in the j-th row, a second electrode connected to the wiring 6412, and a gate electrode connected to the wiring 6412. Note that a potential higher than the maximum value of the video signal input to the j-th signal line Sj is input to the wiring 6412. Accordingly, the transistor 6402 is off when the electric charge is not discharged to the signal line Sj in the j-th row. On the other hand, when positive charges are discharged to the j-th signal line Sj, the potential of the j-th signal line Sj rises instantaneously. At this time, when the potential of the signal line Sj in the j-th row becomes higher than the sum of the potential of the wiring 6412 and the threshold voltage of the transistor 6402, the transistor 6402 is turned on and current flows to the wiring 6412 through the transistor 6402. Flowing. Therefore, with the structure illustrated in FIG. 38B, a large current can be prevented from flowing into the pixel, so that electrostatic breakdown of the pixel can be prevented.

Note that as shown in FIG. 38C, by combining FIGS. 38A and 38B, even when positive charges are discharged to the signal line Sj in the j-th row. Even when negative charges are discharged to the signal line Sj in the j-th row, the electrostatic breakdown of the pixel can be prevented. Note that components similar to those in FIGS. 38A and 38B are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

In this embodiment mode, a configuration for preventing electrostatic breakdown of pixels connected to a scan line and a signal line has been described. However, the configuration of this embodiment is not applied only to prevention of electrostatic breakdown of pixels connected to the scanning line and the signal line. For example, in the case where this embodiment is applied to the scan line driver circuit described in Embodiments 1 to 4 and a wiring to which a signal or a potential connected to the signal line driver circuit is input, the scan line driver circuit In addition, electrostatic breakdown of the signal line driver circuit can be prevented.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or they can be combined. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents or part of the contents described in each drawing in this embodiment mode can be applied to the contents or a part of the contents described in the drawing in another embodiment mode. Or they can be combined. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that this embodiment is an example in which the content described in the other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, an example in which the content is improved, and details An example of the case described, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Or they can be combined.

(Embodiment 7)
In this embodiment, a new structure of a display device which can be applied to the display devices described in Embodiments 1 to 4 will be described.

FIG. 39A illustrates a structure in which a diode-connected transistor is provided between one scan line and another scan line. In FIG. 39A, a diode-connected transistor 6301a is arranged between the (i-1) th scanning line Gi-1 and the ith scanning line Gi, and the ith scanning line Gi and the (i + 1) th row are arranged. A configuration in which a diode-connected transistor 6301b is arranged between the scanning line Gi + 1 of the eye is shown. Note that the transistors 6301a and 6301b are N-channel transistors. Note that a p-channel transistor may be used, and the transistors 6301a and 6301b may have the same polarity as that of the transistor included in the scan line driver circuit or the pixel.

In FIG. 39A, the i-1th scanning line Gi-1, the ith scanning line Gi, and the i + 1th scanning line Gi + 1 are representatively shown, but other scanning lines are also shown. Similarly, diode-connected transistors are arranged.

The first electrode of the transistor 6301 a is connected to the i-th scanning line Gi, the second electrode is connected to the i−1-th scanning line Gi−1, and the gate electrode is the Gi−1-th scanning line. Connected to Gi-1. The first electrode of the transistor 6301b is connected to the (i + 1) th scanning line Gi + 1, the second electrode is connected to the ith scanning line Gi, and the gate electrode is connected to the ith scanning line Gi.

The operation of FIG. 39A will be described. In the scanning line driver circuit described in any of Embodiments 1 to 4, in the non-selection period, the i−1th scanning line Gi−1, the ith scanning line Gi, and the i + 1th scanning line Gi + 1. Maintains the L level. Accordingly, the transistor 6301a and the transistor 6301b are off. However, for example, when the potential of the i-th scanning line Gi increases due to noise or the like, the i-th scanning line Gi selects a pixel, and an invalid video signal is written to the pixel. Thus, by arranging diode-connected transistors as shown in FIG. 39A between scan lines, it is possible to prevent an illegal video signal from being written to a pixel. This is because when the potential of the i-th scanning line Gi rises to the sum of the potential of the (i-1) -th scanning line Gi-1 and the threshold voltage of the transistor 6301a, the transistor 6301a is turned on. The potential of the scanning line Gi of the eye is lowered. Therefore, no pixel is selected by the i-th scanning line Gi.

Note that the structure in FIG. 39A is particularly advantageous when the scan line driver circuit and the pixel portion are formed over the same substrate. This is because in a scan line driver circuit including only an N-channel transistor or a P-channel transistor, the scan line may be in a floating state, and noise is easily generated in the scan line.

Note that FIG. 39B illustrates a structure in which the direction of a diode-connected transistor provided between scan lines is reversed. Note that the transistors 6302a and 6302b are N-channel transistors. Note that a p-channel transistor may be used, and the transistors 6302a and 6302b may have the same polarity as that of the transistor included in the scan line driver circuit or the pixel. In FIG. 39B, the first electrode of the transistor 6302a is connected to the i-th scanning line Gi, the second electrode is connected to the (i-1) th scanning line Gi-1, and the gate electrode is i. Connected to the scanning line Gi of the row. The first electrode of the transistor 6302b is connected to the (i + 1) th scanning line Gi + 1, the second electrode is connected to the ith scanning line Gi, and the gate electrode is connected to the i + 1th scanning line Gi + 1. In FIG. 39B, similarly to FIG. 38A, the potential of the i-th scanning line Gi is equal to or higher than the sum of the potential of the (i−1) -th scanning line Gi + 1 and the threshold voltage of the transistor 6302b. When it rises, the transistor 6302b is turned on, and the potential of the i-th scanning line Gi is lowered. Therefore, the pixel is not selected by the i-th scanning line Gi, and an illegal video signal can be prevented from being written to the pixel.

Note that as shown in FIG. 39C, by combining FIGS. 39A and 39B, the transistor 6301a can be used even when the potential of the i-th scanning line Gi rises. Since the transistor 6302b is turned on, the potential of the i-th scanning line Gi is lowered. Note that in FIG. 39C, current flows through two transistors, so that larger noise can be removed. Note that components similar to those in FIGS. 39A and 39B are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

Note that as shown in FIGS. 37A and 37B, a diode-connected transistor is arranged between the scanning line and the storage capacitor line as in FIGS. 39A, 39B, and 39C. The effect of can be obtained.

Note that although various drawings are used in this embodiment mode, the contents or part of the contents described in each figure can be applied to the contents or part of the contents described in another figure. Or they can be combined. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents or part of the contents described in each drawing in this embodiment mode can be applied to the contents or a part of the contents described in the drawing in another embodiment mode. Or they can be combined. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that this embodiment is an example in which the content described in the other embodiments is embodied, an example in which the content is slightly modified, an example in which a part is changed, an example in which the content is improved, and details An example of the case described, an example of application, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be applied to this embodiment. Or they can be combined.

(Embodiment 8)
In this embodiment, a pixel structure of a display device will be described. In particular, a pixel structure of a liquid crystal display device will be described.

FIG. 46 is a cross-sectional view and a top view of a pixel in the case where a thin film transistor (TFT) is combined with a so-called TN mode of a pixel structure of a liquid crystal display device. 46A is a cross-sectional view of a pixel, and FIG. 46B is a top view of the pixel. A cross-sectional view of the pixel shown in FIG. 46A corresponds to a line segment a-a ′ in the top view of the pixel shown in FIG. By applying the display device of this embodiment mode to the liquid crystal display device having the pixel structure shown in FIG. 46, the liquid crystal display device can be manufactured at low cost.

A pixel structure of a TN liquid crystal display device is described with reference to FIG. The liquid crystal display device has a basic part that displays an image, called a liquid crystal panel. A liquid crystal panel is manufactured by bonding two processed substrates together with a gap of several μm and injecting a liquid crystal material between the two substrates. In FIG. 46A, the two substrates are a first substrate 10101 and a second substrate 10116. A TFT and a pixel electrode are formed over the first substrate, and a light shielding film 10114, a color filter 10115, a fourth conductive layer 10113, a spacer 10117, and a second alignment film 10112 are formed over the second substrate. May be.

Note that the display device of this embodiment can be implemented without forming a TFT over the first substrate 10101. When the TFT is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured, a larger display device can be obtained.

Note that the TFT illustrated in FIG. 46 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost using a large-area substrate. However, the display device of the present embodiment is not limited to this. TFT structures that can be used include a channel etch type, a channel protection type, and the like for bottom-gate TFTs. A top gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that the display device of this embodiment can be implemented without forming the light-blocking film 10114 over the second substrate 10116. In the case where the light-blocking film 10114 is not manufactured, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, when the light-shielding film 10114 is formed, a display device with little light leakage at the time of black display can be obtained.

Note that the display device of this embodiment can be implemented without forming the color filter 10115 over the second substrate 10116. In the case where the color filter 10115 is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. Note that a display device capable of color display by field sequential driving can be obtained even when the color filter 10115 is not manufactured. On the other hand, when the color filter 10115 is manufactured, a display device capable of color display can be obtained.

Note that the display device in this embodiment can be implemented by spraying spherical spacers without forming the spacers 10117 over the second substrate 10116. When the spherical spacers are dispersed, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case of manufacturing the spacer 10117, since the position of the spacer does not vary, the distance between the two substrates can be made uniform,
A display device with little display unevenness can be obtained.

Next, processing performed on the first substrate 10101 will be described. The first substrate 10101 is preferably a light-transmitting substrate, and may be a quartz substrate, a glass substrate, or a plastic substrate, for example. Note that the first substrate 10101 may be a light-shielding substrate, a semiconductor substrate, or an SOI (Silicon on Insulator) substrate.

First, the first insulating film 10102 may be formed over the first substrate 10101. The first insulating film 10102 may be an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxNy). Alternatively, the first insulating film 10102 may be an insulating film having a stacked structure in which two or more films of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiOxNy), and the like are combined. In the case where the first insulating film 10102 is formed, impurities from the substrate can be prevented from affecting the semiconductor layer and changing the properties of the TFT. In addition, since a change in properties of the TFT can be suppressed, a highly reliable display device can be obtained. Note that in the case where the first insulating film 10102 is not formed, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved.

Next, a first conductive layer 10103 is formed over the first substrate 10101 or the first insulating film 10102. Note that the first conductive layer 10103 may be formed by processing a shape. The step of processing the shape is preferably as follows. First, the first conductive layer 10103 is formed over the entire surface. At this time, the first conductive layer 10103 may be formed using a film formation apparatus such as a sputtering apparatus or a CVD apparatus. Next, a photosensitive resist material is formed over the entire surface over the first conductive layer formed over the entire surface. Next, the resist material is exposed according to the shape to be formed by a photolithography method, a laser direct drawing method, or the like. Next, either one of the resist material that has been exposed or the resist material that has not been exposed is removed by etching, whereby a mask for processing the shape of the first conductive layer 10103 can be obtained. After that, the first conductive layer 10103 can be processed into a desired pattern by removing the first conductive layer 10103 by etching according to the formed mask pattern. Note that there are a chemical method (wet etching) and a physical method (dry etching) as a method for etching the first conductive layer 10103. The material of the first conductive layer 10103, the first conductive layer 10103, The material is selected as appropriate in consideration of the properties of the material under the conductive layer 10103 and the like. Note that the material used for the first conductive layer 10103 is preferably Mo, Ti, Al, Nd, Cr, or the like. Or the laminated structure which combined 2 or more of Mo, Ti, Al, Nd, Cr etc. may be sufficient.

Next, a second insulating film 10104 is formed. At this time, the second insulating film 10104 may be formed using a film formation apparatus such as a sputtering apparatus or a CVD apparatus. Note that a material used for the second insulating film 10104 is preferably a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. Alternatively, a stacked structure in which two or more of a thermal oxide film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and the like are combined may be used. Note that the second insulating film 10104 in contact with the first semiconductor layer 10105 is particularly preferably a silicon oxide film. This is because the trap level at the interface with the semiconductor layer 10105 is reduced when a silicon oxide film is used. Note that when the first conductive layer 10103 is formed using Mo, the second insulating film 10104 in contact with the first conductive layer 10103 is preferably a silicon nitride film. This is because the silicon nitride film does not oxidize Mo.

Next, a first semiconductor layer 10105 is formed. After that, the second semiconductor layer 10106 is preferably formed continuously. Note that the first semiconductor layer 10105 and the second semiconductor layer 1
0106 may be formed by processing the shape. The step of processing the shape is preferably a method such as the photolithography method described above. Note that a material used for the first semiconductor layer 10105 is preferably silicon, silicon germanium (SiGe), or the like. The material used for the second semiconductor layer 10106 is preferably silicon containing phosphorus or the like.

Next, a second conductive layer 10107 is formed. At this time, as a formation method of the second conductive layer 10107, it is preferable to use a sputtering method or a printing method. Note that the material used for the second conductive layer 10107 may have transparency or reflectivity. In the case of transparency, for example, an indium tin oxide (ITO) film in which tin oxide is mixed with tin oxide, an indium tin silicon oxide (ITSO) film in which indium tin oxide (ITO) is mixed with silicon oxide, oxidation An indium zinc oxide (IZO) film in which zinc oxide is mixed with indium, a zinc oxide film, or a tin oxide film can be used. Note that IZO is a transparent conductive material formed by sputtering using a target in which 2 to 20 wt% of zinc oxide (ZnO) is mixed with ITO. On the other hand, when it has reflectivity, Ti, Mo, Ta, Cr, W, Al, etc. can be used. Alternatively, a two-layer structure in which Ti, Mo, Ta, Cr, W and Al are stacked, or a three-layer structure in which Al is sandwiched between metals such as Ti, Mo, Ta, Cr, and W may be used. Note that the second conductive layer 10107 may be formed by processing a shape. The method of processing the shape is preferably a method such as the photolithography method described above. Note that the etching method is preferably dry etching. The dry etching may be performed by a dry etching apparatus using a high-density plasma source such as ECR (Electron Cyclotron Resonance) or ICP (Inductive Coupled Plasma).

Next, a channel region of the TFT is formed. At this time, as a mask for etching the second semiconductor layer 10106, the second conductive layer 10107 may be used, or a mask (resist) for etching the second conductive layer 10107 may be used. Good. By doing so, the number of masks can be reduced, so that the manufacturing cost can be reduced. By etching the conductive second semiconductor layer 10106, the removed portion becomes a channel region of the TFT. Note that without forming the first semiconductor layer 10105 and the second semiconductor layer 10106 in succession, after the formation of the first semiconductor layer 10105, a film serving as a stopper is formed in a portion to be a channel region of the TFT. After patterning, the second semiconductor layer 10106 may be formed. Note that the first semiconductor layer 10105 and the second semiconductor layer 10106 are etched using the same mask when the shape of the second conductive layer 10107 is processed by a method such as the photolithography method described above. By doing so, the channel region of the TFT can be formed without using the second conductive layer 10107 as a mask, so that there is an advantage that the degree of freedom of the layout pattern is increased. In addition, since the first semiconductor layer 10105 is not etched when the second semiconductor layer 10106 is etched, there is an advantage that the channel region of the TFT can be surely formed without causing etching failure.

Next, a third insulating film 10108 is formed. It is preferable that the third insulating film has transparency. Note that the material used for the third insulating film 10108 is an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, or the like), a low dielectric constant organic compound material (photosensitive or non-photosensitive organic resin material), or the like. Is preferred. Further, a material containing siloxane may be used. Siloxane is a material in which a skeleton structure is formed by a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. Alternatively, a fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Note that a contact hole is selectively formed in the third insulating film 10108 by etching. The contact hole is formed at least over the second conductive layer 10107. In addition,
By etching the second insulating film 10104 at the same time as etching the third insulating film 10108, a contact hole can be formed not only with the second conductive layer 10107 but also with the first conductive layer 10103. Note that the surface of the third insulating film 10108 is preferably as flat as possible. This is because the alignment of liquid crystal molecules is affected by the unevenness of the surface in contact with the liquid crystal.

Next, a third conductive layer 10109 is formed. At this time, as a formation method of the third conductive layer 10109, a sputtering method or a printing method is preferably used. Note that the material used for the third conductive layer 10109 may be transparent or reflective, like the second conductive layer 10107. Note that a material that can be used for the third conductive layer 10109 may be the same as that of the second conductive layer 10107. Further, the third conductive layer 10109 may be formed by processing a shape. A method for processing the shape may be the same as that of the second conductive layer 10107.

Next, a first alignment film 10110 is formed. As the alignment film 10110, a polymer film such as polyimide can be used. Note that after the first alignment film 10110 is formed, rubbing may be performed in order to control the alignment of liquid crystal molecules. The rubbing is a process of streaking the alignment film by rubbing the alignment film with a cloth. By performing rubbing, the alignment film can be provided with orientation.

The first substrate 10101 manufactured as described above and the second substrate 10116 on which the light shielding film 10114, the color filter 10115, the fourth conductive layer 10113, the spacer 10117, and the second alignment film 10112 are manufactured include a sealing material. Is bonded with a gap of several μm. A liquid crystal panel can be manufactured by injecting a liquid crystal material between two substrates. Note that in the TN liquid crystal panel as illustrated in FIG. 46, the fourth conductive layer 10113 may be formed over the entire surface of the second substrate 10116.

Next, features of the pixel structure of the TN liquid crystal panel shown in FIG. 46 will be described. A liquid crystal molecule 10118 shown in FIG. 46A is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecules 10118, the length is expressed in FIG. That is, the longer expressed liquid crystal molecule 10118 has a long axis direction parallel to the paper surface, and the shorter expressed liquid crystal molecule 10118 has a longer axis direction closer to the normal direction of the paper surface. . That is, the liquid crystal molecule 10118 shown in FIG. 46A has a major axis direction of 90 degrees different between the one close to the first substrate 10101 and the one close to the second substrate 10116. The orientation of the major axis of the liquid crystal molecules 10118 located in the middle of the orientation is such that they are smoothly connected. That is, the liquid crystal molecules 10118 illustrated in FIG. 46A are aligned with each other by 90 degrees between the first substrate 10101 and the second substrate 10116.

Next, an example of a pixel layout in the case where the display device of this embodiment is applied to a TN liquid crystal display device will be described with reference to FIG. A pixel of a TN liquid crystal display device to which the display device of this embodiment is applied includes a scan line 10121, a video signal line 10122, a capacitor line 10123, a TFT 10124, a pixel electrode 10125, and a pixel capacitor 10126. You may have.

The scan line 10121 is preferably formed using the first conductive layer 10103 because it is electrically connected to the gate electrode of the TFT 10124.

The video signal line 10122 is preferably formed of the second conductive layer 10107 because it is electrically connected to the source electrode or the drain electrode of the TFT 10124. In addition, since the scanning lines 10121 and the video signal lines 10122 are arranged in a matrix, at least
It is preferable that the conductive layers are formed of different layers.

The capacitor line 10123 is a wiring for forming the pixel capacitor 10126 by being arranged in parallel with the pixel electrode 10125 and is preferably formed using the first conductive layer 10103. Note that as illustrated in FIG. 46B, the capacitor line 10123 may extend along the video signal line 10122 so as to surround the video signal line 10122. By doing so, it is possible to reduce a phenomenon in which the potential of the electrode that should hold the potential changes, so-called crosstalk, in accordance with the potential change of the video signal line 10122. Note that in order to reduce cross capacitance with the video signal line 10122, the first semiconductor layer 10105 may be provided in a cross region of the capacitor line 10123 and the video signal line 10122 as illustrated in FIG.

The TFT 10124 operates as a switch for electrically connecting the video signal line 10122 and the pixel electrode 10125. Note that as illustrated in FIG. 46B, either the source region or the drain region of the TFT 10124 may be disposed so as to surround the other of the source region or the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. Note that as illustrated in FIG. 46B, the gate electrode of the TFT 10124 may be disposed so as to surround the first semiconductor layer 10105.

The pixel electrode 10125 is electrically connected to one of the source electrode and the drain electrode of the TFT 10124. The pixel electrode 10125 is an electrode for applying a signal voltage transmitted through the video signal line 10122 to the liquid crystal element. Alternatively, the pixel capacitor 10126 may be formed by arranging the capacitor line 10123. Thus, the pixel electrode 10125 can easily hold the signal voltage transmitted through the video signal line 10122. Note that the pixel electrode 10125 may have a rectangular shape as illustrated in FIG. By doing so, the aperture ratio of the pixel can be increased, so that the efficiency of the liquid crystal display device is improved. In the case where the pixel electrode 10125 is formed using a material having transparency, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. In the case where the pixel electrode 10125 is formed using a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors and does not require a backlight, so that power consumption can be extremely reduced. Note that in the case where the pixel electrode 10125 is formed using both a transparent material and a reflective material, a transflective liquid crystal display device having both advantages can be obtained. Note that in the case where the pixel electrode 10125 is formed using a reflective material, the surface of the pixel electrode 10125 may have unevenness. Alternatively, the surface of the third insulating film 10108 can be uneven so that the pixel electrode 10125 can be uneven. By doing so, since the reflected light is irregularly reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a certain brightness at any angle.

Next, a case where the display device of this embodiment is applied to a VA (Vertical Alignment) mode liquid crystal display device will be described with reference to FIG. FIG. 47 shows a so-called MVA (Multi-domain) in which liquid crystal molecules are controlled to have various orientations by using alignment control protrusions in the pixel structure of the VA mode liquid crystal display device, and the viewing angle is increased. FIGS. 7A and 7B are a cross-sectional view and a top view of a pixel in the case where the display device of this embodiment is applied to a vertical alignment (vertical alignment) method. FIGS. 47A is a cross-sectional view of a pixel, and FIG. 47B is a top view of the pixel. In addition, the cross-sectional view of the pixel shown in FIG. 47A corresponds to a line segment a-a ′ in the top view of the pixel shown in FIG. By applying the display device of this embodiment mode to the liquid crystal display device having the pixel structure shown in FIG. 47, a liquid crystal display device with a wide viewing angle, a high response speed, and a high contrast can be obtained.

The pixel structure of the MVA liquid crystal display device is described with reference to FIG. The liquid crystal display device has a basic part that displays an image, called a liquid crystal panel. A liquid crystal panel is manufactured by bonding two processed substrates together with a gap of several μm and injecting a liquid crystal material between the two substrates. In FIG. 47A, the two substrates are a first substrate 10201 and a second substrate 10216. A TFT and a pixel electrode are formed over the first substrate, and a light shielding film 10214, a color filter 10215, a fourth conductive layer 10213, a spacer 10217, a second alignment film 10212, and an alignment control are formed over the second substrate. The protrusion 10219 for use may be produced.

Note that the display device of this embodiment can be implemented without forming a TFT over the first substrate 10201. When the TFT is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured, a larger display device can be obtained.

Note that the TFT illustrated in FIG. 47 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost using a large-area substrate. However, the display device of the present embodiment is not limited to this. TFT structures that can be used include a channel etch type, a channel protection type, and the like for bottom-gate TFTs. A top gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that the display device of this embodiment can be implemented without forming the light-blocking film 10214 over the second substrate 10216. In the case where the light-blocking film 10214 is not manufactured, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, when the light-blocking film 10214 is formed, a display device with little light leakage at the time of black display can be obtained.

Note that the display device of this embodiment can be implemented without forming the color filter 10215 over the second substrate 10216. In the case where the color filter 10215 is not manufactured, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. However, even when the color filter 10215 is not manufactured, a display device capable of color display by field sequential driving can be obtained. On the other hand, when the color filter 10215 is manufactured, a display device capable of color display can be obtained.

Note that the display device in this embodiment can be implemented by spraying spherical spacers without forming the spacers 10217 over the second substrate 10216. When the spherical spacers are dispersed, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case of manufacturing the spacer 10217, since the position of the spacer does not vary, the distance between the two substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, processing performed on the first substrate 10201 may be omitted because the method described in FIG. 46 may be used. Here, the first substrate 10201, the first insulating film 10202, the first conductive layer 10203, the second insulating film 10204, the first semiconductor layer 10205, the second semiconductor layer 10206, and the second conductive layer 10207 are used. , The third insulating film 10208, the third conductive layer 10209, and the first alignment film 10210 are respectively the first substrate 10101, the first insulating film 10102, the first conductive layer 10103, and the second alignment film in FIG. Corresponding to the first insulating film 10104, the first semiconductor layer 10105, the second semiconductor layer 10106, the second conductive layer 10107, the third insulating film 10108, the third conductive layer 10109, and the first alignment film 10110. . Although not shown, an alignment control protrusion may be provided also on the first substrate side. By doing so, the orientation of the liquid crystal molecules can be controlled more reliably. Further, the first alignment film 10210 and the second alignment film 10212 may be vertical alignment films. By doing so, the liquid crystal molecules 10218 can be vertically aligned.

The first substrate 10201 manufactured as described above, the light-shielding film 10214, the color filter 10215, the fourth conductive layer 10213, the spacer 10217, and the second substrate 10216 from which the second alignment film 10212 is manufactured are used as a sealing material. Is bonded with a gap of several μm, and a liquid crystal material is injected between the two substrates, whereby a liquid crystal panel can be manufactured. Note that in the MVA liquid crystal panel illustrated in FIG. 47, the fourth conductive layer 10213 may be formed over the entire surface of the second substrate 10216. Alternatively, the alignment control protrusion 10219 may be formed in contact with the fourth conductive layer 10213. The shape of the orientation control protrusion 10219 is not limited, but is preferably a shape having a smooth curved surface. By doing so, the alignment of the adjacent liquid crystal molecules 10218 becomes very close, and alignment defects are reduced. In addition, defects in the alignment film due to the second alignment film 10212 being stepped by the alignment control protrusion 10219 can be reduced.

Next, features of the pixel structure of the MVA liquid crystal panel illustrated in FIG. 47 will be described. A liquid crystal molecule 10218 shown in FIG. 47A is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecules 10218, the length is expressed in FIG. That is, the longer expressed liquid crystal molecules 10218 are parallel to the paper surface, and the shorter expressed liquid crystal molecules 10218 are closer to the normal direction of the paper surface. . That is, the liquid crystal molecules 10218 shown in FIG. 47A are aligned so that the direction of the major axis is the normal direction of the alignment film. Therefore, the liquid crystal molecules 10218 in a portion where the alignment control protrusion 10219 is located are aligned radially with the alignment control protrusion 10219 as the center. In this state, a liquid crystal display device with a large viewing angle can be obtained.

Next, an example of a pixel layout in the case where the display device of this embodiment is applied to an MVA liquid crystal display device will be described with reference to FIG. A pixel of an MVA liquid crystal display device to which the display device of this embodiment is applied includes a scan line 10221, a video signal line 10222, a capacitor line 10223, a TFT 10224, a pixel electrode 10225, a pixel capacitor 10226, and an orientation. And a control projection 10219.

The scan line 10221 is preferably formed using the first conductive layer 10203 because it is electrically connected to the gate electrode of the TFT 10224.

The video signal line 10222 is preferably formed using the second conductive layer 10207 because it is electrically connected to the source electrode or the drain electrode of the TFT 10224. In addition, since the scan lines 10221 and the video signal lines 10222 are arranged in a matrix, it is preferable to form at least different conductive layers.

The capacitor line 10223 is a wiring for forming the pixel capacitor 10226 by being arranged in parallel with the pixel electrode 10225 and is preferably formed using the first conductive layer 10203. Note that as illustrated in FIG. 47B, the capacitor line 10223 may be extended along the video signal line 10222 so as to surround the video signal line 10222. By doing so, it is possible to reduce a phenomenon in which the potential of the electrode that should hold the potential changes, that is, so-called crosstalk, with the change in the potential of the video signal line 10222. Note that in order to reduce cross capacitance with the video signal line 10222, a first semiconductor layer 10205 may be provided in a cross region of the capacitor line 10223 and the video signal line 10222 as illustrated in FIG.

The TFT 10224 operates as a switch for electrically connecting the video signal line 10222 and the pixel electrode 10225. Note that as shown in FIG. 47B, either the source region or the drain region of the TFT 10224 may be arranged so as to surround the other of the source region or the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. Note that as illustrated in FIG. 47B, the gate electrode of the TFT 10224 may be disposed so as to surround the first semiconductor layer 10205.

The pixel electrode 10225 is electrically connected to one of a source electrode and a drain electrode of the TFT 10224. The pixel electrode 10225 is an electrode for applying a signal voltage transmitted through the video signal line 10222 to the liquid crystal element. Alternatively, the pixel capacitor 10226 may be formed by disposing the capacitor line 10223. Thus, the pixel electrode 10225 can easily hold the signal voltage transmitted through the video signal line 10222. Note that the pixel electrode 10225 may have a rectangular shape as illustrated in FIG. By doing so, the aperture ratio of the pixel can be increased, so that the efficiency of the liquid crystal display device is improved. In the case where the pixel electrode 10225 is formed using a transparent material, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. In the case where the pixel electrode 10225 is formed using a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors and does not require a backlight, so that power consumption can be extremely reduced. Note that in the case where the pixel electrode 10225 is formed using both a transparent material and a reflective material, a transflective liquid crystal display device having both advantages can be obtained. Note that in the case where the pixel electrode 10225 is formed using a reflective material, the surface of the pixel electrode 10225 may be uneven. Alternatively, when the surface of the third insulating film 10208 is uneven, the pixel electrode 10225 can be uneven. By doing so, since the reflected light is irregularly reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a certain brightness at any angle.

Next, another example in which the display device of this embodiment is applied to a VA (Vertical Alignment) mode liquid crystal display device will be described with reference to FIG. FIG. 48 illustrates a so-called pixel structure of a VA mode liquid crystal display device in which the fourth conductive layer 10313 is patterned so that liquid crystal molecules are controlled in various directions to increase the viewing angle. FIGS. 2A and 2B are a cross-sectional view and a top view of a pixel when the display device of this embodiment is applied to a PVA (Patterned Vertical Alignment) method. 48A is a cross-sectional view of a pixel, and FIG. 48B is a top view of the pixel. Further, the cross-sectional view of the pixel shown in FIG. 48A corresponds to a line segment a-a ′ in the top view of the pixel shown in FIG. By applying the display device of this embodiment mode to the pixel structure liquid crystal display device shown in FIG. 48, a liquid crystal display device with a wide viewing angle, a high response speed, and a high contrast can be obtained.

A pixel structure of a PVA liquid crystal display device will be described with reference to FIG. The liquid crystal display device has a basic part that displays an image, called a liquid crystal panel. A liquid crystal panel is manufactured by bonding two processed substrates together with a gap of several μm and injecting a liquid crystal material between the two substrates. In FIG. 48A, the two substrates are a first substrate 10301 and a second substrate 10316. A TFT and a pixel electrode are formed on the first substrate, and a light shielding film 10314, a color filter 10315, a fourth conductive layer 10313, a spacer 10317, and a second alignment film 10312 are formed on the second substrate. It may be produced.

Note that the display device of this embodiment can be implemented without forming a TFT over the first substrate 10301. When the TFT is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured, a larger display device can be obtained.

Note that the TFT illustrated in FIG. 48 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost using a large-area substrate. However, the display device of the present embodiment is not limited to this. TFT structures that can be used include a channel etch type, a channel protection type, and the like for bottom-gate TFTs. A top gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that the display device of this embodiment can be implemented without forming the light-blocking film 10314 over the second substrate 10316. In the case where the light-blocking film 10314 is not manufactured, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case of manufacturing the light-blocking film 10314, a display device with little light leakage during black display can be obtained.

Note that the display device of this embodiment can be implemented without forming the color filter 10315 over the second substrate 10316. In the case where the color filter 10315 is not manufactured, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. Note that a display device capable of color display by field sequential driving can be obtained even when the color filter 10315 is not manufactured. On the other hand, when the color filter 10315 is manufactured, a display device capable of color display can be obtained.

Note that the display device of this embodiment can also be implemented by spraying spherical spacers without forming the spacers 10317 over the second substrate 10316. When the spherical spacers are dispersed, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case of manufacturing the spacer 10317, since the position of the spacer does not vary, the distance between the two substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, processing performed on the first substrate 10301 may be omitted because the method described in FIG. 46 may be used. Here, the first substrate 10301, the first insulating film 10302, the first conductive layer 10303, the second insulating film 10304, the first semiconductor layer 10305, the second semiconductor layer 10306, and the second conductive layer 10307 , The third insulating film 10308, the third conductive layer 10309, and the first alignment film 10310 are respectively the first substrate 10101, the first insulating film 10102, the first conductive layer 10103, and the second alignment film 10310 in FIG. Corresponding to the first insulating film 10104, the first semiconductor layer 10105, the second semiconductor layer 10106, the second conductive layer 10107, the third insulating film 10108, the third conductive layer 10109, and the first alignment film 10110. . Note that an electrode notch portion may be provided in the third conductive layer 10309 on the first substrate 10301 side. By doing so, the orientation of the liquid crystal molecules can be controlled more reliably. Further, the first alignment film 10310 and the second alignment film 10312 may be vertical alignment films. By doing so, the liquid crystal molecules 10318 can be vertically aligned.

The first substrate 10301 manufactured as described above and the second substrate 10316 on which the light-shielding film 10314, the color filter 10315, the fourth conductive layer 10313, the spacer 10317, and the second alignment film 10312 are manufactured are used as a sealing material. Is bonded with a gap of several μm, and a liquid crystal material is injected between the two substrates, whereby a liquid crystal panel can be manufactured. Note that in the PVA liquid crystal panel as illustrated in FIG. 48, the fourth conductive layer 10313 may be subjected to patterning to form the electrode notch portion 10319. Note that the shape of the electrode notch 10319 is not limited, but a shape in which a plurality of rectangles having different directions are combined is preferable. By doing so, a plurality of regions having different orientations can be formed, so that a liquid crystal display device with a large viewing angle can be obtained. In addition, the shape of the fourth conductive layer 10313 at the boundary between the electrode notch 10319 and the fourth conductive layer 10313 is preferably a smooth curve. By doing so, the alignment of the liquid crystal molecules 10318 that are close to each other becomes extremely close, so that alignment defects are reduced. In addition, defects in the alignment film due to the second alignment film 10312 being stepped by the electrode notch 10319 can be reduced.

Next, characteristics of the pixel structure of the PVA liquid crystal panel shown in FIG. 48 will be described. Liquid crystal molecules 10318 shown in FIG. 48A are elongated molecules having a major axis and a minor axis. In order to show the direction of the liquid crystal molecules 10318, the length is expressed in FIG. In other words, the liquid crystal molecule 10318 expressed in a long direction has a long axis direction parallel to the paper surface, and the liquid crystal molecule 10318 expressed in a short direction has a long axis direction closer to the normal direction of the paper surface. . That is, the liquid crystal molecules 10318 shown in FIG. 48A are aligned so that the direction of the long axis is in the normal direction of the alignment film. Therefore, the liquid crystal molecules 10318 in the portion where the electrode cutout portion 10319 exists is aligned radially with the boundary between the electrode cutout portion 10319 and the fourth conductive layer 10313 as the center. In this state, a liquid crystal display device with a large viewing angle can be obtained.

Next, an example of a pixel layout in the case where the display device of this embodiment is applied to a PVA liquid crystal display device will be described with reference to FIG. A pixel of a PVA liquid crystal display device to which the display device of this embodiment is applied includes a scan line 10321, a video signal line 10322, a capacitor line 10323, a TFT 10324, a pixel electrode 10325, a pixel capacitor 10326, and an electrode A notch 10319 may be provided.

Since the scan line 10321 is electrically connected to the gate electrode of the TFT 10324, the scan line 10321 is preferably formed using the first conductive layer 10303.

Since the video signal line 10322 is electrically connected to the source electrode or the drain electrode of the TFT 10324, the video signal line 10322 is preferably formed using the second conductive layer 10307. In addition, since the scan lines 10321 and the video signal lines 10322 are arranged in a matrix, it is preferable to form at least different conductive layers.

The capacitor line 10323 is a wiring for forming the pixel capacitor 10326 by being arranged in parallel with the pixel electrode 10325 and is preferably formed using the first conductive layer 10303. Note that as illustrated in FIG. 48B, the capacitor line 10323 may be extended along the video signal line 10322 so as to surround the video signal line 10322. By doing so, it is possible to reduce a phenomenon in which the potential of the electrode that should hold the potential changes, so-called crosstalk, in accordance with the potential change of the video signal line 10322. Note that in order to reduce cross capacitance with the video signal line 10322, a first semiconductor layer 10305 may be provided in a cross region of the capacitor line 10323 and the video signal line 10322 as illustrated in FIG.

The TFT 10324 operates as a switch for electrically connecting the video signal line 10322 and the pixel electrode 10325. Note that as shown in FIG. 48B, either the source region or the drain region of the TFT 10324 may be disposed so as to surround the other of the source region or the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. As shown in FIG. 48B, the TFT
The gate electrode 10324 may be disposed so as to surround the first semiconductor layer 10305.

The pixel electrode 10325 is electrically connected to one of the source electrode and the drain electrode of the TFT 10324. The pixel electrode 10325 is an electrode for applying a signal voltage transmitted through the video signal line 10322 to the liquid crystal element. Further, the pixel capacitor 10326 may be formed by providing the capacitor line 10323. Thus, the pixel electrode 10325 can easily hold the signal voltage transmitted through the video signal line 10322. Note that as illustrated in FIG. 48B, the pixel electrode 10325 is formed on a portion where the electrode notch portion 10319 is not provided in accordance with the shape of the electrode notch portion 10319 provided in the fourth conductive layer 10313. It is preferable to form a portion where 10325 is cut out. Thus, a plurality of regions with different alignment of the liquid crystal molecules 10318 can be formed, so that a liquid crystal display device with a wide viewing angle can be obtained. In the case where the pixel electrode 10325 is formed using a material having transparency, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. In the case where the pixel electrode 10325 is formed using a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors and does not require a backlight, so that power consumption can be extremely reduced. Note that in the case where the pixel electrode 10325 is formed using both a transparent material and a reflective material, a transflective liquid crystal display device having both advantages can be obtained. Note that in the case where the pixel electrode 10325 is formed using a reflective material, the surface of the pixel electrode 10325 may have unevenness. Alternatively, when the surface of the third insulating film 10308 is uneven, the pixel electrode 10325 can be uneven. By doing so, since the reflected light is irregularly reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a certain brightness at any angle.

Next, a case where the display device of this embodiment is applied to a horizontal electric field type liquid crystal display device will be described with reference to FIG. FIG. 49 shows the pixel electrode 10425 and the common electrode 10423 in the pixel structure of a liquid crystal display device in which an electric field is applied in the lateral direction in order to perform switching so that the alignment of liquid crystal molecules is always horizontal with respect to the substrate. Cross-sectional view and upper surface of a pixel when the display device of this embodiment is applied to a method of applying an electric field in a lateral direction by performing comb-like pattern processing, that is, a so-called IPS (In-Plane-Switching) method FIG. 49A is a cross-sectional view of a pixel, and FIG. 49B is a top view of the pixel. A cross-sectional view of the pixel shown in FIG. 49A corresponds to a line segment a-a ′ in the top view of the pixel shown in FIG. By applying the display device of this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 49, a liquid crystal display device having a large viewing angle in principle and a small dependence of response speed on gray scale can be obtained.

A pixel structure of an IPS liquid crystal display device is described with reference to FIG. The liquid crystal display device has a basic part that displays an image, called a liquid crystal panel. A liquid crystal panel is manufactured by bonding two processed substrates together with a gap of several μm and injecting a liquid crystal material between the two substrates. In FIG. 49A, the two substrates are a first substrate 10401 and a second substrate 10416. A TFT and a pixel electrode may be manufactured over the first substrate, and a light-blocking film 10414, a color filter 10415, a spacer 10417, and a second alignment film 10412 may be manufactured over the second substrate.

Note that the display device of this embodiment can be implemented without forming a TFT over the first substrate 10401. When the TFT is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. Furthermore, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured, a larger display device can be obtained.

Note that the TFT illustrated in FIG. 49 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost using a large-area substrate. However, the display device of the present embodiment is not limited to this. TFT structures that can be used include a channel etch type, a channel protection type, and the like for bottom-gate TFTs. A top gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that the display device of this embodiment can be implemented without forming the light-blocking film 10414 over the second substrate 10416. In the case where the light-blocking film 10414 is not manufactured, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case of manufacturing the light-blocking film 10414, a display device with little light leakage during black display can be obtained.

Note that the display device of this embodiment can be implemented without forming the color filter 10415 over the second substrate 10416. In the case where the color filter 10415 is not manufactured, the number of steps is reduced, so that manufacturing cost can be reduced. Note that a display device capable of color display by field sequential driving can be obtained even when the color filter 10415 is not manufactured. In addition, since the structure is simple, the yield can be improved. On the other hand, when the color filter 10415 is manufactured, a display device capable of color display can be obtained.

Note that the display device of this embodiment can also be implemented by spraying spherical spacers without forming the spacers 10417 over the second substrate 10416. When the spherical spacers are dispersed, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case of manufacturing the spacer 10417, since the position of the spacer does not vary, the distance between the two substrates can be made uniform, and a display device with little display unevenness can be obtained.

Next, processing performed on the first substrate 10401 may be omitted because the method described in FIG. 46 may be used. Here, the first substrate 10401, the first insulating film 10402, the first conductive layer 10403, the second insulating film 10404, the first semiconductor layer 10405, the second semiconductor layer 10406, and the second conductive layer 10407 are used. , The third insulating film 10408, the third conductive layer 10409, and the first alignment film 10410 are respectively the first substrate 10101, the first insulating film 10102, the first conductive layer 10103, and the second alignment film in FIG. Corresponding to the first insulating film 10104, the first semiconductor layer 10105, the second semiconductor layer 10106, the second conductive layer 10107, the third insulating film 10108, the third conductive layer 10109, and the first alignment film 10110. . Note that pattern processing may be performed on the third conductive layer 10409 on the first substrate 10401 side to form two comb-like shapes that are meshed with each other. One comb-like electrode may be electrically connected to one of a source electrode or a drain electrode of the TFT 10424, and the other comb-like electrode may be electrically connected to the common electrode 10423. Thus, a horizontal electric field can be effectively applied to the liquid crystal molecules 10418.

The first substrate 10401 manufactured as described above and the second substrate 10416 on which the light shielding film 10414, the color filter 10415, the spacer 10417, and the second alignment film 10412 are formed have a gap of several μm by a sealant. The liquid crystal panel can be manufactured by laminating and injecting a liquid crystal material between the two substrates. Note that although not illustrated, a conductive layer may be formed on the second substrate 10416 side. By forming the conductive layer on the second substrate 10416 side, it is possible to reduce the influence of electromagnetic wave noise from the outside.

Next, features of the pixel structure of the IPS liquid crystal panel shown in FIG. 49 will be described. FIG.
A liquid crystal molecule 10418 shown in 9A is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecules 10418, the length is expressed in FIG. In other words, the liquid crystal molecule 10418 expressed in a long direction has a long axis direction parallel to the paper surface, and the liquid crystal molecule 10418 expressed in a short direction has a long axis direction closer to the normal direction of the paper surface. . That is, the liquid crystal molecules 10418 shown in FIG. 49A are aligned so that the major axis is always in the horizontal direction to the substrate. In FIG. 49A, the alignment is shown in the absence of an electric field. However, when an electric field is applied to the liquid crystal molecules 10418, the orientation of the major axis always remains horizontal with the substrate. Rotate within. In this state, a liquid crystal display device with a large viewing angle can be obtained.

Next, an example of a pixel layout in the case where the display device of this embodiment is applied to an IPS liquid crystal display device will be described with reference to FIG. A pixel of an IPS liquid crystal display device to which the display device of this embodiment is applied may include a scanning line 10421, a video signal line 10422, a common electrode 10423, a TFT 10424, and a pixel electrode 10425. .

Since the scan line 10421 is electrically connected to the gate electrode of the TFT 10424, the scan line 10421 is preferably formed using the first conductive layer 10403.

Since the video signal line 10422 is electrically connected to the source electrode or the drain electrode of the TFT 10424, the video signal line 10422 is preferably formed using the second conductive layer 10407. In addition, since the scan lines 10421 and the video signal lines 10422 are arranged in a matrix, it is preferable to form at least different conductive layers. Note that as illustrated in FIG. 49B, the video signal line 10422 may be formed to be bent in the pixel so as to match the shape of the pixel electrode 10425 and the common electrode 10423. By doing so, the aperture ratio of the pixel can be increased, so that the efficiency of the liquid crystal display device can be improved.

The common electrode 10423 is an electrode for generating a horizontal electric field by being arranged in parallel with the pixel electrode 10425, and includes the first conductive layer 10403 and the third conductive layer 10409. Is preferred. Note that, as illustrated in FIG. 49B, the common electrode 10423 may extend along the video signal line 10422 so as to surround the video signal line 10422. By doing so, it is possible to reduce a phenomenon in which the potential of the electrode that should hold the potential changes, so-called crosstalk, in accordance with the potential change of the video signal line 10422. Note that in order to reduce cross capacitance with the video signal line 10422, a first semiconductor layer 10405 may be provided in a cross region of the common electrode 10423 and the video signal line 10422 as illustrated in FIG.

The TFT 10424 operates as a switch for electrically connecting the video signal line 10422 and the pixel electrode 10425. Note that as illustrated in FIG. 49B, either the source region or the drain region of the TFT 10424 may be disposed so as to surround the other of the source region or the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. Note that as illustrated in FIG. 49B, the gate electrode of the TFT 10424 may be disposed so as to surround the first semiconductor layer 10405.

The pixel electrode 10425 is electrically connected to one of a source electrode and a drain electrode of the TFT 10424. The pixel electrode 10425 is an electrode for applying a signal voltage transmitted through the video signal line 10422 to the liquid crystal element. Further, a pixel capacitor may be formed by providing the common electrode 10423. Thus, the pixel electrode 10325 can easily hold the signal voltage transmitted through the video signal line 10422. Note that the pixel electrode 10425 and the comb-like common electrode 10423 are preferably formed in a bent comb-like shape as illustrated in FIG. Thus, a plurality of regions with different alignment of the liquid crystal molecules 10418 can be formed, so that a liquid crystal display device with a wide viewing angle can be obtained. In the case where the pixel electrode 10425 and the comb-like common electrode 10423 are formed using a transparent material, a transmissive liquid crystal display device can be obtained. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. Further, in the transmissive liquid crystal display device, the pixel has a high aperture ratio, and light efficiency can be improved. Note that a transmissive liquid crystal display device can be obtained even when the pixel electrode 10425 and the comb-like common electrode 10423 are formed using a material that is not transparent and does not have reflectivity. In the transmissive liquid crystal display device, light is transmitted through only the liquid crystal molecules 10418 in a portion where a lateral electric field exists, so that an image with high color reproducibility and high image quality can be displayed. In the case where the pixel electrode 10425 and the comb-like common electrode 10423 are formed using a reflective material, a transflective liquid crystal display device can be obtained. The transflective liquid crystal display device has high visibility in a bright environment such as outdoors, and can greatly reduce power consumption. Further, the transflective liquid crystal display device has high color reproducibility and can display an image with high image quality. Note that a transflective liquid crystal display device can be obtained even when the pixel electrode 10425 and the comb-like common electrode 10423 are formed using both a transparent material and a reflective material. Note that in the case where the pixel electrode 10425 and the comb-shaped common electrode 10423 are formed using a reflective material, the surface of the pixel electrode 10425 and the comb-shaped common electrode 10423 may be uneven. Alternatively, the surface of the third insulating film 10408 can be uneven so that the pixel electrode 10425 and the comb-shaped common electrode 10423 can be uneven. By doing so, since the reflected light is irregularly reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a certain brightness at any angle.

Note that the comb-like pixel electrode 10425 and the comb-like common electrode 10423 are both formed using the third conductive layer 10409; however, the pixel structure to which the display device in this embodiment can be applied is described here. It is not limited to, It can select suitably. For example, both the comb-like pixel electrode 10425 and the comb-like common electrode 10423 may be formed using the second conductive layer 10407, or both may be formed using the first conductive layer 10403. Either one may be formed of the third conductive layer 10409 and the other may be formed of the second conductive layer 10407, or one of them may be formed of the third conductive layer 10409 and the other is formed of the first conductive layer 10409. The layer 10407 may be formed, or one of them may be formed using the second conductive layer 10409 and the other may be formed using the first conductive layer 10407.

Next, a case where the display device of this embodiment is applied to another horizontal electric field type liquid crystal display device will be described with reference to FIG. FIG. 50 is a diagram showing another pixel structure of a liquid crystal display device of a system in which an electric field is applied in the lateral direction in order to perform switching so that the alignment of liquid crystal molecules is always horizontal with respect to the substrate. More specifically, one of the pixel electrode 10525 and the common electrode 10523 is subjected to comb-like pattern processing, and the other is formed by uniformly forming an electrode in a region overlapping the comb-like shape. 2A and 2B are a cross-sectional view and a top view of a pixel in the case where the display device of this embodiment is applied to a method in which an electric field is applied in a direction, a so-called FFS (Fringe Field Switching) method. 50A is a cross-sectional view of a pixel, and FIG. 50B is a top view of the pixel. Further, the cross-sectional view of the pixel shown in FIG. 50A corresponds to a line segment a-a ′ in the top view of the pixel shown in FIG. By applying the display device of this embodiment to the liquid crystal display device having the pixel structure shown in FIG. 50, a liquid crystal display device having a large viewing angle in principle and a small dependence of response speed on gray scale can be obtained.

A pixel structure of an FFS liquid crystal display device is described with reference to FIG. The liquid crystal display device has a basic part that displays an image, called a liquid crystal panel. A liquid crystal panel is manufactured by bonding two processed substrates together with a gap of several μm and injecting a liquid crystal material between the two substrates. In FIG. 50A, the two substrates are a first substrate 10501 and a second substrate 10516. A TFT and a pixel electrode may be formed over the first substrate, and a light-shielding film 10514, a color filter 10515, a spacer 10517, and a second alignment film 10512 may be formed over the second substrate.

Note that the display device of this embodiment can be implemented without forming a TFT over the first substrate 10501. When the TFT is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, when a TFT is manufactured, a larger display device can be obtained.

Note that the TFT illustrated in FIG. 50 is a bottom-gate TFT using an amorphous semiconductor. A liquid crystal panel to which a TFT using an amorphous semiconductor is applied has an advantage that it can be manufactured at low cost using a large-area substrate. However, the display device of the present embodiment is not limited to this. TFT structures that can be used include a channel etch type, a channel protection type, and the like for bottom-gate TFTs. A top gate type may also be used. Furthermore, not only an amorphous semiconductor but also a polycrystalline semiconductor can be used.

Note that the display device of this embodiment can be implemented without forming the light-blocking film 10514 over the second substrate 10516. In the case where the light-blocking film 10514 is not manufactured, the number of steps is reduced, so that manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, when the light-shielding film 10514 is manufactured, a display device with little light leakage at the time of black display can be obtained.

Note that the display device of this embodiment can be implemented without forming the color filter 10515 over the second substrate 10516. In the case where the color filter 10515 is not manufactured, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. Note that a display device capable of color display by field sequential driving can be obtained even when the color filter 10515 is not manufactured. On the other hand, when the color filter 10515 is manufactured, a display device capable of color display can be obtained.

Note that the display device in this embodiment can be implemented by spraying spherical spacers without forming the spacer 10517 over the second substrate 10516. When the spherical spacers are dispersed, the number of steps is reduced, so that the manufacturing cost can be reduced. In addition, since the structure is simple, the yield can be improved. On the other hand, in the case where the spacer 10517 is manufactured and the display device of this embodiment is used, the distance between the two substrates can be made uniform because the spacer position does not vary, and a display device with little display unevenness is obtained. be able to.

Next, processing performed on the first substrate 10501 may be performed by using the method described with reference to FIG. Here, the first substrate 10501, the first insulating film 10502, the first conductive layer 10503, the second insulating film 10504, the first semiconductor layer 10505, the second semiconductor layer 10506, and the second conductive layer 10507 are used. , The third insulating film 10508, the third conductive layer 10509, and the first alignment film 10510 are respectively the first substrate 10101, the first insulating film 10102, the first conductive layer 10103, and the second alignment film in FIG. Corresponding to the first insulating film 10104, the first semiconductor layer 10105, the second semiconductor layer 10106, the second conductive layer 10107, the third insulating film 10108, the third conductive layer 10109, and the first alignment film 10110. .

46 differs from FIG. 46 in that a fourth insulating film 10519 and a fourth conductive layer 10513 may be formed on the first substrate 10501 side. More specifically, after pattern processing is performed on the third conductive layer 10509, a fourth insulating film 10519 is formed, and after pattern processing is performed to form a contact hole, the fourth conductive layer 10513 is formed. The first alignment film 10510 may be formed after film formation and patterning in the same manner. Note that materials and processing methods that can be used for the fourth insulating film 10519 and the fourth conductive layer 10513 can be the same as those used for the third insulating film 10508 and the third conductive layer 10509. One comb-like electrode may be electrically connected to one of a source electrode and a drain electrode of the TFT 10524, and the other uniform electrode may be electrically connected to the common electrode 10523. Thus, a horizontal electric field can be effectively applied to the liquid crystal molecules 10518.

The first substrate 10501 manufactured as described above and the second substrate 10516 on which the light shielding film 10514, the color filter 10515, the spacer 10517, and the second alignment film 10512 are formed have a gap of several μm by a sealant. The liquid crystal panel can be manufactured by laminating and injecting a liquid crystal material between the two substrates. Note that although not illustrated, a conductive layer may be formed on the second substrate 10516 side. By forming the conductive layer on the second substrate 10516 side, the influence of electromagnetic noise from the outside can be reduced.

Next, features of the pixel structure of the FFS mode liquid crystal panel illustrated in FIG. 50 will be described. A liquid crystal molecule 10518 shown in FIG. 50A is an elongated molecule having a major axis and a minor axis. In order to show the direction of the liquid crystal molecules 10518, the length is expressed in FIG. In other words, the longer expressed liquid crystal molecule 10518 has a major axis direction parallel to the paper surface, and the shorter expressed liquid crystal molecule 10518 has a longer axis direction closer to the normal direction of the paper surface. . That is, the liquid crystal molecules 10518 shown in FIG. 50A are aligned so that the major axis is always in the horizontal direction to the substrate. In FIG. 50A, the alignment is shown in the absence of an electric field. However, when an electric field is applied to the liquid crystal molecules 10518, the orientation of the major axis always maintains the horizontal direction with respect to the substrate. Rotate within. In this state, a liquid crystal display device with a large viewing angle can be obtained.

Next, an example of a pixel layout in the case where the display device of this embodiment is applied to an FFS liquid crystal display device will be described with reference to FIG. A pixel of an FFS liquid crystal display device to which the display device of this embodiment is applied may include a scanning line 10521, a video signal line 10522, a common electrode 10523, a TFT 10524, and a pixel electrode 10525. .

Since the scan line 10521 is electrically connected to the gate electrode of the TFT 10524, the scan line 10521 is preferably formed using the first conductive layer 10503.

Since the video signal line 10522 is electrically connected to the source electrode or the drain electrode of the TFT 10524, the video signal line 10522 is preferably formed using the second conductive layer 10507. In addition, since the scan lines 10521 and the video signal lines 10522 are arranged in a matrix, it is preferable to form at least different conductive layers. Note that as shown in FIG. 50B, the video signal line 10522 may be bent in the pixel so as to match the shape of the pixel electrode 10525. By doing so, the aperture ratio of the pixel can be increased, so that the efficiency of the liquid crystal display device can be improved.

The common electrode 10523 is preferably formed using a first conductive layer 10503 and a third conductive layer 10509. Note that in order to reduce cross capacitance with the video signal line 10522, the first semiconductor layer 10505 may be provided in a cross region of the common electrode 10523 and the video signal line 10522 as illustrated in FIG.

The TFT 10524 operates as a switch for electrically connecting the video signal line 10522 and the pixel electrode 10525. Note that as illustrated in FIG. 50B, either the source region or the drain region of the TFT 10524 may be arranged so as to surround the other of the source region or the drain region. By doing so, a large channel width can be obtained with a small area, and the switching capability can be increased. Note that as illustrated in FIG. 50B, the gate electrode of the TFT 10524 may be disposed so as to surround the first semiconductor layer 10505.

The pixel electrode 10525 is electrically connected to one of the source electrode and the drain electrode of the TFT 10524. The pixel electrode 10525 is an electrode for applying a signal voltage transmitted through the video signal line 10522 to the liquid crystal element. Further, a pixel capacitor may be formed by disposing the common electrode 10523. Thus, the pixel electrode 10525 can easily hold the signal voltage transmitted through the video signal line 10522. Note that the pixel electrode 10525 is preferably formed in a bent comb-like shape as illustrated in FIG. Thus, a plurality of regions with different alignment of the liquid crystal molecules 10518 can be formed, so that a liquid crystal display device with a wide viewing angle can be obtained. In the case where the comb-like pixel electrode 10525 and the common electrode 10523 are formed using a transparent material, a transmissive liquid crystal display device can be obtained. Note that a transmissive liquid crystal display device can be obtained even when the comb-like pixel electrode 10525 is formed using a non-reflective material and the common electrode 10523 is formed using a transparent material. A transmissive liquid crystal display device has high color reproducibility and can display an image with high image quality. In the case where the comb-like pixel electrode 10525 and the common electrode 10523 are formed using a reflective material, a reflective liquid crystal display device can be obtained. However, if at least the common electrode 10523 is made of a reflective material, a reflective liquid crystal display device can be obtained. The reflective liquid crystal display device has high visibility in a bright environment such as outdoors and does not require a backlight, so that power consumption can be extremely reduced. Note that in the case where the comb-like pixel electrode 10525 and the common electrode 10523 are formed using both a transparent material and a reflective material, a transflective liquid crystal display device having both advantages is obtained. Obtainable. However, even when the comb-like pixel electrode 10525 is formed using a reflective material and the pixel electrode 10525 is formed using a transmissive material, a transflective liquid crystal display device can be obtained. Note that in the case where the pixel electrode 10525 and the comb-shaped common electrode 10523 are formed using a reflective material, the surfaces of the comb-shaped pixel electrode 10525 and the common electrode 10523 may be uneven. Alternatively, the surface of the third insulating film 10508 can be uneven so that the comb-like pixel electrode 10525 and the common electrode 10523 can be uneven. By doing so, since the reflected light is irregularly reflected, there is an advantage that the angle dependence of the intensity distribution of the reflected light is reduced. That is, it is possible to obtain a reflective liquid crystal display device having a certain brightness at any angle.

Note that although the comb-like pixel electrode 10525 is formed using the fourth conductive layer 10513 and the uniform common electrode 10523 is formed using the third conductive layer 10509, the display device of this embodiment The pixel configuration to which can be applied is not limited to this, and can be appropriately selected as long as a certain condition is satisfied. More specifically, it is only necessary that the comb-like electrode is positioned closer to the liquid crystal than the uniform electrode when viewed from the first substrate 10501. This is because the horizontal electric field is always generated in the opposite direction to the uniform electrode when viewed from the comb-like electrode. That is, in order to apply a lateral electric field to the liquid crystal, the comb-like electrode must be positioned closer to the liquid crystal than the uniform electrode.

In order to satisfy this condition, for example, a comb-like electrode may be formed of the fourth conductive layer 10513, a uniform electrode may be formed of the third conductive layer 10509, or a comb-like electrode may be formed. The fourth conductive layer 10513 may be used, and a uniform electrode may be formed using the second conductive layer 10507. Alternatively, a comb-like electrode may be formed using the fourth conductive layer 10513 and a uniform electrode may be formed. The first conductive layer 10503 may be formed, a comb-like electrode may be formed of the third conductive layer 10509, a uniform electrode may be formed of the second conductive layer 10507, or a comb A tooth-like electrode may be formed of the third conductive layer 10509, a uniform electrode may be formed of the first conductive layer 10503, or a comb-like electrode may be formed of the second conductive layer 10507, A uniform electrode may be formed using the first conductive layer 10503. Note that the comb-like electrode is electrically connected to one of the source region and the drain region of the TFT 10524, and the uniform electrode is electrically connected to the common electrode 10523, but this connection is reversed. But you can. In that case, a uniform electrode may be formed independently for each pixel.

Next, various liquid crystal modes applicable to the liquid crystal display device of this embodiment will be described.

First, FIGS. 51A1 and 51A2 are schematic views of a TN mode liquid crystal display device.

As in the above embodiment mode, the liquid crystal layer 10600 is sandwiched between the first substrate 10601 and the second substrate 10602 which are arranged to face each other. A layer 10603 including a first polarizer is stacked on the first substrate 10601 side, and a layer 10604 including a second polarizer is disposed on the second substrate 10602 side. Note that the layer 10603 including the first polarizer and the layer 10604 including the second polarizer are arranged so as to be crossed Nicols.

Although not shown, the backlight or the like is disposed outside the layer including the second polarizer. A first electrode 10605 and a second electrode 10606 are provided over the first substrate 10601 and the second substrate 10602, respectively. The first electrode 10605 which is the electrode on the side opposite to the backlight, that is, the viewing side is formed so as to have at least translucency.

In the liquid crystal display device having the structure as illustrated in FIGS. 51A1 and 51A, in the normally white mode, voltage is applied to the first electrode 10605 and the second electrode 10606 (referred to as a vertical electric field mode). Then, black display is performed as shown in FIG. At this time, the liquid crystal molecules are aligned vertically. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

Then, as shown in FIG. 51A2, when a voltage is not applied between the first electrode 10605 and the second electrode 10606, white display is performed. At this time, the liquid crystal molecules are aligned horizontally and are rotated in a plane. As a result, light from the backlight passes through a layer including a pair of polarizers (a layer including a first polarizer 10603 and a layer 10604 including a second polarizer) arranged to be crossed Nicols. And a predetermined video display is performed.

A liquid crystal display device having a structure illustrated in FIGS. 51A1 and 51A2 can perform full-color display by being provided with a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. However, the liquid crystal display device having the configuration shown in FIGS. 51A1 and 51A2 performs full color display by field sequential driving if the light from the backlight changes with time without providing a color filter. Can do.

A known liquid crystal material may be used for the TN mode.

FIG. 51B1 is a schematic view of a VA mode liquid crystal display device. The VA mode is a mode in which liquid crystal molecules are aligned so as to be perpendicular to the substrate when there is no electric field.

Similarly to FIGS. 51A1 and 51A2, a first electrode 10605 and a second electrode 10606 are provided over the first substrate 10601 and the second substrate 10602, respectively. The first electrode 10605 which is the electrode on the side opposite to the backlight, that is, the viewing side is formed so as to have at least translucency. A layer 10603 including a first polarizer is stacked on the first substrate 10601 side, and a layer 10604 including a second polarizer is disposed on the second substrate 10602 side. Note that the layer 10603 including the first polarizer and the layer 10604 including the second polarizer are arranged so as to be crossed Nicols.

In the liquid crystal display device having the structure illustrated in FIGS. 51A1 and 51A2, voltage is applied to the first electrode 10605 and the second electrode 10606 (vertical electric field mode), and FIG. As shown, a white display is performed. At this time, the liquid crystal molecules are arranged side by side. Then, light from the backlight passes through a layer including a pair of polarizers (a layer 10603 including a first polarizer and a layer 10604 including a second polarizer) which are arranged to be crossed Nicols. And a predetermined video display is performed. At this time, a full color display can be performed by providing a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side.

As shown in FIG. 51B2, when no voltage is applied between the first electrode 10605 and the second electrode 10606, black display is performed, that is, an off state is obtained. At this time, the liquid crystal molecules are aligned vertically. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

In the off state, the liquid crystal molecules rise perpendicularly to the substrate and display black, and in the on state, the liquid crystal molecules tilt horizontally with respect to the substrate and display white. Since the liquid crystal molecules are standing up in the off state, the light from the polarized backlight passes through the cell without being affected by the birefringence of the liquid crystal molecules and is blocked by the layer containing the polarizer on the counter substrate side. be able to.

Here, FIGS. 51C1 and 51C2 illustrate examples in which the layer including the stacked polarizers of the display device of this embodiment is applied to the MVA mode in which the alignment of the liquid crystal is divided. The MVA mode is a method for mutually compensating the viewing angle dependency of each part. As shown in FIG. 51C1, in the MVA mode, protrusions 10607 and 10608 having a triangular cross section are provided on the first electrode 10605 and the second electrode 10606 for alignment control. When voltage is applied to the first electrode 10605 and the second electrode 10606 (vertical electric field mode), white display is performed as illustrated in FIG. 51C1. At this time, the liquid crystal molecules are tilted with respect to the protrusions 10607 and 10608. Then, light from the backlight passes through a layer including a pair of polarizers (a layer 10603 including a first polarizer and a layer 10604 including a second polarizer) which are arranged to be crossed Nicols. And a predetermined video display is performed. Note that a liquid crystal display device having a structure illustrated in FIGS. 51C1 and 51C2 can perform full-color display by being provided with a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Needless to say, the liquid crystal display device having the structure shown in FIGS. 51C1 and 51C2 can perform full-color display by field sequential driving without providing a color filter.

Then, as shown in FIG. 51C2, when voltage is not applied between the first electrode 10605 and the second electrode 10606, black display is performed, that is, an off state is obtained. At this time, the liquid crystal molecules are aligned vertically. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

FIG. 54 shows a top view and a cross-sectional view of another example of the MVA mode. As shown in FIG. 54A, the second electrodes 10606a, 10606b, and 10606c may be formed in a bent pattern like a dogleg shape. In addition, insulating layers 10901 and 10902 are formed in the vicinity of the liquid crystal layer 10600. Note that the insulating layers 10901 and 10902 may be alignment films. As shown in FIG. 54B, in the vicinity of the first electrode 10605, the protrusion 1
0607 may be formed corresponding to the second electrodes 10606a, 10606b, and 10606c. By forming the protrusion 10607 corresponding to the second electrodes 10606a, 10606b, and 10606c, the openings of the second electrodes 10606a, 10606b, and 10606c function like protrusions, and the liquid crystal molecules are effectively used. Can be oriented. Note that the order in which the first electrode 10605 and the protrusion 10607 are formed may be opposite to that in FIG.

52A1 and 52A2 are schematic views of an OCB mode liquid crystal display device. In the OCB mode, the alignment of liquid crystal molecules forms an optically compensated state in the liquid crystal layer, which is called bend alignment.

As in FIG. 51, a first electrode 10605 and a second electrode 10606 are provided over the first substrate 10601 and the second substrate 10602, respectively. Although not illustrated, the backlight or the like is disposed outside the layer 10604 including the second polarizer. The first electrode 10605 which is the electrode on the side opposite to the backlight, that is, the viewing side is formed so as to have at least translucency. A layer 10603 including a first polarizer is stacked on the first substrate 10601 side, and a layer 10604 including a second polarizer is disposed on the second substrate 10602 side. Note that the layer 10603 including the first polarizer and the layer 10604 including the second polarizer are arranged so as to be crossed Nicols.

In a liquid crystal display device having a structure as illustrated in FIGS. 52A1 and 52A, when a certain on-voltage is applied to the first electrode 10605 and the second electrode 10606 (vertical electric field mode), FIG. Black display is performed as shown in A1). At this time, the liquid crystal molecules are aligned vertically. Then, the light from the backlight cannot pass through the substrate, and a black display is obtained.

Then, as shown in FIG. 52A2, when a constant off voltage is applied between the first electrode 10605 and the second electrode 10606, white display is performed. At this time, the liquid crystal molecules are in a bend alignment state. As a result, light from the backlight passes through a layer including a pair of polarizers (a layer including a first polarizer 10603 and a layer 10604 including a second polarizer) arranged to be crossed Nicols. And a predetermined video display is performed. Note that a liquid crystal display device having a structure illustrated in FIGS. 52A1 and 52A2 can perform full-color display by being provided with a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Needless to say, a liquid crystal display device having a structure as shown in FIGS. 52A1 and 52A2 can perform full-color display by field sequential driving without providing a color filter.

In the OCB mode as shown in FIGS. 52A1 and 52A, the alignment of the liquid crystal molecules can be optically compensated in the liquid crystal layer, so that the viewing angle dependency is small, and the contrast is increased by the layer including a pair of stacked polarizers. The ratio can be increased.

52B1 and 52B are schematic views of liquid crystals in the FLC mode and the AFLC mode.

As in FIG. 51, a first electrode 10605 and a second electrode 10606 are provided over the first substrate 10601 and the second substrate 10602, respectively. The first electrode 10605 which is the electrode on the side opposite to the backlight, that is, the viewing side is formed so as to have at least translucency. A layer 10603 including a first polarizer is stacked on the first substrate 10601 side, and a layer 10604 including a second polarizer is disposed on the second substrate 10602 side. Note that the layer 10603 including the first polarizer and the layer 10604 including the second polarizer are arranged so as to be crossed Nicols.

In the liquid crystal display device having the structure illustrated in FIGS. 52B1 and 52B, when voltage is applied to the first electrode 10605 and the second electrode 10606 (referred to as a vertical electric field mode), FIG. As shown in FIG. At this time, the liquid crystal molecules are arranged side by side in a direction shifted from the rubbing direction. Therefore, light from the backlight passes through a layer including a pair of polarizers (a layer 10603 including a first polarizer and a layer 10604 including a second polarizer) which are arranged to be crossed Nicols. And a predetermined video display is performed.

Then, as shown in FIG. 52B2, when no voltage is applied between the first electrode 10605 and the second electrode 10606, black display is performed. At this time, the liquid crystal molecules are arranged side by side along the rubbing direction. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

Note that a liquid crystal display device having a structure illustrated in FIGS. 52B1 and 52B2 can perform full-color display by being provided with a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Needless to say, a liquid crystal display device having a structure as shown in FIGS. 52B1 and 52B2 can perform full-color display by field sequential driving without providing a color filter.

As the liquid crystal material used in the FLC mode and the AFLC mode, a known material may be used.

53A1 and 53A2 are schematic views of an IPS mode liquid crystal display device. The IPS mode is a mode in which liquid crystal molecules are always rotated in a plane with respect to a substrate, and an electrode adopts a horizontal electric field method provided only on one substrate side.

The IPS mode is characterized in that the liquid crystal is controlled by a pair of electrodes provided on one substrate. Therefore, a pair of electrodes 10801 and 10802 is provided over the second substrate 10602. The pair of electrodes 10801 and 10802 may each have a light shielding property. A layer 10603 including a first polarizer is stacked on the first substrate 10601 side, and a layer 10604 including a second polarizer is disposed on the second substrate 10602 side. Note that the layer 10603 including the first polarizer and the layer 10604 including the second polarizer may be arranged so as to be crossed Nicols.

In a liquid crystal display device having a structure as shown in FIGS. 53A1 and 53A, when voltage is applied to the pair of electrodes 10801 and 10802, liquid crystal molecules are displaced from the rubbing direction as shown in FIG. It is aligned along the electric lines of force and is turned on so that white display is performed. Then, light from the backlight passes through a layer including a pair of polarizers (a layer 10603 including a first polarizer and a layer 10604 including a second polarizer) which are arranged to be crossed Nicols. And a predetermined video display is performed.

Note that a liquid crystal display device having a structure illustrated in FIGS. 53A1 and 53A2 can perform full-color display by being provided with a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Needless to say, the liquid crystal display device having the structure illustrated in FIGS. 53A1 and 53A2 can perform full-color display by field sequential driving without a color filter.

Then, as shown in FIG. 53A2, when no voltage is applied between the pair of electrodes 10604 and 10602, black display, that is, an off state is obtained. At this time, the liquid crystal molecules are arranged side by side along the rubbing direction. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

An example of a pair of electrodes 10801 and 10802 that can be used in the IPS mode is shown in FIG. In FIGS. 55A to 55D, the electrode 10801 corresponds to the electrode 10801a, the electrode 10801b, the electrode 10801c, and the electrode 10801d. The electrode 10802 corresponds to the electrode 10802a, the electrode 10802b, the electrode 10802c, and the electrode 10802d. In FIG. 55A, the electrode 10801a and the electrode 10802a are wavy shapes having waviness, and in FIG. 55B, the electrode 10801b and the electrode 10802b are shapes having concentric openings, and FIG. In FIG. 55D, the electrode 10801c and the electrode 10802c are comb-like and partly overlapped. In FIG. 55D, the electrode 10801d and the electrode 10802d are comb-like and have a shape in which the electrodes are engaged with each other.

In addition to the IPS mode, an FFS mode can also be used. In the IPS mode, the pair of electrodes are formed on the same insulating film, whereas in the FFS mode, as shown in FIGS. 53 (B1) and (B2), the pair of electrodes 10803 and 10804 are They may be formed on different layers of insulating films.

When a voltage is applied to the pair of electrodes 10803 and 10804 in the liquid crystal display device having the structure illustrated in FIGS. 53B1 and 53B, white display is performed as illustrated in FIG. 53B1. Turns on. Then, light from the backlight passes through a layer including a pair of polarizers (a layer 10603 including a first polarizer and a layer 10604 including a second polarizer) which are arranged to be crossed Nicols. And a predetermined video display is performed.

Note that a liquid crystal display device having a structure illustrated in FIGS. 53B1 and 53B2 can perform full-color display by being provided with a color filter. The color filter can be provided on either the first substrate 10601 side or the second substrate 10602 side. Needless to say, the liquid crystal display device having the structure shown in FIGS. 53B1 and 53B2 can perform full-color display by field sequential driving without providing a color filter.

Then, as shown in FIG. 53B2, when no voltage is applied between the pair of electrodes 10803 and 10804, black display, that is, an off state is obtained. At this time, the liquid crystal molecules are arranged side by side and rotated in a plane. As a result, the light from the backlight cannot pass through the substrate, resulting in a black display.

An example of a pair of electrodes 10803 and 10804 that can be used in the FFS mode is shown in FIG. In FIGS. 56A to 56D, the electrode 10803 corresponds to the electrode 10803a, the electrode 10803b, the electrode 10803c, and the electrode 10803d. The electrode 10804 corresponds to the electrode 10804a, the electrode 10804b, the electrode 10804c, and the electrode 10804d. In FIG. 56A, the electrode 10803a has a bent shape, and the electrode 10804a may not be patterned in the pixel region. In FIG. 56B, the electrode 10803b has a concentric shape, and the electrode 10804b may not be patterned in the pixel region. In FIG. 56C, the electrode 10803c has a comb-like shape and the electrodes are engaged with each other, and the electrode 10804c is not necessarily patterned in the pixel region. In FIG. 56D, the electrode 10803d has a comb-like shape, and the electrode 10804d may not be patterned in the pixel region.

Note that the electrode 10803 (10803a, 10803b, 10803c, 10803d) and the electrode 10804 (10804a, 10804b, 10804c, 10804d) may have a light-transmitting property. With the light-transmitting property, a transmissive display device with a high aperture ratio can be obtained.

Note that the electrode 10803 (10803a, 10803b, 10803c, 10803d) and the electrode 10804 (10804a, 10804b, 10804c, 10804d) may have a light-blocking property or a reflective property. With the light-shielding property or the reflective property, a reflective display device with low power consumption and no backlight can be obtained.

Note that the electrode 10803 (10803a, 10803b, 10803c, and 10803d) and the electrode 10804 (10804a, 10804b, 10804c, and 10804d) each include a light-transmitting region and a light-blocking or reflective region. You may do it. By having both areas, a transmissive display with high display quality is displayed in a dark environment such as indoors, and a reflective display with low power consumption is unnecessary in a bright environment such as outdoors. Thus, a transflective display device can be obtained.

As the liquid crystal material used for the IPS mode and the FFS mode, a known material may be used.

Note that as liquid crystal modes applicable to the liquid crystal display device of this embodiment, there are an ASM (Axial Symmetric Aligned Micro-cell) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, and the like in addition to the above-described liquid crystal mode.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination, or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 9)
In the present embodiment, a display panel configuration and a peripheral configuration of the display device will be described. In particular, a display panel (also referred to as a liquid crystal panel) configuration and a peripheral configuration of a liquid crystal display device will be described.

First, a simple structure of the liquid crystal panel will be described with reference to FIG. FIG. 57A is a top view of the liquid crystal panel.

In the liquid crystal panel illustrated in FIG. 57A, a pixel portion 20101, a scan line side input terminal 20103, and a signal line side input terminal 20104 are formed over a substrate 20100. A scanning line extends from the scanning line side input terminal 20103 in the row direction and is formed on the substrate 20100, and a signal line extends from the signal line input terminal 20104 in the column direction and is formed on the substrate 20100. In the pixel portion 20101, the pixels 20102 are arranged on the matrix where the scanning lines and the signal lines intersect. In addition, in the pixel 20102, a switching element and a pixel electrode layer are arranged.

As shown in the liquid crystal panel in FIG. 57A, the scanning line side input terminals 20103 are formed on both sides of the substrate 20100 in the row direction. The signal line input terminal 20103 is formed on one side in the column direction of the substrate 20100. The scanning lines extending from one scanning line side input terminal 20103 and the scanning lines extending from the other scanning line side input terminal 20103 are alternately formed.

In each pixel 20102 of the pixel portion 20101, the first terminal of the switching element is connected to the signal line, and the second terminal is connected to the pixel electrode layer, so that each pixel 20102 is independent by a signal input from the outside. Can be controlled. Note that on / off of the switching element is controlled by a signal supplied to the scanning line.

Note that the pixels 20102 can be arranged with high density by arranging the scan line side input terminals 20103 in both of the row directions of the substrate 20100. In addition, by arranging the signal line side input terminal 20103 in one of the column directions of the substrate 20100, the frame of the liquid crystal panel can be narrowed or the region of the pixel 20101 can be enlarged.

Note that as described above, the substrate 20100 includes a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a stainless steel substrate, and a stainless steel foil. A substrate or the like can be used.

Note that as described above, a transistor, a diode (for example, a PN diode, a PIN diode, a Schottky diode, a diode-connected transistor, or the like), a thyristor, or a logic circuit combining them can be used as the switching element. .

Note that in the case where a TFT is used as the switching element, the gate of the TFT is connected to the scanning line, the first terminal is connected to the signal line, and the second terminal is connected to the pixel electrode layer. Can be controlled independently by an externally input signal.

Note that the scan line side input terminal 20103 may be arranged in one of the row directions of the substrate 20100. By arranging the scan line side input terminal 20103 in one of the row directions of the substrate 20100, the frame of the liquid crystal panel can be narrowed and the region of the pixel 20101 can be enlarged.

Note that the scanning line extending from one scanning line side input terminal 20103 and the scanning line extending from the other scanning line side input terminal 20103 may be shared.

Note that the signal line side input terminals 20103 may be arranged in both of the column directions of the substrate 20100. By arranging the signal line side input terminals 20103 in both the column directions of the substrate 20100, the pixels 20102 can be arranged with high density.

Note that a capacitor may be further formed in the pixel 20102. In the case where a capacitor is provided in the pixel 20102, a capacitor line may be formed over the substrate 20100. In the case where a capacitor line is formed over the substrate 20100, the first electrode of the capacitor is connected to the capacitor line and the second terminal is connected to the pixel electrode layer. In the case where a capacitor line is not formed over the substrate 20100, the first electrode of the capacitor is connected to a different scan line from the pixel 20102 in which the capacitor is arranged, and the second terminal is connected to the pixel electrode layer. To be.

Here, the liquid crystal panel illustrated in FIG. 57A has a structure in which signals supplied to the scan lines and the signal lines are controlled by an external driver circuit. As illustrated in FIG. The driver IC 20201 may be mounted on the substrate 20100 by a COG (Chip on Glass) method. As another structure, as shown in FIG. 58B, TAB (Tape
The driver IC 20201 may be mounted on an FPC (Flexible Printed Circuit) 20200 by an Automated Bonding method. In FIG. 58, the driver IC 20201 is connected to the FPC 20200.

Note that the driver IC 20201 may be formed over a single crystal semiconductor substrate or a circuit formed with TFTs over a glass substrate.

Note that in the liquid crystal panel illustrated in FIG. 57A, the scan line driver circuit 20105 may be formed over the substrate 20100 as illustrated in FIG. In addition, as illustrated in FIG. 57C, the scan line driver circuit 20105 and the signal line driver circuit 20106 may be formed over the substrate 20100.

Note that the scan line driver circuit 20105 and the scan line driver circuit 2010 are each formed using a large number of N-channel transistors and a large number of P-channel transistors. However, it may be composed of only a large number of N-channel transistors or only a large number of P-channel transistors.

Next, details of the pixel 20102 will be described with reference to circuit diagrams of FIGS.

A pixel 20102 in FIG. 59A includes a transistor 20301, a liquid crystal element 20302, and a capacitor 20303. A gate of the transistor 20301 is connected to the wiring 20305 and a first terminal is connected to the wiring 20304. A first electrode of the liquid crystal element 20302 is connected to the counter electrode 20307, and a second electrode is connected to the second terminal of the transistor 20301. A first electrode of the capacitor 20303 is connected to the wiring 20306, and a second electrode is connected to the second terminal of the transistor 20301.

Note that the wiring 20304 is a signal line, the wiring 20305 is a scanning line, and the wiring 20306 is a capacitor line. The transistor 20301 is a switching transistor and may be a P-channel transistor or an N-channel transistor. In addition, the liquid crystal element 20307 includes, as operation modes, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment), PVA ), ASM (Axial Symmetrical Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Antiferrorefractive Liquid) Or the like can be used.

A video signal and a scanning signal are input to the wiring 20304 and the wiring 20305, respectively. The video signal is an analog voltage signal, and the scanning signal is an H level or L level digital voltage signal. However, the video signal may be a current signal or a digital signal. In addition, the H level and the L level of the scanning signal may be any potential that can control on / off of the transistor 20301.

A constant power supply voltage is supplied to the capacitor line 20306. However, a pulsed signal may be supplied.

An operation of the pixel 20102 in FIG. 59A is described. First, when the wiring 20305 becomes an H level, the transistor 20301 is turned on, and a video signal is supplied from the wiring 20304 to the second electrode of the liquid crystal element 20302 and the second electrode of the capacitor 20303 through the transistor 20301. The capacitor 20303 holds a potential difference between the potential of the wiring 203076 and the potential of the video signal.

Next, when the wiring 20305 is at an L level, the transistor 20301 is turned off, and the wiring 20304 is electrically disconnected from the second electrode of the liquid crystal element 20302 and the second electrode of the capacitor 20303. However, since the capacitor 20303 holds a potential difference between the potential of the wiring 203076 and the potential of the video signal, the potential of the second electrode of the capacitor 20302 can be maintained at the same potential as the video signal.

In this manner, the pixel 20102 in FIG. 59A can maintain the potential of the second electrode of the liquid crystal element 20302 at the same potential as the video signal, and can maintain the transmittance of the liquid crystal element 20302 according to the video signal.

Note that although not illustrated, the capacitor 20303 is not necessarily required as long as the liquid crystal element 20302 has a capacitance component that can hold a video signal.

Note that the first electrode of the liquid crystal element 20302 may be connected to the wiring 20306 as illustrated in FIG. For example, when the liquid crystal mode of the liquid crystal element 20302 is the FFS mode, the liquid crystal element 20302 uses the structure in FIG.

Note that as illustrated in FIG. 60, the first electrode of the capacitor 20303 may be connected to the wiring 20305a in the previous row. Note that when the wiring 20305a is an n-th scanning line (n is a positive integer), the wiring 20305b is an n + 1-th scanning line. Similarly, when the transistor 20301a, the pixel 20102a, and the capacitor 20303a are elements in the n-th row, the transistor 20301b, the pixel 20102b, and the capacitor 20303b are elements in the n + 1-th row. In this manner, the number of wirings can be reduced by connecting the first electrode of the capacitor 20303b to the wiring 20305a in the previous row. Therefore, the aperture ratio of the pixels 20102a and 20102b in FIG. 60 can be increased.

Next, a more detailed configuration of the liquid crystal panel than the configuration of the liquid crystal panel described with reference to FIGS. 57 and 58 will be described with reference to FIG. Specifically, a configuration of a liquid crystal panel including a TFT substrate, a counter substrate, and a liquid crystal layer sandwiched between the counter substrate and the TFT substrate will be described. FIG. 61A is a top view of the liquid crystal panel. FIG. 61B is a cross-sectional view taken along line CD in FIG. FIG. 61B is a cross-sectional view in the case where a top-gate transistor in which a crystalline semiconductor film (polysilicon film) is used as a semiconductor film over a substrate 20100 is formed.

In a liquid crystal panel illustrated in FIG. 61A, a pixel portion 20101, a scan line driver circuit 20105a, a scan line driver circuit 20105b, and a signal line driver circuit 2010 are formed over a substrate 20100. The pixel portion 20101, the scan line driver circuit 20105a, the scan line driver circuit 20105b, and the signal line driver circuit 2010 are sealed between the substrate 20100 and the counter substrate 20515 with a sealant 20516. In addition, by the TAB method, FPC2051
8 and the IC chip 20530 are arranged on the substrate 20100.

A cross-sectional structure taken along line CD in FIG. 61A is described with reference to FIG. A pixel portion 20101 and its peripheral driver circuit portions (a scan line circuit 20105a, a scan line circuit 20105b, and a signal line driver circuit 20106) are formed over a substrate 20100. Here, a driver circuit region 20525 (a scan line driver) A circuit 20105a and a scan line driver circuit 20105b) and a pixel region 20526 (pixel portion 20101) are shown.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. As the insulating film 20501, a single layer of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiOxNy), or a stacked structure including at least two of these films may be used.

Note that a silicon oxide film is preferably used in a portion in contact with the semiconductor. As a result, electron trapping in the base film and hysteresis of transistor characteristics can be suppressed. Further, it is desirable to dispose at least one film containing a large amount of nitrogen as the base film. Thereby, impurities from the glass can be reduced.

Next, a semiconductor film 20502 is formed over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like.

Next, an insulating film 20503 is formed over the insulating film 20501 and the semiconductor film 20502 as a gate insulating film.

Note that as the insulating film 20503, a single-layer structure or a stacked structure such as a thermal oxide film, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used. The insulating film 20503 in contact with the semiconductor film 20503 is preferably a silicon oxide film. This is because a trap level at the interface with the semiconductor film 20503 decreases when a silicon oxide film is used. When the gate electrode is formed of Mo, the gate insulating film in contact with the gate electrode is preferably a silicon nitride film. This is because the silicon nitride film does not oxidize Mo. Here, a 115-nm-thick silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) is formed as the insulating film 20503 by a plasma CVD method.

Next, a conductive film 20504 is formed as a gate electrode over the insulating film 20503 by a photolithography method, an inkjet method, a printing method, or the like.

Note that as the conductive film 20504, Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, and alloys of these elements are used. is there. Or you may comprise by lamination | stacking of these elements or the alloy of these elements. Here, the gate electrode is formed of Mo. Mo is suitable because it is easy to etch and is resistant to heat.

Note that the semiconductor film 20502 is formed by doping the semiconductor film 20502 with an impurity element using the conductive film 20504 or a resist as a mask to form a channel formation region and impurity regions to be a source region and a drain region.

The impurity region may be formed as a high concentration region and a low concentration region by controlling the impurity concentration.

Note that the conductive film 20504 of the transistor 20521 has a dual gate structure.
When the transistor 20531 has a dual-gate structure, the off-state current of the transistor 20531 can be reduced. Note that the dual gate structure is a structure having two gate electrodes. Note that a plurality of gate electrodes may be provided over the channel region of the transistor.

Next, an insulating film 20505 is formed as an interlayer film over the insulating film 20503 and the conductive film 20504.

Note that as the insulating film 20505, an organic material, an inorganic material, or a stacked structure thereof can be used. For example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide or aluminum oxide whose nitrogen content is higher than oxygen content, diamond like carbon (DLC), polysilazane, nitrogen content It can be formed of a material selected from carbon (CN), PSG (phosphorus glass), BPSG (phosphorus boron glass), alumina, and other inorganic insulating materials. An organic insulating material may be used, and the organic material may be either photosensitive or non-photosensitive, and polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane resin, or the like can be used. . Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

Note that a contact hole is selectively formed in the insulating film 20503 and the insulating film 20505. For example, the contact hole is formed on the upper surface of the impurity region of each transistor.

Next, a conductive film 20506 is formed over the insulating film 20505 as a drain electrode, a source electrode, and a wiring by a photolithography method, an inkjet method, a printing method, or the like.

Note that the conductive film 20506 includes Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, and the like. There are alloys. Alternatively, a stacked structure of these elements or an alloy of these elements can be used.

Note that the conductive film 20506 and the impurity region of the semiconductor film 20502 of the transistor are connected to each other in a portion where the insulating film 20503 and the contact hole of the insulating film 20504 are formed.

Next, an insulating film 20507 is formed as a planarization film over the insulating film 20505 and the conductive film 20506 formed over the insulating film 20505.

Note that the insulating film 20507 is preferably formed using an organic material because the insulating film 20507 preferably has good flatness and coverage. Note that the insulating film 20507 may have a multilayer structure, and an organic material may be formed over an inorganic material (silicon oxide, silicon nitride, or silicon oxynitride).

Note that a contact hole is selectively formed in the insulating film 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521.

Next, a conductive film 20508 is formed as a pixel electrode over the insulating film 20507 by a photolithography method, an inkjet method, a printing method, or the like.

Note that as the conductive film 20508, a transparent electrode that transmits light and a reflective electrode that reflects light can be used.

In the case of a transparent electrode, for example, an indium tin oxide (ITO) film in which tin oxide is mixed with tin oxide, an indium tin silicon oxide (ITSO) film in which silicon oxide is mixed in indium tin oxide (ITO), indium oxide An indium zinc oxide (IZO) film, a zinc oxide film, a tin oxide film, or the like in which zinc oxide is mixed can be used. Note that IZO is a transparent conductive material formed by sputtering using a target in which 2 to 20 wt% of zinc oxide (ZnO) is mixed with ITO, but is not limited thereto.

In the case of a reflective electrode, for example, Ti, Mo, Ta, Cr, W, Al, Nd, Cu, Ag, Au, Pt, Nb, Si, Zn, Fe, Ba, Ge, or an alloy thereof is used. Can do. Alternatively, a two-layer structure in which Ti, Mo, Ta, Cr, W and Al are stacked, or a three-layer structure in which Al is sandwiched between metals such as Ti, Mo, Ta, Cr, and W may be used.

Next, an insulating film 20509 is formed as an alignment film over the insulating film 20507 and the conductive film 20508 formed over the insulating film 20507.

Next, a sealant 20516 is formed on the periphery of the pixel portion 20101, or the periphery of the pixel portion 20101 and the periphery of the peripheral driver circuit portion by an inkjet method or the like.

Next, the substrate 20515 over which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed is attached to the substrate 20100 with the spacer 20511 interposed therebetween, and the liquid crystal layer 20510 is disposed in the gap. Has been.

Note that the substrate 20115 may function as a counter substrate. The insulating film 20514 may function as a black matrix (light shielding film). The insulating film 20513 may function as a color filter. Alternatively, the spacer 20531 may be provided by dispersing particles of several μm, or may be formed by etching the resin film after forming the resin film on the entire surface of the substrate. Further, the conductive film 20512 may function as a counter electrode. The conductive film 20512 can be similar to the conductive film 20508. The insulating film 20511 may function as an alignment film.

Note that the insulating film 20532 may be formed between the insulating film 20513 and the insulating film 20514 and the conductive film 20512 as a planarization film. Note that the insulating film 20532 is not illustrated in FIG.

Note that a known liquid crystal can be used freely as the liquid crystal layer 20510. For example, a ferroelectric liquid crystal or an anti-ferroelectric liquid crystal may be used as the liquid crystal 20510. In addition, the driving method of the liquid crystal includes a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, and a PVA (Vertinal Pattern). ASM (Axial Symmetrical Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid)
Crystal) etc. can be used freely.

Next, the FPC 20200 is provided over the conductive film 20531 electrically connected to the pixel portion 20101 and its peripheral driver circuit portion with an anisotropic conductive layer 20517 interposed therebetween. In addition, an IC chip is provided over the FPC 20200 with an anisotropic conductive layer 20517 interposed therebetween. That is, the FPC 20200, the conductive film 20531, and the IC chip 20530 are electrically connected.

Note that the conductive film 20531 has a function of transmitting a signal and a potential input from the FPC 20200 to a pixel or a peripheral circuit. As the conductive film 20531, the same film as the conductive film 20506, the same film as the conductive film 20504, or the same impurity region as the semiconductor film 20502 may be used. A combination of at least two layers may be used.

Note that the IC chip 20530 can effectively use the substrate area by forming a functional circuit (memory or buffer).

In the liquid crystal panel in FIGS. 61A and 61B, the structure in the case where the scan line driver circuit 20105a, the scan line driver circuit 20105b, and the signal line driver circuit 20106 are formed over the substrate 20100 has been described. ), A driver circuit corresponding to the signal line driver circuit 20106 may be formed in the driver IC 20601 and mounted on the liquid crystal panel by a COG method or the like. By forming the signal line driver circuit 20106 in the driver IC 20601, power saving can be achieved. In addition, when the driver IC 20601 is a semiconductor chip such as a silicon wafer, the liquid crystal panel in FIG. 62A can achieve higher speed and lower power consumption.

Similarly, as illustrated in the liquid crystal panel in FIG. 62B, driver circuits corresponding to the scan line driver circuit 20105a, the scan line driver circuit 20105b, and the signal line driver circuit 2010 are assigned to a driver IC 20602a, a driver IC 20602b, and a driver IC 20601, respectively. It may be formed and mounted on a liquid crystal panel by a COG method or the like. In addition, by forming driver circuits corresponding to the scan line driver circuit 20105a, the scan line driver circuit 20105b, and the signal line driver circuit 2010 in the driver IC 20602a, the driver IC 20602b, and the driver IC 20601, cost reduction can be achieved.

Note that although the transistor 20521 has a dual gate structure, the transistor 20521 may have a single gate structure as shown in a pixel portion 20526 in FIG. Note that FIG. 63 illustrates only the pixel portion 20526.

Next, a cross-sectional view in the case where a bottom-gate transistor is formed over the substrate 20100 is described with reference to FIGS. However, FIG. 64 shows only the pixel region 20526.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. Next, a conductive film 20504 is formed over the insulating film 20501 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive film 20504 of the transistor 20521 has a dual gate structure. This is because, as described above, the transistor 20521 can have a dual-gate structure, whereby the off-state current of the transistor 20521 can be reduced. Next, an insulating film 20503 is formed over the insulating film 20501 and the conductive film 20504 as a gate insulating film. Next, a semiconductor film 20502 is formed over the insulating film 20503 by a photolithography method, an inkjet method, a printing method, or the like. Note that in the semiconductor film 20502, an impurity element is doped into the semiconductor film 20502 using a resist as a mask, so that a channel formation region and impurity regions to be a source region and a drain region are formed. The impurity region may be formed as a high concentration region and a low concentration region by controlling the impurity concentration. Next, an insulating film 20505 is formed over the insulating film 20503 and the semiconductor layer 20502 as an interlayer film. Note that a contact hole is selectively formed in the insulating film 20505. For example, the contact hole is formed on the upper surface of the impurity region of each transistor. Next, a conductive film 20506 is formed over the insulating film 20505 as a drain electrode, a source electrode, and a wiring by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive film 20506 is connected to the impurity region of the semiconductor film 20502 of the transistor in a portion where the contact hole of the insulating film 20505 is formed. Next, an insulating film 20507 is formed as a planarization film over the insulating film 20505 and the conductive film 20506. Note that a contact hole is selectively formed in the insulating film 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive film 20508 is formed as a pixel electrode over the insulating film 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20509 is formed as an alignment film over the insulating film 20507 and the conductive film 20508. Next, a liquid crystal layer 20510 is provided in a gap between the substrate 20515 and the substrate 20100 over which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

In FIG. 64, the transistor 20521 has a dual gate structure. Note that as illustrated in the pixel portion 20526 in FIG. 65, the transistor 20521 may have a single gate structure.

Next, a cross-sectional view in the case where a double-gate transistor is formed over the substrate 20100 is described with reference to FIGS. However, FIG. 66 shows only the pixel region 20526.

Note that a double-gate transistor refers to a structure in which gate electrodes are provided above and below a semiconductor film, respectively. In addition, a double-gate transistor has twice the current flowing if it has the same size and the same applied voltage as the top-gate transistor and the bottom-gate transistor. In other words, the double gate transistor can flow more current with a small transistor size.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. Next, a conductive film 20504a is formed as a first gate electrode over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive film 20504a can be formed using a material and a structure similar to those of the conductive film 20504. Next, an insulating film 20503a is formed as a first gate insulating film over the insulating film 20501 and the conductive film 20504a. Note that the insulating film 20503a can be formed using a material and a structure similar to those of the insulating film 20503. Next, a semiconductor film 20502 is formed over the insulating film 20503a by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20503b is formed as a second gate insulating film over the insulating film 20503a and the semiconductor film 20502. Note that the conductive film 20503b can be formed using a material and a structure similar to those of the conductive film 20503. Next, a conductive film 20504b is formed as a second gate electrode over the insulating film 20504b by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive film 20504b can be formed using a material and a structure similar to those of the conductive film 20504. Note that in the semiconductor film 20502, the conductive film 20504b or the resist is used as a mask and the semiconductor film 20502 is doped with an impurity element, so that a channel formation region and impurity regions to be a source region and a drain region are formed. The impurity region may be formed as a high concentration region and a low concentration region by controlling the impurity concentration. Note that before the insulating film 20503b and the conductive film 20504b are formed in the semiconductor film 20502, an impurity element is doped into the semiconductor film 20502 using a resist as a mask so that a channel formation region and an impurity region which serves as a source region and a drain region are formed. And may be formed. Next, an insulating film 20505 is formed as an interlayer film over the insulating film 20503b and the conductive film 20504b. Note that a contact hole is selectively formed in the insulating film 20503b and the insulating film 20505. For example, the contact hole is formed on the upper surface of the impurity region of each transistor. Next, a conductive film 20506 is formed over the insulating film 20505 as a drain electrode, a source electrode, and a wiring by a photolithography method, an inkjet method, a printing method, or the like. Note that the conductive film 20506 and the impurity region of the semiconductor film 20502 of the transistor are connected to each other in a portion where the insulating film 20503 and the contact hole of the insulating film 20504 are formed. Next, an insulating film 20507 is formed over the insulating film 20505 and the conductive film 20506 as a planarization film. Note that a contact hole is selectively formed in the insulating film 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive film 20508 is formed as a pixel electrode over the insulating film 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20509 is formed as an alignment film over the insulating film 20507 and the conductive film 20508. Next, a liquid crystal layer 20510 is provided in a gap between the substrate 20515 and the substrate 20100 over which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

Note that FIGS. 61 and 63 to 66 illustrate cross-sectional views in the case where the insulating film 20507 is formed as a flat film over the insulating film 20505 and the conductive film 20506 formed over the insulating film 20505. . However, the insulating film 20507 is not necessarily required as shown in FIG.

Note that the cross-sectional view in FIG. 67 illustrates the case of a top-gate transistor, but the same applies to the case of a bottom-gate transistor and a double-gate transistor.

Next, a cross-sectional view in the case where a transistor using an amorphous semiconductor film (amorphous silicon film) as a semiconductor film is formed over the substrate 20100 will be described with reference to FIGS. The cross-sectional view in FIG. 68 is a cross-sectional view of an inverted staggered channel-etched transistor.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. Next, a conductive film 20504 is formed over the insulating film 20501 as a gate electrode by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20503 is formed over the insulating film 20501 and the conductive film 20504 as a gate insulating film. Next, a semiconductor film 20502 is formed over the insulating film 20503 by a photolithography method, an inkjet method, a printing method, or the like. Note that the semiconductor film 20502 includes a first semiconductor film and a second semiconductor film, and the second semiconductor film is formed over the first semiconductor film. In addition, the first semiconductor film and the second semiconductor film may be successively formed and simultaneously patterned by a photolithography method. The second semiconductor film contains an impurity element. Next, a conductive film 20506 is formed over the insulating film 20503 and the semiconductor film 20502 by a photolithography method, an inkjet method, a printing method, or the like. Note that the semiconductor film 20502 is etched using the conductive film 20506 as a mask, so that a channel formation region and impurity regions to be a source region and a drain region are formed. That is, in the channel region, the second semiconductor film containing the impurity element is removed. Note that the semiconductor film 20502 may be etched using a resist for etching the conductive film 20506 as a mask. Next, an insulating film 20507 is formed as a planarization film over the insulating film 20503, the semiconductor film 20502, and the conductive film 20506. Note that a contact hole is selectively formed in the insulating film 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive film 20508 is formed as a pixel electrode over the insulating film 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20509 is formed as an alignment film over the insulating film 20507 and the conductive film 20508. Next, a liquid crystal layer 20510 is provided in a gap between the substrate 20515 and the substrate 20100 over which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

Note that although a channel-etched transistor is described, an insulating film 21301 may be provided over the semiconductor film 20502 as illustrated in FIG. The insulating film 21301 is formed between the first semiconductor film and the second semiconductor film. In addition, the semiconductor film 20502 is etched at the same time as the conductive film 20506 is formed.

Note that the transistor 20521 in FIG. 68 is referred to as a channel etch structure, and the transistor 20521 in FIG. 69 is referred to as a channel protection structure.

Next, a cross-sectional view in the case where a top-gate transistor using an amorphous semiconductor film as a semiconductor film is formed over the substrate 20100 is described with reference to FIGS.

First, an insulating film 20501 is formed over the substrate 20100 as a base film. Next, a conductive film 20506 is formed over the insulating film 20501 by a photolithography method, an inkjet method, a printing method, or the like. Next, a semiconductor film 20502a is formed over the conductive film 20506 by a photolithography method, an inkjet method, a printing method, or the like. Note that the semiconductor film 20502a can be formed using a material and a structure similar to those of the semiconductor film 20502. The semiconductor film 20502a contains an impurity element. Next, a semiconductor film 20502b is formed over the insulating film 20501 and the semiconductor film 20502a by a photolithography method, an inkjet method, a printing method, or the like. Note that the semiconductor film 20502b can be formed using a material and a structure similar to those of the semiconductor film 20502. Next, an insulating film 20503 is formed as a gate insulating film over the insulating film 20501, the semiconductor film 20502b, and the conductive film 20506. Next, a conductive film 20504 is formed as a gate electrode over the insulating film 20503 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20507 is formed as a planarization film over the insulating film 20503 and the conductive film 20504 formed over the insulating film 20503. Note that a contact hole is selectively formed in the insulating film 20507. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive film 20508 is formed as a pixel electrode over the insulating film 20507 by a photolithography method, an inkjet method, a printing method, or the like. Next, an insulating film 20509 is formed as an alignment film over the insulating film 20507 and the conductive film 20508. Next, a liquid crystal layer 20510 is provided in a gap between the substrate 20515 and the substrate 20100 over which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

69 and 70, the cross-sectional views in the case where the insulating film 20507 is formed as a flat film over the insulating film 20505 and the conductive film 20506 formed over the insulating film 20505 are described. However, the insulating film 20507 is not necessarily required as shown in FIG.

Note that the cross-sectional view in FIG. 71 illustrates the case of an inverted staggered channel etch transistor, but the same applies to an inverted staggered channel protection transistor. 71 shows the case of an inverted staggered transistor, a top gate transistor may be used. 72 and 73 are cross-sectional views in the case of a top-gate transistor.

72, a conductive film 20508 is formed as a pixel electrode over the insulating film 20501 and the conductive film 20506 by a photolithography method, an inkjet method, a printing method, or the like. The conductive film 20508 is formed after the conductive film 20506 is formed and before the insulating film 20503 is formed.

Note that in the cross-sectional view in FIG. 73, a conductive film 20508 is formed over the insulating film 20501 as a pixel electrode by a photolithography method, an inkjet method, a printing method, or the like. The conductive film 20508 is formed after the insulating film 20501 is formed.

Next, a cross-sectional view of the transflective liquid crystal panel will be described with reference to FIG.

Note that the cross-sectional view of FIG. 74 is a cross-sectional view of a liquid crystal panel in which a transistor uses a polycrystalline semiconductor as a semiconductor film. However, the transistor may be a bottom gate type or a double gate type. The gate electrode of the transistor may have a single gate structure or a dual gate structure.

Note that FIG. 74 is similar to FIG. 63 until the conductive film 20506 is formed. Accordingly, a process and structure after the conductive film 20506 is formed will be described.

First, over the insulating film 20505 and the conductive film 20506 formed over the insulating film 20505, a film for reducing the thickness (a so-called cell gap) of the liquid crystal layer 20510 is a photolithography method, an inkjet method, a printing method, or the like. Thus, an insulating film 21801 is formed. Note that the insulating film 21801 is preferably formed using an organic material because it is desirable that the insulating film 21801 has good flatness and coverage. Note that an organic material may be formed over an inorganic material (silicon oxide, silicon nitride, silicon oxynitride) to have a multilayer structure. Note that a contact hole is selectively formed in the insulating film 21801. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive film 20508a is formed as a first pixel electrode over the insulating film 20505 and the insulating film 20507 by a photolithography method, an inkjet method, a printing method, or the like. Note that as the conductive film 20508a, a transparent electrode that transmits light similar to the conductive film 20508 can be used. Next, a conductive film 20508b is formed as a second pixel electrode over the conductive film 20508a by a photolithography method, an inkjet method, a printing method, or the like. Note that as the conductive film 20508b, a reflective electrode that reflects light similar to the conductive film 20508 can be used. Note that a region where the conductive film 20508b is formed is referred to as a reflective region. In addition, among regions where the conductive film 20508a is formed, a region where the conductive film 20508b is not formed over the conductive film 20508a is referred to as a transmission region. Next, an insulating film 20509 is formed as an alignment film over the insulating film 21801 and over the conductive films 20508a and 20508b. Next, a liquid crystal layer 20510 is provided in a gap between the substrate 20515 and the substrate 20100 over which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

In FIG. 74, the conductive film 20508b is formed after the conductive film 20508a is formed. However, as shown in FIG. 75, the conductive film 20508a may be formed after the conductive film 20508b is formed.

74 and 75, an insulating film for adjusting the liquid crystal layer 20510 (cell gap) is formed under the conductive film 20508a and the conductive film 20508b. However, the insulating film 22001 may be formed on the substrate 20515 side as shown in FIG. The insulating film 22001 is an insulating film for adjusting the liquid crystal layer 20510 (cell gap), like the insulating film 21801.

Note that FIG. 76 illustrates the case where the insulating film 20507 is formed as the planarization film, but the insulating film 20507 may not be formed as illustrated in FIG. 77. In the case of FIG. 77, a conductive film 20506 can be used as the reflective pixel electrode. Of course, another conductive film may be formed as the reflective pixel electrode.

Note that the insulating film 22001 may be formed between the conductive film 20512 and the insulating film 20511, or may be formed between the insulating film 20511 and the liquid crystal layer 20510.

Next, FIG. 78 shows a cross-sectional view of a liquid crystal panel in the case where a polycrystalline semiconductor is used as a semiconductor film of a transistor in a transflective liquid crystal panel.

Note that the cross-sectional view of FIG. 78 is a cross-sectional view of a liquid crystal panel including a transistor using an inverted staggered channel etch structure. However, the transistor may be a top gate type or an inverted stagger type channel protection structure.

Note that FIG. 78 is similar to FIG. 78 until the conductive film 20506 is formed. Accordingly, a process and structure after the conductive film 20506 is formed will be described.

First, over the semiconductor film 20502, the insulating film 20503, and the conductive film 20506, a layer for reducing the thickness (a so-called cell gap) of the liquid crystal layer 20510 is insulated by a photolithography method, an inkjet method, a printing method, or the like. A film 22201 is formed. Note that the insulating film 22201 is preferably formed using an organic material because the insulating film 22201 preferably has good flatness and coverage. Note that an organic material may be formed over an inorganic material (silicon oxide, silicon nitride, silicon oxynitride) to have a multilayer structure. Note that a contact hole is selectively formed in the insulating film 22201. For example, the contact hole is formed on the upper surface of the drain electrode of the transistor 20521. Next, a conductive film 20508a is formed as a first pixel electrode over the insulating film 20503 and the insulating film 22201 by a photolithography method, an inkjet method, a printing method, or the like. Next, a conductive film 20508b is formed as a second pixel electrode over the conductive film 20508a by a photolithography method, an inkjet method, a printing method, or the like. Note that a region where the conductive film 20508b is formed is referred to as a reflective region. In addition, among regions where the conductive film 20508a is formed, a region where the conductive film 20508b is not formed over the conductive film 20508a is referred to as a transmission region. Next, an insulating film 20509 is formed as an alignment film over the insulating film 22201 and over the conductive films 20508a and 20508b. Next, a liquid crystal layer 20510 is provided in a gap between the substrate 20515 and the substrate 20100 over which the insulating film 20514, the insulating film 20513, the conductive film 20512, the insulating film 20511, and the like are formed.

In FIG. 78, the conductive film 20508b is formed after the conductive film 20508a is formed. However, as shown in FIG. 79, the conductive film 20508a may be formed after the conductive film 20508b is formed.

78 and 79, an insulating film for adjusting the liquid crystal layer 20510 (cell gap) is formed under the conductive film 20508a and the conductive film 20508b. However, the insulating film 22001 may be formed on the substrate 20515 side as shown in FIG. Insulating film 2
Reference numeral 2001 denotes an insulating film for adjusting the liquid crystal layer 20510 (cell gap) similarly to the insulating film 22201.

Note that FIGS. 79 and 80 illustrate the case where the insulating film 20507 is formed as the planarization film, but the insulating film 20507 may not be formed as illustrated in FIG. 81. In the case of FIG. 81, a conductive film 20506 can be used as the reflective pixel electrode. Of course, another conductive film may be formed as the reflective pixel electrode.

Note that FIGS. 61 and 63 to 81 show examples in which a pair of electrodes (a conductive film 20508 and a conductive film 20512) for applying a voltage to the liquid crystal layer 20510 are formed over different substrates. However, the conductive film 20512 may be provided over the substrate 20100. Thus, an IPS (In-Plane-Switching) mode can be used as a liquid crystal driving method. Further, depending on the liquid crystal layer 20510, one or both of the two alignment films (the insulating film 20509 and the insulating film 20511) may be omitted.

In FIGS. 61 and 63 to 81, the conductive film 20508 (conductive film 20508b) is formed as the reflective pixel electrode, but the conductive film 20508 is preferably uneven. This is because the reflective pixel electrode is used for display by reflecting external light. This is because in order to efficiently use the external light that has entered the reflective electrode and increase the display luminance, it can be diffusely reflected by the reflective electrode. Note that when the shape of the film (the insulating film 20505, the insulating film 20507, the insulating film 21801, or the insulating film 22201) under the conductive film 20508 is uneven, the shape of the conductive film 20508 becomes uneven.

Subsequently, a liquid crystal display device having the liquid crystal panel described in FIGS. 61 to 81 will be described with reference to FIG.

First, the liquid crystal display device illustrated in FIG. 82 is provided with a backlight unit 22601, a liquid crystal panel 22607, a layer 22608 including a first polarizer, and a layer 22609 including a second polarizer.

Note that the liquid crystal panel 22607 can be the same as that described in this embodiment. In addition, although the liquid crystal panel of this embodiment has been described with respect to an active structure in which a switching element is provided in each pixel, the liquid crystal panel in FIG. 82 may have a passive structure.

The structure of the backlight unit 22601 will be described. The backlight unit 22601 is configured to include a diffusion plate 22602, a light guide plate 22603, a reflection plate 22604, a lamp reflector 22605, and a light source 22606. As the light source 22606, a cold cathode tube, a hot cathode tube, a light emitting diode, an inorganic EL, an organic EL, or the like is used. The light source 22606 has a function of emitting light as necessary. The lamp reflector 22605 has a function of efficiently guiding fluorescence from the light source 22606 to the light guide plate 22603. The light guide plate 22603 has a function of totally reflecting fluorescence and guiding light to the entire surface. The diffusion plate 22602 has a function of reducing brightness unevenness. The reflective plate 22604 has a function of reflecting and reusing light leaked downward from the light guide plate 22603 (the direction opposite to the liquid crystal panel 22607).

In addition, the liquid crystal display device of this embodiment can improve the brightness of the screen of a liquid crystal panel by arrange | positioning a prism sheet between the diffuser plate 22602 and the layer 22609 containing a 2nd polarizer.

A control circuit for adjusting the luminance of the light source 22606 is connected to the backlight unit 22601. The luminance of the light source 22606 can be adjusted by supplying a signal from the control circuit.

A layer 22609 including a second polarizer is provided between the liquid crystal panel 22607 and the backlight unit 22601, and a layer 22608 including the first polarizer is also provided on the liquid crystal panel 22607 in the direction opposite to the backlight unit 22601. Is provided.

Note that the layer 22608 including the first polarizer and the layer 22609 including the second polarizer are arranged so as to be in a crossed Nicol state when the liquid crystal element of the liquid crystal panel 22607 is driven in the TN mode. In addition, the layer 22608 including the first polarizer and the layer 22609 including the second polarizer are arranged so as to be in a crossed Nicol state when the liquid crystal element of the liquid crystal panel 22607 is driven in the VA mode. Further, the layer 22608 including the first polarizer and the layer 22609 including the second polarizer are arranged so as to be in a crossed Nicols state when the liquid crystal element of the liquid crystal panel 22607 is driven in the IPS mode and the FFS mode. It may be arranged so as to be parallel Nicols.

A retardation plate may be provided between both or one of the layer 22608 including the first polarizer and the layer 22609 including the second polarizer and the liquid crystal panel 22607.

As shown in FIG. 85, the slit (grating) 22610 is disposed between the layer 22609 containing the second polarizer and the backlight unit 22601, so that the liquid crystal display device of this embodiment has a three-dimensional display. It can be performed.

A slit 22610 having an opening disposed on the backlight unit side transmits light incident from the light source in a stripe shape and allows the light to enter the display device. With this slit 22610, parallax can be created in both eyes of the viewer on the viewer side, and the viewer sees only the pixels for the right eye in the right eye and only the pixels for the left eye in the left eye at the same time. Therefore, the viewer can see the three-dimensional display. That is, the light given a specific viewing angle by the slit 22610 passes through pixels corresponding to the right-eye image and the left-eye image, so that the right-eye image and the left-eye image are separated into different viewing angles, Three-dimensional display is performed.

If an electronic device such as a television device or a mobile phone is manufactured using the liquid crystal display device in FIG. 85, an electronic device with high functionality and high image quality capable of three-dimensional display can be provided.

Next, a detailed configuration of the backlight will be described with reference to FIG. The backlight is provided in a liquid crystal display device as a backlight unit having a light source, and the light source is surrounded by a reflector so that the backlight unit efficiently scatters light.

As shown in FIG. 84A, the backlight unit 22852 can use a cold cathode tube 22801 as a light source. In addition, a lamp reflector 22832 can be provided in order to efficiently reflect light from the cold cathode tube 22801. The cold cathode tube 22801 is often used for a large display device. This is due to the intensity of the luminance from the cold cathode tube. Therefore, a backlight unit having a cold cathode tube can be used for a display of a personal computer.

As shown in FIG. 84B, the backlight unit 22852 can use a light emitting diode (LED) 22802 as a light source. For example, white light emitting diodes (W) 22802 are arranged at predetermined intervals. In addition, a lamp reflector 22832 can be provided in order to efficiently reflect light from the light emitting diode (W) 22802.

As shown in FIG. 84C, the backlight unit 22852 can use light emitting diodes (LEDs) 22803, 22804, and 22805 for each color RGB as light sources. By using the light emitting diodes (LEDs) 22803, 22804, and 22805 for each color RGB, color reproducibility can be enhanced as compared with only the light emitting diode (W) 22802 that emits white. In addition, a lamp reflector 22832 can be provided to efficiently reflect light from the light emitting diode.

Furthermore, as shown in FIG. 84D, when light-emitting diodes (LEDs) 22803, 22804, and 22805 of each color RGB are used as the light source, it is not necessary to have the same number and arrangement. For example, a plurality of colors with low emission intensity (for example, green) may be arranged.

Furthermore, a light emitting diode 22802 that emits white and a light emitting diode (LED) 22803, 22804, and 22805 of each color RGB may be used in combination.

Note that in the case of having RGB light emitting diodes, when the field sequential mode is applied, color display can be performed by sequentially turning on the RGB light emitting diodes according to time.

When a light-emitting diode is used, it has high luminance and is suitable for a large display device. Further, since the color purity of each of the RGB colors is good, the color reproducibility is superior to that of the cold cathode tube, and the arrangement area can be reduced. Therefore, when the display is adapted to a small display device, the frame can be narrowed.

Further, the light source is not necessarily arranged as the backlight unit shown in FIG. For example, when a backlight having a light emitting diode is mounted on a large display device, the light emitting diode can be disposed on the back surface of the substrate. At this time, the light emitting diodes can maintain predetermined intervals, and the light emitting diodes of the respective colors can be arranged in order. The color reproducibility can be improved by the arrangement of the light emitting diodes.

Next, an example of a layer including a polarizer (also referred to as a polarizing plate or a polarizing film) is described with reference to FIG.

86 includes a protective film 23001, a substrate film 23002, a PVA polarizing film 23003, a substrate film 23004, an adhesive layer 23005, and a release film 23006.

The PVA polarizing film 23003 has a function of generating light only in a certain vibration direction (linearly polarized light). Specifically, the PVA polarizing film 23003 includes molecules (polarizers) in which the electron density differs greatly in the vertical and horizontal directions. The PVA polarizing film 23003 can produce linearly polarized light by aligning the directions of molecules in which the electron density is greatly different in the vertical and horizontal directions.

As an example, the PVA polarizing film 23003 is obtained by doping a polymer film of polyvinyl alcohol (Poly Vinyl Alcohol) with an iodine compound and pulling the PVA film in a certain direction to obtain a film in which iodine molecules are arranged in a certain direction. be able to. And the light parallel to the long axis of an iodine molecule is absorbed by the iodine molecule. In addition, a dichroic dye may be used in place of iodine for high durability use and high heat resistance use. The dye is preferably used in liquid crystal display devices that require durability and heat resistance, such as in-vehicle LCDs and projector LCDs.

The PVA polarizing film 23003 is a film (substrate film 23002 which is a base material on both sides).
And the substrate film 3604), the reliability can be increased. The PVA polarizing film 23003 may be sandwiched between highly transparent and highly durable triacetylrose (TAC) films. In addition, a board | substrate film and a TAC film function as a protective layer of the polarizer which PVA polarizing film 23003 has.

One substrate film (substrate film 23004) has an adhesive layer 23005 attached to a glass substrate of a liquid crystal panel. Note that the pressure-sensitive adhesive layer 23005 is formed by applying a pressure-sensitive adhesive to a substrate film (substrate film 23004) on one side. The pressure-sensitive adhesive layer 23005 is provided with a release film 23005 (separate film).

The other substrate film (substrate film 23002) is provided with a protective film.

A hard coat scattering layer (anti-glare layer) may be provided on the surface of the polarizing film 23000. Since the hard coat scattering layer has fine irregularities formed on the surface by AG treatment and has an antiglare function for scattering external light, reflection of external light on the liquid crystal panel and surface reflection can be prevented.

Further, a plurality of optical thin film layers having different refractive indexes may be formed on the surface of the polarizing film 23000 (also referred to as anti-reflection treatment or AR treatment). The multilayered optical thin film layer having a plurality of refractive indexes can reduce the reflectance of the surface due to the light interference effect.

Next, the operation of each circuit included in the liquid crystal display device will be described with reference to FIG.

FIG. 83 shows a system block diagram of the pixel portion 22705 and the driver circuit portion 22708 of the display device.

The pixel portion 22705 includes a plurality of pixels, and a switching element is provided in an intersection region between the signal line 22712 and the scanning line 22710 which are pixels. Application of a voltage for controlling the tilt of liquid crystal molecules can be controlled by the switching element. A structure in which switching elements are provided in each intersection region in this way is called an active type. The pixel portion of the display device in this embodiment is not limited to such an active type and may have a passive structure. Since the passive type has no switching element in each pixel, the process is simple.

The driver circuit portion 22708 includes a control circuit 22702, a signal line driver circuit 22703, and a scanning line driver circuit 22704. A control circuit 22702 to which the video signal 22701 is input has a function of performing gradation control in accordance with display contents of the pixel portion 22705. Therefore, the control circuit 22702 inputs the generated signal to the signal line driver circuit 22703 and the scan line driver circuit 22704. When a switching element is selected via the scanning line 22710 based on the scanning line driver circuit 22704, a voltage is applied to the pixel electrode in the selected intersection region. The value of this voltage is determined based on a signal input from the signal line driver circuit 22703 via the signal line.

Further, the control circuit 22702 generates a signal for controlling the power supplied to the lighting unit 22706, and the signal is input to the power source 22707 of the lighting unit 22706. The backlight unit described in the above embodiment can be used as the illumination unit. The illumination means includes a front light in addition to the backlight. The front light is a plate-like light unit that is mounted on the front side of the pixel portion and is composed of a light emitter and a light guide that illuminate the whole. Such illumination means can illuminate the pixel portion evenly with low power consumption.

As illustrated in FIG. 83B, the scan line driver circuit 22704 includes circuits that function as a shift register 22741, a level shifter 22742, and a buffer 22743. Signals such as a gate start pulse (GSP) and a gate clock signal (GCK) are input to the shift register 22741. Note that the scan line driver circuit of the display device in this embodiment is not limited to the structure illustrated in FIG.

As shown in FIG. 83C, the signal line driver circuit 22703 includes circuits that function as a shift register 22931, a first latch 22732, a second latch 22733, a level shifter 22734, and a buffer 22735. A circuit functioning as the buffer 22735 is a circuit having a function of amplifying a weak signal and includes an operational amplifier and the like. A signal such as a start pulse (SSP) is input to the level shifter 22734, and data (DATA) such as a video signal is input to the first latch 22732. The second latch 22733 can temporarily hold a latch (LAT) signal and is input to the pixel portion 22705 all at once. This is called line sequential driving. Therefore, the second latch can be omitted if the pixel performs dot sequential driving instead of line sequential driving. As described above, the signal line driver circuit of the display device in this embodiment is not limited to the structure illustrated in FIG.

Such a signal line driver circuit 22703, a scan line driver circuit 22704, and a pixel portion 22705 can be formed using semiconductor elements provided over the same substrate. The semiconductor element can be formed using a thin film transistor provided over a glass substrate. In this case, a crystalline semiconductor film is preferably applied to the semiconductor element. Since the crystalline semiconductor film has high electrical characteristics, particularly mobility, a circuit included in the driver circuit portion can be formed. In addition, the signal line driver circuit 22703 and the scan line driver circuit 22704 can be mounted on a substrate by using an IC (Integrated Circuit) chip. In this case, an amorphous semiconductor film can be applied to the semiconductor element in the pixel portion.

Here, the liquid crystal display module of this embodiment will be described with reference to FIGS. 87 (A) and 87 (B).

FIG. 87A illustrates an example of a liquid crystal display module. A TFT substrate 23100 and a counter substrate 23101 are fixed to each other with a sealant 23102, and a pixel portion 23103 including a TFT and the like and a liquid crystal layer 23104 are provided therebetween to form a display region. ing. The colored layer 23105 is necessary for color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. A layer 23106 including a first polarizer, a layer 23107 including a second polarizer, and a diffusion plate 23113 are disposed outside the TFT substrate 23100 and the counter substrate 23101. The light source is composed of a cold cathode tube 23110 and a reflection plate 23111. The circuit board 23112 is connected to the TFT substrate 23100 by a flexible wiring board 23109, and an external circuit such as a control circuit or a power supply circuit is incorporated.

A layer 23107 including a second polarizer is provided between the TFT substrate 23100 and a backlight as a light source, and a layer 23106 including the first polarizer is provided also on the counter substrate 23101. Yes. On the other hand, the absorption axis of the layer 23107 including the second polarizer and the absorption axis of the layer 23106 including the first polarizer provided on the viewing side are arranged to be crossed Nicols.

The layer 23107 including the second polarizer and the layer 23106 including the first polarizer are bonded to the TFT substrate 23100 and the counter substrate 23101. Moreover, you may laminate | stack in the state which had the phase difference plate between the layer containing the laminated | stacked polarizer, and a board | substrate. Further, if necessary, the layer 23106 including the first polarizer on the viewing side may be subjected to an antireflection treatment.

The liquid crystal display module includes a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, and a PVA (SMB). Axially Symmetrical Aligned Micro-cell (OCB) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid)
Crystal), PDLC (Polymer Dispersed Liquid Crystal) mode, and the like can be used.

87B is an example in which the OCB mode is applied to the liquid crystal display module of FIG. 87A, and is an FS-LCD (Field sequential-LCD). The FS-LCD emits red light, green light, and blue light in one frame period, and can perform color display by combining images using time division. Further, since each light emission is performed by a light emitting diode or a cold cathode tube, a color filter is unnecessary. Therefore, it is not necessary to arrange the color filters of the three primary colors and limit the display area of each color, and it is possible to display all three colors in any area. On the other hand, since three colors of light are emitted in one frame period, a high-speed response of the liquid crystal is required. By applying the FLC mode and the OCB mode using the FS method to the display device of this embodiment mode, a high-performance and high-quality display device or a liquid crystal television device can be completed.

The liquid crystal layer in the OCB mode has a so-called π cell structure. The π cell structure is a structure in which the pretilt angles of liquid crystal molecules are aligned in a plane-symmetric relationship with respect to the center plane between the active matrix substrate and the counter substrate. The alignment state of the π cell structure is splay alignment when no voltage is applied between the substrates, and shifts to bend alignment when a voltage is applied. This bend orientation is white. When a voltage is further applied, the bend-aligned liquid crystal molecules are aligned perpendicularly to both substrates, and light is not transmitted. In the OCB mode, high-speed response that is about 10 times faster than the conventional TN mode can be realized.

Further, as a mode corresponding to the FS method, HV (Half V) -FLC using a ferroelectric liquid crystal (FLC) capable of high-speed operation, SS (Surface Stabilized) -FLC, or the like can be used. .

Further, by narrowing the cell gap of the liquid crystal display module, the optical response speed of the liquid crystal display module can be increased. The speed can also be increased by reducing the viscosity of the liquid crystal material. The increase in speed is more effective when the pixel pitch of the pixel area of the TN mode liquid crystal display module is 30 μm or less. In addition, the speed may be increased by using an overdrive that increases (or lowers) the applied voltage applied to the liquid crystal layer for a moment from the original voltage.

The liquid crystal display module in FIG. 87B is a transmissive liquid crystal display module, and is provided with a red light source 23190a, a green light source 23190b, and a blue light source 23190c as light sources. The light source is provided with a control unit 23199 for controlling on / off of the red light source 23190a, the green light source 23190b, and the blue light source 23190c. The light emission of each color is controlled by the control unit 23199, light enters the liquid crystal, an image is synthesized using time division, and color display is performed.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination,
Alternatively, replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 10)
In this embodiment, a method for driving a display device will be described. In particular, a method for driving a liquid crystal display device will be described.

First, overdrive driving will be described with reference to FIG. FIG. 88A shows the change over time of the output luminance with respect to the input voltage of the display element. The time change of the output luminance of the display element with respect to the input voltage 30121 represented by the broken line is the same as the output luminance 30123 similarly represented by the broken line. That is, the voltage for obtaining the target output luminance Low is Vi, but when Vi is input as it is as the input voltage, it takes time corresponding to the response speed of the element to reach the target output luminance Low. End up.

Overdrive drive is a technique for increasing the response speed. Specifically, first, Vo, which is a voltage higher than Vi, is given to the element for a certain period of time to increase the response speed of the output luminance, approach the target output luminance Low, and then return the input voltage to Vi. Is the method. At this time, the input voltage is represented as an input voltage 30122, and the output luminance is represented as an output luminance 30124. In the graph of the output luminance 30124, the time to reach the target luminance Low is shorter than that of the graph of the output luminance 30123.

In FIG. 88A, the case where the output luminance changes positively with respect to the input voltage has been described. However, the present embodiment includes the case where the output luminance changes negatively with respect to the input voltage. It is out.

A circuit for realizing such driving will be described with reference to FIGS. 88B and 88C. First, the case where the input video signal 30131 is an analog value (may be a discrete value) and the output video signal 30132 is an analog value signal will be described with reference to FIG. The overdrive circuit shown in FIG. 88B includes an encoding circuit 30101, a frame memory 30102, a correction circuit 30103, and a DA conversion circuit 30104.

The input video signal 30131 is first input to the encoding circuit 30101 and encoded. That is, the analog signal is converted into a digital signal having an appropriate number of bits. Thereafter, the converted digital signal is input to the frame memory 30102 and the correction circuit 30103, respectively. The video signal of the previous frame held in the frame memory 30102 is also input to the correction circuit 30103 at the same time. Then, the correction circuit 30103 outputs a corrected video signal according to a numerical table prepared in advance from the video signal of the frame and the video signal of the previous frame. At this time, an output switching signal 30133 may be input to the correction circuit 30103 so that the corrected video signal and the video signal of the frame can be switched and output. Next, the corrected video signal or the video signal of the frame is input to the DA conversion circuit 30104. Then, an output video signal 30132 which is an analog signal having a value according to the corrected video signal or the video signal of the frame is output. In this way, overdrive driving can be realized.

Next, a case where the input video signal 30131 takes a digital value and the output video signal 30132 also takes a digital value will be described with reference to FIG. The overdrive circuit shown in FIG. 88C includes a frame memory 30112 and a correction circuit 30113.

The input video signal 30131 is a digital signal and is first input to the frame memory 30112 and the correction circuit 30113, respectively. The video signal of the previous frame held in the frame memory 30112 is also input to the correction circuit 30113 at the same time. Then, the correction circuit 30113 outputs a corrected video signal according to a numerical table prepared in advance from the video signal of the frame and the video signal of the previous frame. At this time, an output switching signal 30133 may be input to the correction circuit 30113 so that the corrected video signal and the video signal of the frame can be switched and output. In this way, overdrive driving can be realized.

Note that the overdrive circuit in this embodiment includes a case where the input video signal 30131 is an analog signal and the output video signal 30132 is a digital signal. At this time, the DA converter circuit 30104 may be omitted from the circuit shown in FIG. The overdrive circuit in this embodiment includes a case where the input video signal 30131 is a digital signal and the output video signal 30132 is an analog signal. At this time, the encoding circuit 30101 may be omitted from the circuit shown in FIG.

Next, driving for manipulating the potential of the common line will be described with reference to FIG. FIG. 89A illustrates a plurality of pixels when one common line is arranged for one scanning line in a display device using a display element having a capacitive property such as a liquid crystal element. It is a figure showing a circuit. The pixel circuit illustrated in FIG. 89A includes a transistor 30201, an auxiliary capacitor 30202, a display element 30203, a video signal line 30204, a scanning line 30205, and a common line 30206.

The gate electrode of the transistor 30201 is electrically connected to the scan line 30205, one of the source electrode and the drain electrode of the transistor 30201 is electrically connected to the video signal line 30204, and the other of the source electrode and the drain electrode of the transistor 30201 Are electrically connected to one electrode of the auxiliary capacitor 30202 and one electrode of the display element 30203.
The other electrode of the auxiliary capacitor 30202 is electrically connected to the common line 30206.

First, since the transistor 30201 is turned on in the pixel selected by the scanning line 30205, a voltage corresponding to the video signal is applied to the display element 30203 and the auxiliary capacitor 30202 through the video signal line 30204, respectively. At this time, when the video signal is to display the lowest gradation for all the pixels connected to the common line 30206, or the highest gradation for all the pixels connected to the common line 30206. Is displayed, it is not necessary to write a video signal to each pixel via the video signal line 30204. Instead of writing a video signal through the video signal line 30204, the voltage applied to the display element 30203 can be changed by moving the potential of the common line 30206.

Next, FIG. 89B shows a display device using a display element having a capacitive property such as a liquid crystal element when two common lines are arranged for one scanning line. It is a figure showing a plurality of pixel circuits. The pixel circuit illustrated in FIG. 89B includes a transistor 30211, an auxiliary capacitor 30212, a display element 30213, a video signal line 30214, a scanning line 30215, a first common line 30216, and a second common line 30217. .

The gate electrode of the transistor 30211 is electrically connected to the scan line 30215, one of the source electrode and the drain electrode of the transistor 30211 is electrically connected to the video signal line 30214, and the other of the source electrode and the drain electrode of the transistor 30211 Is electrically connected to one electrode of the auxiliary capacitor 30212 and one electrode of the display element 30213.
In addition, the other electrode of the auxiliary capacitor 30212 is electrically connected to the first common line 30216.
In the pixel adjacent to the pixel, the other electrode of the auxiliary capacitor 30212 is electrically connected to the second common line 30217.

The pixel circuit illustrated in FIG. 89B has few pixels electrically connected to one common line; therefore, instead of writing a video signal through the video signal line 30214, the first common line 30216 is used. Alternatively, the frequency at which the voltage applied to the display element 30213 can be changed by moving the potential of the second common line 30217 is significantly increased. Further, source inversion driving or dot inversion driving is possible. By source inversion driving or dot inversion driving, flicker can be suppressed while improving the reliability of the element.

Next, the scanning backlight will be described with reference to FIG. FIG. 90A is a diagram showing a scanning backlight in which cold cathode fluorescent lamps are juxtaposed. The scanning backlight shown in FIG. 90A includes a diffusion plate 30301 and N cold cathode fluorescent lamps 30302-1 to 30302-N. N cold cathode tubes 30302-1 to 30302 -N are juxtaposed behind the diffuser plate 30301, so that the N cold cathode tubes 30302-1 to 30302 -N scan with varying luminance. Can do.

A change in luminance of each cold cathode tube during scanning will be described with reference to FIG. First, the luminance of the cold cathode fluorescent lamp 30302-1 is changed for a certain time. After that, the luminance of the cold cathode tube 30302-2 arranged next to the cold cathode tube 30302-1 is changed for the same time. In this way, the luminance is changed in order from the cold cathode fluorescent lamps 30302-1 to 30302-N. In FIG. 90C, the luminance to be changed for a certain time is smaller than the original luminance, but may be larger than the original luminance. Further, although the cold cathode fluorescent lamps 30302-1 to 30302-N are scanned, the cold cathode fluorescent lamps 30302-N to 30302-1 may be scanned in the reverse direction.

By driving as shown in FIG. 90, the average luminance of the backlight can be reduced. Therefore, the power consumption of the backlight, which accounts for most of the power consumption of the liquid crystal display device, can be reduced.

An LED may be used as the light source of the scanning backlight. The scanning backlight in that case is as shown in FIG. The scanning backlight shown in FIG. 90B includes a diffusion plate 30311 and light sources 30312-1 to 30312 -N in which LEDs are juxtaposed. When an LED is used as the light source of the scanning backlight, there is an advantage that the backlight can be made thin and light. Further, there is an advantage that the color reproduction range can be expanded. Furthermore, since the LEDs juxtaposed in each of the light sources 30312-1 to 30312 -N in which the LEDs are juxtaposed can also be scanned in the same manner, a point scanning backlight can also be obtained. If the point scanning type is adopted, the image quality of the moving image can be further improved.

Note that even when an LED is used as the light source of the backlight, it can be driven with the luminance changed as shown in FIG.

Next, high frequency driving will be described with reference to FIG. 91A is a diagram when one image and one intermediate image are displayed in one frame period 30400. FIG. 30401 is an image of the frame, 30402 is an intermediate image of the frame, 30403 is an image of the next frame, and 30404 is an intermediate image of the next frame.

Note that the intermediate image 30402 of the frame may be an image created based on the video signals of the frame and the next frame. Further, the intermediate image 30402 of the frame may be an image created from the image 30401 of the frame. Further, the intermediate image 30402 of the frame may be a black image. By doing so, the image quality of the moving image of the hold type display device can be improved. In the case where one image and one intermediate image are displayed in one frame period 30400, there is an advantage that consistency with the frame rate of the video signal can be easily obtained and the image processing circuit is not complicated.

FIG. 91B is a diagram when one image and two intermediate images are displayed in a period in which two one-frame periods 30400 are continuous (two-frame periods). Reference numeral 30411 denotes an image of the frame, 30412 denotes an intermediate image of the frame, 30413 denotes an intermediate image of the next frame, and 30414 denotes an image of the next frame.

Note that the intermediate image 30412 of the frame and the intermediate image 30413 of the next frame may be images created based on the video signals of the frame, the next frame, and the next frame. Further, the intermediate image 30412 of the frame and the intermediate image 30413 of the next frame may be black images. When one image and two intermediate images are displayed in two frame periods, there is an advantage that the image quality of the moving image can be effectively improved without significantly increasing the operating frequency of the peripheral drive circuit.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination, or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 11)
In this embodiment, a pixel structure of a display device will be described. In particular, a pixel structure of a display device using an organic EL element will be described.

FIG. 92A shows a layout example of an element of a pixel having two TFTs in one pixel. FIG. 92B shows a cross-sectional view of a portion indicated by X-X ′ in FIG.

  As shown in FIG. 92A, the pixel in this embodiment includes a first TFT 60105, a first wiring 60106, a second wiring 60107, a second TFT 60108, a third wiring 60111, a counter electrode 60112, A capacitor 60113, a pixel electrode 60115, a partition wall 60116, an organic conductor film 60117, an organic thin film 60118, and a substrate 60119 may be included. Note that the first TFT 60105 is a switching TFT, the first wiring 60106 is a gate signal line, the second wiring 60107 is a source signal line, the second TFT 60108 is a driving TFT, and the third wiring 60111 is Each is preferably used as a current supply line.

  As shown in FIG. 92A, the gate electrode of the first TFT 60105 is electrically connected to the first wiring 60106, and one of the source electrode and the drain electrode of the first TFT 60105 is connected to the second wiring 60107. The other of the source electrode and the drain electrode of the first TFT 60105 is preferably electrically connected to the gate electrode of the second TFT 60108 and one electrode of the capacitor 60113. Note that the gate electrode of the first TFT 60105 may include a plurality of gate electrodes as illustrated in FIG. Thus, leakage current in the off state of the first TFT 60105 can be reduced.

One of a source electrode and a drain electrode of the second TFT 60108 is electrically connected to the third wiring 60111, and the other of the source electrode and the drain electrode of the second TFT 60108 is electrically connected to the pixel electrode 60115. It is preferred that Thus, the current flowing through the pixel electrode 60115 can be controlled by the second TFT 60108.

An organic conductor film 60117 may be provided over the pixel electrode 60115, and an organic thin film (organic compound layer) 60118 may be further provided. A counter electrode 60112 may be provided over the organic thin film (organic compound layer) 60118. Note that the counter electrode 60112 may be formed in a solid form so as to be commonly connected to all the pixels, or may be formed in a pattern using a shadow mask or the like.

  Light emitted from the organic thin film (organic compound layer) 60118 is transmitted through either the pixel electrode 60115 or the counter electrode 60112. At this time, in FIG. 92B, a case where light is emitted to the pixel electrode side, that is, a side where a TFT or the like is formed is referred to as bottom emission, and a case where light is emitted to the counter electrode side is referred to as top emission.

  In the case of bottom emission, the pixel electrode 60115 is preferably formed using a transparent conductive film. On the other hand, in the case of top emission, the counter electrode 60112 is preferably formed using a transparent conductive film.

  In a light emitting device for color display, EL elements having emission colors of R, G, and B may be separately applied, or a monochrome EL element is applied in a solid form, and R, G, and B are applied by a color filter. B light emission may be obtained.

Note that the configuration illustrated in FIG. 92 is merely an example, and various configurations other than the configuration illustrated in FIG. 92 can be taken with respect to the pixel layout, the cross-sectional configuration, the stacking order of the electrodes of the EL element, and the like. For the light emitting layer, various elements such as a crystalline element such as an LED and an element composed of an inorganic thin film can be used in addition to the element composed of the illustrated organic thin film.

Next, a layout example of a pixel element having three TFTs in one pixel will be described with reference to FIG. FIG. 93B is a cross-sectional view of a portion indicated by X-X ′ in FIG.

  93A, the pixel in this embodiment includes a substrate 60200, a first wiring 60201, a second wiring 60202, a third wiring 60203, a fourth wiring 60204, a first TFT 60205, The pixel may include a second TFT 60206, a third TFT 60207, a pixel electrode 60208, a partition wall 60211, an organic conductor film 60212, an organic thin film 60213, and a counter electrode 60214. Note that the first wiring 60201 is a source signal line, the second wiring 60202 is a writing gate signal line, the third wiring 60203 is an erasing gate signal line, and the fourth wiring 60204 is a current supply line. The first TFT 60205 is preferably used as a switching TFT, the second TFT 60206 is used as an erasing TFT, and the third TFT 60207 is preferably used as a driving TFT.

  93A, the gate electrode of the first TFT 60205 is electrically connected to the second wiring 60202, and one of the source electrode and the drain electrode of the first TFT 60205 is the first wiring 60201. It is preferable that the other of the source electrode and the drain electrode of the first TFT 60205 is electrically connected to the gate electrode of the third TFT 60207. Note that the gate electrode of the first TFT 60205 may include a plurality of gate electrodes as illustrated in FIG. Thus, leakage current in the off state of the first TFT 60205 can be reduced.

  In addition, the gate electrode of the second TFT 60206 is electrically connected to the third wiring 60203, and one of the source electrode and the drain electrode of the second TFT 60206 is electrically connected to the fourth wiring 60204, and The other of the source electrode and the drain electrode of the second TFT 60206 is preferably electrically connected to the gate electrode of the third TFT 60207. Note that the gate electrode of the second TFT 60206 may include a plurality of gate electrodes as illustrated in FIG. Thus, leakage current in the off state of the second TFT 60206 can be reduced.

One of the source electrode and the drain electrode of the third TFT 60207 is electrically connected to the fourth wiring 60204, and the other of the source electrode and the drain electrode of the third TFT 60207 is electrically connected to the pixel electrode 60208. It is preferred that Thus, the current flowing through the pixel electrode 60208 can be controlled by the third TFT 60207.

An organic conductor film 60212 may be provided over the pixel electrode 60208, and an organic thin film (organic compound layer) 60213 may be further provided. A counter electrode 60214 may be provided over the organic thin film (organic compound layer) 60213. Note that the counter electrode 60214 may be formed in a solid form so as to be commonly connected to all pixels, or may be formed in a pattern using a shadow mask or the like.

  Light emitted from the organic thin film (organic compound layer) 60213 is emitted through either the pixel electrode 60208 or the counter electrode 60214. In this case, in FIG. 93B, a case where light is emitted to the pixel electrode side, that is, a side where a TFT or the like is formed is referred to as bottom emission, and a case where light is emitted to the counter electrode side is referred to as top emission.

  In the case of bottom emission, the pixel electrode 60208 is preferably formed using a transparent conductive film. Conversely, in the case of top emission, the counter electrode 60214 is preferably formed using a transparent conductive film.

  In a light emitting device for color display, EL elements having emission colors of R, G, and B may be separately applied, or a monochrome EL element is applied in a solid form, and R, G, and B are applied by a color filter. B light emission may be obtained.

  Note that the configuration illustrated in FIG. 93 is merely an example, and various configurations other than the configuration illustrated in FIG. 93 can be employed with respect to the pixel layout, the cross-sectional configuration, the stacking order of the electrodes of the EL element, and the like. For the light emitting layer, various elements such as a crystalline element such as an LED and an element composed of an inorganic thin film can be used in addition to the element composed of the illustrated organic thin film.

Next, a layout example of a pixel element having four TFTs in one pixel will be described with reference to FIG. Further, FIG. 94B shows a cross-sectional view of a portion indicated by X-X ′ in FIG.

  As shown in FIG. 94A, a pixel in this embodiment includes a substrate 60300, a first wiring 60301, a second wiring 60302, a third wiring 60303, a fourth wiring 60304, a first TFT 60305, The second TFT 60306, the third TFT 60307, the fourth TFT 60308, the pixel electrode 60309, the fifth wiring 60311, the sixth wiring 60312, the partition wall 60321, the organic conductor film 60322, the organic thin film 60323, and the counter electrode 60324 are provided. You may do it. Note that the first wiring 60301 is a source signal line, the second wiring 60302 is a writing gate signal line, the third wiring 60303 is an erasing gate signal line, and the fourth wiring 60304 is a reverse bias. As signal lines, the first TFT 60305 is a switching TFT, the second TFT 60306 is an erasing TFT, the third TFT 60307 is a driving TFT, the fourth TFT 60308 is a reverse bias TFT, and a fifth wiring. 60311 is preferably used as a current supply line, and the sixth wiring 60312 is preferably used as a reverse bias power supply line.

  As shown in FIG. 94A, the gate electrode of the first TFT 60305 is electrically connected to the second wiring 60302, and one of the source electrode and the drain electrode of the first TFT 60305 is the first wiring 60301. The other of the source electrode and the drain electrode of the first TFT 60305 is preferably electrically connected to the gate electrode of the third TFT 60307. Note that the gate electrode of the first TFT 60305 may include a plurality of gate electrodes as illustrated in FIG. Thus, leakage current in the off state of the first TFT 60305 can be reduced.

  The gate electrode of the second TFT 60306 is electrically connected to the third wiring 60303, and one of the source electrode and the drain electrode of the second TFT 60306 is electrically connected to the fifth wiring 60311, and The other of the source electrode and the drain electrode of the second TFT 60306 is preferably electrically connected to the gate electrode of the third TFT 60307. Note that the gate electrode of the second TFT 60306 may include a plurality of gate electrodes as illustrated in FIG. Thus, leakage current in the off state of the second TFT 60306 can be reduced.

In addition, one of the source electrode and the drain electrode of the third TFT 60307 is electrically connected to the fifth wiring 60311, and the other of the source electrode and the drain electrode of the third TFT 60307 is electrically connected to the pixel electrode 60309. It is preferred that Thus, the current flowing through the pixel electrode 60309 can be controlled by the third TFT 60307.

In addition, the gate electrode of the fourth TFT 60308 is electrically connected to the fourth wiring 60304, and one of the source electrode and the drain electrode of the fourth TFT 60308 is electrically connected to the sixth wiring 60312, and The other of the source electrode and the drain electrode of the fourth TFT 60308 is preferably electrically connected to the pixel electrode 60309. By doing so, the potential of the pixel electrode 60309 can be controlled by the fourth TFT 60308, so that a reverse bias can be applied to the organic conductor film 60322 and the organic thin film 60323. By applying a reverse bias to a light-emitting element including the organic conductor film 60322 and the organic thin film 60323, the reliability of the light-emitting element can be greatly improved.

For example, a light-emitting element whose luminance half-life is about 400 hours when driven by a DC voltage (3.65 V) is an AC voltage (forward bias: 3.7 V, reverse bias: 1.7 V, duty 50%, It is known that when driven at an AC frequency of 60 Hz, the luminance half-life is 700 hours or more.

Next, an organic conductor film 60322 may be provided over the pixel electrode 60309, and an organic thin film (organic compound layer) 60323 may be further provided. A counter electrode 60324 may be provided over the organic thin film (organic compound layer) 60323. Note that the counter electrode 60324 may be formed in a solid form so as to be commonly connected to all the pixels, or may be patterned using a shadow mask or the like.

  Light emitted from the organic thin film (organic compound layer) 60323 is emitted through either the pixel electrode 60309 or the counter electrode 60324. In this case, in FIG. 94B, a case where light is emitted to the pixel electrode side, that is, a side where a TFT or the like is formed is referred to as bottom emission, and a case where light is emitted to the counter electrode side is referred to as top emission.

  In the case of bottom emission, the pixel electrode 60309 is preferably formed using a transparent conductive film. Conversely, in the case of top emission, the counter electrode 60324 is preferably formed of a transparent conductive film.

  In a light emitting device for color display, EL elements having emission colors of R, G, and B may be separately applied, or a monochrome EL element is applied in a solid form, and R, G, and B are applied by a color filter. B light emission may be obtained.

  The configuration illustrated in FIG. 94 is merely an example, and various configurations other than the configuration illustrated in FIG. 94 can be taken with respect to the pixel layout, the cross-sectional configuration, the stacking order of the electrodes of the EL element, and the like. For the light emitting layer, various elements such as a crystalline element such as an LED and an element composed of an inorganic thin film can be used in addition to the element composed of the illustrated organic thin film.

  Next, the structure of an EL element applicable to the present invention will be described.

  The EL device applicable to the present invention includes a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light emitting layer made of a light emitting material, an electron transport layer made of an electron transport material, and an electron injection material The electron injection layer is not a layered structure that is clearly distinguished, but a plurality of materials among hole injection material, hole transport material, light emitting material, electron transport material, electron injection material, etc. A structure having a mixed layer (mixed layer) (hereinafter referred to as a mixed junction type EL element) may be used.

  A schematic diagram showing the structure of a mixed junction type EL element is shown in FIG. In FIG. 95, reference numeral 60401 denotes an anode of an EL element. Reference numeral 60402 denotes a cathode of the EL element. A layer sandwiched between the anode 60401 and the cathode 60402 corresponds to an EL layer.

  95A, the EL layer includes a hole transport region 60403 made of a hole transport material and an electron transport region 60404 made of an electron transport material. The hole transport region 60403 is formed by the electron transport region 60404. And a mixed region 60405 including both the hole transporting material and the electron transporting material is provided between the hole transporting region 60403 and the electron transporting region 60404. be able to.

  At this time, the concentration of the hole transport material in the mixed region 60405 decreases and the concentration of the electron transport material in the mixed region 60405 increases in the direction from the anode 60401 to the cathode 60402. good.

  Note that in the above structure, the hole transport region 60403 made of only the hole transport material does not exist, and the concentration ratio of each functional material changes in the mixed region 60405 including both the hole transport material and the electron transport material. It may be configured (having a concentration gradient). Further, there is no hole transport region 60403 made of only the hole transport material and no electron transport region 60404 made of only the electron transport material, and each functional material is contained in the mixed region 60405 including both the hole transport material and the electron transport material. A configuration in which the ratio of the concentration of (having a concentration gradient) may be employed. The concentration ratio may be changed depending on the distance from the anode or the cathode. Further, the change in the concentration ratio may be continuous. The method of setting the concentration gradient can be set freely.

  A region 60406 to which a light emitting material is added is provided in the mixed region 60405. The emission color of the EL element can be controlled by the light emitting material. Further, carriers can be trapped by the light emitting material. As the light emitting material, various fluorescent dyes can be used in addition to a metal complex including a quinoline skeleton, a metal complex including a benzoxador skeleton, a metal complex including a benzothiazol skeleton, and the like. By adding these light emitting materials, the light emission color of the EL element can be controlled.

As the anode 60401, an electrode material having a high work function is preferably used in order to inject holes efficiently. For example, a transparent electrode such as tin-doped indium oxide (ITO), zinc-doped indium oxide (IZO), ZnO, SnO ₂ , or In ₂ O ₃ can be used. Further, the anode 60401 may be an opaque metal material if it is not necessary to have translucency.

  As the hole transport material, an aromatic amine compound or the like can be used.

As the electron transporting material, a quinoline derivative, a metal complex having 8-quinolinol or a derivative thereof as a ligand (particularly tris (8-quinolinolite) aluminum (Alq ₃ )) or the like can be used.

  As the cathode 60402, an electrode material having a low work function is preferably used in order to inject electrons efficiently. A single metal such as aluminum, indium, magnesium, silver, calcium, barium, or lithium can be used. Moreover, the alloy of these metals may be sufficient and the alloy of these metals and another metal may be sufficient.

FIG. 95B is a schematic diagram of an EL element having a structure different from that in FIG. Note that FIG.
The same parts as those shown in FIG.

In FIG. 95B, there is no region to which the light-emitting material is added. However, as a material to be added to the electron transporting region 60404, a material having both electron transporting property and light emitting property (electron transporting light emitting material), for example, tris (8-quinolinolite) aluminum (Alq ₃ ) is used, and light emission is performed. It can be carried out.

  Alternatively, as a material added to the hole-transport region 60403, a material having both hole-transport property and light-emitting property (hole-transport light-emitting material) may be used.

  FIG. 95C is a schematic diagram of an EL element having a structure different from those in FIGS. 95A and 95B. Note that the same portions as those in FIGS. 95A and 95B are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 95C, a hole blocking material having a large energy difference between the highest occupied molecular orbital and the lowest occupied molecular orbital compared to the hole transporting material has a region 60407 added in the mixed region 60405. . The region 60407 to which the hole blocking material is added is arranged closer to the cathode 60402 than the region 60406 to which the light emitting material is added in the mixed region 60405, so that the carrier recombination rate can be increased and the light emission efficiency can be increased. it can. The above-described structure in which the region 60407 to which a hole blocking material is added is provided is particularly effective in an EL element using light emission (phosphorescence) by triple photoexcitons.

  FIG. 95D is a schematic diagram of an EL element having a structure different from those in FIGS. 95A, 95B, and 95C. Note that the same portions as those in FIGS. 95A, 95B, and 95C are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 95D, an electron blocking material having a larger energy difference between the highest occupied molecular orbital and the lowest occupied molecular orbital than the electron transporting material has a region 60408 added in the mixed region 60405. By disposing the region 60408 to which the electron blocking material is added closer to the anode 60401 than the region 60406 to which the light emitting material is added in the mixed region 60405, the carrier recombination rate can be increased and the light emission efficiency can be increased. . The structure provided with the region 60408 to which the electron blocking material is added is particularly effective in an EL element using light emission (phosphorescence) by triple photoexcitons.

  FIG. 95E is a schematic diagram illustrating a structure of a mixed-junction EL element different from those in FIGS. 95A, 95B, 95C, and 95D. FIG. 95E illustrates an example of a structure including a region 60409 to which a metal material is added in the portion of the EL layer in contact with the electrode of the EL element. In FIG. 95E, the same portions as those in FIGS. 95A to 95D are denoted by the same reference numerals and description thereof is omitted. In the structure shown in FIG. 95E, for example, MgAg (Mg—Ag alloy) is used as the cathode 60401, and an Al (aluminum) alloy is added to a region in contact with the cathode 60402 in the region 60404 to which the electron transport material is added. A configuration including the region 60409 may be employed. With the above structure, oxidation of the cathode can be prevented and the efficiency of electron injection from the cathode can be increased. Thus, the life of the mixed junction type EL element can be extended. Further, the drive voltage can be lowered.

  As a method of manufacturing the mixed junction type EL element, a co-evaporation method or the like can be used.

In the mixed junction EL element as shown in FIGS. 95A to 95E, there is no clear layer interface, and charge accumulation can be reduced. In this way, the lifetime can be extended. Further, the drive voltage can be lowered.

  Note that the structures shown in FIGS. 95A to 95E can be implemented in any combination.

  Note that the structure of the mixed junction EL element is not limited thereto. A known configuration can be used freely.

Note that the organic material constituting the EL layer of the EL element may be a low molecular material or a high molecular material. Moreover, you may use both of these materials. When a low molecular material is used as the organic compound material, the film can be formed by an evaporation method. On the other hand, in the case where a polymer material is used for the EL layer, the polymer material can be dissolved in a solvent and formed into a film by a spin coating method or an inkjet method.

  The EL layer may be made of a medium molecular material. In the present specification, the medium molecular organic light-emitting material refers to an organic light-emitting material having no sublimation property and having a degree of polymerization of about 20 or less. In the case where a medium molecular material is used for the EL layer, it can be formed by an inkjet method or the like.

  Note that a low molecular material, a high molecular material, and a medium molecular material may be used in combination.

  The EL element may be either one that uses light emission (fluorescence) from singlet excitons or one that uses light emission (phosphorescence) from triplet excitons.

  Next, a vapor deposition apparatus for manufacturing a display device applicable to the present invention will be described with reference to the drawings.

  A display device applicable to the present invention may be manufactured by forming an EL layer. The EL layer is formed including at least part of a material that exhibits electroluminescence. The EL layer may be composed of a plurality of layers having different functions. In that case, the EL layer may be configured by combining layers having different functions called a hole injecting and transporting layer, a light emitting layer, and an electron injecting and transporting layer.

  FIG. 96 shows a structure of a vapor deposition apparatus for forming an EL layer on an element substrate over which a transistor is formed. In this vapor deposition apparatus, a plurality of processing chambers are connected to transfer chambers 60560 and 60561. The processing chamber includes a load chamber 60562 for supplying a substrate, an unload chamber 60563 for recovering the substrate, a heat processing chamber 60568, a plasma processing chamber 60572, a film formation processing chamber 60569 to 60575 for depositing an EL material, and an EL element. One electrode includes a deposition treatment chamber 60576 in which aluminum or a conductive film containing aluminum as a main component is formed. In addition, gate valves 60577a to 60577m are provided between the transfer chamber and each processing chamber, and the pressure in each processing chamber can be independently controlled to prevent cross-contamination between the processing chambers.

  The substrate introduced into the transfer chamber 60560 from the load chamber 60562 is carried into a predetermined processing chamber by an arm-type transfer means 60566 that is rotatably provided. Further, the substrate is transported from one processing chamber to another processing chamber by the transporting means 60566. The transfer chamber 60560 and the transfer chamber 60561 are connected to each other through a film formation treatment chamber 60570, and the substrate is transferred by the transfer unit 60566 and the transfer unit 60567.

Each processing chamber connected to the transfer chamber 60560 and the transfer chamber 60561 is kept in a reduced pressure state. Therefore, in this vapor deposition apparatus, the substrate is continuously subjected to film formation of the EL layer without being exposed to the atmosphere. Since the display panel after the EL layer deposition process may be deteriorated by water vapor or the like, in this vapor deposition apparatus, a sealing process for performing a sealing process before exposure to the atmosphere in order to maintain the quality. A chamber 60565 is connected to the transfer chamber 60561. Since the sealing treatment chamber 60565 is placed under atmospheric pressure or a reduced pressure close thereto, an intermediate treatment chamber 60564 is also provided between the transfer chamber 60561 and the sealing treatment chamber 60565. The intermediate processing chamber 60564 is provided for transferring the substrate and buffering the pressure between the chambers.

  The load chamber, the unload chamber, the transfer chamber, and the film forming chamber are provided with exhaust means for maintaining the chamber at a reduced pressure. As the exhaust means, various vacuum pumps such as a dry pump, a turbo molecular pump, and a diffusion pump can be used.

  In the vapor deposition apparatus in FIG. 96, the number of treatment chambers connected to the transfer chamber 60560 and the transfer chamber 60561 and the structure thereof can be combined as appropriate depending on the stacked structure of the EL elements. An example of the combination is shown below.

  In the heat treatment chamber 60568, degassing treatment is performed by first heating the substrate on which the lower electrode, the insulating partition wall, and the like are formed. The plasma treatment chamber 60572 performs rare gas or oxygen plasma treatment on the surface of the base electrode. This plasma treatment is performed to clean the surface, stabilize the surface state, and stabilize the physical or chemical state (eg, work function) of the surface.

  The film formation treatment chamber 60569 is a treatment chamber for forming an electrode buffer layer in contact with one electrode of the EL element. The electrode buffer layer has carrier injection properties (hole injection or electron injection), and is a layer that suppresses the occurrence of short circuits and dark spot defects in EL elements. Typically, the electrode buffer layer is an organic / inorganic mixed material having a resistivity of 5 × 10 4 to 1 × 10 6 Ωcm and a thickness of 30 to 300 nm. A film formation chamber 60571 is a treatment chamber for forming a hole transport layer.

  The structure of the light emitting layer in the EL element differs depending on whether the light emission is monochromatic or white. In the vapor deposition apparatus, it is preferable to arrange the film forming treatment chamber accordingly. For example, when three types of EL elements having different emission colors are formed on the display panel, it is necessary to form a light emitting layer corresponding to each emission color. In this case, the film formation chamber 60570 is used for forming the first light-emitting layer, the film formation chamber 60573 is used for forming the second light-emitting layer, and the film formation chamber 60574 is used for forming the third light-emitting layer. It can be used for membranes. By separating the film formation chamber for each light emitting layer, mutual contamination by different light emitting materials can be prevented, and the throughput of the film formation process can be improved.

  Alternatively, three types of EL materials having different emission colors may be sequentially deposited in the film formation chamber 60570, the film formation chamber 60573, and the film formation chamber 60574. In this case, a shadow mask is used, and vapor deposition is performed by shifting the mask in accordance with the region to be vapor deposited.

  In the case of forming an EL element that emits white light, light emitting layers having different light emission colors are stacked vertically. Also in that case, the element substrate can be sequentially moved through the film formation chamber to form a film for each light emitting layer. In addition, different light emitting layers can be successively formed in the same film formation chamber.

  In the deposition treatment chamber 60576, an electrode is deposited over the EL layer. The electrode can be formed by electron beam evaporation or sputtering, but resistance heating evaporation is preferably used.

After the formation of the electrodes, the element substrate passes through the intermediate processing chamber 60564 and the sealing processing chamber 6056.
5 is carried in. The sealing treatment chamber 60565 is filled with an inert gas such as helium, argon, neon, or nitrogen, and a sealing plate is attached to the element substrate on the side where the EL layer is formed in the atmosphere. Stop. In a sealed state, an inert gas may be filled between the element substrate and the sealing plate, or a resin material may be filled. The sealing processing chamber 60565 includes a dispenser for drawing a sealing material, a mechanical element such as a fixed stage and an arm for fixing a sealing plate facing the element substrate, a dispenser for filling a resin material, a spin coater, and the like. It has been.

  FIG. 97 shows the internal configuration of the film forming chamber. The film formation chamber is kept under reduced pressure. In FIG. 97, the inside between the top plate 60691 and the bottom plate 60692 is a room, and the room is kept under a reduced pressure.

  One or a plurality of evaporation sources are provided in the processing chamber. This is because it is preferable to provide a plurality of evaporation sources when a plurality of layers having different compositions are formed or when different materials are co-evaporated. In FIG. 97, the evaporation sources 60681a, 60681b, and 60681c are attached to the evaporation source holder 60680. The evaporation source holder 60680 is held by an articulated arm 60683. The articulated arm 60683 can move the position of the evaporation source holder 60680 freely within the movable range by expansion and contraction of the joint. Further, a distance sensor 60682 may be provided in the evaporation source holder 60680, and the distance between the evaporation sources 60681a to 60681c and the substrate 60689 may be monitored to control the optimum distance during vapor deposition. In that case, it is good also as an articulated arm which displaces to an articulated arm also in the up-down direction (Z direction).

  The substrate stage 60686 and the substrate chuck 60687 are paired to fix the substrate 60689. The substrate stage 60686 may be configured to heat the substrate 60689 by incorporating a heater. The substrate 60689 is fixed to the substrate stage 60686 and carried in / out by the forcible relaxation of the substrate chuck 60687. In vapor deposition, a shadow mask 60690 having an opening corresponding to a vapor deposition pattern can be used as necessary. In that case, the shadow mask 60690 is arranged between the substrate 60689 and the evaporation sources 60681a to 60681c. The shadow mask 60690 is fixed to the substrate 60689 with a mask chuck 60688 in close contact with or at a constant interval. When the shadow mask 60690 needs to be aligned, the camera is arranged in the processing chamber, and the mask chuck 60688 is provided with positioning means that finely moves in the XY-θ direction, thereby aligning the shadow mask 60690.

  The evaporation source 60681 is provided with a deposition material supply means for continuously supplying the deposition material to the evaporation source. The vapor deposition material supply means includes vapor deposition material supply sources 60685a, 60685b, and 60685c arranged at positions distant from the evaporation source 60681, and a material supply pipe 60684 connecting the two. Typically, the material supply sources 60685a, 60685b, and 60685c are provided corresponding to the evaporation source 60681. In the case of FIG. 97, the material supply source 60685a corresponds to the 606 evaporation source 81a. The same applies to the material supply source 60685b and the evaporation source 60681b, and the material supply source 60685c and the evaporation source 60681c.

  As an evaporation material supply method, an air current conveyance method, an aerosol method, or the like can be applied. In the air current conveyance method, fine powder of vapor deposition material is carried on an air current and is conveyed to the evaporation source 60681 using an inert gas or the like. The aerosol method is vapor deposition performed by conveying a raw material solution in which a vapor deposition material is dissolved or dispersed in a solvent, aerosolizing it with a sprayer, and vaporizing the solvent in the aerosol. In any case, the evaporation source 60681 is provided with a heating unit, and the conveyed vapor deposition material is evaporated to form a film on the substrate 60689. In the case of FIG. 97, the material supply pipe 60684 is formed of a thin tube that can be flexibly bent and has a rigidity that does not deform even under reduced pressure.

  In the case of applying an air current conveyance method or an aerosol method, the film formation may be performed under a reduced pressure of 133 Pa to 13300 Pa in the film formation treatment chamber at atmospheric pressure or lower. The film formation chamber can be filled with an inert gas such as helium, argon, neon, krypton, xenon, or nitrogen, or the pressure can be adjusted while supplying the gas (while exhausting the gas). Further, in the film formation treatment chamber in which an oxide film is formed, a gas such as oxygen or nitrous oxide may be introduced to form an oxidizing atmosphere. Alternatively, a reducing atmosphere may be formed by introducing a gas such as hydrogen into a film formation chamber in which an organic material is deposited.

  As another vapor deposition material supply method, a screw may be provided in the material supply pipe 60684 to continuously extrude the vapor deposition material toward the evaporation source.

  According to this vapor deposition apparatus, even a large-screen display panel can be continuously formed with good uniformity. Further, it is not necessary to replenish the vapor deposition material each time the vapor deposition material runs out of the evaporation source, so that the throughput can be improved.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination, or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 12)
In this embodiment, a pixel circuit and a driving method of a display device will be described.

First, digital time gray scale driving applicable to the present invention will be described. First, a driving method in the case where the signal writing period (address period) to the pixel and the light emission period (sustain period) are separated will be described with reference to FIG. Here, as an example, a case of 4-bit digital time gradation will be described.

Note that a period for completely displaying an image for one display area is referred to as one frame period. One frame period has a plurality of subframe periods, and one subframe period has an address period and a sustain period. The address periods Ta1 to Ta4 indicate the time required for signal writing to pixels for all rows, and the periods Tb1 to Tb4 indicate the time required for signal writing to pixels for one row (or for one pixel). Further, the sustain periods Ts1 to Ts4 indicate the time during which the lighting or non-lighting state is maintained according to the video signal written to the pixels, and the ratio of the lengths is Ts1: Ts2: Ts3: Ts4 = 23: 22: 21: 20 = 8: 4: 2: 1. The gradation is expressed by the sustain period during which light is emitted.

The operation will be described. First, in the address period Ta1, pixel selection signals are input to the scanning lines in order from the first row, and pixels are selected. When a pixel is selected, a video signal is input from the signal line to the pixel. When a video signal is written to the pixel, the pixel holds the signal until the signal is input again. Lighting and non-lighting of each pixel in the sustain period Ts1 are controlled by the written video signal. Similarly, video signals are input to the pixels in the address periods Ta2, Ta3, and Ta4, and lighting and non-lighting of each pixel in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signals. In each subframe period, the pixel is not lit during the address period, and after the address period ends, the sustain period starts, and the pixel in which a signal for lighting is written is lit.

Here, the i-th pixel row will be described with reference to FIG. First, in the address period Ta1, pixel selection signals are sequentially input to the scanning lines from the first row, and the i-th row pixel is selected in the address period Ta1 in the period Tb1 (i). Then, when the i-th row pixel is selected, a video signal is input from the signal line to the i-th row pixel. When a video signal is written to the i-th row pixel, the i-th row pixel holds the signal until the signal is input again. Lighting and non-lighting of the i-th row pixel in the sustain period Ts1 are controlled by the written video signal. Similarly, a video signal is input to the i-th row pixel in the address periods Ta2, Ta3, and Ta4, and lighting and non-lighting of the i-th row pixel in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signal. In each subframe period, the pixel is not lit during the address period, and after the address period ends, the sustain period starts, and the pixel in which a signal for lighting is written is lit.

Although the case where a 4-bit gradation is expressed has been described here, the number of bits and the number of gradations are not limited thereto. Moreover, the order of lighting does not need to be Ts1, Ts2, Ts3, and Ts4, and may be random or may be divided into a plurality of portions to emit light. The lighting times of Ts1, Ts2, Ts3, and Ts4 do not have to be a power of 2, but may be the same lighting time, or may be slightly shifted from the power of 2.

Next, a driving method in the case where the signal writing period (address period) to the pixel and the light emission period (sustain period) are not separated will be described. That is, the pixel in the row where the video signal writing operation is completed holds the signal until the signal is written (or erased) to the pixel next time. A period from writing operation to next signal writing to this pixel is referred to as data holding time. During this data retention time, the pixel is turned on or off according to the video signal written to the pixel. The same operation is performed up to the last line, and the address period ends. Then, the signal writing operation in the next subframe period is started in order from the row where the data holding time has ended.

As described above, when the signal writing operation is completed and the data holding time is reached, in the driving method in which the pixel is turned on or off in accordance with the video signal written to the pixel immediately, the data holding time is attempted to be shorter than the address period. However, since signals cannot be input to two rows at the same time, it is necessary to prevent the address periods from overlapping, and therefore the data holding time cannot be shortened. As a result, it becomes difficult to perform high gradation display.

Therefore, a data holding time shorter than the address period is set by providing an erasing period. A driving method in the case where an erasing period is provided and a data holding time shorter than the address period is set will be described with reference to FIG.

First, in the address period Ta1, pixel scanning signals are input to the scanning lines in order from the first row,
A pixel is selected. When a pixel is selected, a video signal is input from the signal line to the pixel. When a video signal is written to the pixel, the pixel holds the signal until the signal is input again. Lighting and non-lighting of each pixel in the sustain period Ts1 are controlled by the written video signal. In the row where the video signal writing operation is completed, the pixels are turned on or off in accordance with the video signal written immediately. The same operation is performed up to the last row, and the address period Ta1 ends. Then, the signal writing operation in the next subframe period is started in order from the row where the data holding time has ended. Similarly, video signals are input to the pixels in the address periods Ta2, Ta3, and Ta4, and lighting and non-lighting of each pixel in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signals. The end of the sustain period TS4 is set by the start of the erase operation. This is because if the signal written to the pixel is erased at the erase time Te of each row, the signal is forced regardless of the video signal written to the pixel in the address period until the signal is written to the next pixel. This is because the light is not turned on. That is, the data holding time ends from the pixel in the row where the erasing time Te has started.

Here, with reference to FIG. 99B, description will be given focusing on the i-th pixel row. In the i-th pixel row, in the address period Ta1, pixel scanning signals are sequentially input to the scanning lines from the first row, and pixels are selected. Then, when the i-th row pixel is selected in the period Tb1 (i), a video signal is input to the i-th row pixel. When a video signal is written to the i-th row pixel, the i-th row pixel holds the signal until the signal is input again. By the written video signal, lighting and non-lighting of the pixel in the i-th row in the sustain period Ts1 (i) are controlled. That is, when the video signal writing operation is completed in the i-th row, the pixel in the i-th row is turned on or off in accordance with the written video signal. Similarly, a video signal is input to the i-th row pixel in the address periods Ta2, Ta3, and Ta4, and lighting and non-lighting of the i-th row pixel in the sustain periods Ts2, Ts3, and Ts4 are controlled by the video signal. The end of the sustain period Ts4 (i) is set by starting the erase operation. This is because the light is forcibly turned off regardless of the video signal written to the pixel in the i-th row during the erasing time Ts (i) in the i-th row. That is, when the erasing time Te (i) starts, the data holding time of the pixel in the i-th row ends.

Therefore, a display device with a high gradation and a high duty ratio (ratio of lighting period in one frame period) shorter than the address period can be provided without separating the address period and the sustain period. In addition, since the instantaneous luminance can be reduced, the reliability of the display element can be improved.

Although the case where a 4-bit gradation is expressed has been described here, the number of bits and the number of gradations are not limited thereto. Further, the lighting order need not be Ts1, Ts2, Ts3, and Ts4, and may be random or may be divided into a plurality of light emission. The lighting times of Ts1, Ts2, Ts3, and Ts4 do not have to be a power of 2, but may be the same lighting time, or may be slightly shifted from the power of 2.

Here, FIGS. 100A, 100B, 100C, 100D, and 100E are used for the pixel structure capable of digital time gray scale driving described in FIGS. 98A and 99A. The description will be given with reference. Note that as the display element illustrated in FIGS. 100A, 100B, 100C, 100D, and 100E, an EL element (an organic EL element, an inorganic EL element, or an EL element including an organic substance and an inorganic substance), A display medium whose contrast is changed by an electromagnetic action, such as an electron emitting element, a liquid crystal element, electronic ink, a grating light valve (GLV), a digital micromirror device (DMD), or a carbon nanotube, can be applied. In addition, as the display element, a self-luminous element such as an EL element is suitable for the pixels illustrated in FIGS. 100A, 100B, 100C, 100D, and 100E. Note that FIGS. 100A, 100B, 100C, 100D, and 100E illustrate only one pixel, but the pixel portion of the display device is arranged in a matrix in the row direction and the column direction. A plurality of pixels are arranged.

A pixel illustrated in FIG. 100A includes a switching transistor 80301a, a driving transistor 80302a, and a capacitor 80304a. The switching transistor 80301a has a gate terminal connected to the scan line 8031a, a first terminal (source terminal or drain terminal) connected to the signal line 80311a, and a second terminal (source terminal or drain terminal) connected to the driving transistor 80302a. Connected to the gate terminal. The second terminal of the switching transistor 80301a is connected to the power supply line 80313a through the capacitor 80304a. Further, the driving transistor 80302a has a first terminal connected to the power supply line 80313a and a second terminal connected to the first electrode of the display element 80320a. A low power supply potential is set to the second electrode 80321a of the display element 80320a. Note that the low power supply potential is a potential that satisfies the low power supply potential <high power supply potential with reference to the high power supply potential set in the power supply line 80313a. For example, GND, 0V, or the like is set as the low power supply potential. Also good. The potential difference between the high power supply potential and the low power supply potential is applied to the display element 80320a and current is caused to flow through the display element 80320a to cause the display element 80320a to emit light. Each potential is set to be equal to or higher than the forward threshold voltage. Note that the capacitor 80304a can be omitted instead of the gate capacitance of the driving transistor 80302a. With respect to the gate capacitance of the driving transistor 80302a, the capacitance may be formed in a region where the source electrode, the drain region, the LDD region, and the like overlap with the gate electrode, or the channel region and the gate electrode. A capacitance may be formed between the two.

When a pixel is selected by the scan line 8031a, that is, when the switching transistor 80301a is turned on, a video signal is input from the signal line 80311a to the pixel. Then, charge for a voltage corresponding to the video signal is accumulated in the capacitor 80304a, and the capacitor 80304a holds the voltage. This voltage is a voltage between the gate terminal and the first terminal of the driving transistor 80302a, and corresponds to the gate-source voltage Vgs of the driving transistor 80302a.

In general, the operation region of a transistor can be divided into a linear region and a saturation region. The boundary is when (Vgs−Vth) = Vds, where Vds is the drain-source voltage, Vgs is the gate-source voltage, and Vth is the threshold voltage. When (Vgs−Vth)> Vds, it is a linear region, and the current value is determined by the magnitudes of Vds and Vgs. On the other hand, when (Vgs−Vth) <Vds, a saturation region is reached, and ideally, even if Vds changes, the current value hardly changes. That is, the current value is determined only by the magnitude of Vgs.

Here, in the case of the voltage input voltage driving method, a video signal is input to the gate terminal of the driving transistor 80302a so that the driving transistor 80302a is sufficiently turned on or off. . That is, the driving transistor 80302a is operated in a linear region.

Therefore, in the case of a video signal for turning on the driving transistor 80302a, ideally, the power supply potential Vdd set to the power supply line 80313a is set as it is to the first electrode of the display element 80320a.

That is, ideally, the voltage applied to the display element 80320a is made constant, and the luminance obtained from the display element 80320a is made constant. A plurality of subframe periods are provided within one frame period, video signals are written to the pixels for each subframe period, and lighting or non-lighting of the pixels is controlled for each subframe period. The gradation is expressed by the sum of the subframe periods.

Next, the pixel structure in FIG. 100B is described. A pixel illustrated in FIG. 100B includes a switching transistor 80301a, a driving transistor 80302a, a rectifier element 80306a, a capacitor element 80304a, and a display element 80320b. The switching transistor 80301b has a gate terminal connected to the first scan line 8031b, a first terminal (source terminal or drain terminal) connected to the signal line 80311b, and a second terminal (source terminal or drain terminal) for driving. It is connected to the gate terminal of the transistor 80302b. Further, the gate terminal of the driving transistor 80302 is connected to the second scanning line 80313b through the rectifying element 80306a. The second terminal of the switching transistor 80301b is connected to the power supply line 80313b through the capacitor 80304b. Further, the driving transistor 80302b has a first terminal connected to the power supply line 80313b and a second terminal connected to the first electrode of the display element 80320b. A low power supply potential is set to the second electrode 80321b of the display element 80320b. Note that the low power supply potential is a potential that satisfies the low power supply potential <the high power supply potential with reference to the high power supply potential set in the power supply line 80313b. For example, GND, 0 V, or the like is set as the low power supply potential. Also good. The potential difference between the high power supply potential and the low power supply potential is applied to the display element 80320b and current is caused to flow through the display element 80320b to cause the display element 80320b to emit light. Each potential is set to be equal to or higher than the forward threshold voltage. Note that the capacitor 80304b can be omitted instead of the gate capacitor of the driving transistor 80302b. As for the gate capacitance of the driving transistor 80302b, the capacitance may be formed in a region where the source region, the drain region, the LDD region, and the like overlap with the gate electrode, or the channel region and the gate electrode. A capacitance may be formed between the two.

This pixel configuration is obtained by adding a rectifying element 80306a and a second scan line 80313b to the pixel in FIG. Therefore, the switching transistor 80301b, the driving transistor 80302b, the capacitor 80304b, the signal line 80311b, the first scan line 8031b, and the power supply line 80313b are respectively the switching transistor 80301a, the driving transistor 80302a, the capacitor 80304a, and the signal line 80311a. , Which correspond to the scanning line 8031a and the power supply line 80313a, and the writing operation and the light emitting operation are the same, and thus the description thereof is omitted here.

The erase operation will be described. At the time of erasing operation, an H level signal is input to the second scan line 80313b. Then, current flows through the rectifying element 80306a, and the gate potential of the driving transistor 80302b held by the capacitor 80304b can be set to a certain potential. That is, the potential of the gate terminal of the driving transistor 80302b can be set to a certain potential, and the driving transistor 80302b can be forcibly turned off regardless of the video signal written to the pixel.

Note that the L-level signal input to the second scan line 80313b has a potential such that no current flows through the rectifier element 80306a when a video signal that is not lit is written to the pixel. Further, an H-level signal input to the second scan line 80313b is a potential at which the gate terminal can be set to a potential at which the driving transistor 80302b is turned off regardless of the video signal written to the pixel. And

Note that a diode-connected transistor can be used for the rectifying element 80306a. In addition to a diode-connected transistor, a PN junction or PIN junction diode, a Schottky diode, a diode formed of carbon nanotubes, or the like may be used. FIG. 100C illustrates the case where a diode-connected N-channel transistor is used. The first terminal (source terminal or drain terminal) of the diode-connected transistor 80303c is connected to the gate terminal of the driving transistor 80302c. In addition, the second terminal (source terminal or drain terminal) of the diode-connected transistor 80303c is connected to the gate terminal and also connected to the second scanning line 80313c. Then, when the second scanning line 80313c is at the L level, no current flows through the diode-connected transistor 80303c because the gate terminal and the source terminal are connected, but when an H level signal is input to the second scanning line 80313c. Since the second terminal of the diode-connected transistor 80303c serves as the drain terminal, a current flows through the diode-connected transistor 80303c. Therefore, the diode-connected transistor 80303c has a rectifying action.

Note that the switching transistor 80301c, the driving transistor 80302c, the capacitor 80304c, the signal line 80311c, the first scan line 8031c, and the power supply line 80313c are respectively the switching transistor 80301a, the driving transistor 80302a, and the capacitor in FIG. It corresponds to the element 80304a, the signal line 80311a, the scanning line 80312a, and the power supply line 80313a. Further, the second scan line 8031c corresponds to the second scan line 8031d in FIG.

FIG. 100D illustrates the case where a diode-connected P-channel transistor is used. A first terminal (source terminal or drain terminal) of the diode-connected transistor 80303d is connected to the second scanning line 80313d. In addition, the second terminal (source terminal or drain terminal) of the diode-connected transistor 80303d is connected to the gate terminal, and is also connected to the gate terminal of the driving transistor 80302d. Then, when the second scanning line 80313d is at the L level, the diode-connected transistor 80303d is connected to the gate terminal and the source terminal, so that no current flows, but when the H-level signal is input to the second scanning line 80313d. Since the second terminal of the diode-connected transistor 80303d serves as the drain terminal, a current flows through the diode-connected transistor 80303d. Therefore, the diode-connected transistor 80303d has a rectifying action.

Note that the switching transistor 80301d, the driving transistor 80302d, the capacitor 80304d, the signal line 80311d, the first scan line 80312d, and the power supply line 80313d are respectively the switching transistor 80301a, the driving transistor 80302a, and the capacitor in FIG. It corresponds to the element 80304a, the signal line 80311a, the scanning line 80312a, and the power supply line 80313a. The second scanning line 8031d corresponds to the second scanning line 8031d in FIG.

Further, an erasing transistor may be provided in order to erase a signal written to the pixel. A pixel illustrated in FIG. 100E is obtained by adding an erasing transistor 80303e and a second scan line 8031e to the pixel in FIG. Therefore, the switching transistor 80301e, the driving transistor 80302e, the capacitor 80304e, the signal line 80311e, the first scan line 8031e, and the power supply line 80313e are respectively the switching transistor 80301a, the driving transistor 80302a, and the capacitor in FIG. It corresponds to the element 80304a, the signal line 80311a, the scanning line 80312a, and the power supply line 80313a, and the writing operation and the light emitting operation are the same, and thus the description thereof is omitted here.

The erase operation will be described. In the erasing operation, an H level signal is input to the second scan line 8031e. Then, the erasing transistor 80303e is turned on, and the gate terminal and the first terminal of the driving transistor 80302e can be set to the same potential. That is, the gate-source voltage of the driving transistor 80302e can be set to 0V. Note that the H-level potential of the second scan line 8031e is preferably higher than the potential of the power supply line 80313e by the threshold voltage Vth of the erasing transistor 80303e. Thus, the driving transistor 80302e can be forcibly turned off.

Next, an example of a threshold voltage correction pixel circuit and a driving method which can be applied to the present invention will be described with reference to FIG.

A pixel illustrated in FIG. 101A includes a driving transistor 80400, a first switch 80401, a second switch 80402, a third switch 80403, a first capacitor 80404, a second capacitor 80405, and a display element 80420. have. The driving transistor 80400 has a gate terminal connected to the signal line 80411 through the first capacitor 80404 and the first switch 80401 in order, a first terminal connected to the power supply line 80412, and a second terminal connected to the third terminal. The switch 80403 is connected to the first electrode of the display element 80420. Further, the gate terminal of the driving transistor 80400 is connected to the power supply line 80412 through the second capacitor element 80405. Further, the gate terminal of the driving transistor 80400 is connected to the second terminal of the driving transistor 80400 through the second switch 80402. In addition, a low power supply potential is set for the second electrode 80421 of the display element 80420. Note that the low power supply potential is a potential that satisfies the low power supply potential <the high power supply potential with reference to the high power supply potential set in the power supply line 80412. For example, GND, 0V, or the like is set as the low power supply potential. Also good. The potential difference between the high power supply potential and the low power supply potential is applied to the display element 80420 and current is supplied to the display element 80420 to cause the display element 80420 to emit light. Each potential is set to be equal to or higher than the forward threshold voltage. Note that the second capacitor 80405 can be omitted by using the gate capacitor of the driving transistor 80400 instead. As for the gate capacitance of the driving transistor 80400, the capacitance may be formed in a region where the source electrode, the drain region, the LDD region, and the like overlap with the gate electrode, or the channel region and the gate electrode. A capacitance may be formed between the two. Note that the first switch 80401, the second switch 80402, and the third switch 80403 are controlled to be turned on / off by the first scan line 80413, the second scan line 80414, and the third scan line 80414, respectively. .

A driving method of the pixel illustrated in FIG. 101A can be divided into an initialization period, a data writing period, a threshold value acquisition period, and a light emission period.

In the initialization period, the second switch 80402 and the third switch 80403 are turned on, so that the potential of the gate terminal of the driving transistor 80400 is at least lower than the potential of the power supply line 80412. At this time, the first switch 80401 may be turned on or off. Note that the initialization period is not necessarily required.

In the threshold acquisition period, a pixel is selected by the first scan line 80413. That is, the first switch 80401 is turned on and a certain voltage is input from the signal line 80411. At this time, the second switch 80402 is on, and the driving transistor 80400 is diode-connected. Further, the third switch 80403 is off. Therefore, the potential of the gate terminal of the driving transistor 80400 is a value obtained by subtracting the threshold voltage of the driving transistor 80400 from the potential of the power supply line 80412. The first capacitor element 80404 holds the threshold voltage of the driving transistor 80400. The second capacitor element 80405 holds a potential difference between the potential of the gate terminal of the driving transistor 80400 and a constant voltage input from the signal line 80411.

In the data writing period, a video signal (voltage) is input from the signal line 80411. At this time, the first switch 80401 remains on, the second switch 80402 is turned off, and the second switch 80402 remains off. Further, the driving transistor 8040
The gate terminal of 0 is in a floating state. Therefore, the potential of the gate terminal of the driving transistor 80400 changes in accordance with the potential difference between the constant voltage input to the signal line 80411 in the threshold acquisition period and the video signal input to the signal line 80411 in the data writing period. . For example, if the capacitance value of the first capacitor element 80404 << the capacitance value of the second capacitor element 80405, the potential of the gate terminal of the driving transistor 80400 in the data writing period is the signal line 80411 in the threshold value acquisition period. The potential difference between the input constant voltage and the video signal input to the signal line 80411 in the data writing period is approximately equal to the value obtained by subtracting the threshold voltage of the driving transistor 80400 from the potential of the power supply line 80412. . That is, the potential of the gate terminal of the driving transistor 80400 is a potential obtained by correcting the threshold voltage of the driving transistor 80400.

In the light-emitting period, current corresponding to the potential difference (Vgs) between the gate terminal of the driving transistor 80400 and the power supply line 80412 flows to the display element 80420. At this time, the first switch 80401 is turned off, the second switch 80402 is kept off, and the third switch 80403 is turned on. Note that the current flowing through the display element 80420 is constant regardless of the threshold voltage of the driving transistor 80400.

Note that the pixel structure illustrated in FIG. 101A is not limited to FIG. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG. For example, the second switch 80402 is a P-channel transistor or an N-channel transistor, the third switch 80403 is a transistor having a polarity different from that of the second switch 80402, and the second switch 80402 The third switch 80403 may be controlled by the same scanning line.

Next, an example of a current input pixel circuit and a driving method which can be applied to the present invention will be described with reference to FIG.

A pixel illustrated in FIG. 101B includes a driving transistor 80430, a first switch 80431, a second switch 80432, a third switch 80433, a capacitor 80434, and a display element 80450. The driving transistor 80430 has a gate terminal connected to the signal line 80441 through the second switch 80432 and the first switch 80431 in order, a first terminal connected to the power supply line 80442, and a second terminal connected to the third terminal. It is connected to the first electrode of the display element 80450 through the switch 80433. Further, the gate terminal of the driving transistor 80430 is connected to the power supply line 80442 through the capacitor 80434. The gate terminal of the driving transistor 80430 is connected to the second terminal of the driving transistor 80430 through the second switch 80432. In addition, a low power supply potential is set for the second electrode 80451 of the display element 80450. Note that the low power supply potential is a potential that satisfies the low power supply potential <the high power supply potential with reference to the high power supply potential set in the power supply line 80442. For example, GND, 0V, or the like is set as the low power supply potential. Also good. The potential difference between the high power supply potential and the low power supply potential is applied to the display element 80450 and a current is passed through the display element 80450 to cause the display element 80450 to emit light. Each potential is set to be equal to or higher than the forward threshold voltage. Note that the capacitor 80434 can be omitted by using the gate capacitor of the driving transistor 80430 instead. Regarding the gate capacitance of the driving transistor 80430, the capacitance may be formed in a region where the source electrode, the drain region, the LDD region, and the like overlap with the gate electrode, or the channel region and the gate electrode. A capacitance may be formed between the two. Note that the first switch 80431, the second switch 80432, and the third switch 80433 are controlled to be turned on / off by a first scan line 80443, a second scan line 80444, and a third scan line 80454, respectively. .

The driving method of the pixel illustrated in FIG. 101B can be divided into a data writing period and a light emission period.

In the data writing period, a pixel is selected by the first scan line 80443. That is, the first switch 80431 is turned on, and a current is input from the signal line 80431 as a video signal. At this time, the second switch 80432 is turned on and the third switch 80433 is turned off. Accordingly, the potential of the gate terminal of the driving transistor 80430 becomes a potential corresponding to the video signal. That is, the capacitor 80434 holds a gate-source voltage of the driving transistor 80430 that causes the driving transistor 80430 to pass the same current as the video signal.

Next, in the light emission period, the first switch 80431 and the second switch 80432 are turned off, and the third switch 80433 is turned on. Therefore, a current having the same value as the video signal flows through the display element 80450.

Note that the pixel structure illustrated in FIG. 101B is not limited to FIG. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG. In addition, for example, the first switch 80431 is formed of a P-channel transistor or an N-channel transistor, the second switch 80432 is formed of a transistor having the same polarity as the first switch 80431, and the first switch 80431 and the first switch 80431 Two switches 80432 may be controlled by the same scanning line. The second switch 80432 may be provided between the gate terminal of the driving transistor 80430 and the signal line 80431.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination, or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 13)
In this embodiment mode, a method for manufacturing a semiconductor device in the case where the semiconductor device to which the present invention can be applied has a thin film transistor (TFT) as an element will be described with reference to drawings.

FIG. 102 is a diagram showing an example of a structure and manufacturing process of a TFT that can be included in a semiconductor device to which the present invention can be applied. FIG. 102A illustrates an example of a structure of a TFT that can be included in a semiconductor device to which the present invention can be applied. 102B to 102G are diagrams illustrating an example of a manufacturing process of a TFT which can be included in a semiconductor device to which the present invention can be applied.

Note that the structure and manufacturing process of a TFT which can be included in a semiconductor device to which the present invention can be applied are not limited to those shown in FIG. 102, and various structures and manufacturing processes can be used.

First, an example of a structure of a TFT that can be included in a semiconductor device to which the present invention can be applied will be described with reference to FIG. FIG. 102A is a cross-sectional view of a TFT having a plurality of different structures. Here, in FIG. 102A, a plurality of TFTs having different structures are shown side by side, but this is an expression for explaining a structure of a TFT that can be included in a semiconductor device to which the invention can be applied. Therefore, the TFTs that can be included in the semiconductor device to which the invention can be applied do not have to be actually juxtaposed as shown in FIG. 102A, and can be manufactured as needed.

Next, characteristics of each layer constituting a TFT that can be included in a semiconductor device to which the present invention can be applied will be described.

As the substrate 110111, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, a metal substrate including stainless steel, or the like can be used. In addition, it is also possible to use a substrate made of a flexible synthetic resin such as plastic or acrylic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). . By using a flexible substrate, a semiconductor device that can be bent can be manufactured. In addition, since there is no great limitation on the area of the substrate and the shape of the substrate as long as the substrate has flexibility, for example, if the substrate 110111 has a rectangular shape with one side being 1 meter or more, , Productivity can be significantly improved. Such an advantage is a great advantage compared to the case of using a circular silicon substrate.

The insulating film 110112 functions as a base film. An alkali metal or alkaline earth metal such as Na is provided from the substrate 110111 in order to prevent adverse effects on the characteristics of the semiconductor element. As the insulating film 110112, an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y) It is possible to provide a single layer structure or a laminated structure thereof. For example, in the case where the insulating film 110112 is provided with a two-layer structure, a silicon nitride oxide film may be provided as a first insulating film and a silicon oxynitride film may be provided as a second insulating film. In the case where the insulating film 110112 is provided with a three-layer structure, a silicon oxynitride film is provided as a first insulating film, a silicon nitride oxide film is provided as a second insulating film, and an oxynitriding film is used as a third insulating film. A silicon film may be provided.

The semiconductor films 110113, 110114, and 110115 can be formed using an amorphous semiconductor or a semi-amorphous semiconductor (SAS). Alternatively, a polycrystalline semiconductor film may be used. SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is a main component, the Raman spectrum is shifted to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. At least 1 atom% or more of hydrogen or halogen is contained as a terminal of dangling bonds (dangling bonds). The SAS is formed by glow discharge decomposition (plasma CVD) of a gas containing silicidation. As the gas containing silicidation, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like can be used. Or Ge
F ₄ may be mixed. The gas containing silicification may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times. The pressure is generally in the range of 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature may be 300 ° C. or less. As an impurity element in the film, impurities of atmospheric components such as oxygen, nitrogen, and carbon are desirably 1 × 10 ²⁰ cm ⁻¹ or less, and in particular, the oxygen concentration is 5 × 10 ¹⁹ / cm ³ or less, preferably 1 × 10 ¹⁹ / cm ³ or less. Here, an amorphous semiconductor film is formed using a known material (a sputtering method, an LPCVD method, a plasma CVD method, or the like) with a material (eg, SixGe1-x) containing silicon (Si) as a main component. The crystalline semiconductor film is crystallized by a known crystallization method such as a laser crystallization method, a thermal crystallization method using an RTA or furnace annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization.

The insulating film 110116 is an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y). A single-layer structure or a stacked structure thereof can be used.

The gate electrode 110117 can have a single-layer conductive film or a stacked structure of two-layer or three-layer conductive films. As a material of the gate electrode 110117, a known conductive film can be used. For example, a simple film of an element such as tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), silicon (Si), or a nitride film of the element (typically A tantalum nitride film, a tungsten nitride film, a titanium nitride film), an alloy film combining the above elements (typically, a Mo—W alloy or a Mo—Ta alloy), or a silicide film of the above elements (typically, (Tungsten silicide film, titanium silicide film) or the like can be used. Note that the single film, nitride film, alloy film, silicide film, and the like described above may be used as a single layer or may be stacked.

The insulating film 110118 is formed by known means (sputtering method, plasma CVD method, or the like) using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) ( It can be provided in a single layer structure of an insulating film containing oxygen or nitrogen such as x> y) or a film containing carbon such as DLC (diamond-like carbon), or a laminated structure thereof.

The insulating film 110119 is formed using siloxane resin, oxygen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y). A single-layer structure or a multilayer structure made of an insulating film having carbon, a film containing carbon such as DLC (diamond-like carbon), or an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic. it can. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Note that in the semiconductor device applicable to the present invention, the insulating film 110119 can be provided directly so as to cover the gate electrode 110117 without providing the insulating film 110118.

The conductive film 110123 is a single film of an element such as Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, or Mn, a nitride film of the element, or an alloy film in which the elements are combined. Alternatively, a silicide film of the above element or the like can be used. For example, as an alloy containing a plurality of the elements, an Al alloy containing C and Ti, an Al alloy containing Ni, an Al alloy containing C and Ni, an Al alloy containing C and Mn, and the like can be used. Further, in the case of providing a stacked structure, a structure in which Al is sandwiched between Mo or Ti can be employed. By carrying out like this, the tolerance with respect to the heat | fever and chemical reaction of Al can be improved.

Next, features of each structure will be described with reference to cross-sectional views of TFTs having a plurality of different structures shown in FIG.

Reference numeral 110101 denotes a single drain TFT, which can be manufactured by a simple method, and thus has an advantage that a manufacturing cost is low and a yield is high. Here, the semiconductor films 110113 and 110115 have different impurity concentrations, the semiconductor film 110113 is used as a channel region, and the semiconductor film 110115 is used as a source region and a drain region. Thus, the resistivity of the semiconductor film can be controlled by controlling the amount of impurities. Further, the electrical connection state between the semiconductor film and the conductive film 110123 can be made close to ohmic connection. Note that as a method of separately forming semiconductor films having different amounts of impurities, a method of doping impurities into the semiconductor film using the gate electrode 110117 as a mask can be used.

Reference numeral 110102 denotes a TFT having a taper angle of a certain level or more on the gate electrode 110117, which can be manufactured by a simple method, and thus has an advantage that the manufacturing cost is low and the yield is high. Here, the semiconductor films 110113, 110114, and 110115 have different impurity concentrations, the semiconductor film 110113 is a channel region, the semiconductor film 110114 is a lightly doped drain (LDD) region, and the semiconductor film 110115 is a source region and a drain region. Used as Thus, the resistivity of the semiconductor film can be controlled by controlling the amount of impurities. Further, the electrical connection state between the semiconductor film and the conductive film 110123 can be made close to ohmic connection. In addition, since the LDD region is included, a high electric field is not easily applied to the inside of the TFT, and deterioration of the element due to hot carriers can be suppressed. Note that as a method of separately forming semiconductor films having different amounts of impurities, a method of doping impurities into the semiconductor film using the gate electrode 110117 as a mask can be used. In 110102, since the gate electrode 110117 has a certain taper angle or more, the concentration of the impurity doped into the semiconductor film through the gate electrode 110117 can be given a gradient, and the LDD region can be easily formed. Can be formed.

Reference numeral 110103 denotes a TFT in which the gate electrode 110117 is composed of at least two layers, and the lower gate electrode is longer than the upper gate electrode. Since the gate electrode 110117 has two layers and the lower gate electrode is longer than the upper gate electrode, an LDD region can be formed without adding a photomask. Note that a structure in which the LDD region overlaps with the gate electrode 110117 like 110103 is particularly referred to as a GOLD structure (Gate Overlapped LDD). Note that the following method may be used as a method of forming the gate electrode 110117 in two layers and forming the lower gate electrode longer than the upper gate electrode.

First, when the gate electrode 110117 is patterned, the lower gate electrode and the upper gate electrode are etched by dry etching so that the side surfaces are inclined (tapered). Subsequently, the upper-layer gate electrode is processed to be nearly vertical by anisotropic etching. Thereby, a gate electrode whose cross-sectional shape is longer than that of the upper gate electrode is formed. After that, by doping the impurity element twice, a semiconductor film 110113 used as a channel region, a semiconductor film 110114 used as an LDD region, and a semiconductor film 110115 used as a source electrode and a drain electrode are formed.

Note that an LDD region overlapping with the gate electrode 110117 is referred to as a Lov region, and an LDD region not overlapping with the gate electrode 110117 is referred to as a Loff region. Where Lof
The f region has a high effect of suppressing the off-current value, but has a low effect of relaxing the electric field near the drain and preventing the deterioration of the on-current value due to hot carriers. On the other hand, the Lov region relaxes the electric field near the drain and is effective in preventing deterioration of the on-current value, but has a low effect of suppressing the off-current value. Therefore, it is preferable to manufacture a TFT having a structure corresponding to required characteristics for each of various circuits. For example, when a semiconductor device applicable to the present invention is used as a display device, it is preferable to use a TFT having a Loff region as the pixel TFT in order to suppress an off-current value. On the other hand, as the TFT in the peripheral circuit, it is preferable to use a TFT having a Lov region in order to relax the electric field in the vicinity of the drain and prevent deterioration of the on-current value.

Reference numeral 110104 denotes a TFT having a sidewall 110121 in contact with the side surface of the gate electrode 110117. By including the sidewall 110121, a region overlapping with the sidewall 110121 can be an LDD region.

Reference numeral 110105 denotes a TFT in which an LDD (Loff) region is formed by doping a semiconductor film using a mask. By so doing, the LDD region can be formed reliably, and the off-current value of the TFT can be reduced.

Reference numeral 110106 denotes a TFT in which an LDD (Lov) region is formed by doping a semiconductor film using a mask. By doing so, the LDD region can be formed reliably, the electric field in the vicinity of the drain of the TFT can be relaxed, and the deterioration of the on-current value can be reduced.

Next, an example of a manufacturing process of a TFT that can be included in a semiconductor device to which the present invention can be applied will be described with reference to FIGS.
Note that the structure and manufacturing process of a TFT which can be included in a semiconductor device to which the present invention can be applied are not limited to those shown in FIG. 102, and various structures and manufacturing processes can be used.

In this embodiment, on the surface of the substrate 110111, on the surface of the insulating film 110112, on the surface of the semiconductor film 110113, on the surface of 110114, on the surface of 110115, on the surface of the insulating film 110116, and on the surface of the insulating film 110118 Alternatively, the semiconductor film or the insulating film can be oxidized or nitrided by performing oxidation or nitridation on the surface of the insulating film 110119 using plasma treatment. In this manner, the surface of the semiconductor film or the insulating film is modified by oxidizing or nitriding the semiconductor film or the insulating film using plasma treatment, and compared with an insulating film formed by a CVD method or a sputtering method. Since a denser insulating film can be formed, defects such as pinholes can be suppressed and characteristics and the like of the semiconductor device can be improved.

First, the surface of the substrate 110111 is cleaned using hydrofluoric acid (HF), alkali, or pure water. As the substrate 110111, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, a metal substrate including stainless steel, or the like can be used. In addition, it is also possible to use a substrate made of a plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a flexible synthetic resin such as acrylic. is there. Note that here, a case where a glass substrate is used as the substrate 110111 is described.

Here, an oxide film or a nitride film may be formed on the surface of the substrate 110111 by performing plasma treatment on the surface of the substrate 110111 to oxidize or nitride the surface of the substrate 110111 (FIG. 102B). . Hereinafter, an insulating film such as an oxide film or a nitride film formed by performing plasma processing on the surface is also referred to as a plasma processing insulating film. In FIG. 102B, the insulating film 131 is a plasma processing insulating film. In general, when a semiconductor element such as a thin film transistor is provided on a substrate such as glass or plastic, an impurity element such as alkali metal or alkaline earth metal such as Na contained in glass or plastic is mixed in the semiconductor element. Contamination may affect the characteristics of the semiconductor element. However, by nitriding the surface of a substrate made of glass or plastic, it is possible to prevent an impurity element such as an alkali metal or an alkaline earth metal such as Na contained in the substrate from entering the semiconductor element.

Note that in the case of oxidizing the surface by plasma treatment, an oxygen atmosphere (eg, oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere, or an oxygen And hydrogen (H ₂ ) and a rare gas atmosphere or dinitrogen monoxide and a rare gas atmosphere). On the other hand, in the case of nitriding a semiconductor film by plasma treatment, in a nitrogen atmosphere (for example, an atmosphere containing nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe), or Plasma treatment is performed in an atmosphere of nitrogen, hydrogen, and a rare gas, or NH ₃ and a rare gas. As the rare gas, for example, Ar can be used. Alternatively, a gas in which Ar and Kr are mixed may be used. Therefore, the plasma processing insulating film includes a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma processing. For example, when Ar is used, Ar is contained in the plasma processing insulating film.

In addition, the plasma treatment is performed in the above gas atmosphere at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less and an electron temperature of plasma of 0.5 ev or more and 1.5 eV or less. Is preferred. Since the electron density of the plasma is high and the electron temperature in the vicinity of the object to be processed is low, damage to the object to be processed by the plasma can be prevented. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or a nitride film formed by oxidizing or nitriding an irradiation object using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. Alternatively, since the electron temperature of plasma is as low as 1 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature that is 100 degrees or more lower than the strain point temperature of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma. Note that the plasma treatment is performed using the above conditions unless otherwise specified.

Note that FIG. 102B illustrates the case where a plasma treatment insulating film is formed by performing plasma treatment on the surface of the substrate 110111; however, in this embodiment, a plasma treatment insulating film is formed on the surface of the substrate 110111. This includes cases where it is not formed.

Note that in FIGS. 102C to 102G, a plasma treatment insulating film formed by performing plasma treatment on the surface of an object to be processed is not illustrated; however, in this embodiment, the substrate 110111 and the insulating film 110112 are not illustrated. In some cases, the surface of the semiconductor films 110113, 110114, 110115, the insulating film 110116, the insulating film 110118, or the insulating film 110119 includes a plasma treatment insulating film formed by performing plasma treatment.

Next, an insulating film 110112 is formed over the substrate 110111 by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) (FIG. 102C). As the insulating film 110112, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) can be used.

Here, the plasma treatment insulating film may be formed on the surface of the insulating film 110112 by performing plasma treatment on the surface of the insulating film 110112 and oxidizing or nitriding the insulating film 110112. By oxidizing the surface of the insulating film 110112, the surface of the insulating film 110112 can be modified to obtain a dense film with few defects such as pinholes. Further, by oxidizing the surface of the insulating film 110112, a plasma processing insulating film with a low N atom content can be formed. Therefore, when a semiconductor film is provided in the plasma processing insulating film, the plasma processing insulating film and the semiconductor The film interface characteristics are improved. The plasma processing insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma processing. Note that the plasma treatment can be similarly performed under the above-described conditions.

Next, island-shaped semiconductor films 110113 and 110114 are formed over the insulating film 110112 (FIG. 102D). The island-shaped semiconductor films 110113 and 110114 are formed of a material (for example, Si _x Ge ₁₋ ) containing silicon (Si) as a main component on the insulating film 110112 using a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). _x ) or the like is used to form an amorphous semiconductor film, the amorphous semiconductor film is crystallized, and the semiconductor film is selectively etched. The crystallization of the amorphous semiconductor film may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. It can carry out by the well-known crystallization method. Note that here, the end portion of the island-shaped semiconductor film is provided in a shape close to a right angle (θ = 85 to 100 °). Alternatively, the semiconductor film 110114 serving as a low-concentration drain region may be formed by doping impurities using a mask.

Here, a plasma treatment insulating film may be formed on the surfaces of the semiconductor films 110113 and 110114 by performing plasma treatment on the surfaces of the semiconductor films 110113 and 110114 and oxidizing or nitriding the surfaces of the semiconductor films 110113 and 110114. For example, when Si is used for the semiconductor films 110113 and 110114, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the plasma processing insulating film. Alternatively, the semiconductor films 110113 and 110114 may be oxidized by plasma treatment and then nitrided by performing plasma treatment again. In this case, silicon oxide (SiOx) is formed in contact with the semiconductor films 110113 and 110114, and silicon nitride oxide (SiNxOy) (x> y) is formed on the surface of the silicon oxide. Note that in the case where the semiconductor film is oxidized by plasma treatment, in an oxygen atmosphere (for example, an atmosphere of oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe), or Plasma treatment is performed with oxygen and hydrogen (H ₂ ) in a rare gas atmosphere or dinitrogen monoxide and a rare gas atmosphere. On the other hand, in the case of nitriding a semiconductor film by plasma treatment, in a nitrogen atmosphere (for example, an atmosphere containing nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe), or Plasma treatment is performed under nitrogen, hydrogen, and a rare gas atmosphere or NH ₃ and a rare gas atmosphere. As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. Therefore, the plasma processing insulating film includes a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma processing. For example, when Ar is used, Ar is contained in the plasma processing insulating film.

Next, an insulating film 110116 is formed (FIG. 102E). The insulating film 110116 is formed using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), oxynitride using a known means (sputtering method, LPCVD method, plasma CVD method, or the like). A single-layer structure of an insulating film containing oxygen or nitrogen such as silicon (SiNxOy) (x> y) or a stacked structure thereof can be used. Note that in the case where a plasma treatment insulating film is formed on the surfaces of the semiconductor films 110113 and 110114 by performing plasma treatment on the surfaces of the semiconductor films 110113 and 110114, the plasma treatment insulating film can be used as the insulating film 110116. .

Here, the plasma treatment insulating film may be formed on the surface of the insulating film 110116 by performing plasma treatment on the surface of the insulating film 110116 and oxidizing or nitriding the surface of the insulating film 110116. Note that the plasma treatment insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma treatment. Further, the plasma treatment can be similarly performed under the above-described conditions.

Alternatively, the insulating film 110116 may be oxidized by performing plasma treatment once in an oxygen atmosphere and then nitrided by performing plasma treatment again in a nitrogen atmosphere. In this manner, by performing plasma treatment on the insulating film 110116 and oxidizing or nitriding the surface of the insulating film 110116, the surface of the insulating film 110116 can be modified and a dense film can be formed. An insulating film obtained by performing plasma treatment is denser and has fewer defects such as pinholes than an insulating film formed by a CVD method or a sputtering method, so that characteristics of the thin film transistor can be improved.

Next, the gate electrode 110117 is formed (FIG. 102F). The gate electrode 110117 can be formed by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like).

In 110101, by performing impurity doping after forming the gate electrode 110117, the semiconductor film 110115 used as a source region and a drain region can be formed.

In 110102, by performing impurity doping after the gate electrode 110117 is formed, a semiconductor film 110115 used as an LDD region and a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

In 110103, impurity doping is performed after the gate electrode 110117 is formed, so that a semiconductor film 110115 used as an LDD region and a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

In 110104, a sidewall 110121 is formed on the side surface of the gate electrode 110117 and then impurity doping is performed, whereby a semiconductor film 110115 used as an LDD region and a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed. .

Note that the sidewall 110121 can be formed using silicon oxide (SiOx) or silicon nitride (SiNx). As a method of forming the side wall 110121 on the side surface of the gate electrode 110117, for example, after forming the gate electrode 110117, a silicon oxide (SiOx) or silicon nitride (SiNx) film is formed by a known method, and then anisotropic. A method of etching a silicon oxide (SiOx) or silicon nitride (SiNx) film by etching can be used. Thus, a silicon oxide (SiO x) or silicon nitride (SiN x) film can be left only on the side surface of the gate electrode 110117, so that the sidewall 110121 can be formed on the side surface of the gate electrode 110117.

In 110105, a mask 110122 is formed so as to cover the gate electrode 110117, and then impurity doping is performed to form a semiconductor film 110115 used as an LDD (Loff) region and a semiconductor film 110115 used as a semiconductor film source region and a drain region. be able to.

In 110106, by performing impurity doping after forming the gate electrode 110117, a semiconductor film 110115 used as an LDD (Lov) region and a semiconductor film 110115 used as a semiconductor film source region and a drain region can be formed.

Next, an insulating film 110118 is formed (FIG. 102G). The insulating film 110118 is formed by known means (sputtering method, plasma CVD method, or the like) using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) ( It can be provided with a single layer structure of an insulating film containing oxygen or nitrogen such as x> y) or a film containing carbon such as DLC (diamond-like carbon), or a laminated structure thereof.

Here, a plasma treatment insulating film may be formed on the surface of the insulating film 110118 by performing plasma treatment on the surface of the insulating film 110118 and oxidizing or nitriding the surface of the insulating film 110118. Note that the plasma treatment insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma treatment. Further, the plasma treatment can be similarly performed under the above-described conditions.

Next, an insulating film 110119 is formed. The insulating film 110119 is formed by a known means (sputtering method, plasma CVD method, or the like) using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) ( In addition to an insulating film having oxygen or nitrogen such as x> y) or a film containing carbon such as DLC (diamond-like carbon), epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, etc. A single layer structure of an organic material or a siloxane resin, or a stacked structure thereof can be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. The plasma processing insulating film contains a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for the plasma processing. For example, when Ar is used, the plasma processing insulating film is used. Ar is contained in the film.

In the case where an organic material such as polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic, or a siloxane resin is used as the insulating film 110119, the surface of the insulating film 110119 is oxidized or nitrided by plasma treatment. Can be modified. By modifying the surface, the strength of the insulating film 110119 is improved, and it is possible to reduce physical damage such as generation of cracks at the time of opening formation and the like and film reduction at the time of etching. In addition, when the surface of the insulating film 110119 is modified, adhesion with the conductive film is improved when the conductive film 110123 is formed over the insulating film 110119. For example, in the case where siloxane resin is used as the insulating film 110119 and nitridation is performed using plasma treatment, the surface of the siloxane resin is nitrided, so that a plasma treatment insulating film containing nitrogen or a rare gas is formed, and the physical strength is increased. improves.

Next, contact holes are formed in the insulating film 110119, the insulating film 110118, and the insulating film 110116 in order to form the conductive film 110123 electrically connected to the semiconductor film 110115. Note that the shape of the contact hole may be tapered. Thus, the coverage of the conductive film 110123 can be improved.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination, or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 14)
In the present embodiment, a detailed configuration of a light-emitting element that can be applied to a display device will be described.

A light-emitting element utilizing electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The former has an electroluminescent layer in which particles of a luminescent material are dispersed in a binder, and the latter has an electroluminescent layer made of a thin film of luminescent material, but is accelerated by a high electric field. This is common in that it requires more electrons. Note that the obtained light emission mechanism includes donor-acceptor recombination light emission using a donor level and an acceptor level, and localized light emission using inner-shell electron transition of a metal ion. In general, the dispersion-type inorganic EL often has donor-acceptor recombination light emission, and the thin-film inorganic EL element often has localized light emission.

A light-emitting material that can be applied to the present invention includes a base material and an impurity element serving as a light emission center. By changing the impurity element to be contained, light emission of various colors can be obtained. As a method for manufacturing the light-emitting material, various methods such as a solid phase method and a liquid phase method (coprecipitation method) can be used. Alternatively, a spray pyrolysis method, a metathesis method, a precursor thermal decomposition method, a reverse micelle method, a method combining these methods with high-temperature firing, a liquid phase method such as a freeze-drying method, or the like can also be used.

The solid phase method is a method in which a base material and an impurity element or a compound containing the impurity element are weighed, mixed in a mortar, heated and fired in an electric furnace, reacted, and the base material contains the impurity element. The firing temperature is preferably 700 to 1500 ° C. This is because the solid phase reaction does not proceed when the temperature is too low, and the base material is decomposed when the temperature is too high. In addition, although baking may be performed in a powder state, it is preferable to perform baking in a pellet state. Although firing at a relatively high temperature is required, it is a simple method, so it has high productivity and is suitable for mass production.

The liquid phase method (coprecipitation method) is a method in which a base material or a compound containing the base material and an impurity element or a compound containing the impurity element are reacted in a solution, dried, and then fired. The particles of the luminescent material are uniformly distributed, and the reaction can proceed even at a low firing temperature with a small particle size.

As a base material used for the light-emitting material, sulfide, oxide, or nitride can be used. Examples of the sulfide include zinc sulfide (ZnS), cadmium sulfide (CdS), calcium sulfide (CaS), yttrium sulfide (Y ₂ S ₃ ), gallium sulfide (Ga ₂ S ₃ ), strontium sulfide (SrS), sulfide. Barium (BaS) or the like can be used. As the oxide, for example, zinc oxide (ZnO), yttrium oxide (Y ₂ O ₃ ), or the like can be used. As the nitride, for example, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or the like can be used. Furthermore, zinc selenide (ZnSe), zinc telluride (ZnTe), and the like can also be used, such as calcium sulfide-gallium sulfide (CaGa ₂ S ₄ ), strontium sulfide-gallium (SrGa ₂ S ₄ ), barium sulfide-gallium (BaGa). _It may be a ternary mixed crystal such as ₂ S ₄ ).

As the emission center of localized emission, manganese (Mn), copper (Cu), samarium (Sm), terbium (Tb), erbium (Er), thulium (Tm), europium (Eu), cerium (Ce), praseodymium (Pr) or the like can be used. Note that a halogen element such as fluorine (F) or chlorine (Cl) may be added as charge compensation.

On the other hand, a light-emitting material containing a first impurity element that forms a donor level and a second impurity element that forms an acceptor level can be used as the emission center of donor-acceptor recombination light emission. As the first impurity element, for example, fluorine (F), chlorine (Cl), aluminum (Al), or the like can be used. For example, copper (Cu), silver (Ag), or the like can be used as the second impurity element.

In the case where a light-emitting material for donor-acceptor recombination light emission is synthesized using a solid-phase method, a base material, a first impurity element or a compound containing the first impurity element, a second impurity element, or a second impurity element Each compound containing an impurity element is weighed and mixed in a mortar, and then heated and fired in an electric furnace. As the base material, the above-described base material can be used, and examples of the first impurity element or the compound containing the first impurity element include fluorine (F), chlorine (Cl), and aluminum sulfide (Al ₂ S). ₃ ) or the like, and examples of the second impurity element or the compound containing the second impurity element include copper (Cu), silver (Ag), copper sulfide (Cu ₂ S), and silver sulfide (Ag). ₂ S) or the like can be used. The firing temperature is preferably 700 to 1500 ° C. This is because the solid phase reaction does not proceed when the temperature is too low, and the base material is decomposed when the temperature is too high. In addition, although baking may be performed in a powder state, it is preferable to perform baking in a pellet state.

In addition, as an impurity element in the case of using a solid phase reaction, a compound including a first impurity element and a second impurity element may be used in combination. In this case, since the impurity element is easily diffused and the solid-phase reaction easily proceeds, a uniform light emitting material can be obtained. Further, since no extra impurity element is contained, a light-emitting material with high purity can be obtained. As the compound including the first impurity element and the second impurity element, for example, copper chloride (CuCl), silver chloride (AgCl), or the like can be used.

Note that the concentration of these impurity elements may be 0.01 to 10 atom% with respect to the base material, and is preferably in the range of 0.05 to 5 atom%.

In the case of a thin-film inorganic EL, the electroluminescent layer is a layer containing the above-described luminescent material, and is a physical vapor deposition method such as a resistance heating vapor deposition method, a vacuum vapor deposition method such as an electron beam vapor deposition (EB vapor deposition) method, a sputtering method, PVD), metal organic chemical vapor deposition (CVD), chemical vapor deposition (CVD) such as hydride transport low pressure CVD, atomic epitaxy (ALE), or the like.

FIGS. 103A to 103C illustrate an example of a thin-film inorganic EL element that can be used as a light-emitting element. 103A to 103C, the light-emitting element includes a first electrode layer 120100, an electroluminescent layer 120102, and a second electrode layer 120103.

A light-emitting element illustrated in FIGS. 103B and 103C has a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element in FIG. 103A. A light-emitting element illustrated in FIG. 103B includes an insulating layer 120104 between the first electrode layer 120100 and the electroluminescent layer 120102, and the light-emitting element illustrated in FIG. 103C includes the first electrode layer 120100. And an electroluminescent layer 120102, and an insulating layer 120105 is provided between the second electrode layer 120103 and the electroluminescent layer 120102. Thus, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. The insulating layer may be a single layer or a stacked layer including a plurality of layers.

Note that in FIG 103B, the insulating layer 120104 is provided so as to be in contact with the first electrode layer 120100; however, the order of the insulating layer and the electroluminescent layer is reversed so as to be in contact with the second electrode layer 120103. An insulating layer 120104 may be provided.

In the case of a dispersion-type inorganic EL, a particulate luminescent material is dispersed in a binder to form a film-like electroluminescent layer. Process into particles. When particles having a desired size cannot be obtained sufficiently by the method for manufacturing a light emitting material, the particles may be processed into particles by pulverization or the like in a mortar or the like. A binder is a substance for fixing a granular light emitting material in a dispersed state and maintaining the shape as an electroluminescent layer. The light emitting material is uniformly dispersed and fixed in the electroluminescent layer by the binder.

In the case of the dispersion type inorganic EL, the electroluminescent layer can be formed by a droplet discharge method capable of selectively forming an electroluminescent layer, a printing method (screen printing, offset printing, etc.), a coating method such as a spin coating method, dipping, etc. The method, the dispenser method, etc. can also be used. The film thickness is not particularly limited, but is preferably in the range of 10 to 1000 nm. In the electroluminescent layer including the light emitting material and the binder, the ratio of the light emitting material may be 50 wt% or more and 80 wt% or less.

104A to 104C illustrate an example of a dispersion-type inorganic EL element that can be used as a light-emitting element. A light-emitting element in FIG. 104A has a stacked structure of a first electrode layer 120200, an electroluminescent layer 120202, and a second electrode layer 120203, and a light-emitting material 120201 held by a binder in the electroluminescent layer 120202. Including.

As a binder that can be used in this embodiment mode, an insulating material can be used. As the insulating material, an organic material and an inorganic material can be used. Alternatively, a mixed material of an organic material and an inorganic material may be used. As the organic insulating material, a polymer having a relatively high dielectric constant such as a cyanoethyl cellulose resin, or a resin such as polyethylene, polypropylene, polystyrene resin, silicone resin, epoxy resin, or vinylidene fluoride can be used. Alternatively, a heat resistant polymer such as aromatic polyamide, polybenzimidazole, or siloxane resin may be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Alternatively, a resin material such as a vinyl resin such as polyvinyl alcohol or polyvinyl butyral, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, a urethane resin, or an oxazole resin (polybenzoxazole) may be used. The dielectric constant can be adjusted by appropriately mixing fine particles of high dielectric constant such as barium titanate (BaTiO ₃ ) and strontium titanate (SrTiO ₃ ) with these resins.

Examples of the inorganic insulating material included in the binder include silicon oxide (SiOx), silicon nitride (SiNx), silicon containing oxygen and nitrogen, aluminum nitride (AlN), aluminum containing oxygen and nitrogen, and aluminum oxide containing oxygen and nitrogen ( Al ₂ O ₃ ), titanium oxide (TiO ₂ ), BaTiO ₃ , SrTiO ₃ , lead titanate (PbTiO ₃ ), potassium niobate (KN)
bO ₃ ), lead niobate (PbNbO ₃ ), tantalum oxide (Ta ₂ O ₅ ), barium tantalate (BaTa ₂ O ₆ ), lithium tantalate (LiTaO ₃ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide It can be formed of a material selected from substances including (ZrO ₂ ), ZnS and other inorganic insulating materials. By including an inorganic material having a high dielectric constant in the organic material (by addition or the like), the dielectric constant of the electroluminescent layer made of the light emitting material and the binder can be further controlled, and the dielectric constant can be further increased. .

In the manufacturing process, the light-emitting material is dispersed in a solution containing a binder. As a solvent of a solution containing a binder that can be used in this embodiment mode, a method of forming an electroluminescent layer by dissolving a binder material (various wet processes) and a solution having a viscosity suitable for a desired film thickness can be manufactured. Such a solvent may be appropriately selected. For example, an organic solvent or the like can be used as the solvent. When a siloxane resin is used as the binder, propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate (also referred to as PGMEA), 3-methoxy-3-methyl-1-butanol (also referred to as MMB), or the like can be used as a solvent.

104B and 104C each have a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element in FIG. 104A. 104B includes an insulating layer 120204 between the first electrode layer 120200 and the electroluminescent layer 120202. The light-emitting element illustrated in FIG. 104C includes the first electrode layer 120200. And an electroluminescent layer 120202, and an insulating layer 120205 is provided between the second electrode layer 120203 and the electroluminescent layer 120202. Thus, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. The insulating layer may be a single layer or a stacked layer having a plurality of layers.

104B, the insulating layer 120204 is provided so as to be in contact with the first electrode layer 120200; however, the order of the insulating layer and the electroluminescent layer is reversed so as to be in contact with the second electrode layer 120203. An insulating layer 120204 may be provided.

A material that can be used for the insulating layers such as the insulating layer 120104 in FIG. 103 and the insulating layer 120204 in FIG. 104 preferably has high insulation resistance and a dense film quality. Furthermore, it is preferable that the dielectric constant is high. For example, silicon oxide (SiO ₂ ), yttrium oxide (Y ₂ O ₃ ), titanium oxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), Barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), lead titanate (PbTiO ₃ ), silicon nitride (Si ₃ N ₄ ), zirconium oxide (ZrO ₂ ), etc., a mixed film thereof, or two or more kinds thereof A laminated film can be used. These insulating films can be formed by sputtering, vapor deposition, CVD, or the like. The insulating layer may be formed by dispersing particles of these insulating materials in a binder. The binder material may be formed using the same material and method as the binder contained in the electroluminescent layer. The film thickness is not particularly limited, but is preferably in the range of 10 to 1000 nm.

The light-emitting element described in this embodiment can emit light by applying a voltage between a pair of electrode layers sandwiching an electroluminescent layer, but can operate in either direct current drive or alternating current drive.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination, or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 15)
In this embodiment, an example of a display device, particularly a case where optical handling is performed will be described.

A rear projection display device 130100 shown in FIGS. 105A and 105B includes a projector unit 130111, a mirror 130112, and a screen panel 130101. In addition, a speaker 130102 and operation switches 130104 may be provided. The projector unit 130111 is disposed below the casing 130110 of the rear projection display device 130100, and projects projection light that projects an image based on the image signal toward the mirror 130112. The rear projection display device 130100 is configured to display an image projected from the rear surface of the screen panel 130101.

  On the other hand, FIG. 106 shows a front projection display device 130200. The front projection display device 130200 includes a projector unit 130111 and a projection optical system 130201. The front projection optical system 130200 is configured to project an image on a screen or the like disposed on the front surface.

  The configuration of the projector unit 130111 applied to the rear projection display device 130100 shown in FIG. 105 and the front projection display device 130200 shown in FIG. 106 will be described below.

  FIG. 107 shows a configuration example of the projector unit 130111. The projector unit 130111 includes a light source unit 130301 and a modulation unit 130304. The light source unit 130301 includes a light source optical system 130303 including lenses and a light source lamp 130302. The light source lamp 130302 is housed in the housing so that stray light does not diffuse. As the light source lamp 130302, for example, a high-pressure mercury lamp or a xenon lamp capable of emitting a large amount of light is used. The light source optical system 130303 is configured by appropriately providing an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, and the like. The light source unit 130301 is disposed so that the emitted light is incident on the modulation unit 130304. The modulation unit 130304 includes a plurality of display panels 130308, a color filter, a dichroic mirror 130305, a total reflection mirror 130306, a prism 130309, and a projection optical system 130310. Light emitted from the light source unit 130301 is separated into a plurality of optical paths by the dichroic mirror 130305.

Each optical path is provided with a color filter that transmits light of a predetermined wavelength or wavelength band, and a display panel 130308. A transmissive display panel 130308 modulates transmitted light based on a video signal. The light of each color transmitted through the display panel 130308 is reflected by the prism 13.
0309 is entered, and an image is displayed on the screen through the projection optical system 130310. A Fresnel lens may be disposed between the mirror and the screen. The projection light projected by the projector unit 130111 and reflected by the mirror is converted into substantially parallel light by the Fresnel lens and projected onto the screen.

  A projector unit 130111 shown in FIG. 108 has a configuration including reflective display panels 130407, 130408, and 130409.

  A projector unit 130111 shown in FIG. 108 includes a light source unit 130301 and a modulation unit 130400. The light source unit 130301 may have the same configuration as that in FIG. Light from the light source unit 130301 is divided into a plurality of optical paths by the dichroic mirrors 130401 and 130402 and the total reflection mirror 130403, and enters the polarization beam splitters 130404, 130405, and 130406. The polarizing beam splitters 130404, 130405, and 130406 are provided corresponding to the reflective display panels 130407, 130408, and 130409 corresponding to the respective colors. The reflective display panels 130407, 130408, and 130409 modulate reflected light based on the video signal. The light beams of the respective colors reflected by the reflective display panels 130407, 130408, and 130409 are combined by being incident on the prism 130309 and projected through the projection optical system 13041.

  Light emitted from the light source unit 130301 is transmitted through the dichroic mirror 130401 only in the red wavelength region and reflects in the green and blue wavelength regions. Further, the dichroic mirror 130402 reflects only light in the green wavelength region. The light in the red wavelength region that has passed through the dichroic mirror 130401 is reflected by the total reflection mirror 130403 and is incident on the polarization beam splitter 130404. The light in the blue wavelength region is incident on the polarization beam splitter 130405, and the green wavelength The light in the region enters the polarization beam splitter 130406. The polarization beam splitters 130404, 130405, and 130406 have a function of separating incident light into P-polarized light and S-polarized light, and have a function of transmitting only P-polarized light. The reflective display panels 130407, 130408, and 130409 polarize incident light based on the video signal.

  Only S-polarized light corresponding to each color is incident on the reflective display panels 130407, 130408, and 130409 corresponding to the respective colors. Note that the reflective display panels 130407, 130408, and 130409 may be liquid crystal panels. At this time, the liquid crystal panel operates in an electric field controlled birefringence mode (ECB). The liquid crystal molecules are vertically aligned with a certain angle with respect to the substrate. Accordingly, the display molecules of the reflective display panels 130407, 130408, and 130409 are oriented so that they are reflected without changing the polarization state of incident light when the pixel is in the off state. Further, when the pixel is in the ON state, the orientation state of the display molecules changes, and the polarization state of incident light changes.

  A projector unit 130111 shown in FIG. 108 can be applied to the rear projection display device 130100 shown in FIG. 105 and the front projection display device 130200 shown in FIG.

  The projector unit shown in FIG. 109 has a single-plate configuration. A projector unit 130111 shown in FIG. 109A includes a light source unit 130301, a display panel 130507, a projection optical system 130511, and a phase difference plate 130504. The projection optical system 130511 includes one or a plurality of lenses. The display panel 130507 may be provided with a color filter.

  FIG. 109B shows the configuration of a projector unit 130111 that operates in a field sequential manner. The field sequential method is a method in which light of each color such as red, green, and blue is temporally shifted and sequentially incident on a display panel to perform color display without a color filter. In particular, when combined with a display panel having a high response speed with respect to input signal changes, a high-definition image can be displayed. In FIG. 109B, a rotary color filter plate 130505 provided with a plurality of color filters such as red, green, and blue is provided between the light source unit 130301 and the display panel 130508.

  A projector unit 130111 shown in FIG. 109C shows a configuration of a color separation method using a macro lens as a color display method. In this method, a microlens array 130506 is provided on the light incident side of the display panel 130509, and color display is realized by illuminating light of each color from each direction. The projector unit 130111 that employs this method has a feature that light from the light source unit 130301 can be effectively used because light loss due to the color filter is small. A projector unit 130111 shown in FIG. 109C includes a dichroic mirror 130501, a dichroic mirror 130502, and a dichroic mirror for red light 130503 so as to illuminate the display panel 130509 with light of each color from each direction.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination, or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 16)
In this embodiment, an example of an electronic apparatus according to the present invention will be described.

FIG. 110 shows a display panel module in which a display panel 900101 and a circuit board 900111 are combined. A display panel 900101 includes a pixel portion 900102, a scan line driver circuit 900103, and a signal line driver circuit 900104. On the circuit board 900111, for example, a control circuit 900112 and a signal dividing circuit 900113 are formed. The display panel 900101 and the circuit board 900111 are connected by a connection wiring 900114. An FPC or the like can be used for the connection wiring.

In the display panel 900101, a pixel portion 900102 and a part of peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are integrally formed using a TFT over a substrate, and a part of the peripheral driver circuits (a plurality of peripheral driver circuits) A driver circuit having a high operating frequency among driver circuits) may be formed over an IC chip, and the IC chip may be mounted on the display panel 900101 using COG (Chip On Glass) or the like. Thus, the area of the circuit board 900111 can be reduced, and a small display device can be obtained. Alternatively, the IC chip may be mounted on the display panel 900101 using TAB (Tape Auto Bonding) or a printed board. Thus, the area of the display panel 900101 can be reduced, so that a display device with a small frame size can be obtained.

For example, in order to reduce power consumption, a pixel portion is formed using a TFT on a glass substrate, all peripheral drive circuits are formed on an IC chip, and the IC chip is mounted on a display panel by COG or TAB. May be.

A television receiver can be completed with the display panel module illustrated in FIG. FIG. 111 is a block diagram illustrating a main configuration of a television receiver. A tuner 900201 receives a video signal and an audio signal. The video signal includes a video signal amplifying circuit 900202, a video signal processing circuit 900203 for converting a signal output from the video signal amplifying circuit 900202 into a color signal corresponding to each color of red, green, and blue, and a driving circuit for the video signal. Is processed by a control circuit 900212 for conversion to the input specification of The control circuit 900212 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 900213 may be provided on the signal line side, and an input digital signal may be divided into m pieces (m is a positive integer) and supplied.

Of the signals received by the tuner 900201, the audio signal is sent to the audio signal amplifier circuit 900205, and the output is supplied to the speaker 900207 via the audio signal processing circuit 900206. The control circuit 900208 receives the receiving station (reception frequency) and volume control information from the input unit 9000020, and sends a signal to the tuner 900201 and the audio signal processing circuit 900206.

FIG. 112A illustrates a television receiver in which a display panel module different from that in FIG. 111 is incorporated. In FIG. 112A, a display screen 900302 housed in a housing 900301 is formed using a display panel module. Note that a speaker 900303, an operation switch 900304, and the like may be provided as appropriate.

FIG. 112B illustrates a television receiver that can carry only a display wirelessly. A housing 900312 includes a battery and a signal receiver, and the display portion 900313 and the speaker portion 900317 are driven by the battery. The battery can be repeatedly charged with a charger 900310. The charger 900310 can transmit and receive a video signal, and can transmit the video signal to a signal receiver of the display. The housing 900312 is controlled by operation keys 900316. Alternatively, the device illustrated in FIG. 112B may be a video / audio bidirectional communication device capable of transmitting a signal from the housing 900312 to the charger 900310 by operating the operation key 900316. Alternatively, by operating the operation key 900316, a signal is transmitted from the housing 900312 to the charger 900310, and further, a signal that can be transmitted by the charger 900310 is received by another electronic device, thereby controlling communication of the other electronic device. It may be a general purpose remote control device. The present invention can be applied to the display portion 900313.

FIG. 113A illustrates a module in which a display panel 900401 and a printed wiring board 900402 are combined. A display panel 900401 includes a pixel portion 900403 provided with a plurality of pixels, a first scan line driver circuit 900404, a second scan line driver circuit 9000040, and a signal line driver circuit that supplies a video signal to a selected pixel. 900406 may be provided.

The printed wiring board 900402 includes a controller 900407, a central processing unit (CPU) 9000040, a memory 9000040, a power supply circuit 900410, an audio processing circuit 90000411, a transmission / reception circuit 900412, and the like. The printed wiring board 900402 and the display panel 900401 are connected by a flexible wiring board (FPC) 900413. The printed wiring board 900413 may be provided with a storage capacitor, a buffer circuit, and the like to prevent generation of noise in the power supply voltage and signal and increase in signal rise time. The controller 900407, the audio processing circuit 9000041, the memory 900409, the CPU 900408, the power supply circuit 900410, and the like can also be mounted on the display panel 900401 using a COG (Chip On Glass) method. The scale of the printed wiring board 900402 can be reduced by the COG method.

Various control signals are input / output through an interface (I / F) unit 900414 provided in the printed wiring board 900402. Further, an antenna port 900415 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 900402.

FIG. 113B shows a block diagram of the module shown in FIG. This module includes a VRAM 900416, a DRAM 9000041, a flash memory 900418, and the like as the memory 900409. The VRAM 900416 stores image data to be displayed on the panel, the DRAM 900417 stores image data or audio data, and the flash memory stores various programs.

The power supply circuit 900410 supplies power for operating the display panel 900401, the controller 900407, the CPU 9000040, the sound processing circuit 9000041, the memory 900409, and the transmission / reception circuit 9000041. Depending on the panel specifications, the power supply circuit 900410 may be provided with a current source.

The CPU 900408 has a control signal generation circuit 900420, a decoder 900421, a register 900422, an arithmetic circuit 9000042, a RAM 900394, an interface 900419 for the CPU 900408, and the like. Various signals input to the CPU 900408 via the interface 900419 are temporarily held in the register 9000042 and then input to the arithmetic circuit 9000042, the decoder 900421, and the like. The arithmetic circuit 900423 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 900411 is decoded and input to the control signal generation circuit 900420. The control signal generation circuit 900420 generates a signal including various instructions based on the input signal, and a location specified in the arithmetic circuit 9000042, specifically, a memory 9000040, a transmission / reception circuit 90000412, a sound processing circuit 9000041, a controller 900407, and the like. Send to.

The memory 9000040, the transmission / reception circuit 9000041, the sound processing circuit 9000041, and the controller 900407 operate according to received commands. The operation will be briefly described below.

A signal input from the input unit 9000042 is sent to the CPU 900408 mounted on the printed wiring board 900402 via the interface 9000041. The control signal generation circuit 900420 converts the image data stored in the VRAM 900416 into a predetermined format according to the signal sent from the input means 9000042 such as a pointing device or a keyboard, and sends it to the controller 900407.

The controller 900407 performs data processing on a signal including image data sent from the CPU 900408 in accordance with the panel specification, and supplies the processed signal to the display panel 900401. Further, the controller 900407 receives the Hsync signal, the Vsync signal, the clock signal CLK, the AC voltage (AC Cont), and the switching signal L / R based on the power supply voltage input from the power supply circuit 900410 and various signals input from the CPU 900408. Generated and supplied to the display panel 900401.

In the transmission / reception circuit 9000041, a signal transmitted / received as a radio wave in the antenna 9000042 is processed. Specifically, high-frequency signals such as an isolator, a band pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun A circuit may be included. A signal including audio information among signals transmitted and received in the transmission / reception circuit 900412 is transmitted to the audio processing circuit 900411 in accordance with a command from the CPU 900408.

A signal including audio information transmitted in accordance with a command of the CPU 900408 is demodulated into an audio signal in the audio processing circuit 900411 and is transmitted to the speaker 9000042. The audio signal sent from the microphone 9000042 is modulated in the audio processing circuit 9000041 and sent to the transmission / reception circuit 9000041 in accordance with a command from the CPU 900408.

A controller 900407, a CPU 900408, a power supply circuit 900410, an audio processing circuit 90000411, and a memory 9000040 can be mounted as a package of this embodiment.

Needless to say, this embodiment is not limited to a television receiver, and various uses as a display medium of a particularly large area such as a personal computer monitor, an information display board at a railway station or airport, an advertisement display board in a street, etc. Can be applied to.

Next, a configuration example of the mobile phone according to the present invention will be described with reference to FIG.

The display panel 900501 is incorporated in a housing 900530 so as to be detachable. The shape and size of the housing 900530 can be changed as appropriate in accordance with the size of the display panel 900501. A housing 900530 to which the display panel 900501 is fixed is fitted into the printed circuit board 900531 and assembled as a module.

The display panel 900501 is connected to the printed circuit board 900531 through the FPC 900531. A signal processing circuit 9000053 including a speaker 900532, a microphone 900533, a transmission / reception circuit 90000534, a CPU, a controller, and the like is formed on the printed circuit board 900531. Such a module is combined with the input means 900566 and the battery 900577 and stored in the housing 9000053. The pixel portion of the display panel 900501 is arranged so as to be visible from an opening window formed in the housing 9000053.

In the display panel 900501, a pixel portion and some peripheral driver circuits (a driver circuit having a low operating frequency among a plurality of driver circuits) are integrally formed using a TFT over a substrate, and some peripheral driver circuits (a plurality of driver circuits) are formed. A driving circuit having a high operating frequency among the circuits) may be formed over an IC chip, and the IC chip may be mounted on the display panel 900501 using COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Auto Bonding) or a printed board. With such a structure, the power consumption of the display device can be reduced, and the usage time by one charge of the mobile phone can be extended. In addition, the cost of the mobile phone can be reduced.

115 includes an operation switch 9000060, a microphone 90, and the like.
A main body (A) 9000060 provided with 0605 and the like, and a main body (B) 9000060 provided with a display panel (A) 900068, a display panel (B) 9000060, a speaker 9000060, and the like are connected with a hinge 900610 so as to be opened and closed. ing. The display panel (A) 900608 and the display panel (B) 900609 are housed in a housing 900603 of the main body (B) 900602 together with the circuit board 9000060. The pixel portions of the display panel (A) 900608 and the display panel (B) 900609 are arranged so as to be visible from an opening window formed in the housing 900603.

In the display panel (A) 900608 and the display panel (B) 900609, specifications such as the number of pixels can be set as appropriate depending on the function of the mobile phone 900600. For example, the display panel (A) 900608 can be combined as a main screen and the display panel (B) 900609 can be combined as a sub-screen.

The mobile phone according to the present embodiment can be transformed into various modes depending on the function and application. For example, a mobile phone with a camera may be provided by incorporating an image sensor at the hinge 900610. In addition, even when the operation switches 9000060, the display panel (A) 900068, and the display panel (B) 900609 are housed in one housing, the above-described effects can be obtained. Further, even when the configuration of the present embodiment is applied to an information display terminal having a plurality of display units, the same effect can be obtained.

The present invention can be applied to various electronic devices. Specifically, it can be applied to a display portion of an electronic device. Such electronic devices include video cameras, digital cameras, goggles-type displays, navigation systems, sound playback devices (car audio, audio components, etc.), computers, game devices, portable information terminals (mobile computers, mobile phones, portable games) Or an image reproducing apparatus (specifically, an apparatus having a display capable of reproducing a recording medium such as a digital versatile disc (DVD) and displaying the image). .

FIG. 116A shows a display, which includes a housing 900711, a supporting base 900712, a display portion 900713, and the like.

FIG. 116B shows a camera, which includes a main body 900721, a display portion 900722, an image receiving portion 900723, operation keys 900724, an external connection port 900725, a shutter 900726, and the like.

  FIG. 116C illustrates a computer, which includes a main body 900731, a housing 900732, a display portion 900733, a keyboard 900734, an external connection port 900735, a pointing device 9000073, and the like.

  FIG. 116D shows a mobile computer, which includes a main body 900741, a display portion 900742, a switch 900743, operation keys 900744, an infrared port 900745, and the like.

FIG. 116E shows a portable image reproducing device (eg, a DVD reproducing device) provided with a recording medium, which includes a main body 900711, a casing 9000075, a display portion A90073, a display portion B90074, and a recording medium (DVD etc.) reading portion. 900755, operation keys 900756, a speaker unit 900777, and the like. The display portion A90073 can mainly display image information, and the display portion B900743 can mainly display character information.

FIG. 116F illustrates a goggle type display, which includes a main body 900761 and a display portion 90076.
2, including an earphone 900763 and a support portion 900764.

FIG. 116G illustrates a portable game machine including a housing 900771, a display portion 900772, a speaker portion 900773, operation keys 900774, a storage medium insertion portion 900775, and the like. A portable game machine in which the display device of the present invention is used for the display portion 900772 can express bright colors.

FIG. 116H illustrates a digital camera with a television receiving function, which includes a main body 900781, a display portion 900782, operation keys 900783, a speaker 900784, a shutter 900785, an image receiving portion 900786, an antenna 900787, and the like.

As shown in FIGS. 116A to 116E, an electronic device according to the present invention has a display portion for displaying some information.

Next, application examples of the semiconductor device according to the present invention will be described.

FIG. 117 shows an example in which a semiconductor device according to the present invention is provided in a building. FIG. 117 includes a housing 900810, a display portion 900811, a remote control device 900812 as an operation portion, a speaker portion 9000081, and the like. The semiconductor device according to the present invention is integrated with a building as a wall-hanging type, and can be installed without requiring a large installation space.

FIG. 118 shows another example in which the semiconductor device according to the present invention is provided in a building. The display panel 900901 is integrally attached to the unit bath 900902, so that the bather can view the display panel 900901. The display panel 900901 has a function of displaying information by being operated by a bather and being used as an advertisement or an entertainment means.

Note that the semiconductor device according to the present invention can be installed not only on the side wall of the unit bus 900902 shown in FIG. For example, it may be integrated with part of the mirror surface or the bathtub itself. At this time, the shape of the display panel 900901 may be adapted to the shape of a mirror surface or a bathtub.

FIG. 119 shows another example in which the semiconductor device according to the present invention is provided in a building. The display panel 901002 is attached so as to be curved according to the curved surface of the columnar body 901001. Here, the columnar body 901001 is described as a utility pole.

A display panel 901002 illustrated in FIG. 119 is provided at a position higher than the human viewpoint. By installing the display panel 901002 on a building that is repeatedly forested outdoors such as an electric pole, an advertisement can be made to an unspecified number of viewers. Here, since the display panel 901002 can easily display the same image and can switch the image instantly by control from the outside, extremely efficient information display and advertising effect can be expected. Further, it can be said that providing a self-luminous display element in the display panel 901002 is useful as a display medium with high visibility even at night. In addition, it is easy to secure the power supply means of the display panel 901002 by installing the power pole. Also, in the event of an emergency such as the occurrence of a disaster, it can also be a means for quickly and accurately transmitting information to the victims.

Note that as the display panel 901002, for example, a display panel which displays an image by providing a switching element such as an organic transistor on a film-like substrate and driving the display element can be used.

In this embodiment, a wall, a columnar body, and a unit bus are taken as an example of a building, but this embodiment is not limited to this, and the semiconductor device according to the present invention can be installed in various buildings. .

Next, an example in which the semiconductor device according to the present invention is provided in a moving body is described.

FIG. 120 is a diagram showing an example in which a semiconductor device according to the present invention is provided in an automobile. A display panel 901102 is attached integrally with a vehicle body 901101 of an automobile, and can display on-demand information on the operation of the vehicle body and information input from inside and outside the vehicle body. Moreover, you may have a navigation function.

Note that the semiconductor device according to the present invention can be installed not only in the vehicle body 901101 shown in FIG. For example, it may be integrated with a glass window, a door, a handle, a shift lever, a seat, a room mirror, and the like. At this time, the shape of the display panel 901102 may be adapted to the shape of the object to be installed.

FIG. 121 is a diagram showing an example in which a semiconductor device according to the present invention is provided in a train car.

FIG. 121 (a) is a diagram showing an example in which a display panel 901202 is provided on the glass of a door 901201 of a train car. Compared to conventional paper advertisements, there is an advantage that labor costs required for advertisement switching are not incurred. In addition, since the display panel 901202 can instantaneously switch the image displayed on the display unit in response to an external signal, for example, the display panel image is displayed every time when the customer class of passengers on the train changes. Can be switched, and more effective advertising effect can be expected.

FIG. 121B is a diagram showing an example in which a display panel 901202 is provided on a glass window 901203 and a ceiling 901204 in addition to the glass of the door 901201 of the train car. As described above, since the semiconductor device according to the present invention can be easily installed in a place where it has been difficult to install conventionally, an effective advertising effect can be obtained. In addition, since the semiconductor device according to the present invention can instantaneously switch the image displayed on the display unit by an external signal, the cost and time at the time of advertisement switching can be reduced, and a more flexible advertisement Operation and information transmission.

Note that the semiconductor device according to the present invention can be installed not only in the door 901201, the glass window 901203, and the ceiling 901204 shown in FIG. 121 but also in various places. For example, it may be integrated with a strap, a seat, a rail, a floor or the like. At this time, the shape of the display panel 901202 may be matched with the shape of the display panel.

FIG. 122 is a diagram showing an example in which the semiconductor device according to the present invention is provided in a passenger airplane.

FIG. 122A is a diagram showing a shape in use when a display panel 901302 is provided on a ceiling 901301 above a seat of a passenger airplane. The display panel 901302 is integrally attached via a ceiling 901301 and a hinge part 901303, and the passenger can view the display panel 901302 by expansion and contraction of the hinge part 901303. A display panel 901302 has a function of displaying information by being operated by a passenger and being used as an advertisement or an entertainment means. In addition, as shown in FIG. 122 (b), by folding the hinge portion and storing it in the ceiling 901301, safety during takeoff and landing can be considered. In addition, by turning on the display element of the display panel in an emergency, it can be used as an information transmission means and a guide light.

Note that the semiconductor device according to the present invention can be installed not only in the ceiling 901301 shown in FIG. 122 but also in various places. For example, it may be integrated with a seat seat, a seat table, an armrest, a window and the like. In addition, a large display panel that can be viewed simultaneously by a large number of people may be installed on the wall of the aircraft. At this time, the shape of the display panel 901302 may be adapted to the shape of the object to be installed.

In the present embodiment, examples of the moving body include a train car body, an automobile body, and an airplane body. However, the present invention is not limited to this, and a motorcycle, an automobile (including an automobile, a bus, etc.) It can be installed on various things such as railways) and ships. Since the semiconductor device according to the present invention can instantaneously switch the display of the display panel in the moving body by an external signal, the moving body can be mounted by installing the semiconductor device according to the present invention in the moving body. It can be used for applications such as an advertisement display board for an unspecified number of customers and an information display board at the time of disaster.

Note that in this embodiment mode, description has been made using various drawings. However, the contents (or part of the contents) described in each figure may be different from the contents (or part of the contents) described in another figure. , Application, combination, or replacement can be performed freely. Further, in the drawings described so far, more parts can be formed by combining each part with another part.

Similarly, the contents (may be a part) described in each drawing of this embodiment are applied, combined, or replaced with the contents (may be a part) described in the figure of another embodiment. Can be done freely. Further, in the drawings of this embodiment mode, more drawings can be formed by combining each portion with a portion of another embodiment.

Note that the present embodiment is an example in which the contents (may be part) described in other embodiments are embodied, an example in which the content is slightly modified, an example in which a part is changed, and an improvement. An example of a case, an example of a case where it is described in detail, an example of a case where it is applied, an example of a related part, and the like are shown. Therefore, the contents described in other embodiments can be freely applied to, combined with, or replaced with this embodiment.

(Embodiment 17)
As described above, the present specification includes at least the following inventions.

A pixel having a liquid crystal element; and a driver circuit, wherein the driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, 6 transistor, the seventh transistor, and the eighth transistor, the first electrode of the first transistor is electrically connected to the fourth wiring, and the second transistor of the first transistor An electrode is electrically connected to a third wiring, a first electrode of the second transistor is electrically connected to a seventh wiring, and a second electrode of the second transistor is connected to the third wiring. Electrically connected to a wiring; a gate electrode of the second transistor is electrically connected to a fifth wiring; a first electrode of the third transistor is electrically connected to a sixth wiring; The second of the third transistor; An electrode is electrically connected to the gate electrode of the sixth transistor, a gate electrode of the third transistor is electrically connected to the fourth wiring, and a first electrode of the fourth transistor is Electrically connected to a seventh wiring; a second electrode of the fourth transistor is electrically connected to a gate electrode of the sixth transistor; and a gate electrode of the fourth transistor is connected to the fifth electrode Electrically connected to the wiring, the first electrode of the fifth transistor is electrically connected to the sixth wiring, and the second electrode of the fifth transistor is the gate electrode of the first transistor. The gate electrode of the fifth transistor is electrically connected to the first wiring, the first electrode of the sixth transistor is electrically connected to the seventh wiring, The sixth A second electrode of the transistor is electrically connected to a gate electrode of the first transistor, a first electrode of the seventh transistor is electrically connected to the seventh wiring, and the seventh transistor The second electrode of the eighth transistor is electrically connected to the gate electrode of the first transistor, the gate electrode of the seventh transistor is electrically connected to the second wiring, and the first electrode of the eighth transistor An electrode is electrically connected to the seventh wiring, a second electrode of the eighth transistor is electrically connected to a gate electrode of the sixth transistor, and a gate electrode of the eighth transistor is It is electrically connected to the gate electrode of the first transistor.

In the above structure, the first transistor is provided so that the value of W / L of the first transistor is maximized in the ratio W / L of the channel length L to the channel width W of the eighth transistor. be able to. In the above configuration, the value of the first transistor W / L may be 2 to 5 times the value of the fifth transistor W / L. The channel length L of the third transistor may be set larger than the channel length L of the eighth transistor. In addition, a capacitor may be provided between the second electrode of the first transistor and the gate electrode of the first transistor. The first to seventh transistors may be N-channel transistors. In addition, the first to seventh transistors may be formed using amorphous silicon.

A pixel having a liquid crystal element; a first driver circuit; and a second driver circuit, wherein the first driver circuit includes a first transistor, a second transistor, a third transistor, 4 transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor, and the first electrode of the first transistor is electrically connected to the fourth wiring. Connected, a second electrode of the first transistor is electrically connected to a third wiring, a first electrode of the second transistor is electrically connected to a seventh wiring, and the second electrode The second electrode of the transistor is electrically connected to the third wiring, the gate electrode of the second transistor is electrically connected to the fifth wiring, and the first electrode of the third transistor Is electrically connected to the sixth wiring, The second electrode of the third transistor is electrically connected to the gate electrode of the sixth transistor, the gate electrode of the third transistor is electrically connected to the fourth wiring, and the fourth electrode A first electrode of the transistor is electrically connected to the seventh wiring, a second electrode of the fourth transistor is electrically connected to a gate electrode of the sixth transistor, and the fourth electrode A gate electrode of the transistor is electrically connected to the fifth wiring, a first electrode of the fifth transistor is electrically connected to the sixth wiring, and a second electrode of the fifth transistor Is electrically connected to the gate electrode of the first transistor, the gate electrode of the fifth transistor is electrically connected to the first wiring, and the first electrode of the sixth transistor is the seventh electrode. Wiring Electrically connected, the second electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor, and the first electrode of the seventh transistor is electrically connected to the seventh wiring. The second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and the gate electrode of the seventh transistor is electrically connected to the second wiring. The first electrode of the eighth transistor is electrically connected to the seventh wiring, the second electrode of the eighth transistor is electrically connected to the gate electrode of the sixth transistor, The gate electrode of the eighth transistor is electrically connected to the gate electrode of the first transistor, and the second driver circuit includes a ninth transistor, a tenth transistor, and an eleventh transistor. A transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, and the first electrode of the ninth transistor is a twelfth wiring. The second electrode of the ninth transistor is electrically connected to the tenth wiring, and the first electrode of the tenth transistor is electrically connected to the fourteenth wiring. , The second electrode of the tenth transistor is electrically connected to the tenth wiring, the gate electrode of the tenth transistor is electrically connected to the twelfth wiring, The first electrode is electrically connected to the thirteenth wiring, the second electrode of the eleventh transistor is electrically connected to the gate electrode of the fourteenth transistor, and the eleventh transistor is electrically connected. A gate electrode of the transistor is electrically connected to the eleventh wiring, a first electrode of the twelfth transistor is electrically connected to the fourteenth wiring, and a second electrode of the twelfth transistor Is electrically connected to the gate electrode of the fourteenth transistor, the gate electrode of the twelfth transistor is electrically connected to the twelfth wiring, and the first electrode of the thirteenth transistor is connected to the first electrode. 13 is electrically connected, the second electrode of the thirteenth transistor is electrically connected to the gate electrode of the ninth transistor, and the gate electrode of the thirteenth transistor is connected to the eighth wire. Electrically connected, the first electrode of the fourteenth transistor is electrically connected to the fourteenth wiring, and the second electrode of the fourteenth transistor is electrically connected to the ninth transistor. Electrically connected to the gate electrode, the first electrode of the fifteenth transistor is electrically connected to the fourteenth wiring, and the second electrode of the fifteenth transistor is the gate of the ninth transistor; The gate electrode of the fifteenth transistor is electrically connected to the ninth wiring, and the first electrode of the sixteenth transistor is electrically connected to the fourteenth wiring. The second electrode of the sixteenth transistor is electrically connected to the gate electrode of the fourteenth transistor, and the gate electrode of the sixteenth transistor is electrically connected to the gate electrode of the ninth transistor. It is.

In addition, the fourth wiring and the eleventh wiring are electrically connected, the fifth wiring and the twelfth wiring are electrically connected, and the sixth wiring and the thirteenth wiring are electrically connected. A wiring may be electrically connected, and the seventh wiring and the fourteenth wiring may be electrically connected. Further, the fourth wiring and the eleventh wiring are provided by the same wiring, the fifth wiring and the twelfth wiring are provided by the same wiring, the sixth wiring and the thirteenth wiring. The wiring may be the same wiring, and the seventh wiring and the fourteenth wiring may be the same wiring. Further, the third wiring and the tenth wiring may be electrically connected. Further, the third wiring and the tenth wiring may be provided by the same wiring. In addition, among the values of the ratio W / L of the channel length L to the channel width W of the first to eighth transistors, the value of W / L of the first transistor is maximized, and the ninth Among the values of the ratio W / L of the channel length L to the channel width W of the transistor to the sixteenth transistor, the value of W / L of the ninth transistor may be the maximum. The value of the first transistor W / L is set to 2 to 5 times the value of the fifth transistor W / L, and the value of the ninth transistor W / L is set to the twelfth transistor W / L. It is good also as 2-5 times the value of. Further, the channel length L of the third transistor is made larger than the channel length L of the eighth transistor, and the channel length L of the eleventh transistor is made larger than the channel length L of the sixteenth transistor. Also good. In addition, a capacitor is provided between the second electrode of the first transistor and the gate electrode of the first transistor, and the second electrode of the ninth transistor and the gate of the ninth transistor A capacitor may be provided between the electrodes. The first to sixteenth transistors may be N-channel transistors. The first to sixteenth transistors may be provided using amorphous silicon as a semiconductor layer.

The liquid crystal display device described in this embodiment is described in this specification, and thus has the same effects as those of the other embodiments.

10 Wiring 101 Transistor 101 + Vth
101 + α (Vth
102 transistor 103 transistor 103 wiring 104 transistor 105 transistor 106 transistor 107 transistor 108 transistor 109 transistor 110 transistor 121 wiring 122 wiring 123 wiring 124 wiring 124 node 125 wiring 126 wiring 127 wiring 128 wiring 129 wiring 130 wiring 131 wiring 132 wiring 133 wiring 134 wiring 135 wiring 136 wiring 141 node 142 node 151 capacitive element 152 transistor 211 signal 212 signal 213 signal 214 signal 215 signal 216 signal 221 signal 222 signal 223 signal 225 signal 227 signal 228 signal 234 signal 241 potential 242 potential 501 transistor 511 wiring 701 wiring 702 Wiring 703 Wiring 704 Wiring 705 Wiring 7 6 wiring 707 wiring 708 wiring 709 wiring 710 wiring 717 wiring 901 transistor 1011 resistance element 1012 resistance element 1021 transistor 1022 transistor 1023 transistor 1024 transistor 1101 flip flip 1111 wiring 1112 wiring 1113 wiring 1114 wiring 1115 wiring 1116 wiring 1117 wiring 1211 signal 1212 signal 1213 Signal 1216 Signal 1401 Buffer 1701 Signal line driver circuit 1702 Scan line driver circuit 1703 Pixel 1704 Pixel unit 1705 Insulating substrate 1801 Flip flop 1914 Wiring 2221 Signal 2222 Signal 2223 Signal 2225 Signal 2227 Signal 2228 Signal 2401 Flip flop 2402 Flip flip 2411 Wiring 2412 Wiring 2413 Wiring 414 wiring 2415 wiring 2416 wiring 2416 wiring 2417 wiring 2418 wiring 2419 wiring 2420 wiring 2424 wiring 2511 signal 2512 signal 2513 signal 2514 signal 2515 signal 2518 signal 2519 signal 2595 wiring 2702 scanning line driver circuit 2901 conductive layer 2902 conductive layer 2903 conductive layer 2904 conductive layer 2905 Conductive layer 2906 Conductive layer 2907 Conductive layer 2908 Conductive layer 2909 Conductive layer 2910 Conductive layer 2911 Conductive layer 2912 Conductive layer 2913 Conductive layer 2914 Conductive layer 2915 Conductive layer 2916 Conductive layer 2951 Wire 2952 Wire 2953 Wire 2954 Wire 2955 Wire 2957 Wire 2957 Wire 2958 Wiring 2960 Wiring 2981 Semiconductor layer 2982 Semiconductor layer 2983 Semiconductor layer 2984 Semiconductor layer 2985 Semiconductor layer 2986 Conductor layer 2987 Semiconductor layer 2988 Semiconductor layer 4201 Flip-flop 4211 wiring 4212 wiring 4213 wiring 4214 wiring 4215 wiring 4216 wiring 4217 wiring 4218 wiring 4311 signal 4312 signal 4313 signal 4314 signal 4315 signal 4401 transistor 4402 transistor 4403 transistor 4404 transistor 4405 transistor 4406 transistor 4407 Transistor 4408 transistor 4421 wiring 4421 signal 4422 wiring 4422 signal 4423 wiring 4423 signal 4424 wiring 4425 wiring 4425 signal 4426 wiring 4427 wiring 4427 signal 4428 wiring 4428 signal 4429 wiring 4430 wiring 4431 wiring 4432 wiring 4433 wiring 4441 node 4442 node 4442 503 Transistor 4521 Signal 4522 Signal 4525 Signal 4527 Signal 4527 Signal 4528 Signal 4541 Potential 4542 Potential 8000 Buffer 8011 Wiring 8012 Wiring 8100 Buffer 8201 Transistor 8202 Transistor 8211 Wiring 8212 Wiring 8213 Wiring 8214 Wiring 8301 Transistor 8302 Transistor 8303 Transistor 8304 Wiring 8383 Wiring 8312 Wiring 8314 wiring 8315 wiring 8316 wiring 8316 node 8401 transistor 8401 transistor 8403 transistor 8403 transistor 8404 transistor 8411 wiring 8412 wiring 8413 wiring 8414 wiring 8415 wiring 8416 wiring 8417 wiring 8441 node 8501 transistor 8502 transistor 8503 Transistor 8511 wiring 8512 wiring 8513 wiring 8514 wiring 8515 wiring 8516 wiring 8541 node 8601 transistor 8602 transistor 8603 transistor 8604 transistor 8611 wiring 8612 wiring 8613 wiring 8614 wiring 8615 wiring 8616 wiring 8641 node 1902a scanning line driving circuit 1902b scanning line driving circuit 1902b driving circuit 2002a scan line driver circuit 2002b scan line driver circuit 2802a scan line driver circuit 2802b scan line driver circuit 2802b drive circuit 8001a inverter 8001b inverter 8001c inverter 8002a inverter 8002b inverter 8002c inverter 8003a inverter 8003b inverter 8003c inverter

Claims (9)

Having a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; And
One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor;
One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor;
A gate of the fourth transistor is electrically connected to a gate of the second transistor;
One of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor;
One of a source and a drain of the sixth transistor is electrically connected to a gate of the first transistor;
A gate of the sixth transistor is electrically connected to one of a source and a drain of the third transistor;
One of a source and a drain of the seventh transistor is electrically connected to a gate of the first transistor;
One of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the third transistor;
A gate of the eighth transistor is electrically connected to a gate of the first transistor;
The other of the source and the drain of the second transistor is electrically connected to the first wiring;
The other of the source and the drain of the fourth transistor is electrically connected to the first wiring;
The other of the source and the drain of the sixth transistor is electrically connected to the first wiring;
The other of the source and the drain of the seventh transistor is electrically connected to the first wiring;
The other of the source and the drain of the eighth transistor is electrically connected to the first wiring;
The other of the source and the drain of the first transistor is electrically connected to a second wiring;
A gate of the third transistor is electrically connected to the second wiring;
The other of the source and the drain of the fifth transistor is electrically connected to a third wiring;
A gate of the second transistor is electrically connected to a fourth wiring;
The semiconductor device is characterized in that the gate of the seventh transistor is electrically connected to a fifth wiring. In claim 1,
The semiconductor device is characterized in that the gate of the fifth transistor is electrically connected to the third wiring. In claim 1,
The semiconductor device is characterized in that the other of the source and the drain of the third transistor is electrically connected to the third wiring. In any one of Claims 1 thru | or 3,
The semiconductor device, wherein the gate of the third transistor is directly connected to the second wiring. In any one of Claims 1 thru | or 4,
The first wiring has a function of supplying a first potential;
The second wiring has a function of supplying a first clock signal;
The third wiring has a function of supplying a start pulse or a second potential;
The fourth wiring has a function of supplying a second clock signal;
The semiconductor device, wherein the fifth wiring has a function of supplying a reset pulse. In any one of Claims 1 thru | or 5,
The channel region of the first to eighth transistors includes an oxide semiconductor. In claim 6,
The semiconductor device, wherein the oxide semiconductor contains In and Zn. In claim 6,
The semiconductor device, wherein the oxide semiconductor includes InGaZnO. In claim 6,
The semiconductor device, wherein the oxide semiconductor includes a-InGaZnO.

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