JP2012099015A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a boot loading time of a nonvolatile semiconductor memory device used for a system which requires boot loading.SOLUTION: The nonvolatile semiconductor memory device includes a storage area 10a which stores boot data; a first RAM (boot RAM 21) which stores the boot data; a second RAM (buffer RAM 22 or buffer RAM 23) which stores the remaining data of the boot data when the boot data exceeds the storage capacity of the first RAM; a nonvolatile area 40 which stores flag information indicative of whether the second RAM is performed in storing operation and address information indicative of a location of the boot data stored in the second RAM in the first storage area; and a control part 30 which transfers the boot data from the first storage area to the first RAM, and then transfers the remaining boot data of the boot data from the first storage area to the second RAM based upon the flag information and address information.

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device used in a system that requires bootloading.

  An electrically erasable and rewritable nonvolatile semiconductor memory device (EEPROM) such as a flash memory constitutes a system together with a processor (CPU) and a main memory (for example, DRAM). In this system, system boot data (boot data) stored in the flash memory is used when the system is started up (powered up).

  For example, Patent Documents 1 and 2 listed below disclose a flash memory that outputs boot data to a system and a technique related to a flash memory access method. Further, the above document discloses a technique for transferring boot data from a non-volatile storage area of a non-volatile storage device to a data register or a volatile memory provided inside the device in order to output the boot data to the outside. Yes.

Special table 2008-530683 gazette JP 2006-221807 A

  In the nonvolatile semiconductor memory device related to the present invention, there is a problem in transferring boot data stored in the nonvolatile memory area to a data register or volatile memory provided in the device. Hereinafter, problems of the related nonvolatile semiconductor memory device will be described with reference to FIG. 3 which is a related diagram created as a problem by the inventor of the present application.

FIG. 3 is a schematic block diagram of a nonvolatile semiconductor memory device 300 related to the present invention.
The nonvolatile semiconductor memory device 300 includes an electrically erasable and rewritable storage area (NAND Flash Core, hereinafter referred to as a flash core 10), an SRAM unit 20 that is an interface to a system including the nonvolatile semiconductor memory device 300, control The unit 30 is provided.
The flash core 10 (first storage area) stores boot data and a system operating system (OS). The boot data is data including a program used for transferring the OS to the main memory at the time of starting the system, an address of the transfer destination of the OS, and the like. Since the boot data has different processing at the time of booting depending on the user who uses the system, the capacity to be used varies depending on the user. Therefore, when the flash core 10 requires a storage area 10a having a predetermined storage capacity (a storage area storing the boot data BL1) and a storage capacity larger than the storage capacity of the storage area 10a, A storage area for storing boot data (boot data exceeding the storage capacity of the storage area 10a) (not shown in FIG. 3, but areas for storing boot data BL2 and BL3, respectively).

The SRAM unit 20 includes a boot RAM 21 (BootRAM), a buffer RAM 22 (BufferRAM1), and a buffer RAM23 (BufferRAM2).
The boot RAM 21 (first RAM) is a storage area for storing boot data BL1 transferred from the flash core 10, and the buffer RAM 22 and the buffer RAM 23 (second RAM) are boot data transferred from the flash core 10. This is a storage area for storing BL2 and BL3.

The control unit 30 includes a load control 31 (Load Control), an address register 32, and an address control 33.
The load control 31 decodes a command input from the CPU and controls the timing of a data read operation from the memory cell of the flash core 10 in a normal operation after the system is started. In addition, the load control 31 detects the rise of the power supply voltage level at the time of system startup, and if it reaches a predetermined voltage, the word line driver, sense amplifier, column decoder, etc. included in the flash core 10 (not shown in FIG. 4). The operation timing of the circuit related to the read operation (shown) is controlled, and the boot data BL1 is transferred to the boot RAM 21 without any command input from the CPU.

The address register 32 captures and stores address information from the CPU in synchronization with a command input to the load control 31 in a normal operation after the system is started. This address information is data indicating the position of the memory cell in the flash core 10, and corresponding to the memory cell block constituting the flash core 10, block address information FBA (Flash Block Address), page address information FPA (Flash Page) Address).
The flash core 10 includes a plurality of memory cell blocks (for example, 1024 Blocks and 2048 Blocks), and the position is indicated by block address information FBA. The memory cell block is a basic unit of data erasing operation. One memory cell block includes a plurality of pages (for example, 16 Pages, 32 Pages, or 64 Pages), and the position is indicated by page address information FPA. A page is the basic unit of data write and read operations.
The address control 33 is timing-controlled by the load control 31 and outputs the address information taken into the address register 32 to the flash core 10. In the read operation, the load control 31 reads data from the flash core in units of pages determined by the block address information FBA and page address information FPA, and transfers the data to the SRAM unit 20.

  As described above, the transfer of the boot data BL1 to the boot RAM 21 is automatically executed (without inputting a command and an address from the CPU) when the system is activated (with power-up of the system). That is, for example, 0 is stored as the block address information FBA and page address information FPA as defaults in the address register 32, and the load control 31 is stored in the boot area stored in the storage area 10a (address 0). Data is read and stored in the boot RAM 21.

  The system is activated as follows using the boot data BL1. When the boot data is configured by boot data BL1 (when boot data BL2 and BL3 are not stored), the CPU waits for a predetermined time from completion of the transfer of boot data BL1 (a transfer completion signal is sent to the nonvolatile semiconductor memory device 300). After that, the transfer command and the address information are input to the load control 31 and the address register 32, respectively. The boot RAM 21 is controlled by the load control 31 and executes the boot data BL1 stored in the boot RAM 21. Further, the buffer RAM 22 is controlled by the load control 31, and based on the execution result of the boot data BL1 (for example, address information of the area where the OS is stored, address information in the system memory to which the OS is transferred, etc.) The OS stored in the flash core 10 is transferred to a specific area of the main memory that constitutes. Thereby, the CPU executes the OS transferred to the main memory and starts up the system.

  Further, when booting the system, when only the boot data BL1 stored in the storage area 10a is insufficient and boot data having a capacity larger than the boot data BL1 is necessary, the boot data BL2 to the boot buffer RAM 22 and the buffer RAM 23 and The load (transfer) of BL3 is executed by inputting an instruction command from the CPU constituting the system after transferring the boot data BL1 to the SRAM unit 20. That is, the load control 31 reads the remaining boot data BL2 from the area for storing the boot data BL2 of the flash core 10 based on the transfer command input from the CPU and the address information input to the address register 32, and the buffer RAM 22 Forward to. Further, as necessary (when boot data BL3 is stored), the load control 31 stores the boot data BL3 of the flash core 10 based on the input transfer command and the address information input to the address register 32. The remaining boot data BL3 is read from the area to be transferred and transferred to the buffer RAM 23.

  For example, when the boot data is composed of boot data BL1 and boot data BL2 (when boot data BL3 is not stored), the system is started as follows. The buffer RAM 22 stores boot data BL2 transferred from the flash core 10 under the control of the load control 31 when a transfer command and address information are input to the load control 31 and the address register 32, respectively. The boot RAM 21 is controlled by the load control 31 and executes the boot data BL1 stored in the boot RAM 21. Further, the buffer RAM 22 is controlled by the load control 31 and transfers the boot data BL2 to a specific area of the main memory (DARM) constituting the system based on the execution result of the boot data BL1.

Similarly, when a transfer command and address information are input to the load control 31 and the address register 32, respectively, the buffer RAM 23 is controlled by the load control 31 and the OS stored in the flash core 10 based on the boot data BL2. Is transferred to the main memory.
Thus, the CPU executes the boot data BL2 transferred to the main memory (DRAM), initializes the system based on the execution result, and subsequently executes the OS transferred to the main memory to start the system. .

  As described above, in the related nonvolatile semiconductor memory device 300, when the system including the self-volatile semiconductor memory device is started, the boot data exceeding the storage capacity of the boot RAM 21 (first RAM) is transferred to the buffer RAM 22 or the buffer RAM 23 ( In this case, there is the following problem. That is, as described above, the CPU receives a signal indicating completion of transfer of the boot data BL1 to the boot RAM 21 from the nonvolatile semiconductor memory device 300, and then receives the address information and the flash core 10 from the buffer RAM 22 or the buffer RAM 23. It is necessary to issue a transfer command instructing data transfer to. After issuing this transfer command, the boot core BL2 or the boot data BL3 is transferred from the flash core 10 to the buffer RAM 22 or the buffer RAM 23. For this reason, there is a problem that the startup (power-up time) of the system including the nonvolatile semiconductor memory device 300 becomes long.

  The present invention includes a first storage area that is configured of a nonvolatile memory cell and stores boot data for starting a system including a self-volatile semiconductor memory device, and a system including the self-volatile semiconductor memory device. When the boot data exceeds a preset storage capacity when the system including the first RAM for storing the boot data and the self-volatile semiconductor memory device is started, the remaining data of the boot data is stored. And a first RAM of the boot data stored in the second RAM, the flag information indicating whether or not the second RAM is to perform a storing operation, and the second RAM. Address information indicating a position in the storage area, a second storage area storing the address information, and a system including a self-volatile semiconductor memory device, Data is transferred from the first storage area to the first RAM, and then the remaining boot data of the boot data is transferred from the first storage area to the first RAM based on the flag information and the address information. And a control unit that transfers the data to the RAM.

  Thus, even when boot data is stored from the first storage area to the second RAM at the time of starting the system including the self-volatile semiconductor memory device, the address information is input from the outside (CPU) and the second It is not necessary to issue a load command for commanding data transfer from one storage area to the second RAM, and the start-up time (power-up time) of the system including the self-volatile semiconductor memory device can be shortened.

  In the non-volatile semiconductor memory device, the control unit stores the first data in the first storage area that is necessary following boot load when the system is started up, when the boot data does not exceed the preset storage capacity. The processed data is transferred from the first storage area to the second RAM based on the flag information and the address information.

  As a result, data (OS data, etc.) required following boot load when the system is started can be automatically transferred to the second RAM, and the OS data can be transferred from the outside (CPU) to the flash core 10. It is unnecessary to input address information indicating the position where the data is stored and to issue a load command for commanding data transfer from the first storage area (flash core 10) to the second RAM (buffer RAM 22 or buffer RAM 23). Become. Therefore, the startup time (power-up time) of the system including the self-volatile semiconductor memory device can be further shortened.

  In the nonvolatile semiconductor memory device, the preset storage capacity is a storage capacity of the first RAM.

  Thus, with the storage capacity of the first RAM as a boundary condition, the remaining boot data out of the boot data exceeding the storage capacity of the first RAM or the data required following the boot load is transferred to the second RAM. Can be transferred to.

  In the nonvolatile semiconductor memory device, the second storage area is a partial area of the first storage area that stores boot data stored in the first RAM.

  As a result, a layout area for realizing the second storage area on the semiconductor chip becomes unnecessary, and the cost can be reduced by reducing the chip size.

  In addition, the present invention is characterized in that data required following boot load when a system including a self-volatile semiconductor memory device is started is distributed and stored in each first storage area.

  As a result, in a plurality of nonvolatile semiconductor memory devices, the storage area of the second RAM increases in accordance with the number of memory devices, so that the data (after the boot load at the time of starting the system stored in a distributed manner) ( OS data, etc.) can be automatically transferred to the second RAM. Therefore, at the time of starting the system, it is possible to efficiently start up the system by using the interleave reading function to read out OS data or the like already stored in the second RAM.

The nonvolatile semiconductor memory device according to the present invention includes flag information indicating whether or not to perform a storing operation in the buffer RAM, boot data transferred to the buffer RAM, or data (OS required for boot loading when the system is started up). A non-volatile memory (second storage area) for storing address information indicating the position of the data in the flash core. The control logic (control unit) automatically (without input of address information and transfer command) automatically stores boot data, OS data, etc. in the buffer RAM according to the flag information and address information stored in the second storage area. Forward to.
As a result, boot data or OS data that can be automatically stored in the SRAM section can be expanded to a capacity including the capacity of the first RAM and the capacity of the second RAM (variation of the automatic load area). Since the boot data or the OS data for a predetermined capacity can be transferred to the second RAM, the system power-up time can be further shortened.
Further, by setting the flag information indicating whether or not to use the automatic load area function in the second storage area in advance, the user can determine whether or not the capacity is to be expanded to the capacity of the second RAM. Can be determined.
Thus, design flexibility can be provided to a user (system designer, for example, a system designer of a mobile phone device).

1 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory device 100 of the present invention. 1 is a block diagram showing an overall configuration of a semiconductor memory device 200 in which a nonvolatile semiconductor memory device 100 has a multichip configuration. 2 is a block diagram showing an overall configuration of a related nonvolatile semiconductor memory device 300. FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram showing a nonvolatile semiconductor memory device 100 according to an embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 3 used for the description of the related nonvolatile semiconductor memory device 300 are denoted by the same reference numerals, and the description of the same parts will be omitted as appropriate.

  The nonvolatile semiconductor memory device 100 is different from the nonvolatile semiconductor memory device 300 in that a nonvolatile region 40 is provided. The nonvolatile area 40 is composed of electrically erasable and erasable nonvolatile memory cells, and flag information (load enable flag 1 and load enable flag 2 in FIG. 1) indicating whether or not the buffer RAM 22 and the buffer RAM 23 are to perform a storage operation. And address information (block address information FBA, page address information FPA) indicating the position of the boot data in the flash core 10 are stored.

The nonvolatile area 40 is configured such that these flag information and address information can be written and erased from the outside of the nonvolatile semiconductor memory device 100. These flag information and address information are programmed in the nonvolatile area 40 by a tester such as a tester by a semiconductor vendor or a system designer.
For example, when the capacity of the boot data exceeds the storage capacity of the boot RAM 21 (first RAM), that is, when the boot data is composed of boot data BL1, boot data BL2, and boot data BL3, flag information and address information Is the following information.
That is, the address information indicating the position of the area where the boot data BL2 (not shown) in the flash core 10 stored in the buffer RAM 22 is stored is FBA / FPA Set1, and the boot data in the flash core 10 stored in the buffer RAM 23 Address information indicating the position of an area in which BL3 (not shown) is stored is FBA / FPA Set2.

The load control 31 in the nonvolatile semiconductor memory device 100 is similar to the nonvolatile semiconductor memory device 300 at the time of system startup, based on the FBA / FPA stored in the address register 32 as a default, word line, sense amplifier, column The decoder or the like is controlled to read the boot data BL1 in the storage area 10a (address 0), transfer it to the boot RAM 21, and store the boot data BL1.
Further, after storing the boot data BL1 in the boot RAM 21, the load control 31 subsequently determines the logical level (0 or 1) of the Load Enable Flag 1 in the nonvolatile area 40. The load control 31 transfers the address information (FBA / FPA Set1) stored in the non-volatile storage area from the non-volatile area 40 to the address register 32 according to the determination result (for example, if it is determined as logic 1). Further, the load control 31 controls the address control 33 to control the timing of the address information fetched into the address register 32 and output it to the flash core 10.

That is, the load control 31 controls the timing of circuit operations such as a word line, a sense amplifier, and a column decoder based on the address information (FBA / FPA Set1) stored in the nonvolatile area 40. In this way, the load control 31 reads the boot data BL2 in the flash core 10, transfers it to the buffer RAM 22, and stores the boot data BL2.
When the determination by the load control 31 is determined to be logic 0, the transfer of the boot data to the SRAM unit ends with the transfer of the boot data BL1.

  Similarly, after storing the boot data BL2 in the buffer RAM 22, the load control 31 subsequently determines the logic level of the Load Enable Flag2 in the nonvolatile area 40. The load control 31 transfers the address information (FBA / FPA Set2) stored in the non-volatile storage area from the non-volatile area 40 to the address register 32 according to the determination result (for example, if it is determined as logic 1). Further, the load control 31 controls the address control 33 to control the timing of the address information fetched into the address register 32 and output it to the flash core 10.

That is, the load control 31 controls the timing of circuit operations of the word line, sense amplifier, column decoder, and the like based on the address information (FBA / FPA Set2) stored in the nonvolatile area 40. In this way, the load control 31 reads the boot data BL3 in the flash core 10, transfers it to the buffer RAM 23, and stores the boot data BL3.
When the determination by the load control 31 is determined to be logic 0, the transfer of boot data to the SRAM unit ends with the transfer of the boot data BL1 and BL2.

  As described above, the nonvolatile semiconductor memory device (nonvolatile semiconductor memory device 100) according to the present embodiment is composed of nonvolatile memory cells, and stores boot data for starting a system including the self-volatile semiconductor memory device. A first storage area (flash core 10); and a first RAM (boot RAM 21) for storing the boot data (boot data BL1) when a system including the self-volatile semiconductor storage device is started. In addition, the nonvolatile semiconductor memory device 100 may include one of the boot data when the boot data exceeds the storage capacity of the first RAM (for example,> 1 kB) when a system including the self-volatile semiconductor memory device is started. And a second RAM (buffer RAM 22 or buffer RAM 23) for storing the remaining data (data exceeding 1 kB). The nonvolatile semiconductor memory device 100 includes nonvolatile memory cells, and includes flag information (Load Enable Flag 1 or Load Enable Flag 2) indicating whether or not to cause the second RAM to perform a storage operation, and the second RAM. A second storage area (nonvolatile area 40) storing address information (FBA / FPA Set1 or FBA / FPA Set2) indicating the position of the boot data stored in the RAM in the first storage area; Is provided. In addition, the nonvolatile semiconductor memory device 100 transfers the boot data from the first storage area to the first RAM when a system including the self-volatile semiconductor memory device is started up. Subsequently, the flag information and And a control unit (control unit 30) that transfers the remaining boot data of the boot data from the first storage area to the second RAM based on the address information.

  Thereby, even when boot data exceeding the storage capacity of the first RAM is stored in the second RAM when the system including the self-volatile semiconductor memory device is started, the external (CPU) From the first storage area (flash core 10) to the second RAM (buffer RAM 22 or buffer RAM 23) issuance of a load command is no longer required. It is possible to shorten the startup time (power-up time) of the system including it.

When the boot data capacity does not exceed the storage capacity of the boot RAM 21 (first RAM), that is, when the boot data is composed only of the boot data BL1, the flag information and the address information are the following information: Become.
That is, FBA / FPA Set1 is address information indicating the position in the flash core 10 in which data stored in the buffer RAM 22 and necessary data (for example, OS data) following boot load is stored when the system is started. . Further, the address information indicating the position in the flash core 10 that is stored in the buffer RAM 23 and stores the remaining data required after the boot load when the system is started is FBA / FPA Set2.
The remaining data is OS data stored in the flash core 10 when the OS data exceeds the storage capacity of the buffer RAM 22, for example. Of course, when the OS data does not exceed the storage capacity of the buffer RAM 22, it is not necessary to set the logic of the Load Enable Flag 2 to 0 in advance in the nonvolatile area 40 and store the address information in the FBA / FPA Set 2. Alternatively, the logic of Load Enable Flag 2 may be set to 1 in advance, and address information of data other than OS data (for example, file system data read after system startup) may be stored in FBA / FPA Set2. .

When the flag information and the address information are set as described above, the control unit (control unit 30) stores the first storage area (flash core 10) at the time of system startup, similarly to the above-described automatic transfer of boot data. Transfers necessary data (OS data, etc.) following boot load when the stored system is started up from the first storage area to the second RAM (buffer RAM 22 or buffer RAM 23) based on flag information and address information. To do.
Thus, the OS data and the like can be automatically transferred to the second RAM, the address information indicating the location where the OS data and the like are stored in the flash core 10 can be input from the outside (CPU), and the second It is no longer necessary to issue a load command for data transfer from one storage area (flash core 10) to the second RAM (buffer RAM 22 or buffer RAM 23), and the startup time (power-up) of the system including the self-volatile semiconductor memory device is eliminated. Time) can be further shortened.

As described above, the nonvolatile semiconductor memory device of the present invention has the flag information indicating whether or not the buffer RAM (buffer RAM 22 or buffer RAM 23) performs the storage operation, the boot data transferred to the buffer RAM, or the system startup. A non-volatile memory (second storage area) is provided for storing address information indicating the position in the flash core of data (OS data or the like) that is sometimes required following boot load. Further, the control logic (control unit) automatically (without input of address information and transfer command) boot data exceeding the storage capacity of the boot RAM according to flag information and address information stored in the second storage area, or OS data and the like are transferred to the buffer RAM.
As a result, the capacity of boot data that can be automatically stored in the SRAM unit can be expanded to a capacity including the capacity of the second RAM in addition to the capacity of the first RAM (variation of the automatic load area). Even when the storage capacity of the system is not sufficient, the system startup time (power-up time) can be shortened. In addition, when the storage capacity of the first RAM is sufficient, data (OS data and the like) necessary following boot load can be transferred to the second RAM when the system is started up. Further shortening is possible.
Further, by setting the flag information indicating whether or not to use the automatic load area function in the second storage area in advance, the user can determine whether or not the capacity is to be expanded to the capacity of the second RAM. Can be determined.
Thus, design flexibility can be provided to a user (system designer, for example, a system designer of a mobile phone device).

  The nonvolatile area 40 (second storage area) is a storage area 10a for storing boot data BL1 (part of the first storage area for storing boot data stored in the first RAM). It may be. In such a configuration, the load control 31 transfers the data (flag information and address information) stored in, for example, the last preset area of the boot data BL1 after transferring the boot data BL1 to the boot RAM 21. The circuit configuration is referred to. Then, the load control 31 refers to the data (flag information and address information) in the preset area of the boot data BL1, and as described above, the boot data BL2 or BL3, or the boot load when the system is started Following this, it is determined whether or not necessary data (OS data or the like) is to be transferred to the SRAM unit, and is transferred.

  As a result, a layout area for realizing the nonvolatile area 40 (second storage area) in the semiconductor chip is not necessary, and cost reduction can be realized by reducing the chip size.

  Also, as shown in FIG. 2, when realizing a multi-chip nonvolatile semiconductor memory device 200 having a plurality (N + 1) of nonvolatile semiconductor memory devices 100, it is necessary to follow the boot load when the system is started. Data (OS data or the like) may be distributed and stored in the flash cores 10-1 to 10- (N + 1) (in the respective first storage areas). By adopting such a configuration, when the capacity of the boot data does not exceed the storage capacity of the boot RAM (first RAM), the nonvolatile semiconductor memory devices 100-1 to 100- (N + 1) are activated when the system is started. In each, the OS data and the like can be transferred and stored in each of the SRAM units 20-1 to 20-(N + 1) by the flag information and the address information stored in the nonvolatile area 40.

  As a result, in a plurality of nonvolatile semiconductor memory devices, when the boot data does not exceed the storage capacity of the first RAM, the storage area of the second RAM increases according to the number of the storage devices, thereby being distributed. Data (OS data, etc.) required following boot load when the stored system is started can be automatically transferred to the second RAM. Therefore, at the time of starting the system, it is possible to efficiently start up the system by using the interleave reading function to read out OS data or the like already stored in the second RAM.

As mentioned above, although the invention made | formed by this inventor was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to embodiment demonstrated, and can be variously changed in the range which does not deviate from the summary. .
For example, in the description of the embodiment, the boot data BL2 and BL3 (remaining data of the boot data) stored in the flash core 10 (first storage area) or the boot load is required when the system is started. In the above description, the data (OS data or the like) is transferred to the buffer RAM 22 or the buffer RAM 23 (second RAM) when the storage capacity of the boot RAM 21 (first RAM) is exceeded or not. However, the boundary condition is not limited to the storage capacity of the first RAM, but may be any storage capacity set in advance. For example, address information (block address and page address) indicating an area where the boot data BL1 is stored in the nonvolatile area 40 (second storage area) or other nonvolatile storage area (including the flash core 10). The control unit 30 (control unit) may automatically transfer boot data BL1 having a capacity set in advance based on the address information to the boot RAM 21 when the power is turned on.

  DESCRIPTION OF SYMBOLS 100, 200, 300 ... Nonvolatile semiconductor memory device, 10 ... Flash core, 10a ... Memory area, 20 ... SRAM part, 30 ... Control part, 31 ... Load control, 32 ... Address register, 33 ... Address control, 40 ... Nonvolatile Sex region, 21, 22, 23 ... RAM

Claims (5)

A first storage area configured by a nonvolatile memory cell and storing boot data for starting a system including the self-volatile semiconductor storage device;
A first RAM for storing the boot data when a system including the self-volatile semiconductor memory device is started;
A second RAM for storing the remaining data of the boot data when the boot data exceeds a preset storage capacity at the time of starting a system including the self-volatile semiconductor memory device;
Flag information indicating whether or not to cause the second RAM to perform a storage operation and a position of the boot data stored in the second RAM in the first storage area, which is configured by a nonvolatile memory cell A second storage area storing address information;
When booting a system including a self-volatile semiconductor memory device, the boot data is transferred from the first storage area to the first RAM, and then the boot data is based on the flag information and the address information. A controller for transferring the remaining boot data from the first storage area to the second RAM;
A non-volatile semiconductor memory device comprising:   The control unit, when the boot data does not exceed the preset storage capacity, the data stored in the first storage area that is necessary following the boot load at the time of system startup, the flag information and the The nonvolatile semiconductor memory device according to claim 1, wherein transfer is performed from the first storage area to the second RAM based on address information.   3. The nonvolatile semiconductor memory device according to claim 1, wherein the preset storage capacity is a storage capacity of the first RAM.   The said 2nd storage area is a partial area | region of the 1st storage area which memorize | stored the boot data memorize | stored in said 1st RAM, Either of Claim 1 to 3 characterized by the above-mentioned. The nonvolatile semiconductor memory device described.   A plurality of the nonvolatile semiconductor memory devices according to any one of claims 2 to 4, wherein data required following boot load when a system including the self-volatile semiconductor memory device is started up is A non-volatile semiconductor memory device, wherein the non-volatile semiconductor memory device is distributed and stored in a memory area.

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