JP2012098985A - Direct memory access control device, direct memory access control system, program, image processing device and compound machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent malfunction continuation by memory access to a transfer source and a transfer area while DMA is running.SOLUTION: A DMA controller performing transfer control of DMA and memory access using the same system bus comprises: registers 22-25 in which address range of a transfer source in DMA and address range of a transfer destination in DMA are stored; and an unauthorized access detection circuit 1 which outputs an unauthorized access alarm signal showing that data in memory access is an unauthorized access, if a designated address is in the address range of the transfer source of DMA or in the address range of the transfer destination of DMA when the address for data transfer in the memory access is designated on the system bus.

Description

  The present invention relates to a technology of a direct memory access control device, a direct memory access control system, a program, an image processing device, and a multifunction peripheral used for direct memory access.

Conventionally, in the operation of direct memory access (hereinafter referred to as DMA), the system bus gives the bus right to the DMA controller during DMA execution. Therefore, other peripheral circuits including the processor are disconnected from the system bus and cannot be accessed.
However, in recent years, in order to improve system performance, low-speed DMA operations, such as DMA operations for peripheral I / O (Input / Output) devices, have a higher priority even during the period until the DMA end address is reached. In response to a bus access request from a high device, it has become common to pass the bus right from the DMA controller to another device.
Therefore, even during DMA activation, access to the system bus by a processor or another DMA controller may occur.

  In Patent Document 1, writing to the main storage device by DMA write (Write) is overtaken by reading from the CPU (processor) by the following method, and illegal data is read or data is lost. An access control apparatus for preventing the above is disclosed. That is, in the access control device described in Patent Document 1, in the image processing by DMA, the DMA control device (DMA controller) finishes writing the last data, and this write data is retained in the buffer in the memory control device. . Then, if the access to the memory area occurs before the data writing to the memory is completely completed, the access control device, the memory address at which the memory write request is generated by the DMA control device, The memory address to which the access request by the CPU is issued is compared. If the memory addresses match as a result of the comparison, the access control device restricts the access by the CPU until the data writing staying in the buffer in the memory control device is completed.

JP-A-6-231032

  However, in the access control described in Patent Document 1, DMA is stopped because only the access request address from the CPU (processor) is compared with the data write request address stored in the buffer in the access control device. There is a problem that there is no effect on unauthorized access to the DMA transfer destination area before the data transfer or unauthorized access to the DMA transfer source area.

  The present invention has been made to solve such a problem, and an object of the present invention is to make it possible to prevent malfunctions due to memory access to a transfer source and a transfer area during DMA execution.

  In order to solve the above-described problems, the present invention provides a DMA control device that performs transfer control of DMA and memory access using the same system bus, and includes a transfer source address range in the DMA and transfer in the DMA When the storage means for storing the previous address range and the address for performing data transfer in the memory access are designated on the system bus, the designated address is the address range of the DMA transfer source. Or unauthorized access detection means for outputting an unauthorized access warning signal indicating that the data in the memory access is unauthorized access when the address is within the address range of the DMA transfer destination. To do.

  According to the present invention, it is possible to prevent continuation of malfunction due to memory access to a transfer source and transfer area during DMA execution.

It is a figure which shows the structural example of the unauthorized access detection circuit which concerns on 1st Embodiment. It is a figure which shows the structural example of the image processing apparatus which concerns on 1st Embodiment. It is a figure which shows the structural example of the DMA controller which concerns on 1st Embodiment. It is a flowchart which shows the flow of a process in a DMA controller (the 1). It is a flowchart which shows the flow of a process in a DMA controller (the 2). It is a flowchart which shows the flow of the unauthorized access detection process which concerns on 1st Embodiment. It is a figure which shows the structural example of the DMA control system which concerns on 2nd Embodiment. It is a flowchart which shows the flow of a process in the DMA control system which concerns on 2nd Embodiment. It is a flowchart which shows the flow of the interruption process which concerns on 2nd Embodiment. FIG. 3 is a schematic perspective view of a multi-function peripheral equipped with an image processing apparatus and a DMA control system according to the first and second embodiments.

  Embodiments of a DMA control device and a DMA control system according to the present invention will be described below with reference to the drawings. Note that it is assumed that the DMA by one DMA controller (direct memory access) and the DMA by the other DMA controller (memory access) are different in speed, and both DMAs are executed at the same time. The DMA by the other DMA controller is not limited to DMA, but may be general memory access.

<< First Embodiment >>
First, a first embodiment according to the present invention will be described with reference to FIGS. It is assumed that the DMA in this embodiment is intended for image data sent from a scanner, image data sent from a host interface, image data sent from a PC (Personal Computer), and the like. ing.

(Configuration of unauthorized access detection circuit)
FIG. 1 is a diagram illustrating a configuration example of an unauthorized access detection circuit according to the first embodiment.
The unauthorized access detection circuit (unauthorized access detection means) 1 is included in the DMA controller 2 shown in FIGS.
The unauthorized access detection circuit 1 includes four address comparators 11 (11a to 11d), a transfer source AND gate 12, a transfer destination AND gate 13, and an OR gate 14.
The address comparator 11a has a function of comparing the transfer source start address of the DMA transfer source start address register 22 included in the DMA controller 2 with the bus address sent from the address bus 81 (FIG. 3).
The address comparator 11b has a function of comparing the transfer source end address of the DMA transfer source end address register 23 included in the DMA controller 2 with the bus address sent from the address bus 81 (FIG. 3).
The address comparator 11c has a function of comparing the transfer destination start address of the DMA transfer destination start address register 24 included in the DMA controller 2 with the bus address sent from the address bus 81 (FIG. 3).
The address comparator 11d has a function of comparing the transfer destination end address of the DMA transfer destination end address register 25 included in the DMA controller 2 with the bus address sent from the address bus 81 (FIG. 3).
The DMA activation signal 53 is a signal that becomes “P”, that is, “1” when the own DMA controller 2 is DMA activation. The DMA read access signal 51 is a signal that becomes “N”, that is, “0” when reading by the own DMA controller 2 occurs. The DMA write access signal 52 is a signal that becomes “N”, that is, “0” when writing by its own DMA controller 2 occurs.

The transfer source AND gate 12 receives a DMA read access signal 51 input from a DMA transfer source address register 26 described later in FIG. 3 and a DMA write access signal input from a DMA transfer destination address register 27 described later in FIG. 52, a DMA activation signal 53 input from the DMA controller control register 21 described later in FIG. 3, a comparison result signal from the address comparator 11a, and a comparison result signal from the address comparator 11b. It has a function of outputting a logical product.
The transfer destination AND gate 13 also receives a DMA read access signal 51 input from a DMA transfer source address register 26 described later in FIG. 3 and a DMA write input from a DMA transfer destination address register 27 described later in FIG. The access signal 52, the DMA activation signal 53 input from the DMA controller control register 21 described later in FIG. 3, the comparison result signal from the address comparator 11c, and the comparison result signal from the address comparator 11d It has a function of outputting a logical product of signals.

The OR gate 14 has a function of outputting a logical sum of an output from the transfer source AND gate 12 and an output from the transfer destination AND gate 13 as an unauthorized access warning signal.
Details of the operation of the unauthorized access detection circuit 1 will be described later with reference to FIG.

(Configuration of image processing apparatus)
FIG. 2 is a diagram illustrating a configuration example of the image processing apparatus according to the first embodiment.
The image processing apparatus 100 includes a DMA controller 2 (DMA controller A2a, DMA controller B2b), a processor 3 (processor A3a, processor B3b), and an I / O device 4 (I / O device A4a, I / O device B4b). The main storage device controller 5 controls the main storage device 6 and a display device (display means) 7 such as a display.
Each DMA controller 2, processor 3, I / O device 4, main storage device controller 5, and display device 7 are connected to each other via a system bus 8.
The DMA controller 2 outputs a DMA read / write access signal, an unauthorized access warning signal, and the like to the system bus 8.
In FIG. 2, two DMA controllers 2 and two I / O devices 4 are shown. However, the present invention is not limited to this, and there may be three or more. One processor 3 may be provided.
Note that DMA performed by the DMA controller A2a is direct memory access, and DMA performed by the DMA controller B2b is memory access.

(Configuration of DMA controller)
FIG. 3 is a diagram illustrating a configuration example of the DMA controller according to the first embodiment.
The DMA controller (DMA controller) 2 includes an unauthorized access detection circuit 1, a DMA controller control register 21, a DMA transfer source start address register (storage means) 22, a DMA transfer source end address register (storage means) 23, and a DMA transfer destination start. It has an address register (storage means) 24, a DMA transfer destination end address register (storage means) 25, a DMA transfer source address register 26, a DMA transfer destination address register 27, and a DMA data buffer 28.

  The system bus 8 includes a data bus 82 for transferring data and an address bus 81 for transferring the address of the data transfer source or transfer destination. A bus address (address indicating a data write / read location) is input from the address bus 81, and an unauthorized access warning signal is output from the unauthorized access detection circuit 1 to the data bus 82.

The unauthorized access detection circuit 1 has been described with reference to FIG.
The DMA controller control register 21 stores control parameters for overall control of the DMA controller 2. The control parameter particularly controls the start / stop from the idle state. During the start of the DMA controller 2, the DMA controller 2 outputs the DMA start signal 53 (actually “1” signal) to the unauthorized access detection circuit 1. During stop (idle state), “0” is output.

The DMA transfer source start address register 22 stores a DMA transfer source start address which is a start (start) address in the address range of a data transfer source (for example, the I / O device 4) in the DMA. The unauthorized access detection circuit 1 is configured to capture the transfer source start address.
The DMA transfer source end address register 23 stores the DMA transfer source end address which is the end (last) address in the address range of the data transfer source in the DMA, and this DMA transfer source end address is detected as unauthorized access. The circuit 1 is configured to capture.

The DMA transfer destination start address register 24 stores a DMA transfer destination start address which is a start (start) address in the address range of a data transfer destination (for example, the main storage device 6) in the DMA. The unauthorized access detection circuit 1 is configured to capture the destination start address.
The DMA transfer destination end address register 25 stores a DMA transfer destination end address which is an end (last) address in the address range of the data transfer destination in the DMA, and this DMA transfer destination end address is detected as unauthorized access. The circuit 1 is configured to capture.

The DMA transfer source address register 26 stores a DMA transfer source address that is an address of a data transfer source (for example, the I / O device 4) in the DMA. The DMA controller 2 has a function of sending this DMA transfer source address to the address bus 81 while changing the DMA transfer source address from the DMA transfer source start address to the DMA transfer source end address, and sending a DMA read access signal 51 to the unauthorized access detection circuit 1. Have.
The DMA transfer destination address register 27 stores a DMA transfer destination address which is an address of a data transfer destination (for example, the main storage device 6) in the DMA. The DMA controller 2 sends the DMA transfer destination address to the address bus 81 while changing the DMA transfer destination address from the DMA transfer destination start address to the DMA transfer destination end address, and sends a DMA write access signal 52 to the unauthorized access detection circuit 1 Have

  The DMA data buffer 28 has a function of storing DMA transfer data sent from the data bus 82 and a DMA acceptance signal indicating that the DMA data sent from the address bus 81 is valid.

(DMA controller processing)
Next, processing in the DMA controller 2 and the unauthorized access detection circuit 1 will be described along FIGS. 4 to 6 with reference to FIGS.
4 and 5 are flowcharts showing the flow of processing in the DMA controller. 4 and 5, step S101 and step S102 are processing by the processor, and steps after step S103 are processing by the DMA controller 2. Further, the processing in step S105 and step S109 is processing performed by the devices (I / O device 4 and main storage device controller 5) that are controlled.
When starting DMA, the processor 3 first writes the transfer source address range and DMA data for reading DMA transfer data (DMA data) to the preset DMA controller 2 (DMA controller 2a side). A transfer destination address range is read (S101 in FIG. 4).
Then, the processor 3 sets the transfer source address range by writing the start address in the DMA transfer source start address register 22 of the DMA controller 2 and writing the end address in the DMA transfer source end address register 23 of the DMA controller 2.
Similarly, the processor 3 sets a transfer destination address range by writing a start address in the DMA transfer destination start address register 24 of the DMA controller 2 and writing an end address in the DMA transfer destination end address register 25 of the DMA controller 2. .
Next, in accordance with the activation timing of the I / O device 4, the processor 2 activates the DMA controller 2 (on the DMA controller 2a side) that has been in the idle state through the control register 21 (S102).

The activated DMA controller 2 sets the DMA activation signal 53 input from the DMA controller control register 21 to the unauthorized access detection circuit 1 to “1” (S103), and starts DMA.
In this embodiment, as described above, “1” of the DMA activation signal 53 indicates that the DMA controller 2 is being activated, and “0” indicates that it is idle.

  If the DMA controller 2 (DMA controller 2a side) is immediately after startup, the contents of the DMA transfer source start address register 22 are copied to the DMA transfer source address register 26, and the DMA is transferred to the system bus 8 (address bus 81). The transfer source address is output, and a read access is requested to a read destination device (for example, the I / O device 4) (S104). At this time, the DMA read access signal 51 is input to the unauthorized access detection circuit 1.

The I / O device 4 that has received the read access request reads the data corresponding to the DMA transfer source address included in the read access signal, and outputs the read data to the system bus 8 (data bus 82) (S105).
The data output to the data bus 82 is temporarily stored in the data buffer 28 of the DMA controller 2 (DMA controller 2a side).

Next, the DMA controller 2 (DMA controller 2a side) determines whether or not the reading of the DMA data to be read by the DMA is completed based on the read state signal from the I / O device 4 (S106). ).
As a result of step S106, when the reading is not completed (S106 → No), the controller of the device to be read repeats step S105.
As a result of step S106, when the reading is completed (S106 → Yes), the DMA controller 2 increments the DMA transfer source address in the DMA transfer source address register 26 by 1 (S107), and further cancels the read access. Prepare for the next read access request.

  Next, the DMA controller 2 (the DMA controller 2a side) copies the contents of the DMA transfer destination start address register 24 to the DMA transfer destination address register 26 immediately after startup, and puts it in the system bus 8 (address bus 81). In response to this, the DMA transfer destination address is output, and a write access is requested to the write destination device (for example, the main storage controller 5) (S108 in FIG. 5). At this time, the DMA write access signal 52 is input to the unauthorized access detection circuit 1.

  Receiving the write access request, the main storage controller 5 writes the data corresponding to the DMA transfer destination address included in the write access signal (S109).

Next, the DMA controller 2 determines whether or not the writing of the DMA data to be written into the DMA is completed based on the signal from the I / O device 4 (S110).
If the result of step S110 is that writing has not been completed (S110 → No), the main memory controller 5 repeats step S109.
As a result of step S110, when the writing is completed (S110 → Yes), the DMA controller 2 increments the DMA transfer destination address in the DMA transfer destination address register 27 by 1 (S111), and further cancels the write access. Then, the main storage controller 5 is released from the write access to prepare for the next write access request.

Then, the DMA controller determines whether the DMA transfer source address is the value of the DMA transfer source end address or whether the DMA transfer destination address is the value of the DMA transfer destination end address (S112).
When the DMA transfer source address is not the value of the DMA transfer source end address and the DMA transfer destination address is not the value of the DMA transfer destination end address (S112 → No), the DMA controller 2 returns the process to step S104 in FIG.
When the DMA transfer source address is the value of the DMA transfer source end address or the DMA transfer destination address is the value of the DMA transfer destination end address (S112 → Yes), the processor 3 sets the DMA controller 2 in the idle state and performs processing. End. The DMA controller 2 becomes idle, and the DMA activation signal 53 becomes “0”.

(Processing in unauthorized access detection circuit)
FIG. 6 is a flowchart showing the flow of unauthorized access detection processing according to the first embodiment. In addition, the process of FIG. 6 is a process performed in parallel with the process of FIG. 4 and FIG.
The unauthorized access detection circuit 1 determines whether or not the DMA of its own device is being activated (S301). In this case, the own device is, for example, the DMA controller 2 on which the unauthorized access detection circuit 1 itself is mounted.
As a result of step S301, if the DMA of the device itself is not activated (S301 → No), the unauthorized access detection circuit 1 outputs “0” (S309).
If the result of step S301 is that the own device is being activated (S301 → Yes), the unauthorized access detection circuit 1 determines whether it is the DMA read access signal 51 of the own device (S302).

If the result of step S302 is the DMA read access signal 51 of the device itself (S302 → Yes), the unauthorized access detection circuit 1 outputs “0” (S309).
If the result of step S302 is not the DMA read access signal 51 of the own device (S302 → No), the unauthorized access detection circuit 1 determines whether it is the DMA write access signal 52 of the own device (S303).
If the result of step S303 is the DMA write access signal 52 of the own device (S303 → Yes), the unauthorized access detection circuit 1 outputs “0” (S309).

  If it is not the DMA write access signal 52 of the own device as a result of step S303 (S303 → No), the bus address sent from the other DMA controller 2 or the like, which is input via the address bus 81 by the address comparator 11a. Is compared with the DMA transfer source start address in the DMA transfer source start address register 22 to determine whether or not the bus address is equal to or higher than the DMA transfer source start address (S304). If the own device is the DMA controller A2a, the other device corresponds to the DMA controller B2b, the processor A3a, the processor B3b, and the like.

If the result of step S304 is that the bus address is less than the DMA transfer source start address (S304 → No), the unauthorized access detection circuit 1 advances the processing to step S306.
If the result of step S304 is that the bus address is greater than or equal to the DMA transfer source start address (S304 → Yes), the address comparator 11b performs the DMA transfer of the bus address input from the address bus 81 and the DMA transfer source end address register 23. The original end address is compared, and it is determined whether or not the bus address is equal to or less than the DMA transfer source end address (S305).

If the result of step S305 is that the bus address is equal to or less than the DMA transfer source end address (S305 → Yes), the address comparator 11b outputs “1” to the transfer source AND gate 12 (S308), and the bus address is DMA transfer. If it is larger than the original end address (S305 → No), the address comparator 11c compares the bus address input from the address bus 81 with the DMA transfer destination start address of the DMA transfer destination start address register 24, and the bus address is It is determined whether it is equal to or greater than the DMA transfer destination start address (S306).
As a result of step S306, if the bus address is less than the DMA transfer destination start address (S306 → No), the address comparator 11c outputs “0” to the transfer destination AND gate 13 (S309).

If the result of step S306 is that the bus address is greater than or equal to the DMA transfer destination start address (S306 → Yes), the address comparator 11d performs the DMA transfer of the bus address input from the address bus 81 and the DMA transfer destination end address register 25. It is compared with the destination end address to determine whether or not the bus address is equal to or lower than the DMA transfer destination end address (S307).
As a result of step S307, if the bus address is equal to or less than the DMA transfer destination end address (S307 → Yes), the address comparator 11d outputs “1” to the transfer destination AND gate 13 (S308), and the bus address is DMA transfer. If it is larger than the destination end address (S307 → No), the address comparator 11d outputs “0” to the transfer destination AND gate 13 (S309).

Then, the transfer source AND gate 12 calculates the logical product of the input transfer source related signals and outputs the calculation result to the OR gate 14. Here, the transfer source related signals are the comparison results output from the address comparators 11a and 11b, the DMA activation signal 53, the DMA read access signal 51, and the DMA write access signal 52.
Here, the DMA read access signal 51 and the DMA write access signal 52 are negative logic, and are input to exclude access of the DMA controller 2 itself.

  With the above operation, when the bus address is within the range from the DMA transfer source start address to the DMA transfer source end address, the DMA controller 2 is being activated, and the bus address is not an access of the DMA controller 2 itself, The transfer source AND gate 12 outputs “1”. On the other hand, if the bus address is outside the range from the DMA transfer source start address to the DMA transfer source end address, the DMA controller 2 is stopped, or the DMA controller 2 itself is accessing, the transfer source AND gate 12 outputs “0”.

Then, the transfer destination AND gate 13 calculates a logical product of the input transfer destination related signals and outputs the calculation result to the OR gate 14. Here, the transfer destination related signals are the comparison results output from the address comparators 11c and 11d, the DMA activation signal 53, the DMA read access signal 51, and the DMA write access signal 52.
Here, the DMA read access signal 51 and the DMA write access signal 52 are negative logic, and are input to exclude access of the DMA controller 2 itself.

  With the above operation, the bus address is within the range from the DMA transfer destination start address to the DMA transfer destination end address, the DMA controller 2 is being activated, and the bus address is not an access of the DMA controller 2 itself The transfer destination AND gate 13 outputs “1”. On the other hand, if the bus address is outside the range from the DMA transfer destination start address to the DMA transfer destination end address, the DMA controller 2 is stopped, or the DMA controller 2 itself is accessing, the transfer destination AND gate 13 outputs “0” (S309).

The OR gate 14 calculates the logical sum of the output of the transfer source AND gate 12 and the output of the transfer destination AND gate 13 and outputs the logical sum to the data bus 82 as an unauthorized access warning signal. A flag is set on the device 6.
In other words, the unauthorized access warning signal is sent to the other device bus address sent by the other DMA controller or the like of the other device, not the DMA read or write of the own device when the DMA of the own device is active. Further, if the bus address range falls within the range from the start to the end of the DMA transfer source of the own device or the range of the bus address falls within the range from the start to the end of the own DMA transfer destination, “1” is output (S308). On the other hand, the DMA of the own device is not used or the bus address is based on the DMA read or write of the own device, or the bus address range is outside the range from the start to the end of the own DMA transfer source, or the bus address range is If it is outside the range from the start to the end of the DMA transfer destination, “0” is output (S309).
The controller 3 periodically monitors the unauthorized access warning signal or flag written in the main storage device 6, and if the information is “1” indicating unauthorized access, displays an alert on the display device 7. Then, the DMA processing is interrupted by the DMA controller A2a and the DMA controller B2b, and the processing ends.

  According to the first embodiment, unauthorized access to the DMA transfer source address range and the DMA transfer destination address range can be detected. That is, it is possible to detect unauthorized access to the DMA transfer destination area before DMA stops and unauthorized access to the DMA transfer source area.

<< Second Embodiment >>
The conventional techniques have a problem that malfunctions cannot be prevented even when DMA transfer areas overlap when a plurality of DMA control devices are operating.
Next, a second embodiment according to the present invention for solving such a problem will be described with reference to FIGS.

(Configuration of DMA control system)
FIG. 7 is a diagram illustrating a configuration example of a DMA control system according to the second embodiment.
Further, the system bus 8 is connected to an interrupt controller 93 that detects the occurrence of an interrupt based on an output from the unauthorized access detection OR gate 92.

The unauthorized access detection OR gate 92 calculates the logical sum of the unauthorized access warning signals output from the plurality of DMA controllers 2, outputs the logical sum to the bus access state output circuit 91, and passes through the system bus 8. And has a function of outputting an interrupt signal to the interrupt controller 93.
The bus access status output circuit 91 receives a DMA read access signal 51 and a DMA write access signal 52 (collectively referred to as a bus access request signal) input from each DMA controller 2 to the device to be DMA-targeted. Is always input and the signal output from the unauthorized access detection OR gate 92 is “1”, the input state of the bus access request signal is stored in a storage medium such as the main storage device 6, and the processor 3 When receiving an instruction to output the status of the bus access request signal, it has a function of outputting the input status of the bus access request signal stored in the system bus 8.

(Processing of DMA control system)
Next, the processing of the DMA control system will be described along FIG. 8 with reference to FIG.
FIG. 8 is a flowchart showing the flow of processing in the DMA control system according to the second embodiment.
The unauthorized access detection OR gate 92 receives unauthorized access warning signals from the plurality of DMA controllers 2, and the unauthorized access detection OR gate 92 calculates the logical sum of these unauthorized access warning signals (S401). The calculation result is output to the bus access state output circuit 91.
The bus access status output circuit 91 determines whether the logical sum sent from the unauthorized access detection OR gate 14 is “1” (S402). In other words, the bus access status output circuit 91 determines whether or not at least one DMA controller detects a DMA unauthorized access and outputs an unauthorized access warning signal “1”.
If the logical sum is “0” as a result of step S402 (S402 → No), the DMA control system 9 returns the process to step S401.
If the logical sum is “1” as a result of step S402 (S402 → Yes), the bus access state output circuit 91 stores the state of the bus access request signal in a storage medium such as the main storage device 6 (S403), An interrupt signal is transmitted to the interrupt controller 93 via the system bus 8 (S404), and the DMA control system 9 returns the process to step S401.

FIG. 9 is a flowchart showing a flow of interrupt processing according to the second embodiment.
When the interrupt controller 93 receives the interrupt signal and detects the occurrence of the interrupt, the interrupt controller 93 notifies the processor 3 to that effect, and the processor 3 instructs the bus access state output circuit 91 to output the bus access request signal state. To do. Then, the bus access state output circuit 91 outputs the state of the stored bus access request signal to the system bus 8 (S501).
Then, the display device 7 (FIG. 2) displays the state of the bus access request signal acquired via the system bus 8 (S502).

  As described above, according to the second embodiment, in addition to the detection and display (alert display) of DMA unauthorized access in the first embodiment, when a plurality of DMA control devices are operating, the DMA transfer areas overlap. In addition to preventing malfunction, the cause of the occurrence can be displayed, and useful information for debugging the program of the image processing apparatus 100 can be obtained.

  In the present embodiment, the unauthorized access detection circuit 1 and the DMA controller 2 are configured by hardware incorporating a CPU, but may be realized by software. For example, a program stored in a ROM (Read Only Memory) or an HD (Hard Disk) in a PC is expanded in a RAM (Random Access Memory) and executed by the CPU, whereby the unauthorized access detection circuit 1 or DMA The controller 2 may be embodied. By executing such a program on the PC, the PC can be used as a simulator for the unauthorized access detection circuit 1 or the DMA controller 2.

<Machine>
FIG. 10 is a schematic perspective view of a multifunction machine equipped with the image processing apparatus and the DMA control system according to the first and second embodiments.
The multi-function device 200 roughly includes a reading unit 201, a display unit 202, a control unit 203, a printing unit 204, an operation panel unit 205, and a communication unit 206.
The reading unit 201 is a scanner device having a reading sensor such as an LED (Light Emitting Diode) (linear light source) or a CCD (Charge Coupled Device). The reading unit 201 reads an original, converts it into an electrical signal, and further converts it into image data. It has a function. The reading unit 201 corresponds to the I / O device 4 in FIG.
The control unit 203 incorporates a processing device for controlling the multifunction device 200. For example, the DMA controller 2, the processor 3, the main storage device controller 5, the main storage device 6, and the DMA control system shown in FIG. 9 etc. are built in.

The printing unit 204 is a printer device using an electrophotographic method, and has a function of printing image data read by the reading unit 201 and data from a communication line or an external interface received by the communication unit 206. The printing unit 204 corresponds to the I / O device 4 in FIG.
The operation panel unit 205 includes a display unit 202 that displays various settings of image processing conditions, the state of the apparatus, and the like, and an operation unit for inputting commands to the apparatus. The display unit 202 has a configuration corresponding to the display device 7 in FIG. 2, and the operation unit corresponds to the I / O device 4 in FIG.
The communication unit 206 is a part to which other devices such as a PC are connected, and corresponds to the I / O device 4 in FIG. Note that the communication unit 206 is hidden in FIG.

Although the unauthorized access detection circuit 1 is provided in the DMA controller 2 in the first embodiment, it may be mounted on the main memory controller 5 or a bus controller (not shown).
In addition, the image processing apparatus 100 according to the present embodiment can be applied to general electronic devices having a DMA function such as a printer (impact printer, inkjet printer), a facsimile, a scanner, or a composite device thereof, or a PC.

1 Unauthorized access detection circuit (unauthorized access detection means)
2 DMA controller (DMA controller)
3 processor 4 I / O device 5 main memory controller 6 main memory 7 display device (display means)
8 System bus 9 DMA control system 11 (11a to 11d) Address comparator 12 AND gate for transfer source 13 AND gate for transfer destination 14 OR gate 21 DMA controller control register 22 DMA transfer source start address register (storage means)
23 DMA transfer source end address register (storage means)
24 DMA transfer destination start address register (storage means)
25 DMA transfer destination end address register (storage means)
26 DMA transfer source address register 27 DMA transfer destination address register 28 DMA data buffer 51 DMA read access signal 52 DMA write access signal 53 DMA start signal 81 Address bus 82 Data bus 91 Bus access status output circuit (DMA illegal access factor output circuit) means)
92 Unauthorized access detection OR gate 93 Interrupt controller 100 Image processing device 200 Multifunction machine 201 Reading unit 202 Display unit 203 Control unit 204 Printing unit 205 Operation panel unit 206 Communication unit

Claims (12)

A direct memory access control device for performing direct memory access and memory access transfer control using the same system bus,
Storage means for storing a transfer source address range in the direct memory access and a transfer destination address range in the direct memory access;
When an address for performing data transfer in the memory access is designated on the system bus,
If the specified address is within the address range of the direct memory access transfer source or the address range of the direct memory access transfer destination, the data in the memory access is an unauthorized access. Unauthorized access detection means for outputting an unauthorized access warning signal;
A direct memory access control device comprising: The storage means stores a start address and an end address in a transfer source address of the direct memory access,
The unauthorized access detection means includes
Outputting the unauthorized access warning signal when an address designated on the system bus is a value equal to or greater than the start address and an address from the external device is equal to or less than the end address. 2. The direct memory access control apparatus according to claim 1, wherein The storage means stores a start address and an end address in a transfer destination address of the direct memory access,
The unauthorized access detection means includes
Outputting the unauthorized access warning signal when an address designated on the system bus is a value equal to or greater than the start address and an address from the external device is equal to or less than the end address. 2. The direct memory access control apparatus according to claim 1, wherein The unauthorized access detection means includes
When there is no write request or read request for the direct memory access control device itself in addition to the address within the address range of the direct memory access transfer source or the address range of the transfer destination of the direct memory access The direct memory access control apparatus according to claim 1, wherein the unauthorized access warning signal is output. The memory access is another direct memory access, and another device including the other direct memory access includes other unauthorized access detection means. The direct memory access control device according to item. A direct memory access control system having at least one direct memory access control device according to any one of claims 1 to 5,
Improper direct memory access that outputs the status of the bus access request signal for the device subject to direct memory access to the display means when the unauthorized access warning signal is received from at least one of the direct memory access control devices A direct memory access control system comprising access factor output means.   The program for making a computer perform the process which concerns on the unauthorized access detection means of the direct memory access control apparatus as described in any one of Claims 1-5.   The program for making a computer perform the process of the direct memory access unauthorized access factor output means of the direct memory access control system of Claim 6. An image processing apparatus comprising the direct memory access control device according to claim 1. An image processing apparatus comprising the direct memory access control system according to claim 6. A multi-function machine comprising a reading unit, a communication unit, a main storage device and a printing unit,
6. The data is transferred from the reading unit or the communication unit to the main storage device by the direct memory access, and is transferred from the main storage device to the printing unit by the memory access. 6. A multi-function machine comprising the direct memory access control device. A multi-function machine comprising a reading unit, a communication unit, a main storage device and a printing unit,
The direct memory access control system according to claim 6, wherein the direct memory access is transferred from the reading unit or the communication unit to the main storage device by the direct memory access, and is transferred from the main storage device to the printing unit by the memory access. A multi-function machine characterized by

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