JP2023021707A - Information processing device, control method of information processing device, and program - Google Patents

Abstract

To provide an information processing device which can suppress a failure of a semiconductor device which communicates with a storage device for readout and write of data.SOLUTION: An image processing device 100 includes a nonvolatile memory 102, a nonvolatile memory 104 and an arithmetic processing unit 101 which controls readout and write of data for the nonvolatile memory 102. The image processing device 100 calculates a cumulative communication data size 403 which is an accumulated value of communication data sizes of the readout and write of the data for the nonvolatile memory 102 and, when the cumulative communication data size 403 exceeds a failure prediction threshold value, changes a write destination of predetermined data from the nonvolatile memory 102 to the nonvolatile memory 104.SELECTED DRAWING: Figure 6

Description

The present invention relates to an information processing device, a control method for an information processing device, and a program.

An information processing apparatus including a semiconductor device such as a CPU (Central Processing Unit) is known. With the miniaturization of semiconductor processes, high integration and high-speed communication can be realized, but the durability of semiconductor devices is declining. For example, an interface unit of a CPU that communicates with a storage device such as an SSD (Solid State Drive) for reading and writing data is likely to fail in proportion to the frequency of access to the storage device. As described above, semiconductor devices have a limited life, and when a semiconductor device reaches the end of its life, it is necessary to replace electronic components including the semiconductor device. In order to suppress the replacement frequency of electronic parts, techniques for making semiconductor devices less likely to fail have been proposed. For example, in Japanese Unexamined Patent Application Publication No. 2002-200012, when a predetermined operation related to processing that requires writing to a storage device is performed, writing to the storage device is permitted, and when the predetermined operation is not performed, storage is permitted. Writing to the device is prohibited. As a result, among accesses from the CPU, which is a semiconductor device, to the storage device, the frequency of access related to data writing can be suppressed, and failure of the semiconductor device can be suppressed.

JP 2020-145582 A

However, accesses from the CPU to the storage device include accesses related to data reading, so simply reducing the frequency of accesses related to data writing as described above cannot sufficiently suppress semiconductor device failures. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide an information processing apparatus, a control method for the information processing apparatus, and a program capable of suppressing a failure of a semiconductor device that communicates with a storage device regarding reading and writing of data.

To achieve the above object, an information processing apparatus of the present invention comprises a first storage device, a second storage device, and arithmetic processing means for controlling reading and writing of data to and from the first storage device. The information processing apparatus comprising: calculating means for calculating an accumulated value of communication data size of data read and written to the first storage device; The means is characterized by changing the write destination of the predetermined data from the first storage device to the second storage device.

According to the present invention, it is possible to suppress failure of a semiconductor device that communicates with a storage device regarding reading and writing of data.

1 is a block diagram schematically showing the hardware configuration of an image processing apparatus according to an embodiment of the invention; FIG. 2 is a conceptual diagram of Clock Gate control performed by the arithmetic processing unit of FIG. 1; FIG. FIG. 2 is a flowchart showing the procedure of activation control processing of the arithmetic processing unit of FIG. 1; FIG. 2 is a diagram showing an example of a switching rate management file stored in the nonvolatile memory of FIG. 1; FIG. FIG. 2 is a flow chart showing the procedure of write control processing executed by the arithmetic processing unit of FIG. 1; FIG. FIG. 2 is a flowchart showing a procedure of shutdown control processing executed by the arithmetic processing unit of FIG. 1; FIG.

EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing this invention is demonstrated using drawing. However, the constituent elements described in this embodiment are merely examples, and the scope of the present invention is not intended to be limited to them.

FIG. 1 is a block diagram schematically showing the hardware configuration of an image processing apparatus 100 according to an embodiment of the invention. 1, an image processing apparatus 100 includes an arithmetic processing unit 101, a nonvolatile memory 102, a volatile memory 103, a nonvolatile memory 104, a communication control unit 105, an image processing unit 106, a volatile memory 107, an image reading unit 108, and an image forming unit 109 .

The arithmetic processing unit 101 is a so-called CPU, loads program data stored in the nonvolatile memory 102 into the volatile memory 103, and sequentially executes processing according to the operation of a program counter (not shown) of the arithmetic processing unit 101. do. The program data is, for example, a boot loader or an OS (Operating System), and controls the entire system of the image processing apparatus 100 . In addition, in the present embodiment, the arithmetic processing unit 101 corresponds to a semiconductor device in which miniaturization is progressing as described in Background Art.

The nonvolatile memory 102 is a storage device capable of retaining data even when power supply is stopped, and is, for example, an eMMC (embedded Multi Media Card). The nonvolatile memory 102 stores program data such as the OS for controlling the image processing apparatus 100 as described above. The nonvolatile memory 102 is also used as a storage area for user data, various setting information, operation logs, and the like that are necessary for using the image processing apparatus 100 . In other words, the arithmetic processing unit 101 does not access the nonvolatile memory 102 only when the image processing apparatus 100 is activated, but frequently accesses the nonvolatile memory 102 during operation of the image processing apparatus 100 to read data. and writing.

The nonvolatile memory 102 is connected to the arithmetic processing unit 101 via multiple buses. The plurality of buses are, for example, clock signal bus 110 , clock signal bus 111 , command signal bus 112 , and data signal bus 113 . A clock signal bus 110 is a bus for transferring the first clock signal output from the arithmetic processing unit 101 to the nonvolatile memory 102 . A clock signal bus 111 is a bus for transferring the second clock signal output from the nonvolatile memory 102 to the arithmetic processing unit 101 . A command signal bus 112 is a bus for bidirectionally communicating command signals between the arithmetic processing unit 101 and the nonvolatile memory 102 . A data signal bus 113 is a bus for bidirectionally communicating data signals between the arithmetic processing unit 101 and the nonvolatile memory 102 .

Arithmetic processing unit 101 serving as a host outputs a first clock signal to nonvolatile memory 102 via clock signal bus 110 . Normally, the first clock signal is used as a reference clock during communication. On the other hand, the eMMC standard supports multiple communication modes. When communicating in the HS400 communication mode, the nonvolatile memory 102 must output a reference clock for the host to sample data output from the nonvolatile memory 102, which is a device. The clock signal used at this time is the second clock signal. Then, the arithmetic processing unit 101 instructs the non-volatile memory 102 via the command signal bus 112 to read or write data, and the data corresponding to each instruction is transmitted to and from the arithmetic processing unit 101 via the data signal bus 113 . Communicated between non-volatile memories 102 .

Reading and writing performed by the arithmetic processing unit 101 on the nonvolatile memory 102 are performed in units of blocks. The data size per block is managed by the file system of the image processing apparatus 100. FIG. In this embodiment, it is executed with a data size of 512 bytes per block. The arithmetic processing unit 101 also includes a communication data size counter (not shown). The communication data size counter counts the number of times reading and writing are performed in block units while the image processing apparatus 100 is powered on, and stores the counted number of times in the nonvolatile memory 102 . For example, the communication data size counter indicates that the number of read operations executed in units of 1 block is 10, the number of write operations executed in unit of 1 block is 2, and the number of read operations executed in unit of 2 blocks is 5. The number of times of writing is counted once, the number of times of reading executed in units of four blocks is counted three times, the number of times of writing executed in units of four blocks is counted twice, and so on.

In the present embodiment, normal operation is not guaranteed if the interface unit (hereinafter referred to as “PHY”) for communication between the arithmetic processing unit 101 and the non-volatile memory 102 continues to be subjected to a certain load or more. ). Further, in the present embodiment, when the operation rate of the first clock signal is 80% or more, it is defined that the PHY is loaded with a certain amount or more. For example, in the image processing apparatus 100 that has been in operation for five years, if the cumulative time during which the first clock signal oscillates exceeds four years, the PHY is more likely to fail.

In view of such a situation, in the present embodiment, the arithmetic processing unit 101 performs Clock Gate control on the first clock signal to be output to the nonvolatile memory 102 . In Clock Gate control, the arithmetic processing unit 101 stops oscillation of the first clock signal while no command or data communication is performed. Note that the operation of Clock Gate control will be described later.

The volatile memory 103 is a storage device, such as a DRAM, that cannot retain data when power supply is stopped. Program data stored in the non-volatile memory 102 is loaded into the volatile memory 103 according to instructions from the arithmetic processing unit 101 . The volatile memory 103 is used as a work memory for the arithmetic processing unit 101 and is used for purposes such as temporarily storing arithmetic processing data.

The nonvolatile memory 104 is a storage device capable of retaining data even when power supply is stopped, and is connected to the arithmetic processing unit 101 through an interface of a standard different from that of the nonvolatile memory 102 . For example, communication with the non-volatile memory 102 is based on the eMMC standard, while communication with the non-volatile memory 104 is based on the SATA (Serial ATA) standard. Non-volatile memory 104 is, for example, an SSD. Note that the nonvolatile memory 104 is not limited to an SSD, and may be a storage device other than an SSD as long as it is a nonvolatile storage device. The nonvolatile memory 104 is mainly used for storing image data read by the main body of the image processing apparatus 100 . In addition, there is no prescribed value for the operation rate in the SATA PHY to which the nonvolatile memory 104 is connected. In the nonvolatile memory 104, an area for copying part of the data in the nonvolatile memory 102 is reserved in advance.

The communication control unit 105 communicates with a server (not shown) connected via a network using the TCP/IP protocol. In this embodiment, it is assumed that the server is connected by an Ethernet cable. It is also possible to connect to an information device such as a PC (not shown) in a peer-to-peer manner using an Ethernet cable. The communication control unit 105 has a function of transmitting PDL (Page Description Language) data transmitted from the information device to the arithmetic processing unit 101 .

The image processing unit 106 performs overall image processing in the image processing apparatus 100 , such as image processing for image data received from the image reading unit 108 and image processing for image data output to the image forming unit 109 . Examples of image processing include packetization, compression, rotation, and halftone processing. The image processing unit 106 also includes an arithmetic processing unit (not shown), and uses the volatile memory 107 as a work memory when executing image processing.

The image reading unit 108 has a contact image sensor (not shown) that converts characters and images printed on a document into electronic data, and functions as an input unit during copying and scanning, which are the basic functions of the image processing apparatus 100 . .

The image forming unit 109 is an output unit used when executing copying or printing, and forms desired electronic data on a paper medium using a photoreceptor, toner, fixing device, etc. of the image processing apparatus 100 . .

Next, Clock Gate control of the first clock signal output from the arithmetic processing unit 101 to the nonvolatile memory 102 will be described.

Clock gate control is control performed mainly to reduce the power consumption of semiconductor devices. Normally, the clock signal continues to oscillate while power is supplied to the PHY that outputs the clock signal of a certain semiconductor device. However, in most cases, command signals and data signals are not constantly being transmitted and received while the clock signal continues to oscillate. The semiconductor device that is the output source of the clock signal detects that no command signal or data signal is being transmitted or received, and stops the oscillation of the clock signal, thereby suppressing power consumption. This technique is useful not only for suppressing power consumption but also for delaying the failure time of PHY in recent years when the arithmetic processing unit 101 is becoming finer.

In the present embodiment, Clock Gate control is enabled by setting a desired value in a register (not shown) of the arithmetic processing unit 101 from software such as BIOS (Basic Input Output System) or OS.

FIG. 2 is a conceptual diagram of Clock Gate control performed by the arithmetic processing unit 101 of FIG. Normally, while power is being supplied to the PHY, the first clock signal oscillates regardless of the presence or absence of access such as reading or writing to the nonvolatile memory 102 (eMMC), as shown in FIG. keep doing. On the other hand, when the Clock Gate control is enabled, as shown in FIG. controlled. That is, the operating rate of the first clock signal is proportional to the data size when the arithmetic processing unit 101 reads data from the nonvolatile memory 102 and the data size when writing data to the nonvolatile memory 102 .

In the present embodiment, in Clock Gate control, attention is focused on the proportional relationship between the operation rate and the read/write data size, and the failure timing of the PHY is predicted.

For example, if the arithmetic processing unit 101 continues to operate the first clock signal at a frequency of 200 MHz for five years, theoretically about 3.2×10 ¹⁶ clocks are output. That is, a data size of approximately 4.0×10 ¹⁵ bytes can be read from and written to the nonvolatile memory 102 . In the present embodiment, as described above, there is a constraint that the operation rate of the first clock signal is 80%, so the total data size of reading and writing of the nonvolatile memory 102 is theoretically about 3.2×10 ¹⁵ bytes. must converge within the data size of This data size is called a communication limit data size. On the other hand, in an actual system, the cumulative value of the read and write data sizes of the nonvolatile memory 102 must be converged within the data size considering the communication limit data size with a certain margin. A value considering this margin is called a failure prediction threshold, and in the present embodiment, the failure prediction threshold is defined as a value of 70% of the communication limit data size. The arithmetic processing unit 101 determines that the PHY will fail in the near future when the cumulative value of the read and write data sizes of the nonvolatile memory 102 exceeds the failure prediction threshold. Then, in order to extend the life of the PHY, the arithmetic processing unit 101 switches the write destination so that the predetermined data written in the nonvolatile memory 102 is written in another storage device, for example, the nonvolatile memory 104. .

FIG. 3 is a flow chart showing the procedure of activation control processing of the arithmetic processing unit 101 of FIG. The processing in FIG. 3 is implemented by the arithmetic processing unit 101 loading the program stored in the nonvolatile memory 102 into the volatile memory 103 and executing the loaded program. The processing in FIG. 3 is executed when power is supplied to the arithmetic processing unit 101 and the arithmetic processing unit 101 completes the initialization of the software (eMMC driver) that controls the nonvolatile memory 102 and the initialization of the file system. .

In FIG. 3, the arithmetic processing unit 101 starts measurement by the communication data size counter (step S301). Next, the arithmetic processing unit 101 reads the switching rate management file 400 of FIG. 4 stored in the nonvolatile memory 102 (step S302).

The operating ratio management file 400 is a file for managing the total communication data size when the arithmetic processing unit 101 reads and writes to the nonvolatile memory 102 . The activity rate management file 400 is composed of a total read data size 401, a total write data size 402, and a cumulative communication data size 403. FIG. The total read data size 401 is the total read data size (GByte) obtained by multiplying the read count counted by the communication data size counter and the data size per block (here, 512 bytes). The total write data size 402 is the total write data size (GByte) obtained by multiplying the number of writes counted by the communication data size counter and the data size per block (here, 512 bytes). A cumulative communication data size 403 is a cumulative value (GB bytes) of communication data sizes obtained by adding the total read data size 401 and the total write data size 402 . In this embodiment, the communication data size counter counts the number of readouts and writes from the time the image processing apparatus 100 is started up until it shuts down. 400. As described above, in the present embodiment, the count result is recorded in the operation rate management file 400 only when the image processing apparatus 100 is shut down, thereby minimizing the access from the arithmetic processing unit 101 to the nonvolatile memory 102. is kept in

Next, the arithmetic processing unit 101 determines whether or not the cumulative communication data size 403 in the read switching rate management file 400 exceeds the failure prediction threshold (step S303).

If the cumulative communication data size 403 does not exceed the failure prediction threshold as a result of determination in step S303, the activation control process ends. If the cumulative communication data size 403 exceeds the failure prediction threshold as a result of the determination in step S303, the arithmetic processing unit 101 sets an access destination change flag (step S304). When the access destination change flag is set, the arithmetic processing unit 101 changes the write destination of data such as user data and various setting values from the nonvolatile memory 102 to the nonvolatile memory 104 in the write control processing of FIG. 5, which will be described later. do. As described above, in this embodiment, control is performed so that new data is not written to the nonvolatile memory 102 when the cumulative communication data size 403 exceeds the failure prediction threshold. Next, the arithmetic processing unit 101 determines whether it is the first time that the total communication data size 403 has exceeded the failure prediction threshold (step S305).

If it is not the first time that the cumulative communication data size 403 has exceeded the failure prediction threshold as a result of the determination in step S305, the activation control process ends. If it is the first time that the cumulative communication data size 403 has exceeded the failure prediction threshold as a result of the determination in step S305, the arithmetic processing unit 101 stores the predetermined data stored in the nonvolatile memory 102 in the nonvolatile memory 104. Copy (step S306). The predetermined data are, for example, user data and various setting values. Accordingly, the arithmetic processing unit 101 can read user data and various setting values by accessing the nonvolatile memory 104 instead of the nonvolatile memory 102 . Note that, in the present embodiment, an area for copying predetermined data stored in the nonvolatile memory 102 is reserved in advance in the nonvolatile memory 104 as described above. For example, the arithmetic processing unit 101 specifies the logical address of the copy destination area, and copies data from the nonvolatile memory 102 to the nonvolatile memory 104 by DMA (Dynamic Memory Access). After that, the activation control process ends. In this embodiment, the boot program stored in the nonvolatile memory 102 is copied to the nonvolatile memory 104 and the boot storage is not changed.

FIG. 5 is a flow chart showing the procedure of write control processing executed by the arithmetic processing unit 101 of FIG. The processing of FIG. 5 is also implemented by the arithmetic processing unit 101 loading the program stored in the nonvolatile memory 102 into the volatile memory 103 and executing the loaded program. In the process of FIG. 5, it is assumed that the activation control process of FIG. 3 has already been executed.

In FIG. 5, when the arithmetic processing unit 101 detects that a predetermined event requiring writing of the predetermined data to the nonvolatile memory 102 has occurred (Yes in step S501), the write control process proceeds to step S502. In step S502, the arithmetic processing unit 101 determines whether or not the access destination change flag is set.

As a result of the determination in step S502, if the access destination change flag is set, the life of the PHY for the arithmetic processing unit 101 to communicate with the nonvolatile memory 102 is approaching. In this case, the arithmetic processing unit 101 changes the write destination of the predetermined data from the nonvolatile memory 102 to the nonvolatile memory 104, writes the predetermined data to the nonvolatile memory 104 (step S503), and terminates this processing. do.

As a result of the determination in step S502, if the access destination change flag is not set, the arithmetic processing unit 101 determines the total number of accesses that the arithmetic processing unit 101 has made to the nonvolatile memory 102 since the image processing apparatus 100 started up. Calculate the communication data size. Specifically, the arithmetic processing unit 101 calculates the total communication data size by multiplying the number of times of reading and writing, which are started to be measured in step S301, by the data size per block of 512 bytes. The arithmetic processing unit 101 adds this total communication data size to the cumulative communication data size 403 in the switching rate management file 401 read in step S301 to calculate the cumulative communication data size after activation. Naturally, the cumulative communication data size after activation is a value larger than the value of the cumulative communication data size 403 in the switching rate management file 401 read in step S301. Next, the arithmetic processing unit 101 determines whether or not the cumulative communication data size after startup exceeds the failure prediction threshold (step S504).

As a result of the determination in step S504, if the cumulative communication data size after startup exceeds the failure prediction threshold, the arithmetic processing unit 101 sets an access destination change flag (step S505). As described above, in this embodiment, even if the cumulative communication data size does not exceed the failure prediction threshold when the image forming apparatus is started, the arithmetic processing unit 101 can read and write data to the nonvolatile memory 102 during normal operation. By doing so, when the cumulative communication data size exceeds the failure prediction threshold value, the predetermined data write destination is changed from the nonvolatile memory 102 to the nonvolatile memory 104 .

Next, the arithmetic processing unit 101 determines whether or not it is the first time that the cumulative communication data size after startup has exceeded the failure prediction threshold (step S506).

As a result of the determination in step S506, if it is not the first time that the cumulative communication data size after startup has exceeded the failure prediction threshold, the write control process proceeds to step S503. As a result of the determination in step S506, if it is the first time that the cumulative communication data size after startup has exceeded the failure prediction threshold, the arithmetic processing unit 101 stores the Predetermined data is copied to the nonvolatile memory 104 (step S507). The write control process then proceeds to step S503.

As a result of the determination in step S504, if the cumulative communication data size after startup does not exceed the failure prediction threshold, the arithmetic processing unit 101 writes predetermined data to the nonvolatile memory 102 (step S508). Next, the arithmetic processing unit 101 increments the count value of the communication data size counter (step S509), and the write control process ends.

FIG. 6 is a flow chart showing the procedure of shutdown control processing executed by the arithmetic processing unit 101 of FIG. The processing of FIG. 6 is also implemented by the arithmetic processing unit 101 loading the program stored in the nonvolatile memory 102 into the volatile memory 103 and executing the loaded program.

In FIG. 6, first, the arithmetic processing unit 101 waits until a shutdown interrupt is received. For example, when receiving a signal output in response to pressing of a power switch (not shown) of the image processing apparatus 100, the arithmetic processing unit 101 determines that a shutdown interrupt has been received. When a shutdown interrupt is received (YES in step S601), the arithmetic processing unit 101 manages the count value counted by the communication data size counter during the period from when the image processing apparatus 100 is started until when the shutdown interrupt is received. Write to file 400 (step S602). Next, the arithmetic processing unit 101 terminates counting by the communication data size counter (step S603), clears the count value of the communication data size counter, and terminates this processing.

According to the above-described embodiment, when the cumulative communication data size 403 or the cumulative communication data size after activation exceeds the failure prediction threshold, the predetermined data write destination is changed from the nonvolatile memory 102 to the nonvolatile memory 104. be done. As a result, the frequency of access from the arithmetic processing unit 101 to the non-volatile memory 102 can be suppressed, and failure of the arithmetic processing unit 101 can be suppressed.

Further, in the above-described embodiment, when the cumulative communication data size 403 or the cumulative communication data size after activation exceeds the failure prediction threshold, the predetermined data stored in the nonvolatile memory 102 is copied to the nonvolatile memory 102. be done. As a result, the arithmetic processing unit 101 can read predetermined data by accessing the nonvolatile memory 104 instead of the nonvolatile memory 102 . Access frequency can be suppressed.

Furthermore, in the embodiment described above, the predetermined data are user data (data relating to the user of the image processing apparatus 100) and various setting values. As a result, it is possible to suppress failures in the arithmetic processing unit 101 without imposing restrictions on reading and writing of user data and various setting values.

Further, in the above-described embodiment, the arithmetic processing unit 101 outputs a clock signal used for reading and writing data to the nonvolatile memory 102, and stops generating the clock signal during a period in which data is not read or written. Clock Gate control is performed. As a result, failure of the arithmetic processing unit 101 that performs Clock Gate control can be suppressed.

In the embodiments described above, the non-volatile memory 102 is an eMMC. As a result, in a configuration in which a load is applied to the PHY such that the second clock signal is supplied not only from the arithmetic processing unit 101 but also from the nonvolatile memory 102 in the communication mode of the HS400 or the like, failure of the PHY can be suppressed. can be done.

In the above-described embodiment, the non-volatile memory 102 is connected to the arithmetic processing unit 101 by a PHY having a performance rate constraint, and the non-volatile memory 104 is operated by another PHY not having a performance rate constraint. It is connected to the processing unit 101 . In other words, even if the write destination of the predetermined data is changed from the nonvolatile memory 102 to the nonvolatile memory 104, other PHYs will not be overloaded to the point of failure. As a result, the failure of the arithmetic processing unit 101 can be suppressed without imposing a load to the extent that other components will fail.

In the embodiment described above, the image processing apparatus 100 includes the image reading unit 108 that reads a document and generates image data of the document. As a result, it is possible to prevent the arithmetic processing unit 101 from malfunctioning due to execution of a job using the image reading unit 108 .

In the above-described embodiment, the case where the present invention is applied to an image processing apparatus, which is an example of an information processing apparatus, has been described. However, the present invention is not limited to an image processing apparatus. You may apply this invention to the apparatus provided with a part.

The present invention supplies a program that implements one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in the computer of the system or apparatus reads the program. It can also be realized by executing processing. The invention can also be implemented by a circuit (eg, an ASIC) that implements one or more functions.

100 Image processing device 101 Operation processing unit 102 Non-volatile memory 104 Non-volatile memory 403 Cumulative communication data size

Claims (10)

An information processing apparatus comprising a first storage device, a second storage device, and arithmetic processing means for controlling reading and writing of data to and from the first storage device,
calculating means for calculating a cumulative value of communication data sizes for reading and writing data to the first storage device;
The information processing apparatus, wherein, when the accumulated value exceeds a predetermined threshold, the arithmetic processing means changes the write destination of the predetermined data from the first storage device to the second storage device. 2. The method according to claim 1, wherein when said cumulative value exceeds a predetermined threshold, said arithmetic processing means copies predetermined data stored in said first storage device to said second storage device. information processing equipment. 3. The information processing apparatus according to claim 1, wherein said predetermined data includes data relating to a user of said information processing apparatus and setting values of said information processing apparatus. The arithmetic processing means outputs a clock signal used for reading and writing the data to the first storage device, and stops generating the clock signal during a period in which the data is not read or written. The information processing apparatus according to any one of claims 1 to 3. 5. The information processing apparatus according to claim 1, wherein said first storage device and said second storage device are non-volatile memories. 6. The information processing apparatus according to claim 1, wherein said first storage device is an eMMC. the first storage device is connected to the arithmetic processing means through a communication interface having a limited operation rate;
7. The information processing according to any one of claims 1 to 6, wherein said second storage device is connected to said arithmetic processing means through another communication interface which does not impose restrictions on operation rate. Device. 8. The information processing apparatus according to any one of claims 1 to 7, wherein the information processing apparatus is an image processing apparatus comprising reading means for reading a document and generating image data of the document. A control method for an information processing apparatus comprising a first storage device, a second storage device, and arithmetic processing means for controlling reading and writing of data to and from the first storage device, comprising:
a step of calculating a cumulative value of communication data size of reading and writing of data in the first storage device by the arithmetic processing means;
and a step of causing the arithmetic processing means to change the write destination of the predetermined data from the first storage device to the second storage device when the cumulative value exceeds a predetermined threshold. A method of controlling a processing device. A program for causing a computer to execute each means of the information processing apparatus according to any one of claims 1 to 8.

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