JP2012093251A - Testing apparatus and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem in which, if correction values for a driver and a comparator which are set in a state where a performance board is not connected are close to the upper value or lower value in the allowable setting range, margins for further adjustment of the correction values are reduced in a calibration that is performed in a state where the performance board is connected.SOLUTION: A testing apparatus comprises: a correction part for adding/subtracting a set output correction value to/from an output setting value; a first addition/subtraction part for adding/subtracting a stored offset value to/from the output setting value; and a setting part for calculating a first output correction value, setting a difference between a reference value within an allowable setting range and the first output correction value as an offset value to the first addition/subtraction part, calculating a second output correction value on the basis of the reference value, and setting it to the correction part.

Description

  The present invention relates to a test apparatus and a program.

  A test apparatus for testing a semiconductor device or the like outputs a test signal with high accuracy at a timing designated for the device under test, and measures the signal under measurement. The test apparatus calibrates the timing at which a signal is output from the driver and the timing at which the signal is measured by a comparator (see, for example, Patent Documents 1 to 3) prior to the test so that these can be accurately performed.

Patent Literature 1 Pamphlet of International Publication No. 2008/044444 Patent Literature 2 JP 2000-199781 Patent Literature 3 JP 2003-43124 A

  In the timing calibration of the driver and the comparator, the test apparatus calculates a correction value for adjusting the timing for outputting the test signal and a correction value for adjusting the timing for measuring the signal under measurement. The test apparatus sets the calculated correction value in the calibration unit, and adjusts the timing for outputting the test signal and the timing for measuring the signal under measurement.

  Here, the test apparatus sets the correction values for the driver and comparator without connecting the performance board on which the device under test is mounted, and further sets the correction values for the driver and comparator with the performance board connected. May be adjusted. However, if the initially set correction value is close to the upper limit value or lower limit value of the settable range in the calibration unit, there is room for further adjustment of the correction value in calibration with the performance board connected. Less.

  In addition, if the correction value calculated in the calibration with the performance board connected exceeds the range that can be set in the calibration unit, the user of the test equipment adds or subtracts the offset value to the timing itself specified. As a result, the timing for manually outputting the test signal and the timing for measuring the signal under measurement have been adjusted.

  In order to solve the above problems, in a first aspect of the present invention, a test apparatus for testing a device under test, a signal output unit for outputting a test signal at a timing according to an output set value, and a signal output In the signal transmission path between the unit and the device under test, an output correction value for correcting the output setting value is set based on the signal delay time in each of the first transmission path and the second transmission path including the other A calibration unit that can set an output correction value within a predetermined settable range, a correction unit that adds or subtracts the set output correction value to the output set value, and a stored offset A first addition / subtraction unit that adds / subtracts the value to / from the output set value, and a first output correction value that compensates for the signal delay time in the first transmission path, and calculates the reference value within the settable range and the first A setting for setting the difference between the force correction values as an offset value in the first addition / subtraction unit and calculating the second output correction value for compensating for the signal delay time in the second transmission path based on the reference value as the correction unit. And a test apparatus having a portion.

  In the second aspect of the present invention, there is provided a test apparatus for testing a device under test, a signal measuring unit for measuring a signal under measurement output from the device under test at a timing according to a measurement set value, and a device under test In the signal transmission path between the device and the signal measurement unit, a measurement correction value for correcting the measurement setting value is set based on the signal delay time in each of the third transmission path and the fourth transmission path including the other. A calibration unit that can set a measurement correction value within a predetermined settable range, a correction unit that adds or subtracts the set measurement correction value to the measurement set value, and a stored offset A first addition / subtraction unit that adds / subtracts the value to / from the measurement set value, and a first measurement correction value that compensates for the signal delay time in the third transmission path, and calculates the reference value and the first value within the settable range A setting for setting the difference between the measurement correction values as an offset value in the first addition / subtraction unit and calculating the second measurement correction value for compensating for the signal delay time in the fourth transmission path based on the reference value as the correction unit. And a test apparatus having a portion.

  According to a third aspect of the present invention, there is provided a program for causing a computer to function as the setting unit in the first aspect or the second aspect.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

FIG. 1 shows a configuration of a test apparatus 10 according to the present embodiment. FIG. 2 shows a transmission path among the driver circuit 70, the comparator circuit 90, the performance board 100, and the device under test 120 according to the present embodiment. FIG. 3 shows an example of the configuration of the calibration unit 50. FIG. 4 shows an example of a processing flow in calibration of the test apparatus 10 according to the present embodiment. FIG. 5A shows examples of output set values, output correction values, offset values, and delay amount values. FIG. 5B shows examples of output set values, output correction values, offset values, and delay amount values. FIG. 5C shows examples of output setting values, output correction values, offset values, and delay amount values. FIG. 6A shows examples of measurement set values, measurement correction values, offset values, and delay amount values. FIG. 6B shows examples of measurement set values, measurement correction values, offset values, and delay amount values. FIG. 6C shows an example of measurement setting values, measurement correction values, offset values, and delay amount values. FIG. 7 shows another example of the configuration of the calibration unit 50. FIG. 8 shows a configuration of a test apparatus 10 according to a first modification of the present embodiment. FIG. 9 shows an example of the configuration of the calibration unit 50 according to the first modification of the present embodiment. FIG. 10 shows a hardware configuration of the computer 800.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows a configuration of a test apparatus 10 according to the present embodiment. The test apparatus 10 tests the device under test 120. The test apparatus 10 includes a timing generation unit 20, a pattern generation unit 30, a waveform shaping unit 40, a calibration unit 50, a replaceable performance board 100, a signal output unit 130, a signal measurement unit 140, and a comparison unit 150. As an example, the signal output unit 130 and the signal measurement unit 140 are connected to the common connection terminal 102 of the performance board 100. The device under test 120 is a semiconductor chip as an example.

  The timing generator 20 generates a timing signal that specifies the timing of outputting a test signal to the device under test 120, the cycle of the test signal, the edge timing, the timing of measuring the signal under measurement output from the device under test 120, and the like. To do. For example, when supplying a test signal to the device under test 120, the timing generator 20 sets the timing for outputting the test signal in the signal output unit 130. Further, when measuring the signal under measurement of the device under test 120, the timing generator 20 sets the timing (strobe timing) for measuring the signal under measurement in the signal measurement unit 140.

  The pattern generation unit 30 generates a logical pattern representing the logical pattern of the signal output from the signal output unit 130 and supplies the logical pattern to the waveform shaping unit 40. For example, when the device under test 120 is tested, the pattern generator 30 generates a logic pattern that represents the logic of a test signal supplied to the device under test 120. The pattern generator 30 also generates an expected value pattern indicating a logic pattern that the signal under measurement output from the device under test 120 should have.

  The waveform shaping unit 40 outputs a waveform signal corresponding to the input logical pattern. For example, the waveform shaping unit 40 has a voltage corresponding to the logic value of the input logic pattern and outputs a signal whose logic value transitions at a timing corresponding to the input timing signal.

  The signal output unit 130 outputs a test signal at a timing according to an output set value set by a user or the like. The signal output unit 130 includes a timing adjustment circuit 60 and a driver circuit 70. The timing adjustment circuit 60 delays the signal output from the waveform shaping unit 40 by a delay amount corresponding to the output set value and outputs the delayed signal. The timing generation unit 20 supplies the output setting value to the signal output unit 130.

  The driver circuit 70 supplies a signal output from the timing adjustment circuit 60 to the device under test 120. The driver circuit 70 may be a circuit that outputs a voltage corresponding to a logical value of an input signal. With such a configuration, the timing at which the signal output unit 130 outputs the test signal is adjusted according to the output set value.

  The performance board 100 mounts the device under test 120. On the performance board 100, a transmission path for connecting the connection terminal 102 and the device under test 120 is provided.

  The signal measuring unit 140 measures the signal under measurement output from the device under test 120 at a timing according to the measurement setting value set by the user or the like. The signal measurement unit 140 includes a timing adjustment circuit 80 and a comparator circuit 90. The comparator circuit 90 of this example measures the logical value of the signal under measurement at the edge timing of the input strobe signal Strb. The comparator circuit 90 may include a level comparator that converts the signal under measurement into a logic signal, and a timing comparator that samples the logic signal at the edge timing of the strobe signal. The timing generator 20 may generate a strobe signal.

  The timing adjustment circuit 80 delays the strobe signal by a delay amount corresponding to the measurement setting value set by the user or the like. The timing generation unit 20, the pattern generation unit 30, and the waveform shaping unit 40 may generate a strobe signal and supply it to the signal measurement unit 140. With such a configuration, the signal measuring unit 140 measures the signal under test output from the device under test 120 at a designated timing.

  The comparison unit 150 compares whether the logical value of the signal under test of the device under test 120 measured by the signal measurement unit 140 matches the expected value generated by the pattern generation unit 30. Further, the comparison unit 150 may compare whether or not the logical value of the logical signal measured by the signal measurement unit 140 and the expected value generated by the pattern generation unit 30 match in a calibration operation described later. .

  With the configuration described above, a test signal can be output at a designated timing, and a signal under measurement can be measured at a designated timing. However, the test signal and the signal under measurement are delayed due to the signal delay in the transmission path between the signal output unit 130 and the signal measurement unit 140 and the device under test 120. The calibration unit 50 calculates a correction value that compensates for the delay in the transmission path, and corrects the output setting value and the measurement setting value described above. As a result, the timing for inputting the test signal to the device under test 120 and the timing for measuring the signal under measurement are accurately controlled.

  The calibration unit 50 is based on signal delay times in the first transmission path A and the second transmission path B, one of which includes the other in the signal transmission path between the signal output unit 130 and the device under test 120. The output correction value for correcting the output set value is set. The calibration unit 50 is based on signal delay times in the third transmission path C and the fourth transmission path D, one of which includes the other in the signal transmission path between the device under test 120 and the signal measurement unit 140. The measurement correction value for correcting the measurement setting value is set.

  FIG. 2 shows an example of a transmission path among the driver circuit 70, the comparator circuit 90, the performance board 100, and the device under test 120 according to the present embodiment. The first signal transmission path A is a transmission path between the signal output unit 130 and the connection terminal 102, and may not include the transmission path on the performance board 100. The second signal transmission path B is a transmission path between the signal output unit 130 and the device under test 120, and may include the first transmission path A and the transmission path on the performance board 100. The first transmission path A may be included in the second transmission path B. In this example, the transmission path from the output terminal of the driver circuit 70 to the input terminal of the device under test 120 is a second transmission path B. The second transmission path B is connected to the input terminal of the comparator circuit 90. A transmission path from the connection point to the output end of the driver circuit 70 is a first transmission path A.

  The third signal transmission path C is a transmission path between the connection terminal 102 and the signal measuring unit 140 and does not have to include the transmission path on the performance board 100. The fourth signal transmission path D is a transmission path between the device under test 120 and the signal measuring unit 140, and may include a third transmission path C and a transmission path on the performance board 100. The third transmission path C may be included in the fourth transmission path D. A transmission path from the connection point to the input end of the comparator circuit 90 is a third transmission path C. A transmission path from the output end of the device under test 120 to the input end of the comparator circuit 90 is a fourth transmission path D.

  FIG. 3 shows a configuration of the calibration unit 50 according to the present embodiment. The calibration unit 50 includes a correction unit 300, a first addition / subtraction unit 400, and a setting unit 200.

  The correction unit 300 can set the output correction value (DrCal) within a predetermined settable range, and adds or subtracts the set output correction value (DrCal) to the output set value (DrClock). Further, the correction unit 300 can further set the measurement correction value (StrbCal) within a predetermined settable range, and adds or subtracts the set measurement correction value (StrbCal) to the measurement setting value (Strb).

  The correction unit 300 includes an addition circuit 320 corresponding to the signal output unit 130 and an addition circuit 330 corresponding to the signal measurement unit 140. The adder circuit 320 adds the set output correction value (DrCal) and the output set value (DrClock), and outputs the result to the first addition / subtraction unit 400. The addition circuit 330 adds the set measurement correction value (StrbCal) and the measurement set value (Strb), and outputs the result to the first addition / subtraction unit 400.

  The first addition / subtraction unit 400 stores an offset value with respect to the output setting value (DrClock) and the measurement setting value (Strb), and the stored offset value is used as the corresponding output setting value (DrClock) and the measurement setting value (Strb). Add and subtract. The first addition / subtraction unit 400 may include a variable subtracter 420 corresponding to the signal output unit 130 and a variable adder 430 corresponding to the signal measurement unit 140.

  The variable subtractor 420 subtracts the offset value for the output setting value from the output setting value (DrClock) and outputs the result to the timing adjustment circuit 60. The variable adder 430 adds an offset value for the measurement setting value to the measurement setting value (Strb), and outputs the result to the timing adjustment circuit 80.

  The setting unit 200 calculates a first output correction value that compensates for the signal delay time in the first transmission path A. In addition, the setting unit 200 calculates a first measurement correction value that compensates for the signal delay time in the third transmission path C.

  For example, the setting unit 200 causes the driver circuit 70 to output a reference signal whose logic value transitions at a predetermined timing, and causes the comparator circuit 90 to measure the reference signal. At this time, until the comparator circuit 90 detects the transition of the logic value in the reference signal, the output timing setting value of the driver circuit 70 or the setting value of the strobe timing of the comparator circuit 90 is gradually changed. The signal delay in the transmission path A and the third transmission path C can be measured.

  As an example, first, the setting unit 200 sets an output correction value and a measurement correction value using the median value of each setting allowable range as a starting point. When the logical value measured in the comparator circuit 90 is the logical value before the transition, the setting unit 200 sequentially subtracts the predetermined value from the output correction value and sequentially adds the predetermined value to the measurement correction value. Repeat the measurement. Then, the correction values when the comparator circuit 90 measures the logical value after the transition are set as the first output correction value and the first measurement correction value.

  When the first logical value measured in the comparator circuit 90 is the logical value after the transition, the setting unit 200 sequentially adds a predetermined value to the output correction value, and sequentially adds the predetermined value from the measurement correction value. Subtract and repeat measurement. Then, the correction values when the comparator circuit 90 measures the logical value before the transition are set as the first output correction value and the first measurement correction value.

  Next, the setting unit 200 sets the difference between the reference value within the settable range in the correction unit 300 and the first output correction value in the first addition / subtraction unit 400 as an offset value. Further, the setting unit 200 sets the difference between the reference value within the settable range in the correction unit 300 and the first measurement correction value in the first addition / subtraction unit 400 as an offset value with respect to the measurement setting value. At this time, the setting unit 200 may set the difference between the reference value and the first output correction value in the variable subtracter 420 as an offset value. The setting unit 200 may set the difference between the reference value and the first measurement correction value in the variable adder 430 as an offset value.

  The reference value may be an upper limit value, a lower limit value, a median value, or the like in the settable range. The setting unit 200 may use the reference value corresponding to the first output correction value as the upper limit value of the settable range. The setting unit 200 may use the reference value corresponding to the first measurement correction value as the lower limit value of the settable range.

  At this time, the setting unit 200 may set each reference value in the correction unit 300 as an output correction value. Next, the setting unit 200 calculates a second output correction value that compensates for the signal delay time in the second transmission path B using the above-described reference value as a reference, and sets the second output correction value in the correction unit 300. The setting unit 200 calculates a second measurement correction value that compensates for the signal delay time in the fourth transmission path D, using the reference value for the first measurement correction value as a reference, and sets the second measurement correction value in the correction unit 300.

  The setting unit 200 may measure the correction value that compensates for the signal delay time in the second transmission path B and the fourth transmission path D in the same manner as the first transmission path A and the third transmission path C. In this case, the comparator circuit 90 may measure the signal output from the driver circuit 70 and reflected from the device under test 120. In this case, the setting unit 200 may gradually change each correction value from the reference value described above.

  The signal delay times in the second transmission path B and the fourth transmission path D may be measured in advance and set in the setting unit 200. Since the signal delay time is mostly the delay time in the performance board 100, the signal delay time may be set in the setting unit 200 for each performance board 100. In this case, the setting unit 200 adds or subtracts a value corresponding to the set signal delay time from the above-described reference value.

  When the performance board 100 is replaced, the first addition / subtraction unit 400 may maintain the offset value for the output setting value and the measurement setting value stored before the performance board 100 is replaced. In this case, the setting unit 200 calculates each of the second output correction value and the second measurement correction value calculated for the new performance board connected after replacement by using the corresponding reference value as a reference, and the correction unit 300. You may set a new one. The setting unit 200 can measure the second output correction value and the second measurement correction value after replacing the performance board 100 in the same manner as described above.

  As an example, the first addition / subtraction unit 400 is connected between the correction unit 300 and the signal output unit 130. As another example, the correction unit 300 may be connected between the setting unit 200 and the first addition / subtraction unit 400. As another example, the first addition / subtraction unit 400 may be connected to a terminal that inputs an output set value to the correction unit 300.

  FIG. 4 shows a processing flow in calibration of the test apparatus 10 according to the present embodiment. 5A, FIG. 5B, and FIG. 5C show the output setting value (DrClock), the output correction value (DrCal), the offset value of the variable subtractor 420, and the timing adjustment circuit 60 that are set by the setting unit 200 in the processing flow of FIG. An example of the value of the delay amount (DrVd) in FIG. 6A, 6B and 6C show the measurement setting value (Strb), the measurement correction value (StrbCal) set by the setting unit 200, the offset value of the variable adder 430, and the timing adjustment circuit 80 in the processing flow of FIG. An example of the value of the delay amount (StrbVd) in FIG. The calibration process flow will be described below.

  In step S10 of FIG. 4, the setting unit 200 calculates the first output correction value and the first measurement correction value that compensate for the signal delay time in the first transmission path A and the third transmission path C as described above. To do. The setting unit 200 may set the calculated first output correction value in the adding circuit 320. The setting unit 200 may set the calculated first measurement correction value in the adding circuit 330.

  The setting unit 200 sets the output correction value in the correction unit 300 within a predetermined settable range. At this time, the setting unit 200 may set a first output correction value (DrCal) that compensates for the delay time in the first transmission path A between the upper limit and the lower limit in the adding circuit 320. The setting unit 200 may set the output setting value (DrClock) in the addition circuit 320 in advance between the upper limit and the lower limit of the output setting value.

  5A shows an output set value (DrClock), an output correction value (DrCal), an offset value set in the variable subtractor 420, and a delay in the timing adjustment circuit 60 set by the setting unit 200 in step S10 of FIG. An example of the value of quantity (DrVd) is shown. In this example, the setting unit 200 can set the output correction value (DrCal) in the addition circuit 320 between the upper limit value 20 and the lower limit value 0. The setting unit 200 may set the output setting value (DrClock) in the addition circuit 320 in advance between the upper limit value 100 and the lower limit value 0. The upper limit value and the lower limit value are DA values, which are numerical values without units.

  FIG. 5A shows an example in which the setting unit 200 sets the output set value (DrClock) to 50, the first output correction value (DrCal) to 10, and the offset value of the variable subtractor 420 to 0. In this example, the addition circuit 320 adds 10 of the first output correction value (DrCal) to 50 of the output set value (DrClock) and outputs the result to the variable subtractor 420. The variable subtracter 420 subtracts 0 of the set offset value from the value input from the adder circuit 320 and sets the delay amount (DrVd) of the timing adjustment circuit 60 to 60. Here, the output set value, the first output correction value, the offset value, and the delay amount are DA values and are unitless numerical values.

  The setting unit 200 may set the measurement correction value within a settable range predetermined in the correction unit 300. At this time, the setting unit 200 may set a third measurement correction value (StrbCal) that compensates for the delay time in the third transmission path C between the upper limit and the lower limit in the adder circuit 330. The setting unit 200 may set the measurement setting value (Strb) in the addition circuit 330 in advance between the upper limit and the lower limit of the measurement setting value.

  6A shows the measurement set value (Strb), the measurement correction value (StrbCal), the offset value set in the variable adder 430, and the delay amount (StrbVd) set by the setting unit 200 in step S10. ) Shows an example of the value. In this example, the setting unit 200 can set the measurement correction value (StrbCal) in the adder circuit 330 between the upper limit value 20 and the lower limit value 0. The setting unit 200 may set the measurement setting value (Strb) in the addition circuit 330 in advance between the upper limit value 100 and the lower limit value 0. The upper limit value and the lower limit value are DA values, which are numerical values without units.

  FIG. 6A shows an example in which the setting unit 200 sets the measurement set value (Strb) to 50, the first measurement correction value (StrbCal) to 10, and the offset value of the variable adder 430 to zero. In this example, the addition circuit 330 adds 10 of the first measurement correction value (StrbCal) to 50 of the measurement set value (Strb) and outputs the result to the variable adder 430. The variable adder 430 adds the set offset value 0 to the value input from the adder circuit 330 and sets the delay amount (StrbVd) of the timing adjustment circuit 80 to 60. Here, the measurement set value, the first measurement correction value, the offset value, and the delay amount are DA values and are unitless numerical values.

  In step S20 of FIG. 4, the setting unit 200 sets the difference between the reference value within the settable range of the output correction value and the first output correction value in the first addition / subtraction unit 400 as an offset value with respect to the output set value. The setting unit 200 may set the difference between the reference value within the settable range of the measurement correction value and the first measurement correction value in the first addition / subtraction unit 400 as an offset value with respect to the measurement setting value.

  In step S30 of FIG. 4, the setting unit 200 sets the output correction value of the correction unit 300 to a reference value within the settable range. The setting unit 200 may set the measurement correction value of the correction unit 300 to a reference value within a settable range.

  In the example of FIG. 5A, the setting unit 200 sets 20 as the upper limit value of the output correction value (DrCal) that can be set in the adding circuit 320 as a reference value. In the example of FIG. 6A, the setting unit 200 sets 0 as the lower limit value of the measurement correction value (StrbCal) that can be set in the addition circuit 330 as a reference value.

  5B shows the output setting value (DrClock), the output correction value (DrCal), the offset value set in the variable subtractor 420, and the timing adjustment circuit 60 set by the setting unit 200 in steps S20 and S30 of FIG. Shows an example of the value of the delay amount (DrVd). In this example, the setting unit 200 sets -10, which is a difference between the reference value 20 and the first output correction value 10, to the variable subtractor 420 as an offset value (S20).

  In addition, the setting unit 200 sets the output correction value (DrCal) of the correction unit 300 to the reference value 20 (S30). The variable subtracter 420 subtracts 10 from the value 70 input from the adder circuit 320 corresponding to the set offset value −10, and sets the delay amount (DrVd) of the timing adjustment circuit 60 to 60. .

  6B shows the measurement setting value (Strb), the measurement correction value (StrbCal), the offset value set in the variable adder 430, and the timing adjustment circuit 80 set by the setting unit 200 in steps S20 and S30 of FIG. An example of the value of the delay amount (StrbVd) in FIG. In this example, the setting unit 200 sets the difference adder 430 as 10 as the difference between 0 as the reference value and 10 as the first measurement correction value (S20).

  The setting unit 200 sets the output correction value (DrCal) to 0, which is the lower limit value of the settable range (S30). The variable adder 430 adds the set offset value 10 to the value 50 input from the adder circuit 320 and sets the delay amount (StrbVd) of the timing adjustment circuit 80 to 60.

  In step S40 of FIG. 4, the setting unit 200 calculates a second output correction value that compensates for the signal delay time in the second transmission path B with reference to a reference value within a settable range of the output correction value. The setting unit 200 may calculate the second measurement correction value that compensates for the signal delay time in the fourth transmission path D with reference to a reference value within a settable range of the measurement correction value.

  For example, the setting unit 200 measures the correction value that compensates for the signal delay time in the second transmission path B and the fourth transmission path D as described above. At this time, the second transmission path B and the fourth transmission path D may include transmission paths on the performance board 100.

  In addition, the setting unit 200 calculates the second output correction value by adding or subtracting the correction value for compensating the signal delay time in the second transmission path B to the reference value of the output correction value set in the correction unit 300. At this time, when the second transmission path B is longer than the first transmission path A and the correction value for compensating for the signal delay time in the second transmission path B is measured as a negative value, the setting unit 200 corrects the correction. The second output correction value may be calculated by subtracting the value from the reference value of the output set value.

  Further, the setting unit 200 calculates the second measurement correction value by adding or subtracting the correction value for compensating the signal delay time in the fourth transmission path D to the reference value of the measurement correction value set in the correction unit 300. Good. At this time, when the fourth transmission path D is longer than the third transmission path C and the correction value that compensates for the signal delay time in the fourth transmission path D is measured as a positive value, the setting unit 200 The second measurement correction value may be calculated by adding the correction value to the reference value of the measurement correction value.

  In step S50 of FIG. 4, the setting unit 200 determines whether or not the second output correction value is a value within a settable range of the output correction value of the correction unit 300. The setting unit 200 determines whether the second measurement correction value is a value within a settable range of the correction unit 300.

  The setting unit 200 may determine that the second output correction value is within a settable range if the second output correction value is not less than the lower limit value and not more than the upper limit value of the output correction value (DrCal) that can be set in the correction unit 300. . The setting unit 200 may calculate a difference between the lower limit value or the upper limit value and the second output correction value when the second output correction value is smaller than the lower limit value or larger than the upper limit value.

  If the second measurement correction value is not less than the lower limit value and not more than the upper limit value of the measurement correction value (StrbCal) that can be set in the correction unit 300, the setting unit 200 determines that the value is within the settable range. Good. The setting unit 200 may calculate a difference between the lower limit value or the upper limit value and the second measurement correction value when the second measurement correction value is smaller than the lower limit value or larger than the upper limit value.

  The setting unit 200 proceeds to step S70 of FIG. 4 if the second output correction value and the second measurement correction value are within a range that can be set in the correction unit 300, and proceeds to step S60 if not within the settable range. .

  In step S60 of FIG. 4, the user of the test apparatus sets a value (DrOffset) for adjusting the output timing of the test signal. Thus, the user can set the output set value (DrClock) to a value obtained by adding or subtracting a value (DrOffset) for adjusting the output timing of the test signal to the original value.

  The user sets a value (StrbOffset) for adjusting the timing of measuring the signal under measurement. Thus, the user can set the measurement set value (Strb) to the original value and a value obtained by adding / subtracting the value (StrbOffset) for adjusting the timing of measuring the signal under measurement.

  Thereafter, the process proceeds to step S40, where the setting unit 200 uses the output setting value (DrClock) and the measurement setting value (Strb) set in step S60 to obtain the second output correction value and the second measurement correction value as described above. Thus, it can be calculated.

  In step S70 of FIG. 4, the second output correction value and the second measurement correction value are set in the correction unit 300, and the calibration is completed.

  The first transmission path A and the third transmission path C may not include the transmission path on the performance board 100. Even if the performance board 100 is replaced, the first addition / subtraction unit 400 may maintain the value stored as the offset value before the performance board 100 is replaced. In this case, in the calibration after replacing the performance board 100, the steps S10, S20, and 30 may be omitted and the process may start from step S40.

  As an example, when the second output correction value calculated in the state of FIG. 5B is −5 (S40), the user sets a value (DrOffset) for adjusting the timing of outputting the test signal to −5. (S60). Thereby, the user of the test apparatus can set the output setting (DrClock) to 45, which is a value obtained by subtracting the value (DrOffset) for adjusting the timing of outputting the test signal from the original value 50. .

  For example, when the second measurement correction value calculated in the state of FIG. 6B is 25 (S40), the user sets a value (StrbOffset) for adjusting the timing of measuring the signal under measurement to 5 as an example. (S60). Accordingly, the user of the test apparatus sets the measurement set value (Strb) to 55, which is a value obtained by adding the original value 50 and the value (StrbOffset) for adjusting the timing of measuring the signal under measurement. be able to.

  5C, the setting unit 200 sets the output setting value (DrClock) to 50, the second output setting value (DrCal) to 5, and the offset value of the variable subtracter 420 to −10 in step S70 of FIG. An example of setting is shown below. This example corresponds to the case where the setting unit 200 measures the correction value for compensating the signal delay time in the second transmission path B as −15 (S40) in the state of FIG. 5B. In this example, similarly to the above, the variable subtractor 420 subtracts 10 from the value 55 input from the adder circuit 320 in accordance with the set offset value −10, and delays the timing adjustment circuit 60. The quantity (DrVd) is set to 45.

  6C, the setting unit 200 sets the measurement setting value (Strb) to 50, the second measurement correction value (StrbCal) to 15, and the offset value of the variable adder 430 to 10 in step S70 of FIG. An example of setting is shown. This example corresponds to the case where the setting unit 200 measures the correction value for compensating the signal delay time in the fourth transmission path D as 15 (S40) in the state of FIG. 6B. In this example, similarly to the above, the variable adder 430 adds the set offset value 10 to the value 65 input from the adder circuit 330, and sets the delay amount (StrbVd) of the timing adjustment circuit 80. Set to 75.

  FIG. 7 shows another configuration of the calibration unit 50. The calibration unit 50 may include a correction unit 300, a first addition / subtraction unit 400, a second addition / subtraction unit 500, and a setting unit 200.

  The setting unit 200 calculates the second output correction value as described above. The setting unit 200 determines whether or not the calculated second output correction value is a value within a range that can be set in the correction unit 300. When the setting unit 200 determines that the second output correction value is outside the settable range of the correction unit 300, the setting unit 200 may set a predetermined offset value in the second addition / subtraction unit 500. In this case, the setting unit 200 may set a second output correction value obtained by adding the offset value to the second output correction value determined to be outside the settable range in the correction unit 300.

  The setting unit 200 calculates the second measurement correction value as described above. The setting unit 200 determines whether the calculated second measurement correction value is a value within a range that can be set in the correction unit 300. The setting unit 200 may set a predetermined offset value in the second addition / subtraction unit 500 when it is determined that the second measurement correction value is outside the settable range of the correction unit 300. In this case, the setting unit 200 may set, in the correction unit 300, a second measurement correction value obtained by subtracting the offset value from the second measurement correction value determined to be outside the settable range.

  The second addition / subtraction unit 500 stores an offset value for the output setting value and the measurement setting value, respectively. The second addition / subtraction unit 500 may set the timing adjustment circuit 60 by adding / subtracting the offset value stored corresponding to the output set value to / from the output set value. The second addition / subtraction unit 500 may set the timing adjustment circuit 80 by adding / subtracting the offset value stored corresponding to the measurement setting value to / from the measurement setting value.

  The second adder / subtractor 500 may include a second variable subtracter 520 corresponding to the signal output unit and a second variable adder 530 corresponding to the signal measuring unit 140. The second variable subtracter 520 may subtract an offset value for the output set value from the output set value (DrCal) and output the result to the timing adjustment circuit 60. The second variable adder 530 may add an offset value for the measurement correction value to the measurement set value (Strb) and output the result to the timing adjustment circuit 80.

  The first addition / subtraction unit 400 may store an offset value for the output setting value and the measurement setting value, respectively. Further, the first addition / subtraction unit 400 adds / subtracts the offset value for the stored output setting value and measurement setting value to the corresponding output setting value and measurement setting value. The first addition / subtraction unit 400 may include a variable subtracter 420 corresponding to the signal output unit and a variable adder 430 corresponding to the signal measurement unit 140. The variable subtractor 420 may subtract an offset value for the output set value from the output set value (DrCal) and output the result to the second variable subtracter 520. The variable adder 430 may add an offset value for the measurement correction value to the measurement set value (Strb) and output the result to the second variable adder 530.

  The setting unit 200 stores the difference between the upper limit value and the lower limit value of the output correction value that can be set in the correction unit 300 as a predetermined offset value that is set in the second addition / subtraction unit 500 corresponding to the output correction value. It's okay.

  The setting unit 200 may store a plurality of types of values as predetermined offset values set in the second addition / subtraction unit. In this case, the setting unit 200, in order from the small offset value, adds the second output correction value to the second addition / subtraction unit when the second output correction value becomes a value within a settable range in addition to the second output correction value. 500, the second output correction value may be set in the correction unit 300.

  The setting unit 200 stores the difference between the upper limit value and the lower limit value of the measurement correction value that can be set in the correction unit 300 as a predetermined offset value that is set in the second addition / subtraction unit 500 corresponding to the set correction value. It's okay.

  The setting unit 200 may store a plurality of types of values as predetermined offset values set in the second addition / subtraction unit. In this case, the setting unit 200 subtracts the offset value from the second measurement correction value in order from the smallest offset value, and when the second measurement correction value becomes a value within a settable range, 500, and the second measurement correction value may be set in the correction unit 300.

  FIG. 8 shows another configuration of the test apparatus 10. The test apparatus 10 tests the device under test 120. The test apparatus 10 includes a timing generation unit 20, a pattern generation unit 30, a waveform shaping unit 40, a calibration unit 50, a replaceable performance board 100, a plurality of signal output units 130, a plurality of signal measurement units 140, and a comparison unit 150. Is provided. Here, the test apparatus 10 includes a plurality of signal output units 130 and a plurality of signal measurement units 140 in parallel. The device under test 120 is a semiconductor chip as an example.

  The plurality of signal output units 130 each output a test signal corresponding to an output set value set by a user or the like. Each of the plurality of signal output units 130 includes a timing adjustment circuit 60 and a driver circuit 70. The plurality of timing adjustment circuits 60 delay the signals output from the waveform shaping unit 40 by a delay amount corresponding to the output set value set in each timing adjustment circuit 60 and output the delayed signals. The timing generation unit 20 supplies the output setting value to each signal output unit 130. The plurality of driver circuits 70 supply signals output from the respective timing adjustment circuits 60 to the device under test 120.

  The plurality of signal measuring units 140 measure the signals under measurement output from the device under test 120 at timings corresponding to the measurement setting values set by the user. Each of the plurality of signal measurement units 140 includes a timing adjustment circuit 80 and a comparator circuit 90. The plurality of comparator circuits 90 measure the logical value of the signal under measurement at the edge timing of the strobe signal Strb input to each comparator circuit 90. The plurality of timing adjustment circuits 80 delay the strobe signal by a delay amount corresponding to a measurement correction value set by the user or the like in each timing adjustment circuit 80.

  FIG. 9 shows a configuration of the calibration unit 50 included in the test apparatus 10 shown in FIG. The calibration unit 50 includes a setting unit 200. The setting unit 200 includes a correction unit 300 for each of the signal output units 130 and the signal measurement units 140, and the first addition / subtraction unit 400 for the plurality of signal output units 130 and the plurality of signal measurement units 140. May have in common.

  The setting unit 200 may detect the first output correction value closest to the upper limit value of the settable range among the first output correction values for the respective signal output units 130. The setting unit 200 may set a difference between the first output correction value closest to the upper limit value of the settable range and the upper limit value in the first addition / subtraction unit 400. The setting unit 200 sets the second output correction value for each signal output unit 130 in the corresponding correction unit 300 based on the value obtained by adding the difference from the upper limit value to the corresponding first output correction value. It's okay.

  The setting unit 200 may detect the first measurement correction value closest to the lower limit value of the settable range among the first measurement correction values for the respective signal measurement units 140. The setting unit 200 may set a difference between the first measurement correction value closest to the lower limit value of the settable range and the lower limit value in the first addition / subtraction unit 400. The setting unit 200 sets the second measurement correction value for each signal measurement unit 140 in the corresponding correction unit 300 with reference to a value obtained by subtracting the difference from the lower limit value from the corresponding first measurement correction value. It's okay.

  Each correction unit 300 includes an addition circuit 320 corresponding to the signal output unit 130 and an addition circuit 330 corresponding to the signal measurement unit 140. Each addition circuit 320 adds the set output correction value (DrCal) and the output set value (DrClock), and outputs the result to the first addition / subtraction unit 400. Each addition circuit 330 adds the set measurement correction value (StrbCal) and the measurement set value (Strb), and outputs the result to the first addition / subtraction unit 400.

  The first addition / subtraction unit 400 stores an offset value for the output setting value (DrClock) and the measurement setting value (Strb), and stores the offset value for the stored output setting value in the output setting value (DrClock). Is added to or subtracted from the measurement setting value (Strb). The first addition / subtraction unit 400 may include a variable subtracter 420 corresponding to the plurality of signal output units 130 and a variable adder 430 corresponding to the plurality of signal measurement units 140.

  The variable subtracter 420 subtracts the offset value from the output set value (DrClock) and outputs the result to the corresponding timing adjustment circuit 60. The variable adder 430 adds the offset value to the measurement set value (Strb) and outputs the result to the corresponding timing adjustment circuit 80.

  FIG. 10 shows an example of a hardware configuration of the computer 800. The computer 800 functions as the setting unit 200 described with reference to FIGS. 1 to 9 according to a given program.

  The computer 800 according to the present embodiment is connected to the CPU peripheral unit including the CPU 2000, the RAM 2020, the graphic controller 2075, and the display device 2080 that are connected to each other by the host controller 2082, and the host controller 2082 by the input / output controller 2084 Input / output unit having communication interface 2030, hard disk drive 2040, and CD-ROM drive 2060, and legacy input / output unit having ROM 2010, flexible disk drive 2050, and input / output chip 2070 connected to input / output controller 2084 With.

  The host controller 2082 connects the RAM 2020 to the CPU 2000 and the graphic controller 2075 that access the RAM 2020 at a high transfer rate. The CPU 2000 operates based on programs stored in the ROM 2010 and the RAM 2020 and controls each unit. The graphic controller 2075 acquires image data generated by the CPU 2000 or the like on a frame buffer provided in the RAM 2020 and displays it on the display device 2080. Instead of this, the graphic controller 2075 may include a frame buffer for storing image data generated by the CPU 2000 or the like.

  The input / output controller 2084 connects the host controller 2082 to the communication interface 2030, the hard disk drive 2040, and the CD-ROM drive 2060, which are relatively high-speed input / output devices. The communication interface 2030 communicates with other devices via a network. The hard disk drive 2040 stores programs and data used by the CPU 2000 in the computer 800. The CD-ROM drive 2060 reads a program or data from the CD-ROM 2095 and provides it to the hard disk drive 2040 via the RAM 2020.

  The input / output controller 2084 is connected to the ROM 2010, the flexible disk drive 2050, and the relatively low-speed input / output device of the input / output chip 2070. The ROM 2010 stores a boot program that the computer 800 executes at startup and / or a program that depends on the hardware of the computer 800. The flexible disk drive 2050 reads a program or data from the flexible disk 2090 and provides it to the hard disk drive 2040 via the RAM 2020. The input / output chip 2070 connects the flexible disk drive 2050 to the input / output controller 2084 and inputs / outputs various input / output devices via, for example, a parallel port, a serial port, a keyboard port, a mouse port, and the like. Connect to controller 2084.

  A program provided to the hard disk drive 2040 via the RAM 2020 is stored in a recording medium such as the flexible disk 2090, the CD-ROM 2095, or an IC card and provided by the user. The program is read from the recording medium, installed in the hard disk drive 2040 in the computer 800 via the RAM 2020, and executed by the CPU 2000.

  The program installed in the computer 800 and causing the computer 800 to function as the setting unit 200 includes at least one of an image generation module, an image processing module, an arrangement direction control module, and a mode switching module. These programs or modules work on the CPU 2000 or the like to cause the computer 800 to function as the setting unit 200, respectively.

  Information processing described in these programs functions as the setting unit 200, which is a specific means in which the software and the various hardware resources described above cooperate with each other when read by the computer 800. And the specific setting part 200 according to the intended use is constructed | assembled by implement | achieving the calculation or processing of the information according to the intended use of the computer 800 in this embodiment by these specific means.

  As an example, when communication is performed between the computer 800 and an external device or the like, the CPU 2000 executes a communication program loaded on the RAM 2020, and based on the processing contents described in the communication program, the communication interface A communication process is instructed to 2030. Under the control of the CPU 2000, the communication interface 2030 reads transmission data stored in a transmission buffer area or the like provided on a storage device such as the RAM 2020, the hard disk drive 2040, the flexible disk 2090, or the CD-ROM 2095, and sends it to the network. The reception data transmitted or received from the network is written into a reception buffer area or the like provided on the storage device. As described above, the communication interface 2030 may transfer transmission / reception data to / from the storage device by a DMA (direct memory access) method. Instead, the CPU 2000 transfers the storage device or the communication interface 2030 as a transfer source. The transmission / reception data may be transferred by reading the data from the data and writing the data to the communication interface 2030 or the storage device of the transfer destination.

  The CPU 2000 is all or necessary from among files or databases stored in an external storage device such as a hard disk drive 2040, a CD-ROM drive 2060 (CD-ROM 2095), and a flexible disk drive 2050 (flexible disk 2090). This portion is read into the RAM 2020 by DMA transfer or the like, and various processes are performed on the data on the RAM 2020. Then, CPU 2000 writes the processed data back to the external storage device by DMA transfer or the like. In such processing, since the RAM 2020 can be regarded as temporarily holding the contents of the external storage device, in the present embodiment, the RAM 2020 and the external storage device are collectively referred to as a memory, a storage unit, or a storage device.

  Various types of information such as various programs, data, tables, and databases in the present embodiment are stored on such a storage device and are subjected to information processing. Note that the CPU 2000 can also store a part of the RAM 2020 in the cache memory and perform reading and writing on the cache memory. Even in such a form, the cache memory bears a part of the function of the RAM 2020. Therefore, in the present embodiment, the cache memory is also included in the RAM 2020, the memory, and / or the storage device unless otherwise indicated. To do.

  In addition, the CPU 2000 performs various operations, such as various operations, information processing, condition determination, information search / replacement, etc., described in the present embodiment, specified for the data read from the RAM 2020 by the instruction sequence of the program. Is written back to the RAM 2020. For example, when performing the condition determination, the CPU 2000 determines whether the various variables shown in the present embodiment satisfy the conditions such as large, small, above, below, equal, etc., compared to other variables or constants. When the condition is satisfied (or not satisfied), the program branches to a different instruction sequence or calls a subroutine.

  Further, the CPU 2000 can search for information stored in a file or database in the storage device. For example, in the case where a plurality of entries in which the attribute value of the second attribute is associated with the attribute value of the first attribute are stored in the storage device, the CPU 2000 displays the plurality of entries stored in the storage device. The entry that matches the condition in which the attribute value of the first attribute is specified is retrieved, and the attribute value of the second attribute that is stored in the entry is read, thereby associating with the first attribute that satisfies the predetermined condition The attribute value of the specified second attribute can be obtained.

  The program or module shown above may be stored in an external recording medium. As the recording medium, in addition to the flexible disk 2090 and the CD-ROM 2095, an optical recording medium such as DVD or CD, a magneto-optical recording medium such as MO, a tape medium, a semiconductor memory such as an IC card, and the like can be used. Further, a storage device such as a hard disk or a RAM provided in a server system connected to a dedicated communication network or the Internet may be used as a recording medium, and the program may be provided to the computer 800 via the network.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

10 test devices, 20 timing generation units, 30 pattern generation units, 40 waveform shaping units, 50 calibration units, 60 timing adjustment circuits, 70 driver circuits, 80 timing adjustment circuits, 90 comparator circuits, 100 performance boards, 102 connection terminals, 120 device under test, 130 signal output unit, 140 signal measurement unit, 150 comparison unit, 200 setting unit, 300 correction unit, 320 addition circuit, 330 addition circuit, 400 first addition / subtraction unit, 420 variable subtractor, 430 variable adder , 500 Second adder / subtractor, 800 computer, 2000 CPU, 2010 ROM, 2020 RAM, 2030 communication interface, 2040 hard disk drive, 2050 flexible disk drive, 2060 CD-R M Drive, 2070 output chip, 2075 graphic controller, 2080 a display device, 2082 host controller 2084 output controller, 2090 a flexible disk, 2095 CD-ROM

Claims (10)

A test apparatus for testing a device under test,
A signal output unit for outputting a test signal at a timing according to the output set value;
In the signal transmission path between the signal output unit and the device under test, the output setting value is corrected based on the signal delay time in each of the first transmission path and the second transmission path, one of which includes the other. A calibration unit for setting the output correction value, and
The calibration unit
A correction unit capable of setting the output correction value within a predetermined settable range, and adding or subtracting the set output correction value to or from the output set value;
A first addition / subtraction unit for adding / subtracting the stored offset value to / from the output set value;
A first output correction value that compensates for the signal delay time in the first transmission path is calculated, and a difference between a reference value within the settable range and the first output correction value is used as the offset value, and the first addition / subtraction unit And a setting unit that calculates a second output correction value that compensates for the signal delay time in the second transmission path based on the reference value and sets the second output correction value in the correction unit. The first transmission path is included in the second transmission path;
The setting unit sets the offset value of the first output correction value with respect to the upper limit value of the settable range in the first addition / subtraction unit, and the second output correction calculated based on the upper limit value of the settable range The test apparatus according to claim 1, wherein a value is set in the correction unit. A signal measurement unit that measures the signal under measurement output from the device under test at a timing according to a measurement setting value;
In the signal transmission path between the device under test and the signal measurement unit, the calibration unit is based on the signal delay time in each of the third transmission path and the fourth transmission path, one of which includes the other, Set the measurement correction value to correct the measurement setting value,
The correction unit can further set the measurement correction value within a predetermined settable range, and adds or subtracts the set measurement correction value to the measurement set value,
The first addition / subtraction unit stores the offset value for each of the output setting value and the measurement setting value,
The setting unit calculates a first measurement correction value that compensates for the signal delay time in the third transmission path, and calculates a difference between a reference value within the settable range and the first measurement correction value as the measurement setting. A second measurement correction value that is set in the first addition / subtraction unit as the offset value with respect to a value and compensates for the signal delay time in the fourth transmission path is calculated based on the reference value with respect to the first measurement correction value The test apparatus according to claim 2, which is set in the correction unit. The third transmission path is included in the fourth transmission path;
The setting unit sets the offset value of the first measurement correction value with respect to the lower limit value of the settable range in the first addition / subtraction unit, and calculates the second measurement correction calculated based on the lower limit value of the settable range. The test apparatus according to claim 3, wherein a value is set in the correction unit. The device under test is placed and further provided with a performance board that can be replaced,
The test apparatus according to any one of claims 2 to 4, wherein the first transmission path does not include a transmission path on the performance board, and the second transmission path includes a transmission path on the performance board. The setting unit maintains the offset value stored by the first addition / subtraction unit when the performance board is replaced, and sets the second output correction value calculated for the new performance board as the reference The test apparatus according to claim 5, wherein a value is used as a reference and newly set in the correction unit. A second addition / subtraction unit for adding / subtracting the stored offset value to / from the output set value;
The setting unit sets a predetermined offset value in the second addition / subtraction unit when the calculated second output correction value is outside the settable range of the correction unit, and sets the offset value to the second addition / subtraction unit. The test apparatus according to claim 6, wherein the added second output correction value is set in the correction unit. A plurality of the signal output units are provided in parallel,
The calibration unit
The correction unit is provided for each of the signal output units,
The first addition / subtraction unit is commonly used for a plurality of the signal output units,
The setting unit calculates a difference between the first output correction value closest to the upper limit value of the settable range and the first addition / subtraction among the first output correction values for the respective signal output units. The second output correction value for each of the signal output units is set in the corresponding correction unit with reference to a value obtained by adding the difference to the corresponding first output correction value. To 7. The test apparatus according to any one of 7 to 7. A test apparatus for testing a device under test,
A signal measuring unit that measures a signal under measurement output by the device under test at a timing according to a measurement setting value;
In the signal transmission path between the device under test and the signal measuring unit, the measurement setting value is corrected based on the signal delay time in each of the third transmission path and the fourth transmission path, one of which includes the other. A calibration section for setting the measurement correction value, and
The calibration unit
A correction unit that can set the measurement correction value within a predetermined settable range, and adds or subtracts the set measurement correction value to or from the measurement setting value;
A first addition / subtraction unit for adding / subtracting the stored offset value to / from the measurement set value;
The first addition / subtraction unit calculates a first measurement correction value that compensates for the signal delay time in the third transmission path, and uses a difference between the reference value within the settable range and the first measurement correction value as the offset value. And a setting unit that calculates a second measurement correction value that compensates for the signal delay time in the fourth transmission path and sets the second measurement correction value in the correction unit.   A program that causes a computer to function as the setting unit in the test apparatus according to any one of claims 1 to 9.

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