JP2012074801A - Analog-digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mixedly mount a digital circuit and an analog circuit, which can achieve a single power voltage and low power consumption.SOLUTION: An analog-digital conversion section 32 includes a digital signal generation section 32a which is connected between a power terminal and a ground terminal and generates a high-level or a low-level output depending upon an input voltage, and an offset voltage generation section 32b which generates an offset voltage Vofs as a potential difference between the ground terminal and the digital signal generation section 32a. The offset voltage generation section 32b generates the offset voltage Vofs to reduce a power voltage applied to the digital signal generation section 32a.

Description

  The present invention relates to an analog-to-digital converter that converts a signal from an analog circuit into a digital signal and outputs the analog circuit and digital circuit to which driving power is supplied from a common power source.

  In recent years, a technique for performing data transmission between various electronic devices mounted on a vehicle such as an automobile using an optical cable is known. An electronic device connected by an optical cable includes a connector for connecting the optical cable, and this connector includes a photoelectric conversion module called FOT (Fiber Optic Transcever). The photoelectric conversion element module converts an optical signal into an electrical signal.

  The photoelectric conversion module mainly includes, for example, a photoelectric conversion element (light receiving element) that receives an optical signal transmitted from the optical cable side and an element driving IC. The element driving IC has a function as a signal transmission device that performs data transmission to an electronic device (for example, a control circuit) in accordance with an optical signal received through the light receiving element. By the way, as this kind of element driving IC, there is known one in which a digital circuit (CMOS digital circuit) and an analog circuit are mixedly mounted (for example, see Patent Documents 1 to 3).

JP 2006-54269 A JP 2007-281111 A JP-A-9-197916

  The power supply voltage of the CMOS digital circuit cannot be larger than the voltage determined by the transistor breakdown voltage. On the other hand, the analog circuit can increase the power supply voltage by avoiding the transistor withstand voltage limitation by devising the circuit configuration, and the higher the power supply voltage, the higher the performance.

  Therefore, for example, when there is no significant restriction on power consumption, a digital power supply is generated from an external power supply by providing a power supply voltage generation circuit (regulator), and power is supplied individually to the analog circuit and the digital circuit. Can be considered. However, in the case of such a method, there is a problem that it is difficult to reduce the power consumption because appropriate power is required for the regulator.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a digital circuit in which it is difficult to increase the power supply voltage due to restrictions on the breakdown voltage of the transistor and an analog circuit in which high performance can be obtained by increasing the power supply voltage. In other words, it is possible to mount them with a single power supply voltage and low power consumption.

  In order to solve such a problem, the present invention is directed to an analog circuit and a digital circuit to which driving power is respectively supplied from a common power source, and converts the signal from the analog circuit into a digital signal and outputs the digital signal Providing equipment. This analog-to-digital converter is connected between a power supply terminal and a ground terminal, and generates a high level output or a low level output according to an input voltage, a ground terminal and a digital signal generation unit, And an offset voltage generator for generating an offset voltage as a potential difference between the two. Here, the offset voltage generator generates an offset voltage to reduce the power supply voltage applied to the digital signal generator.

  In the present invention, the digital signal generator is preferably composed of a P-channel MOS transistor and an N-channel MOS transistor that form an inverter. Alternatively, it is desirable that the digital signal generator is composed of two sets of P-channel MOS transistors and N-channel MOS transistors that form NAND gates.

  In the present invention, the analog-digital converter preferably further includes a current bias constant current source for supplying a current to the offset voltage generator. In this case, the offset voltage generation unit is preferably configured with a diode.

  In the present invention, it is preferable that the analog-digital conversion device further includes a switch for controlling whether or not the current from the current bias constant current source is supplied to the offset voltage generation unit.

  According to the present invention, by setting the offset voltage in consideration of the withstand voltage limitation of the transistors constituting the digital circuit, it is possible to achieve a configuration that satisfies the withstand voltage conditions of the transistors in the digital circuit even if the power supply is a high voltage. Become. Thereby, it becomes possible to mount a digital circuit and an analog circuit together with a single power supply voltage and low power consumption.

The block diagram which shows the structure of the optical connector 1 typically Block configuration diagram schematically showing the element driving IC 12 The block diagram which shows typically the structure of the A / D conversion part 32 concerning this embodiment. The block diagram which shows typically the structure as a modification of the A / D conversion part 32 concerning this embodiment.

  FIG. 1 is a block diagram schematically showing a configuration of an optical connector 1 to which an analog-digital conversion apparatus according to an embodiment of the present invention is applied. The optical connector 1 according to the present embodiment is, for example, a receptacle-type female optical connector used in the optical communication field. The optical connector 1 is provided in various electronic devices such as a display and a navigation system, and is electrically connected to a printed wiring board 2 included in the electronic device. The optical connector 1 is capable of performing large-capacity optical communication between electronic devices by connecting, for example, a male optical connector to which an optical cable is attached.

  The optical connector 1 includes a photoelectric conversion module 10 called FOT (Fiber Optic Transcever). In the photoelectric conversion element module 10, a plurality of lead terminals extended from a metallic lead frame are soldered onto the printed wiring board 2.

  The optical connector 1 also includes a sleeve 13 as an optical component interposed between the photoelectric conversion module 10 (specifically, a light receiving element 11 described later) and a ferrule end surface (optical cable end surface) of the male optical connector. ing. The sleeve 13 is composed of a light guide member formed of a transparent material having optical transparency, and a cylindrical portion provided around the light guide member.

  The photoelectric conversion module 10 is mainly composed of a light receiving element 11 and an element driving IC 12 which are photoelectric conversion elements, and the light receiving element 11 and the element driving IC 12 are wire-bonded on a conductive metal lead frame. It is mounted in the state.

  As the light receiving element 11, a photodiode (PD: Photo Diode) can be used. That is, the optical connector 1 according to the present embodiment is configured as a connector for receiving an optical signal via an optical cable.

  In addition to the light receiving element 11 and the element driving IC 12, the photoelectric conversion module 10 may further include a light emitting element and the element driving IC so that an optical signal can be transmitted and received.

  FIG. 2 is a block diagram schematically showing the element driving IC 12. The element driving IC 12 receives an optical signal sent from the optical cable side via the light receiving element 11 and transmits a data signal RD to the electronic device (printed wiring board 2) in accordance with the optical signal. It has a function as a signal transmission device. The element driving IC 12 includes a main control unit 20 and a power management unit 30 when this is viewed functionally.

  As one of the features of this embodiment, the main control unit 20 and the power management unit 30 are not only functionally separated, but the power systems are also independent of each other. Specifically, a switch 21 is provided in a power supply line that supplies operating power from the power supply unit 40 to the main control unit 20. By switching the on / off state of the switch 21, the power source of the main control unit 20 can be turned on or off. If the switch 21 is on, the main control unit 20 is turned on. If the switch 21 is off, the main control unit 20 is turned off. On the other hand, the power supply line that supplies operating power from the power supply unit 40 to the power management unit 30 is always set to on. That is, the power management unit 30 is different from the main control unit 20 in that the power management unit 30 is constantly set in an operation state (a state where the power is turned on).

  Based on an electrical signal (hereinafter referred to as “input signal”) Sig output from the light receiving element 11, the main control unit 20 is based on an element in the subsequent stage (specifically, a printed wiring board 2 (for example, a control circuit) )) To transmit data. The main control unit 20 includes an amplification unit 22, an LVDS unit 23, an LOS unit 24, a timer unit 25, and a timing control unit 26.

  The amplifying unit 22 is a signal amplifier that amplifies the input signal Sig from the light receiving element 11 and outputs the amplified signal.

  The LVDS unit 23 has a substantial function related to data transmission, and outputs a data signal RD according to the input signal Sig amplified by the amplification unit 22. As a data transmission specification by the LVDS unit 23, a low voltage differential signal suitable for transmission of a high-speed digital signal called LVDS (Low Voltage Differential Signaling) can be used. The LVDS performs signal transmission using a voltage difference between transmission lines by applying different voltages to a pair of transmission lines. That is, the LVDS unit 23 outputs the data signals RD + and RD− to the pair of transmission lines in order to output the data signal RD based on the input signal Sig.

  Based on the input signal Sig amplified by the amplification unit 22, the LOS unit 24 determines whether or not the input signal Sig is an appropriate input signal due to communication. This determination is performed by comparing the amplitude of the input signal Sig with a preset reference amplitude (reference voltage) (signal amplitude determination). The determination result by the LOS unit 24 is output to the timing control unit 26 as the LOS signal Sos. Specifically, when the amplitude of the input signal Sig does not reach the reference amplitude, the LOS unit 24 outputs a signal (Low signal) indicating that the input signal Sig is not an appropriate input signal Sig as the LOS signal Sos. Is equal to or larger than the reference amplitude, a signal (High signal) indicating that the input signal Sig is appropriate is output as the LOS signal Sos.

  In the present embodiment, the LOS signal Sos output from the LOS unit 24 is also input to the power management unit 30 via the timer unit 25. The LOS unit 24 determines whether or not to continue the power-on state of the main control unit 20 through the output of the LOS signal Sos using the amplitude of the amplified input signal Sig as a judgment material, that is, the power source is switched from on to off. Whether or not the power management unit 30 is instructed.

  The timer unit 25 has a function of delaying the execution timing of the signal amplitude determination by the LOS unit 24 by a predetermined period (for example, several μ seconds) immediately after the power is turned on (that is, immediately after the main control unit 20 is activated). The timer unit 25 is provided from the viewpoint that the signal amplitude determination by the LOS unit 24 is performed in a stable operation state, avoiding an unstable operation state immediately after power-on.

  Specifically, the timer unit 25 outputs a trigger signal Stg to the LOS unit 24 after a predetermined time (for example, several μ seconds) has elapsed since the main control unit 20 was turned on. When the LOS unit 24 determines the signal amplitude after the trigger signal Stg is input, the signal amplitude can be determined based on the amplitude of the input signal Sig monitored with high accuracy. That is, the timer unit 25 masks the LOS signal Sos from the LOS unit 24 for a predetermined time.

  In addition, when the LOS signal Sos output to the power management unit 30 is a low signal, the timer unit 25 masks the output of the LOS signal Sos for a predetermined time. That is, the timer unit 25 outputs the LOS signal Sos (Low signal) to the power management unit 30 after the Low signal as the LOS signal Sos has elapsed for a predetermined time.

  The timing control unit 26 controls the operation timing of the LVDS unit 23 through the LOS signal Sos input thereto. By controlling the operation timing by the timing control unit 26, the LVDS unit 23 outputs the data signal RD (RD +, RD−) according to the input signal Sig, or the data signal RD despite the input signal Sig. Can be output or not.

  Further, the timing control unit 26 can output a WSD signal or an SD signal to a subsequent element (specifically, a control circuit for the printed wiring board 2 that is an electronic device). Here, the WSD signal is a control circuit for the printed circuit board 2 when the signal received as the input signal Sig corresponds to a tone signal (hereinafter referred to as “initial signal”) received for the first time after the previous power-off. Is a signal output to activate Here, the tone signal is a signal transmitted to obtain a response from the communication destination prior to the communication so that the communication source can recognize the presence of the communication destination, and the communication source recognizes the response from the communication destination. The tone signal is output a plurality of times during a predetermined period. On the other hand, the SD signal is a signal output to the control circuit of the printed circuit board 2 in synchronization with the output timing of the data signal RD when the data signal RD is output to the control circuit of the printed circuit board 2. .

  The power management unit 30 manages the power on / off of the main control unit 20 based on the input signal Sig. The power management unit 30 is mainly configured by an input signal detection unit 31, an A / D conversion unit 32 as an analog-digital conversion device, and a SW control unit 33.

  The input signal detector 31 compares the magnitude of the signal DC level of the input signal Sig, which is an output from the light receiving element 11, and a preset reference signal level (voltage), and outputs a signal corresponding to the comparison result. Output. Specifically, the input signal detection unit 31 inverts the output according to the reference signal level with respect to the input signal Sig that is the output from the light receiving element 11, and is configured as an analog circuit including an operational amplifier, for example. Has been.

  The A / D converter 32 converts the analog signal from the input signal detector 31 into a digital signal and outputs it. FIG. 3 is a configuration diagram schematically illustrating the configuration of the A / D conversion unit 32 according to the present embodiment. The A / D conversion unit 32 is mainly configured by the digital signal generation unit 32a. In the present embodiment, the A / D conversion unit 32 further includes an offset voltage generation unit 32b, a constant current source 32c, a switch 32d, and a capacitor 32e. ing.

  The digital signal generation unit 32a includes a P-channel type MOS transistor Mp and an N-channel type MOS transistor Mn that form an inverter, and is connected between a power supply terminal and a ground terminal, and has an input IN (input signal detection unit). A high-level signal (High signal) or a low-level signal (Low signal) is generated as an output OUT in accordance with the input voltage from 31. The offset voltage generator 32b reduces the voltage applied between the gate and source of the MOS transistors Mp and Mn, and generates an offset voltage Vofs for satisfying the withstand voltage condition. The offset voltage Vofs functions as a potential difference between the ground terminal and the digital signal generator 32a. In the present embodiment, the offset voltage generator 32b is configured by a diode.

  The constant current source 32c is a current bias constant current source for the offset voltage generator 32b. The switch 32d controls whether or not the current of the constant current source 32c is supplied to the offset voltage generator 32b in accordance with the analog signal from the input signal detector 31. Specifically, the switch 32d is turned on when the analog signal from the input signal detection unit 31 is at a high level (H), whereby the current of the constant current source 32c is supplied to the offset voltage generation unit 32b. . On the other hand, the switch 32d is turned off when the analog signal from the input signal detector 31 is at a low level (L), and the current of the constant current source 32c is not supplied to the offset voltage generator 32b. The capacitor 32e suppresses the voltage lip of the output from the offset voltage generator 32b due to the through current that flows when the state of the switch 32d and the digital signal generator (inverter) 32a that is a digital circuit changes.

  When the signal direct current level of the input signal Sig has reached the reference signal level, the A / D conversion unit 32 outputs a High signal as the WD signal Swd according to the output signal from the input signal detection unit 31. The High signal as the WD signal Swd functions as a signal for turning on the main control unit 20. On the other hand, when the signal DC level of the input signal Sig does not reach the reference signal level, the A / D conversion unit 32 outputs a Low signal as the WD signal Swd according to the output signal from the input signal detection unit 31. . The Low signal as the WD signal Swd functions as a signal indicating that the main control unit 20 is not turned on.

  The SW control unit 33 controls the on / off state of the switch 21 based on the WD signal Swd from the A / D conversion unit 32 and the LOS signal Sos from the main control unit 20 (LOS unit 24). The SW control unit 33 is configured as a digital circuit. Specifically, the SW control unit 33 controls the on / off state of the switch 21 according to the following conditions.

(1) During Sleep State When the optical signal is not continuously input to the light receiving element 11, the element driving IC 12 is set to the sleep state. In this sleep state, the switch 21 is set to OFF, the main control unit 20 is turned off, and only the power management unit 30 is turned on.

  When the signal DC level of the input signal Sig from the light receiving element 11 has reached the reference signal level, the A / D conversion unit 32 responds to the output signal from the input signal detection unit 31 as a WD signal Swd as a High signal. Is output. The SW control unit 33 receives the High signal as the WD signal Swd and controls the switch 21 to be turned on. Thereby, the power supply of the main control unit 20 is switched from OFF to ON. If the main control unit 20 is already turned on, the SW control unit 33 keeps the switch 21 on.

  On the other hand, when the signal DC level of the input signal Sig from the light receiving element 11 does not reach the reference signal level, the A / D conversion unit 32 generates a WD signal Swd according to the output signal from the input signal detection unit 31. A Low signal is output. In this case, the SW control unit 33 keeps the switch 21 in the OFF state, and the main control unit 20 is kept powered off.

(2) After the power of the main control unit 20 is turned on When the amplitude of the input signal Sig amplified by the amplification unit 22 is greater than or equal to the reference amplitude, the LOS unit 24 outputs a high signal as the LOS signal Sos, A signal indicating that the input signal Sig is appropriate is output. In this case, the SW control unit 33 receives the High signal as the LOS signal Sos, and controls the switch 21 to remain on. Therefore, if the LOS unit 24 determines that the input signal Sig is appropriate after the main control unit 20 is turned on, the main control unit 20 is kept in the power-on state.

  On the other hand, when the amplitude of the input signal Sig amplified by the amplifying unit 22 is smaller than the reference amplitude, the LOS unit 24 indicates that the LOS signal Sos is not a Low signal, that is, an appropriate input signal Sig. A signal is output to the timer unit 25. After a predetermined elapsed time, the LOS signal Sos (Low signal) masked by the timer unit 25 is output to the SW control unit 33. The SW control unit 33 receives the Low signal as the LOS signal Sos and controls the switch 21 to be turned off. Thereby, the power supply of the main control unit 20 is turned off.

Hereinafter, the operation of the A / D converter 32 of the power management unit 30 will be described. Here, Table 1 is a correspondence table showing each state of the A / D conversion unit 32 shown in FIG. The low level output of the input signal detection unit 31 is designed to be equal to or higher than Vofs.

  As one of the features of the A / D converter 32, when the input IN (signal input from the input signal detector 31) to the A / D converter 32 is “H (H = VDD)”, the digital signal The switch 32d is turned on so as to reduce the voltage Vgsn applied to the N-channel MOS transistor Mn side of the generation unit 32a. As a result, a current is supplied from the constant current source 32c to the offset voltage generator 32b, and a ground terminal and a digital signal generator 32a (source terminal of the N-channel MOS transistor Mn) offset voltage Vofs is generated. At this time, the output OUT becomes “L (low level signal)” and becomes the offset voltage Vofs. On the other hand, when the input IN to the A / D converter 32 is “L (L ≧ Vofs)”, the switch 32d is turned OFF. In this case, no current is supplied from the constant current source 32c to the offset voltage generator 32b, and the ground terminal and the digital signal generator 32a (the source terminal of the N-channel MOS transistor Mn) offset voltage Vofs are not substantially generated. At this time, the output OUT becomes “H (high level signal)”. As shown in the table, the voltages Vgsp and Vgsn applied to the P-channel and N-channel MOS transistors Mp and Mn are reduced to VDD-Vofs.

  Thus, in the present embodiment, the A / D conversion unit 32 includes the offset voltage generation unit 32b that generates the offset voltage Vofs as a potential difference between the ground terminal and the digital signal generation unit 32a. The offset voltage generator 32b generates an offset voltage Vofs in order to reduce the power supply voltage applied to the digital signal generator 32a. Here, the digital signal generation unit 32a includes a P-channel MOS transistor Mp and an N-channel MOS transistor Mn that form an inverter.

  According to such a configuration, the low level output of the input signal detector 31 is designed to be equal to or higher than Vofs, and the offset voltage Vofs is generated, whereby the voltage Vgsp applied to the P-channel MOS transistor Mp side is VDD. The voltage Vgsn applied to the N-channel MOS transistor Mn side is also equal to VDD-Vofs. In this way, by setting the offset voltage Vofs in consideration of transistor withstand voltage limitations, a configuration that satisfies the withstand voltage conditions of the transistors forming a part of the digital circuit even when the power supply is a high voltage is possible. Thereby, it becomes possible to mount a digital circuit and an analog circuit together with a single power supply voltage and low power consumption.

  Further, according to the present embodiment, it is not necessary to provide a power circuit dedicated to a digital circuit that consumes a large amount of power in order to satisfy the withstand voltage condition of the transistor, so that the power consumption can be greatly reduced. In the case of a general internal logic circuit, the transistor size is small, the through current is 1 μA or less, the bias current is about 1 μA, and the withstand voltage condition of the transistor can be satisfied with low power consumption.

  Further, according to the present embodiment, the A / D converter 32 further includes a switch 32d that controls whether or not the current from the current bias constant current source 32c is supplied to the offset voltage generator 32b. . As a result, it is only necessary to supply bias power when the input IN to the digital signal generation unit 32a is “H”, so that power consumption can be greatly reduced.

(Modification)
FIG. 4 is a configuration diagram schematically illustrating the configuration of the A / D conversion unit 32 according to the second embodiment. The A / D converter 32 according to this embodiment is different from that of the first embodiment in the configuration of the digital signal generator. The description of the configuration common to the first embodiment will be omitted, and the following description will be focused on the differences.

  The digital signal generation unit 32f of this embodiment includes two sets of P-channel MOS transistors Mp1 and Mp2 and N-channel MOS transistors Mn1 and Mn2 that form NAND gates. The digital signal generation unit 32f is connected between a power supply terminal and a ground terminal, and is a high level (H) signal (High signal) or a low level according to an input IN (input voltage from the input signal detection unit 31). The (L) signal (Low signal) is generated as the output OUT.

  Even in such a configuration, as in the configuration shown in FIG. 3, by setting the offset voltage Vofs in consideration of transistor breakdown voltage limitation, there is a configuration that satisfies the breakdown voltage condition of the transistor even if it is a high-voltage power supply. It becomes possible. Thereby, it becomes possible to mount a digital circuit and an analog circuit together with a single power supply voltage and low power consumption.

  The digital signal generation unit 32f according to the present embodiment can be variously modified in addition to such modified examples. For example, as the digital signal generation unit 32f, a NOR gate, a 3-input NAND circuit, or the like can be used.

  The analog-digital conversion apparatus according to this embodiment has been described above, but the present invention is not limited to this embodiment, and it goes without saying that various modifications can be made within the scope of the invention. Since the offset voltage generator 32b has a problem that its output increases due to the through current of the digital circuit, it is necessary to design the impedance of the offset voltage generator 32b so that the potential rise does not become a problem. When the offset voltage Vofs is about 1 V, a diode (MOS diode) can be applied as the offset voltage generator 32b as described above. Then, the impedance is set according to the bias current value. In a digital circuit having a large load driving capability, since the transistor size is large and the through current also increases, a three-terminal regulator may be used as the offset voltage generator 32b. Further, a MOS transistor may be used as the offset voltage generator 32b.

DESCRIPTION OF SYMBOLS 1 Optical connector 2 Printed wiring board 10 Photoelectric conversion module 11 Light receiving element 12 Element drive IC
20 main control unit 21 switch 22 amplifying unit 23 LVDS unit 24 LOS unit 25 timer unit 26 timing control unit 30 power management unit 31 input signal detection unit 32 A / D conversion unit 32a digital signal generation unit 32b offset voltage generation unit 32c constant current Source 32d Switch 32e Capacitor 33 SW control unit

Claims (5)

In an analog-to-digital conversion apparatus that converts a signal from the analog circuit into a digital signal and outputs the analog circuit and digital circuit to which driving power is supplied from a common power source, respectively,
A digital signal generator that is connected between the power supply terminal and the ground terminal and generates a high-level output or a low-level output according to the input voltage;
An offset voltage generator that generates an offset voltage as a potential difference between the ground terminal and the digital signal generator;
The analog-to-digital converter according to claim 1, wherein the offset voltage generator generates the offset voltage to reduce a power supply voltage applied to the digital signal generator.   2. The analog-to-digital converter according to claim 1, wherein the digital signal generation unit includes a P-channel MOS transistor and an N-channel MOS transistor that form an inverter.   2. The analog-to-digital converter according to claim 1, wherein the digital signal generation unit includes two sets of P-channel MOS transistors and N-channel MOS transistors that form a NAND gate. A constant current source for current bias for supplying current to the offset voltage generator;
4. The analog-to-digital conversion device according to claim 1, wherein the offset voltage generation unit includes a diode.   5. The analog-to-digital converter according to claim 1, further comprising a switch for controlling whether or not a current from the current bias constant current source is supplied to the offset voltage generator. 6. .