JP2012064892A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of mounting decoupling capacitors that can obtain a high effect against variation in power supply voltage.SOLUTION: A semiconductor device 10 includes: a semiconductor substrate 23; a plurality of through electrodes 21 that penetrate through the semiconductor substrate 23 and are electrically connected to a power supply line 12 and a ground line 13; and a plurality of terminals 22 that are provided on the rear surface of the semiconductor substrate 23, are electrically connected to the plurality of electrodes 21, and on which decoupling capacitors 40 are mounted.

Description

  Embodiments described herein relate generally to a semiconductor device.

  A semiconductor integrated circuit is configured by mounting a plurality of semiconductor chips on a printed circuit board (PCB), and the plurality of semiconductor chips configure one system, for example. The power supply network is optimized for stable operation of the entire system, but it is very difficult to evaluate and examine the power supply design on a time axis. For this reason, for example, by analyzing the impedance between the power supply line and the ground line connected to the voltage supply source in the frequency domain, and suppressing the impedance below the allowable value, a method for optimizing the voltage fluctuation in the time axis domain Is used. Then, a plurality of decoupling capacitors are mounted on a silicon substrate, a package, a PCB, or the like so that the value is equal to or less than the target by analyzing the impedance of the system to optimize the power supply network.

  These decoupling capacitors are placed as close as possible to the target device, and the best effect can be obtained by keeping the current loop as small as possible. For this reason, in general, measures are taken to mount a plurality of decoupling capacitors on the PCB directly under the target device. However, as the solder balls (bumps) of the package become narrower in pitch, decoupling is performed. It is becoming difficult to secure an area for mounting a capacitor. Also, by providing an area for mounting a decoupling capacitor on the PCB, when producing a signal line on the PCB, the influence on the production process of the wiring is increased, such as being unable to wire or being forced to bypass. ing.

  Further, although a method of embedding a decoupling capacitor in a PCB or a package is used, the characteristics cannot be adjusted later in such a structure. In addition, when the decoupling capacitor fails, it is not possible to replace only the components, so the entire package or the entire PCB must be replaced as a defective product, resulting in an increase in cost.

JP 2007-311676 A

  The embodiment provides a semiconductor device in which a decoupling capacitor capable of obtaining a high effect against fluctuations in power supply voltage can be mounted.

  The semiconductor device according to the embodiment is provided with a semiconductor substrate, a plurality of through electrodes that penetrate the semiconductor substrate and are electrically connected to a power supply line and a ground line, the back surface of the semiconductor substrate, and the plurality of the plurality of through electrodes And a plurality of terminals that are electrically connected to the through electrode and on which a decoupling capacitor is mounted.

1 is a cross-sectional view illustrating a configuration of a semiconductor package 10 according to an embodiment. FIG. 2 is a cross-sectional view illustrating a configuration of a semiconductor chip 20 illustrated in FIG. 1. FIG. 3 is a cross-sectional view showing an example of a semiconductor integrated circuit 30 on which the semiconductor package 10 is mounted. FIG. 3 is a cross-sectional view showing a configuration of a semiconductor chip 20 on which a decoupling capacitor 40 is mounted. FIG. 3 is a plan view showing an example of a semiconductor chip 20. 1 is a cross-sectional view illustrating a configuration of a semiconductor package 10 according to a first embodiment. FIG. 10 is a cross-sectional view showing a manufacturing process of the semiconductor package 10 according to the second embodiment. FIG. 6 is a cross-sectional view illustrating a configuration of a semiconductor package 10 according to a second embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. However, it should be noted that the drawings are schematic or conceptual, and the dimensions and ratios of the drawings are not necessarily the same as the actual ones. Further, even when the same portion is represented between the drawings, the dimensional relationship and ratio may be represented differently. In particular, the following embodiments exemplify an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention depends on the shape, structure, arrangement, etc. of components. Is not specified. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

  FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor package (semiconductor device) 10 according to an embodiment. Inside the package substrate (interposer) 11, a plurality of wirings including a power supply line (VDD line) 12, a ground line (VSS line) 13, and a signal line are provided. The power supply voltage VDD is supplied to the VDD line 12. A ground voltage VSS is supplied to the VSS line 13.

  A semiconductor chip 20 is flip-chip connected to the surface of the interposer 11. That is, the semiconductor chip 20 is mounted (mounted) on the interposer 11 via a plurality of protruding electrodes (bumps) so that the surface of the interposer 11 and the surface of the semiconductor chip 20 face each other.

  The semiconductor chip 20 is sealed on the interposer 11 by a mold (sealing material) 15 made of, for example, resin. Specifically, the space between the interposer 11 and the semiconductor chip 20 is filled with the mold 15, and the back surface and side surfaces of the semiconductor chip 20 are covered with the mold 15. A plurality of bumps 14 are provided on the back surface of the interposer 11 so as to be electrically connected to the wiring in the interposer 11. The semiconductor package 10 is configured as described above.

  FIG. 2 shows the semiconductor chip 20 shown in FIG. 1 in more detail. For example, a semiconductor circuit 24 including semiconductor elements and wirings is provided on the surface of a semiconductor substrate 23 made of a silicon substrate. The semiconductor circuit 24 includes a VDD line to which the power supply voltage VDD is supplied and a VSS line to which the ground voltage VSS is supplied. In FIG. 2, the lower surface of the semiconductor substrate 23 corresponds to the front surface, and the upper surface of the semiconductor substrate 23 corresponds to the back surface.

  A plurality of bumps 25 for electrically connecting the semiconductor chip 20 to the interposer 11 are provided on the semiconductor circuit 24 (lower side in FIG. 2). Although the bumps 25 are not shown in FIG. 1, the semiconductor chip 20 is mounted on the interposer 11 so that the bumps 25 of the semiconductor chip 20 are in contact with the surface of the interposer 11.

  A plurality of through electrodes 21 are provided in the semiconductor substrate 23 so as to penetrate vertically therethrough. A plurality of terminals 22 for mounting a decoupling capacitor are provided on the back surface of the semiconductor substrate 23 via an insulating film 26. One end of the plurality of through electrodes 21 is electrically connected to the plurality of terminals 22, and the other end of the plurality of through electrodes 21 is connected to the VDD line 12 and the VSS line 13 in the interposer 11 via the semiconductor circuit 24 and the bumps 25. Is electrically connected. The semiconductor chip 20 is configured as described above.

  FIG. 3 is a cross-sectional view showing an example of the semiconductor integrated circuit 30 on which the semiconductor package 10 is mounted. In the printed circuit board (printed wiring board) 31, a plurality of wirings including a power line (VDD line) 32, a ground line (VSS line) 33, and a signal line are provided.

  A power supply circuit 34 is provided on the printed circuit board 31. The power supply circuit 34 supplies the power supply voltage VDD to the VDD line 32 of the printed circuit board 31 and supplies the ground voltage VSS to the VSS line 33.

  Further, the semiconductor package 10 shown in FIG. 1 is mounted on the printed circuit board 31. The semiconductor package 10 is arranged such that the bumps 14 thereof are electrically connected to the wiring of the printed circuit board 31. Further, the VDD line 32 and the VSS line 33 in the printed circuit board 31 are electrically connected to the VDD line 12 and the VSS line 13 in the semiconductor package 10 via the bumps 14, respectively. A decoupling capacitor 40 is electrically connected to the terminal 22 of the semiconductor chip 20. The semiconductor integrated circuit 30 is configured as described above.

  Next, a method for mounting the decoupling capacitor 40 on the semiconductor chip 20 will be described. FIG. 4 is a cross-sectional view showing a configuration of the semiconductor chip 20 on which the decoupling capacitor 40 is mounted.

  After the semiconductor package 10 and other devices are mounted on the printed circuit board 31 and the semiconductor integrated circuit 30 is manufactured, the power supply analysis of the entire system is performed. As a result, it is determined that an additional decoupling capacitor 40 is necessary.

  When the package is manufactured, as shown in FIG. 1, the semiconductor chip 20 and the terminals 22 are covered with the mold 15. First, as shown in FIG. 4, the mold 15 is polished to expose a plurality of terminals 22 for mounting the decoupling capacitor 40. Subsequently, a predetermined number of decoupling capacitors 40 for realizing the capacity determined to be necessary by the power supply analysis are mounted on the terminal 22. As a circuit configuration, the predetermined number of decoupling capacitors 40 are connected in parallel between the VDD line 12 and the VSS line 13.

  The decoupling capacitor 40 is connected between the VDD line 12 and the VSS line 13, and suppresses fluctuations in the power supply voltage to reduce jitter and noise. Therefore, a plurality of terminals 22 electrically connected to the VDD line 12 and a plurality of terminals 22 electrically connected to the VSS line 13 are alternately arranged along one direction on the back surface of the semiconductor chip 20. Are lined up. Each decoupling capacitor 40 is electrically connected to one terminal 22 electrically connected to the VDD line 12 and one terminal 22 electrically connected to the VSS line 13.

  Next, the size and layout of the terminals 22 provided in the semiconductor chip 20 will be described. Consider using a general-purpose capacitor as the decoupling capacitor 40 in order to reduce the cost. The size of the general-purpose capacitor is predetermined according to the capacity.

  On the other hand, the capacity required by the power supply analysis of the entire system varies depending on the specifications and configuration of the semiconductor integrated circuit 30 on which the semiconductor package 10 is mounted. In order to realize the calculated capacity, it is necessary to combine a plurality of types of general-purpose capacitors having different sizes, that is, different capacities.

  FIG. 5 is an example of a plan view of the semiconductor chip 20. A decoupling capacitor 40-1 as a general-purpose capacitor is electrically connected to a power supply terminal 22A-1 electrically connected to the VDD line 12 and a ground terminal 22B-1 electrically connected to the VSS line 13. Has been. Since the size of the decoupling capacitor 40-1 as a general-purpose capacitor is known in advance, the pair of the power supply terminal 22A-1 and the ground terminal 22B-1 is sized and laid out in accordance with the size of the decoupling capacitor 40-1. Is determined.

  The decoupling capacitor 40-2, which is a general-purpose capacitor having a size different from that of the decoupling capacitor 40-1, is electrically connected to the power supply terminal 22A-2 electrically connected to the VDD line 12 and the VSS line 13. Is electrically connected to the ground terminal 22B-2. The size and layout of the pair including the power supply terminal 22A-2 and the ground terminal 22B-2 are determined according to the size of the decoupling capacitor 40-2.

  As described above, in the present embodiment, as the terminals 22 provided on the semiconductor chip 20, terminals having a plurality of types of sizes and layouts are prepared in accordance with the sizes of a plurality of types of general-purpose capacitors.

Example 1
FIG. 6 is a cross-sectional view illustrating the configuration of the semiconductor package 10 according to the first embodiment. As shown in FIG. 6, the terminal 22 for the decoupling capacitor 40 may be exposed from the beginning without being covered with the mold 15 at the stage where the production of the semiconductor package 10 is completed.

  That is, in the manufacturing process of sealing the semiconductor chip 20 on the interposer 11 with the mold 15, the mold 15 is formed so that the upper surface thereof is lower than the upper surface of the terminals 22. This may be achieved by adjusting the amount of resin that is the material of the mold 15. Thereby, the terminal 22 is exposed in a state where the mold 15 is formed. Then, when the semiconductor package 10 is mounted on the semiconductor integrated circuit 30, a necessary number of decoupling capacitors 40 are connected to the terminal 22.

  In the first embodiment, when the decoupling capacitor 40 is required by the power supply analysis of the entire system (semiconductor integrated circuit 30), the step of polishing the mold 15 can be omitted. Thereby, manufacturing cost can be reduced.

(Example 2)
The semiconductor chip 20 and the decoupling capacitor 40 may be covered with the mold 15 after the decoupling capacitor 40 required by the power supply analysis of the entire system is mounted on the semiconductor chip 20.

  First, as shown in FIG. 7, the semiconductor package 10 is mounted on the printed circuit board 31 in a state where the semiconductor chip 20 is not covered with the mold 15. Subsequently, a power supply analysis of the entire system is performed, and a decoupling capacitor 40 that realizes a necessary capacity is calculated. Subsequently, the decoupling capacitor 40 is mounted on the semiconductor chip 20.

  Subsequently, as shown in FIG. 8, the semiconductor chip 20 is sealed on the interposer 11 so as to cover the terminal 22 and the decoupling capacitor 40. In the second embodiment, the process for forming the mold 15 may be performed only once, and the terminal 22 and the decoupling capacitor 40 can be covered with the mold 15.

  As described above in detail, in the present embodiment, a plurality of through electrodes 21 that penetrate through the semiconductor substrate 23 and are electrically connected to the VDD line and the VSS line are provided. Furthermore, a plurality of terminals 22 that are electrically connected to the through electrode 21 and for mounting the decoupling capacitor 40 are provided on the back surface of the semiconductor chip 20. The semiconductor chip 20 and the interposer 11 are flip-chip connected via the bumps 25 so that the surface of the semiconductor chip 20 faces the interposer 11.

  Therefore, according to the present embodiment, the decoupling capacitor 40 can be disposed in the vicinity of the semiconductor chip 20. As a result, a high effect for stabilizing the power supply voltage can be obtained, so that jitter and noise can be reduced for the entire system (semiconductor integrated circuit 30) on which the semiconductor chip 20 is mounted. As a result, malfunction of the semiconductor integrated circuit 30 can be prevented.

  Further, even when it is necessary to change the optimal decoupling capacitor to be mounted due to the convenience of the system, such as changing the board size, it is possible to add a decoupling capacitor without redesigning the package. Thereby, manufacturing cost can be reduced.

  Further, since the decoupling capacitor 40 is mounted on the front surface of the semiconductor package 10 (that is, the back surface of the semiconductor chip 20), the decoupling capacitor 40 can be easily replaced even if the decoupling capacitor 40 is damaged for some reason. . Therefore, it is not necessary to replace the entire semiconductor package 10 with respect to the damage of the decoupling capacitor 40, so that the manufacturing cost can be reduced.

  Further, the size and layout of the terminal 22 are determined in accordance with the size of the general-purpose capacitor. Further, in order to be able to mount a plurality of types of general-purpose capacitors, a plurality of terminals 22 having a plurality of types of sizes and layouts adapted to the general-purpose capacitors are provided on the semiconductor chip 20. As a result, a plurality of decoupling capacitors 40 corresponding to the optimum capacitance can be mounted on the semiconductor chip 20 while using a general-purpose capacitor.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor package, 11 ... Interposer, 12, 32 ... Power supply line, 13, 33 ... Ground line, 14, 25 ... Bump, 15 ... Mold, 20 ... Semiconductor chip, 21 ... Through electrode, 22 ... Terminal, 23 ... Semiconductor Substrate, 24 ... semiconductor circuit, 26 ... insulating film, 30 ... semiconductor integrated circuit, 31 ... printed circuit board, 34 ... power supply circuit, 40 ... decoupling capacitor.

Claims (7)

A semiconductor substrate;
A plurality of through electrodes penetrating the semiconductor substrate and electrically connected to a power line and a ground line;
A plurality of terminals provided on the back surface of the semiconductor substrate and electrically connected to the plurality of through electrodes, and on which a decoupling capacitor is mounted;
A semiconductor device comprising:   The semiconductor device according to claim 1, further comprising a mold that covers the plurality of terminals.   The semiconductor device according to claim 1, further comprising a mold provided on a back surface of the semiconductor substrate so as to expose the plurality of terminals. A semiconductor substrate;
A plurality of through electrodes penetrating the semiconductor substrate and electrically connected to a power line and a ground line;
A plurality of terminals provided on the back surface of the semiconductor substrate and electrically connected to the plurality of through electrodes;
A plurality of decoupling capacitors electrically connected to the plurality of terminals;
A semiconductor device comprising:   The semiconductor device according to claim 4, further comprising a mold that covers the plurality of terminals and the decoupling capacitor.   The semiconductor device according to claim 4, further comprising a mold provided on a back surface of the semiconductor substrate so as to expose the plurality of terminals and the plurality of decoupling capacitors. The plurality of terminals are composed of a plurality of pairs each having a plurality of first terminals electrically connected to the power supply line and a plurality of second terminals electrically connected to the ground line,
7. The semiconductor device according to claim 1, wherein a plurality of types of sizes of the plurality of pairs are prepared according to the size of the decoupling capacitor.

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