TWM511729U - Circuit board structure - Google Patents

Abstract

A circuit board structure including a first circuit board, a chip and a second circuit board is provided. The first circuit board includes a first dielectric core, a first circuit structure, a second circuit structure and a plurality of solder balls. The dielectric core has opposing first and second surfaces. The first and second circuit structures are disposed on the first and second surfaces, respectively. The solder balls are electrically connected to the first circuit structure. The chip is disposed on the first circuit board. The second circuit board disposed opposite to the first circuit board includes a second dielectric core, a third circuit structure, a fourth circuit structure and a plurality of conductive pillars. The second dielectric core has opposing third and fourth surfaces. The third and fourth circuit structures are disposed on the third and fourth surface, respectively. The conductive pillars are connected to the solder balls and electrically connected to the fourth circuit structure.

Description

Circuit board structure

The present invention relates to a circuit board structure, and more particularly to a circuit board structure having a buried chip.

The chip packaging technology is to place the wafer on the circuit board and electrically connect the circuit board through the wires or bumps and cover the wafer by a molding compound to provide sufficient signal path, heat dissipation path and structural protection of the chip. The prior art proposes a package-on-package (POP) method that can reduce the load-bearing area occupied by the chip package structures on the circuit board by stacking a plurality of chip package structures on each other. In the case of a POP structure formed by stacking two wafer package structures, the stacked upper package structure and the lower package structure may be different, for example, the upper package structure has a memory element, and the lower package structure has a logic element. In this case, the input/output (I/O) end of the lower package structure has a higher density than the input/output end of the upper package structure, that is, the line pattern pitch of the lower package structure is smaller than that of the upper package structure. Line pattern spacing. Therefore, input/output of the input/output terminal and the lower package structure of the upper package structure occurs when the upper package structure and the lower package structure are connected by solder balls. The problem that the output could not be matched.

In order to solve the above problems, in the current technology, the upper package structure will be An interposer is disposed between the lower package structure and the lower package structure. The interposer element is usually a circuit board having different line pattern pitches on the upper surface and the lower surface, and solder balls are disposed on the line patterns on the upper surface and the lower surface to be connected to the external components. The side of the interposer having a larger line pattern pitch and the upper package structure are connected to each other by respective solder balls, and the side having a smaller line pattern pitch is soldered to the lower package structure by the respective soldering. The balls are connected to each other. In this way, the problem that the input/output terminals of the upper package structure and the input/output terminals of the lower package structure cannot be matched can be solved.

As the line width of the circuit board of the circuit board continues to shrink, the line pattern spacing is also It will shrink. At this time, the volume of the solder balls of the package structure having a smaller line pattern pitch must also be reduced to avoid contact between adjacent solder balls due to the narrowing of the line pattern pitch. However, a solder ball that is too small in size often causes the interposer to be disconnected from the package structure. In addition, since the hardness of the solder ball is small, in the process of connecting the interposer layer and the package structure with the solder ball, the gap between the interposer element and the package structure is likely to be large due to uneven press force. Variability. Furthermore, when the solder balls in the interposer and the solder balls in the package structure are connected to each other, it is easy to cause inaccurate alignment and cause gap variation.

The novel creation provides a circuit board structure by using conductive pillars and solder balls To connect two boards.

The novel creation provides a circuit board structure including a first circuit board, Wafer and second circuit board. The first circuit board includes a first dielectric core, a first line structure, a second line structure, and a plurality of solder balls, wherein the first dielectric core has first and second surfaces opposite to each other, and the first line structure is configured On the first surface, the second line structure is disposed on the second surface and electrically connected to the first line structure, and the solder ball is electrically connected to the first line structure. In addition, the wafer is disposed on the first circuit board and electrically connected to the first circuit board by a plurality of bumps. The second circuit board is disposed opposite to the first circuit board, and the second circuit board includes a second dielectric core, a third line structure, a fourth line structure and a plurality of conductive columns, wherein the second dielectric core has a third opposite to each other The surface and the fourth surface are disposed on the third surface, and the fourth line structure is disposed on the fourth surface and electrically connected to the third line structure. The conductive post is electrically connected to the fourth line structure and connected to the solder ball.

In an embodiment of the novel creation, the ball diameter of the solder ball is, for example, 60 μm. Between 180μm.

In an embodiment of the novel creation, the length of the conductive post is, for example, Between 30 μm and 200 μm.

In an embodiment of the present invention, the gap between the first circuit board and the second circuit board is, for example, between 60 μm and 200 μm.

In an embodiment of the novel creation, the thickness of the first dielectric core is, for example, between 50 μm and 250 μm.

In an embodiment of the novel creation, the thickness of the second dielectric core is, for example Between 50μm and 150μm.

In an embodiment of the present invention, the circuit board structure further includes an encapsulant disposed on the first circuit structure, the encapsulant exposing the solder ball and covering the wafer.

In an embodiment of the present invention, the circuit board structure further includes an encapsulant disposed on the first circuit structure, the encapsulant exposing the solder ball and exposing the back surface of the wafer.

In an embodiment of the present invention, the circuit board structure further includes an encapsulant disposed between the first circuit board and the second circuit board, and the encapsulant fills the space between the first circuit board and the second circuit board. .

In an embodiment of the present invention, the pitch of the line patterns in the first line structure is, for example, smaller than the pitch of the line patterns in the third line structure.

Based on the above, in the circuit board structure of the present invention, the conductive pillar of the upper circuit board as the intermediate component is connected with the solder ball of the lower circuit board on which the wafer is disposed, so that the upper circuit board and the lower circuit board can be made. There is a uniform and fixed gap between them, which also avoids the problem of inaccurate alignment.

The above described features and advantages of the present invention will become more apparent and understood from the following description.

10, 20, 30‧‧‧ circuit board structure

100‧‧‧First circuit board

101‧‧‧ first surface

102‧‧‧ wafer

103‧‧‧ second surface

104‧‧‧First dielectric core

105‧‧‧Bumps

106‧‧‧First line structure

107‧‧‧Package colloid

108‧‧‧Second line structure

110‧‧‧ solder balls

111, 113, 115, 211‧‧ ‧ through holes

112, 114, 116, 118, 212, 214‧‧‧ line patterns

117, 119‧‧‧ dielectric layer

120‧‧‧ pads

121, 123, 221, 223‧‧‧ solder mask

122‧‧‧Active surface

132‧‧‧Back

200‧‧‧second circuit board

201‧‧‧ third surface

203‧‧‧ fourth surface

204‧‧‧Second dielectric core

206‧‧‧ Third line structure

208‧‧‧fourth line structure

210‧‧‧conductive column

L1, L2‧‧‧ line pattern spacing

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing the structure of a wiring board according to a first embodiment of the present invention.

2 is a cross-sectional view showing the structure of a wiring board according to a second embodiment of the present invention.

3 is a cross-sectional view showing the structure of a wiring board in accordance with a third embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing the structure of a wiring board according to a first embodiment of the present invention. Referring to FIG. 1, the circuit board structure 10 of the present embodiment includes a first circuit board 100, a wafer 102, and a second circuit board 200. The first circuit board 100 includes a first dielectric core 104, a first wiring structure 106, a second wiring structure 108, and a plurality of solder balls 110. In the present embodiment, the material of the first dielectric core 104 is, for example, an epoxy resin. The thickness of the first dielectric core 104 is, for example, between 50 μm and 250 μm. The first dielectric core 104 has a first surface 101 and a second surface 103 opposite to each other. The first line structure 106 is disposed on the first surface 101 and the second line structure 108 is disposed on the second surface 103.

The first wiring structure 106 includes a wiring pattern 112, via holes 113, a wiring pattern 114, a dielectric layer 117, and a solder resist layer 121. The line pattern 112 is disposed on the first surface 101. The material of the line pattern 112 is, for example, copper. The dielectric layer 117 is disposed on the line pattern 112. The material of the dielectric layer 117 is, for example, an epoxy resin. The line pattern 114 is disposed on the dielectric layer 117. The material of the line pattern 114 is, for example, copper. The via hole 113 is disposed in the dielectric layer 117 for electrically connecting the line pattern 112 and the line pattern 114. The material of the via hole 113 is, for example, copper. The solder resist layer 121 is disposed on the dielectric layer 117 And having an opening exposing a portion of the line pattern 114. The line pattern 114 exposed by the solder resist layer 121 can serve as a pad for connection with external components. The material of the solder resist layer 121 is, for example, a commonly known green lacquer.

The second line structure 108 includes a line pattern 116, a via 115, and a line The pattern 118, the dielectric layer 119, and the solder resist layer 123. The line pattern 116 is disposed on the second surface 103. The material of the line pattern 116 is, for example, copper. The dielectric layer 119 is disposed on the line pattern 116. The material of the dielectric layer 119 is, for example, an epoxy resin. The line pattern 118 is disposed on the dielectric layer 119. The material of the line pattern 118 is, for example, copper. The via 115 is disposed in the dielectric layer 119 for electrically connecting the line pattern 116 and the line pattern 118. The material of the via 115 is, for example, copper. The solder resist layer 123 is disposed on the dielectric layer 119 and has an opening exposing a portion of the wiring pattern 118. The material of the solder resist layer 123 is, for example, a commonly known green lacquer. The line pattern 118 exposed by the solder resist layer 123 can serve as a pad for connection to external components. In addition, the second line structure 108 is electrically connected to the first line structure 106 by the via hole 111 located in the first dielectric core 104. The material of the via hole 111 is, for example, copper.

In the present embodiment, the first line structure 106 and the second line structure 108 Each has a two-layer wiring layer, that is, the first wiring board 100 is a wiring board having four wiring layers, but the present invention is not limited thereto. In other embodiments, the number of layers of the circuit layer in the first circuit board 100 may be increased as needed.

The wafer 102 has an active surface 122 and a back surface 132, wherein the active surface A pad 120 is disposed on the 122. The wafer 102 is disposed on the first circuit board 100 with the active surface 122 facing the first circuit board 100, and the bumps 105 and the first lines are The board 100 is electrically connected, wherein the bumps 105 are connected to the pads 120 on the active surface 122 and a portion of the second circuit layer 114 in the first circuit board 106 that is used as a pad. The material of the bump 105 is, for example, copper. The encapsulant 107 is disposed on the first line structure 106. The encapsulant 107 exposes the solder balls 110 and covers the entire wafer 102 to prevent the wafer 102 from coming into contact with the outside environment. The material of the encapsulant 107 is, for example, an epoxy resin or a silicone rubber.

The solder ball 110 is disposed in the opening of the exposed portion of the line pattern 114, and The line patterns 114 are connected. The material of the solder ball 110 is, for example, tin. The ball diameter of the solder ball 110 is, for example, between 60 μm and 180 μm. In the present embodiment, the wafer 102 disposed on the first circuit board 100 is, for example, a logic element wafer or a base frequency chip. Therefore, the first circuit board 100 requires a large number of input/output terminals, that is, the lines in the first circuit board 100 need to be thin lines, and the line pattern pitch is small. Since the solder ball 110 of the present embodiment has a small ball diameter (for example, between 60 μm and 180 μm), the adjacent solder balls 110 can be prevented from contacting each other even when the pitch of the line pattern is small.

The second circuit board 200 is disposed opposite to the first circuit board 100. The second circuit board 200 includes a second dielectric core 204, a third line structure 206, a fourth line structure 208, and a plurality of conductive pillars 210. The material of the second dielectric core 104 is, for example, an epoxy resin. The thickness of the second dielectric core 204 is, for example, between 50 μm and 150 μm. The second dielectric core 204 has a third surface 201 and a fourth surface 203 opposite to each other. The third line structure 206 is disposed on the third surface 201, and the fourth line structure 208 is disposed on the fourth surface 203.

The third line structure 206 includes a line pattern 212 and a solder resist layer 221 . line The road pattern 212 is disposed on the third surface 201. The material of the line pattern 212 is, for example, copper. The solder resist layer 221 is disposed on the line pattern 212 and has an opening exposing a portion of the line pattern 212. The material of the solder resist layer 221 is, for example, a commonly known green lacquer. The line pattern 212 exposed by the solder resist layer 221 can serve as a pad for connection to external components.

The fourth line structure 208 includes a line pattern 214 and a solder resist layer 223. line The road pattern 214 is disposed on the fourth surface 203. The material of the line pattern 214 is, for example, copper. The solder resist layer 223 is disposed on the line pattern 214 and has an opening exposing a portion of the line pattern 214. The number and position of the openings in the solder resist layer 223 correspond to the number and position of the solder balls 110 disposed on the first wiring board. In addition, the fourth line structure 208 is electrically connected to the third line structure 206 by the via holes 211 located in the second dielectric core 204. The material of the via hole 211 is, for example, copper.

The conductive pillar 210 is disposed in the fourth line structure 208 to expose the line pattern 214 In the opening, and connected to the line pattern 214. The length of the conductive pillars 210 is, for example, between 30 μm and 200 μm. The material of the conductive pillar is, for example, copper. In addition, the conductive pillars 210 are connected to the solder balls 110 of the first circuit board 100 to electrically connect the first circuit board 100 and the second circuit board 200 to each other.

In this embodiment, the second circuit board 200 is used as a connection external The pads of the component (the trace pattern 212 exposed by the solder resist layer 221) can be used to connect to a circuit board configured with a memory component chip or a radio frequency/power management IC module. Since the wiring layers in these boards generally have a wider line width and a larger line pattern pitch, the line patterns 212 of the second board 200 thus have a wider line width and The larger line pattern pitch, that is, the line pattern pitch L2 of the third line structure 206 is greater than the line pattern pitch L1 of the first line structure 106.

In addition, in the embodiment, the conductive pillars 210 of the first circuit board 100 are utilized. It is connected to the solder ball 110 of the second wiring board 200. Since the conductive pillar 210 can be accurately connected to the solder ball 110 through the encapsulant 107 and the solder resist layer 121, a uniform and fixed gap between the first wiring board 100 and the second wiring board 200 can be achieved. In the present embodiment, the gap between the first wiring board 100 and the second wiring board 200 is, for example, between 60 μm and 200 μm. Furthermore, in general, the hardness of the conductive post is greater than the hardness of the solder ball. Therefore, the present embodiment can avoid the problem that the connection between the solder ball and the solder ball in the prior art is deformed by the press-fit to cause gap variation.

In addition, in the embodiment, the first circuit board 100 and the second line The board 200 is connected to the conductive post 210 by the solder ball 110. Therefore, the length of the solder ball 110 can be adjusted to match the line width and the line pattern pitch required by the first circuit board 100 by adjusting the length of the conductive post 210. The gap between a circuit board 100 and the second circuit board 200 meets the requirements.

2 is a circuit board structure in accordance with a second embodiment of the present invention A schematic view of the section of 20. In FIG. 2, the same elements as those in FIG. 1 will be denoted by the same reference numerals and will not be separately described. Referring to FIG. 2, the difference between the circuit board structure 20 of the present embodiment and the circuit board structure 10 of FIG. 1 is that, in the embodiment, the encapsulant 107 disposed on the first line structure 106 does not cover the entire wafer 102. Instead, the back side 132 of the wafer 102 is exposed. In this way, the heat dissipation effect of the wafer 102 can be effectively improved.

Figure 3 is a cross-sectional view showing a circuit board structure in accordance with a third embodiment of the present invention Schematic diagram. In FIG. 3, the same components as those in FIG. 1 will be denoted by the same reference numerals and will not be described herein. Referring to FIG. 3, the difference between the circuit board structure 30 of the present embodiment and the circuit board structure 10 of FIG. 1 is that, in the embodiment, the encapsulant 107 is disposed between the first circuit board 100 and the second circuit board 200. And the encapsulant 107 fills the space between the first circuit board 100 and the second circuit board 200. In this way, since the conductive pillars 210 are covered by the encapsulant 107, the conductive pillars 210 can obtain more supporting force and are not easily bent, deformed or broken, thereby enabling the first circuit board 100 and the second circuit board 200 to be Has a uniform and fixed gap.

In particular, when the creation of the circuit board structure 10, 20, 30 When the two circuit boards 200 are connected to the circuit board on which the wafers are disposed, the formed structure can be regarded as a generally known POP structure, wherein the second circuit board 200 is an intermediate component that connects the upper package structure and the lower package structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the novel creation, and any person skilled in the art can make some changes without departing from the spirit and scope of the novel creation. Retouching, the scope of protection of this new creation is subject to the definition of the scope of the patent application attached.

10‧‧‧Circuit board structure

100‧‧‧First circuit board

101‧‧‧ first surface

102‧‧‧ wafer

103‧‧‧ second surface

104‧‧‧First dielectric core

105‧‧‧Bumps

106‧‧‧First line structure

107‧‧‧Package colloid

108‧‧‧Second line structure

110‧‧‧ solder balls

111, 113, 115, 211‧‧ ‧ through holes

112, 114, 116, 118, 212, 214‧‧‧ line patterns

117, 119‧‧‧ dielectric layer

120‧‧‧ pads

121, 123, 221, 223‧‧‧ solder mask

122‧‧‧Active surface

132‧‧‧Back

200‧‧‧second circuit board

201‧‧‧ third surface

203‧‧‧ fourth surface

204‧‧‧Second dielectric core

206‧‧‧ Third line structure

208‧‧‧fourth line structure

210‧‧‧conductive column

L1, L2‧‧‧ line pattern spacing

Claims (10)

A circuit board structure comprising: a first circuit board comprising a first dielectric core, a first line structure, a second line structure and a plurality of solder balls, wherein the first dielectric core has a first surface opposite to each other a second surface, the first line structure is disposed on the first surface, and the second line structure is disposed on the second surface and electrically connected to the first line structure, the solder ball and The first circuit structure is electrically connected; the wafer is disposed on the first circuit board and electrically connected to the first circuit board by a plurality of bumps; and the second circuit board, and the first The circuit board is oppositely disposed, the second circuit board includes a second dielectric core, a third line structure, a fourth line structure and a plurality of conductive columns, wherein the second dielectric core has a third surface opposite to each other a fourth surface, the third line structure is disposed on the third surface, and the fourth line structure is disposed on the fourth surface and electrically connected to the third line structure, the conductive column and the The fourth line structure is electrically connected, and The solder balls connected to the conductive posts. The circuit board structure according to claim 1, wherein the ball diameter of the solder ball is between 60 μm and 180 μm. The circuit board structure of claim 1, wherein the length of the conductive pillar is between 30 μm and 200 μm. The circuit board structure of claim 1, wherein a gap between the first circuit board and the second circuit board is between 60 μm and 200 μm. The circuit board structure of claim 1, wherein the first dielectric core has a thickness of between 50 μm and 250 μm. The circuit board structure of claim 1, wherein the second dielectric core has a thickness of between 50 um and 150 um. The circuit board structure of claim 1, further comprising an encapsulant disposed on the first circuit structure, the encapsulant exposing the solder ball and covering the wafer. The circuit board structure of claim 1, further comprising an encapsulant disposed on the first circuit structure, the encapsulant exposing the solder ball and exposing a back surface of the wafer. The circuit board structure of claim 1, further comprising an encapsulant disposed between the first circuit board and the second circuit board, and filling the first circuit board and the first The space between the two boards. The circuit board structure of claim 1, wherein a pitch of the line patterns in the first line structure is smaller than a pitch of the line patterns in the third line structure.