JP2012063462A - Lcd control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of making an LCD module securely operate with a clock signal and image data output from a DSP.SOLUTION: An LCD control system includes the LCD module, the DSP which generates the clock signal and the image data to be output to the LCD module, and a clock frequency division circuit which converts the clock signal to a clock signal of lower frequency. The DSP generates an output image data having pixels increased in a horizontal direction so that when the clock signal to be output does not meet conditions under which the LCD module operates, the image data is expanded in lateral width at a magnification ratio, matching a multiple of the clock signal, to the frequency of the clock with which the LCD module operates, and the clock frequency division circuit converts the clock signal so as to meet conditions under which the LCD module operates, and outputs the converted clock signal and the output image data to the LCD module.

Description

  The present invention relates to an LCD control system, and more particularly to a control method for controlling an LCD using a latest DSP.

  The conventional LCD control system has a first mode that operates with a clock signal with a high frequency and a second mode that operates with a clock signal with a low frequency, and displays a still image, a low-speed moving image, or the like on the LCD panel. Inputs image data from the external memory to the LCD controller in the state of the first mode, and then switches to the low speed mode to input image data from the LCD controller to the LCD module to display an image on the LCD module. (For example, refer to Patent Document 1).

JP 2007-121699 A (paragraph “0036” -paragraph “0055”, FIG. 1)

  However, in the above-described conventional technology, the frequency of the clock signal corresponds to the operation of the LCD module in any mode, and a DSP that outputs a frequency different from the frequency for operating the LCD module is used as the LCD controller. It does not mention a method of operating the LCD module.

In general, the control method by the LCD control system cannot operate the LCD module unless the frequency output by the LCD controller is a frequency satisfying the operation condition of the LCD module. Therefore, a DSP specialized for image processing used in recent years is used. Even if it is used instead of the conventional LCD controller, there is a problem that it cannot be used unless the frequency condition for operating the LCD module is met.
An object of the present invention is to provide means for solving the above problems.

  In order to solve the above-described problems, the present invention provides an LCD module, a DSP that generates a clock signal and image data output to the LCD module, and a clock frequency dividing circuit that converts the clock signal into a low-frequency clock signal. When the clock signal to be output does not meet the conditions for operating the LCD module, the DSP performs horizontal conversion of the image data at a magnification that matches the multiple of the clock signal with respect to the frequency of the clock for operating the LCD module. In order to expand the width of the direction, the output image data with the increased number of pixels in the horizontal direction is generated, and the clock signal is converted by the clock frequency dividing circuit so as to meet the conditions for operating the LCD module. Outputting a clock signal and the output image data to the LCD module; And butterflies.

  As a result, the present invention provides an effect that the LCD module can be operated using the latest DSP.

1 is a block diagram showing an LCD control system of Embodiment 1. FIG. Explanatory drawing which shows the example of mapping which displays the image data in Example 1 Explanatory drawing showing an example of generated output image data Timing chart of one horizontal line displayed on the LCD module

  Embodiments of an LCD control system according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram illustrating an LCD control system according to the first embodiment.
In FIG. 1, reference numeral 1 denotes an LCD control system, which performs control for displaying an image based on image data received from a CPU of a device (not shown) equipped with the present system on an LCD (Liquid Crystal Display).

Reference numeral 2 denotes a DSP (Digital Signal Processor), which is a processor for processing a digital signal, and includes a built-in LCD controller for controlling an LCD module 5 to be described later, an internal memory 2a, and a program stored in the internal memory 2a. The image data is calculated and processed according to the above, and the processed image data, horizontal synchronization signal, and clock signal are output.
The DSP 2 in this embodiment outputs a clock frequency in the range of 6.25 MHz to 75 MHz.

Reference numeral 3 denotes an SDRAM (Synchronous DRAM) as a semiconductor memory, which is an external memory connected to the DSP 2 and stores image data input to a device (not shown) equipped with the LCD control system 1 of the present invention.
Although SDRAM is used as the semiconductor memory 3, it is needless to say that the present invention is not limited to this and can be used in memory systems other than SDRAM.

  Reference numeral 4 denotes a clock frequency dividing circuit, which divides an inputted clock signal and converts a high frequency clock signal to a low frequency. For example, if a 10 MHz clock signal is inputted, the clock signal is converted to a 5 MHz clock signal.

Reference numeral 5 denotes an LCD module, which is connected to the DSP 2 via the clock frequency dividing circuit 4 by the connection cable 6a, and further directly connected to the DSP 2 by the connection cable 6b.
In the LCD module 5, image data output from the DSP 2 is input via the connection cable 6 b, and a clock signal output from the DSP 2 is input via the connection cable 6 a and the clock frequency dividing circuit 4. Displays video according to the image data.

Note that the LCD module 5 includes a horizontal counter (not shown), and has a function of recognizing the voltage level of the horizontal synchronization signal by the horizontal counter and measuring the timing of video display start.
A mapping process for displaying an image on the LCD module 5 will be described.

  Here, FIG. 2 is an explanatory diagram showing an example of mapping for displaying image data in the first embodiment. As shown in FIG. 2, the pixels of the LCD module 5 are 15 pixels in one line in the horizontal direction. It is assumed that a predetermined number n of the lines are arranged. At this time, the 15 pixels arranged in the horizontal direction are distinguished by identifiers 1 to 9 and AF.

Then, when displaying an image based on the received image data, the LCD module 5 uses the first pixel in the upper left of FIG. 2 as the first pixel of the first line, and the color based on the image data in order from the first to the right. Are displayed until the Fth pixel as the last pixel of the first line.
When the display of the first line is finished, the display after the second line is performed in the same manner as described above, and the video display is completed by finishing the display of the nth line as the final line.

The operation of the above configuration will be described.
In this embodiment, a CPU of a device (not shown) equipped with the LCD control system 1 stores image data in the SDRAM 3 of the LCD control system 1. The DSP 2 reads image data from the SDRAM 3 and generates output image data based on the read image data.
In this embodiment, it is assumed that the image frequency of the output image data output from the DSP 2 and the clock frequency are both 10 MHz, whereas the frequency supported by the LCD module 5 is 5 MHz.

Here, FIG. 3 is an explanatory diagram showing an example of generated output image data.
The output image data generated by the DSP 2 increases the data to be displayed on each pixel 1 to F in one line twice as shown in FIG. 3 for the image data to display the video as shown in FIG. The increased data is adjacent to the base data, that is, as shown in FIG. 2, arranged in the order 1, 1, 2, 2,... E, E, F, F from the left, and this is performed on each line. Go.

The output image data generated in this way becomes double-width expanded data for displaying a video that is doubled only in the horizontal direction with respect to the original image data.
When the DSP 2 transmits a horizontal synchronization signal to the LCD module 5 via the connection cable 6b and receives a signal from the LCD module 5 indicating that the voltage level of the horizontal synchronization signal has reached the maximum value H, the generated output image is generated. Data is transmitted to the LCD module 5 via the connection cable 6b, and a clock signal is transmitted to the LCD module 5 via the connection cable 6a and the clock frequency dividing circuit 4.

Here, FIG. 4 is a timing chart of one line in the horizontal direction displayed on the LCD module, and the horizontal axis represents time.
In FIG. 4, the DSP output clock is the clock signal output from the DSP 2, the DSP output data is the output image data output from the DSP 2, the LCD input clock is the clock signal input to the LCD module 5, and the LCD input data is It is shown as image data input to the LCD module 5.

The LCD module 5 sequentially outputs the data of each pixel according to the output image data in accordance with the frequency of the clock signal, and composes an image.
At this time, the clock signal becomes 5 MHz, which is half of 10 MHz, by the clock frequency dividing circuit 4, so that an image based on the output image data is constructed in synchronization with the 5 MHz clock signal.

  The DSP 2 outputs the data of each pixel according to the output image data in accordance with the frequency of 10 MHz, but the clock signal becomes 5 MHz through the clock frequency dividing circuit 4, and the LCD is synchronized with the clock signal that has become 5 MHz. The module 5 side receives the output image data.

  For this reason, output image data is sent from the DSP 2 at a clock twice that of the clock for operating the LCD module 5, but the LCD module 5 can only accept one of the data, so that the result of FIG. Data 1 to F indicated by the LCD input data are sequentially input, and the same data as the original image data received by the DSP 2 from a CPU (not shown) is input.

  As described above, in this embodiment, data that is doubled horizontally is generated for a DSP and an LCD module having different clock conditions, and data from the DSP is divided into two clocks with twice the clock of the LCD module. By outputting continuously, data can be input under a clock condition suitable for the LCD module, and an image can be displayed.

1 LCD control system 2 DSP
2a Internal memory 3 SDRAM
4 Clock divider circuit 5 LCD module 6a, 6b Connection cable

Claims (2)

An LCD module, a DSP that generates a clock signal and image data to be output to the LCD module, and a clock frequency dividing circuit that converts the clock signal into a low-frequency clock signal;
If the clock signal to be output does not meet the conditions for operating the LCD module, the DSP expands the width of the image data in the horizontal direction at a magnification that matches the multiple of the clock signal with respect to the frequency of the clock on which the LCD module operates. And generating output image data in which the number of pixels in the horizontal direction is increased, and converting the clock signal to meet the conditions for operating the LCD module by the clock frequency dividing circuit, and converting the converted clock signal and the output An LCD control system for outputting image data to the LCD module. The LCD control system according to claim 1.
When the frequency of the clock signal output by the DSP is 10 MHz and the LCD module operates under the condition of 5 MHz, the DSP generates output image data in which the horizontal width of the image data is doubled. And a clock signal is converted from 10 MHz to 5 MHz by the clock frequency dividing circuit.

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