JP5198818B2 - Synchronous processing system and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a synchronous processing system that controls a predetermined object to be processed by synchronous processing of a plurality of ICs (semiconductor integrated circuits), and a semiconductor integrated circuit used in the synchronous processing system.

  2. Description of the Related Art Conventionally, there is known a synchronous processing system that controls a predetermined processing object by synchronous processing of a plurality of ICs.

  For example, Patent Document 1 describes a technique for controlling display of one liquid crystal panel by synchronization processing of a plurality of ICs (two ICs in Patent Document 1).

  FIG. 6 shows an example of a configuration in the case where the display of the panel 18 ′ such as a liquid crystal panel is controlled by synchronization processing of two ICs.

  In general, when one panel 18 'is controlled by two ICs, one of the ICs is a master IC 12', the other IC is a slave IC 14 ', and the master IC 12' is a control clock signal (see FIG. 6 (1) clock) and a signal for synchronizing the display timing of the frame (frame-synchronizing-signal (hereinafter referred to as “fsync signal” shown in FIG. 6)). In this configuration, the signals are output to the slave ICs 14 ′ for synchronization. This frame generally indicates a display interval of one screen, and this interval is generally controlled with a period of several tens to several hundreds of Hz.

  Further, the host (Host) 16 ′ performs various settings to the master IC 12 ′ and the slave IC 14 ′ through the parallel IF (interface) and the serial IF ((3) in FIG. 6), writing of display image data, and display start / stop. Take control.

  At this time, the timing of the clock signal ((1) in FIG. 6) generated by the master IC 12 'and the data write from the host 16' ((3) in FIG. 6) are completely asynchronous. For this reason, the master IC 12 'and the slave IC 14' generally receive data set from the host 16 'and use the data internally at the timing of processing based on the clock signal.

  FIG. 7 shows an example of a timing chart regarding the operation of the conventional master IC 12 'and slave IC 14'.

  For example, when the display of the panel 18 ′ is started using the master IC 12 ′ and the slave IC 14 ′, as shown in FIG. 7, the host 16 ′ displays both the master IC 12 ′ and the slave IC 14 ′ as Display-ON (FIG. 7 (4), (7)) is set. This Display-ON is a signal indicating a display start request from the host 16 '.

  The timing at which the Display-ON signal becomes High is completely asynchronous with the clock signals of the master IC 12 'and the slave IC 14'. Therefore, in each IC, the Display-ON signal is once latched in accordance with the control clock signal in the IC in order to synchronize the Display-ON signal. This is a metastable measure. Although it depends on the process and operating frequency, it is usually latched by two or more flip-flops, but this flip-flop is not shown. This metastable is a phenomenon in which the output races when the setup / hold time of the data with respect to the clock signal of the flip-flop cannot be satisfied, and it finally cannot be settled to either High or Low. Therefore, in order to absorb the racing time, several stages of flip-flops are provided, and latching is performed by the several stages of flip-flops.

  The master IC 12 ′ and the slave IC 14 ′ do not use the timing of the signal latched in accordance with the clock signal ((5) and (8) in FIG. 7) as they are, but starts display after receiving the fsync signal (see FIG. 7). 7 (6), (9)).

This is because the display timing of the panel 18 'is synchronized with the display timing of the frame indicated by the fsync signal so that the display start timing can be easily controlled, and the synchronization can be easily performed when a plurality of ICs are used. There is a purpose.
JP-A-6-274134

  However, in the general control described above, the ON / OFF control of the display on the panel 18 ′ by the synchronization processing of the master IC 12 ′ and the slave IC 14 ′ is shifted by one frame period of the fsync signal due to the following factors. There was a problem that there was.

  The following factors can be considered for the occurrence of this problem.

<Factor 1>
The Display-ON command set from the host 16 ′ is issued to both the master IC 12 ′ and the slave IC 14 ′, but is the same depending on the clock skew difference between ICs and the metastable because it is asynchronous with the clock signal inside the IC. Data may not be latched at the timing.

<Factor 2>
In the case of a specification in which settings from the host 16 ′ cannot be performed simultaneously on two ICs, there is no choice but to set serially (for example, set the slave IC 14 ′ after setting the master IC 12 ′). There is a possibility of crossing the display timing. In general, the host 16 'side does not perform the setting by detecting the signal state inside the IC such as the fsync signal. This is because the wiring increases and the burden on the host 16 'side increases.

  Even if the settings can be made at the same time, the latch timing for latching data will eventually shift due to the problem of <Factor 1>.

  FIG. 8 shows a case where data cannot be latched at the same timing due to the above-described <Factor 1> when display start (Display-ON) is set simultaneously from the host 16 'to both the master IC 12' and the slave IC 14 '. An example of the timing chart is shown.

  (1) and (2) in FIG. 8 are delays that occur when a signal output from the master IC 12 'is input to the slave IC 14', and this always occurs due to wiring delay and IO delay.

  (3), (4), (5), and (6) in FIG. 8 are control signals latched by flip-flops for taking measures against metastable in each IC, and are set asynchronously with the clock signal. This control is necessary for using the Display-ON in synchronization with the clock signal. Note that (3), (4), (5), and (6) in FIG. 8 are provided with two stages of flip-flops (FF), for example, and two stages of asynchronous signals are converted into two stages by an internal clock signal. It is an example of the timing received.

  Here, when Display-ON is set from the host 16 ′ to the master IC 12 ′ and the slave IC 14 ′ at the timing of (7) in FIG. 8, the output of the anti-metastable flip-flop in each IC is shown in FIG. The timing is as shown ((3), (4), (5), (6) in FIG. 8).

  As described above, the final display start timing inside the IC is a clock signal in which the signals (4) and (6) are High and the fsync signal is High in order to synchronize between the ICs. Is the processing timing ((8), (9) in FIG. 8), and the panel 18 ′ starts display at this timing.

  From the above results, it can be seen that the display start timing of the master IC 12 ′ and the slave IC 14 ′ is shifted by one frame period depending on the display-ON timing set by the host 16 ′ as shown in FIG. .

  This is due to signal line skew and metastable problems that are always present when synchronizing the ICs of two or more chips as shown in (1) and (2) of FIG. Is not supplied to the two chips at the same time, the skew cannot be prevented due to variations in the characteristics of each IC.

  In addition, this problem occurs not only in the control of synchronization processing at the start of display, but also at the time of display stop, and the display start and stop in the 1 fsync (several tens to several hundreds of Hz) section occurs. This may cause problems such as flickering on the screen.

  The present invention has been made in view of the above facts, and an object thereof is to provide a synchronization processing system and a semiconductor integrated circuit that can synchronize synchronization processing by a plurality of semiconductor integrated circuits.

In order to achieve the above object, according to the first aspect of the present invention, there is provided a clock generation means for generating and outputting a clock signal, and a synchronization timing signal indicating a timing for performing processing synchronously with respect to a predetermined processing object. timing generating means for outputting the periodically generated based on the clock signal, and periodically generated when an instruction signal for instructing the start of a predetermined process from an external apparatus is input by said timing generation means First processing execution means for executing the predetermined processing at a timing based on the synchronization timing signal, the clock signal output from the first semiconductor integrated circuit , and the synchronization timing enter the signal, the case where the command signal from the external device is input, before the timing based on the synchronization timing signal A second semiconductor integrated circuit having a second process execution means for executing predetermined processing, the synchronization processing system wherein the first semiconductor integrated circuit, for an instruction to start predetermined processing from the external device When an instruction signal is input, a notification signal for notifying that the start of a predetermined process is instructed from the external device is generated at a timing that does not overlap with the synchronization timing signal periodically generated by the timing generation unit. The first processing execution means is periodically generated by the timing generation means after the notification means generates the notification signal. The predetermined processing is executed at a timing based on a synchronization timing signal, and the second processing execution means of the second semiconductor integrated circuit is the first semiconductor integrated circuit. Executing the predetermined process at the timing based on the inputted synchronizing timing signal after et input the notification signal, Ru Monodea.

  The first semiconductor integrated circuit according to the first aspect of the present invention periodically generates and outputs a synchronous timing signal indicating a timing for performing processing synchronously with respect to a predetermined processing object, and from an external device. An instruction signal for instructing the start of a predetermined process is input, and when the start of the predetermined process is instructed by the input instruction signal, the start of the predetermined process is instructed After generating and outputting a notification signal for notifying the signal, and outputting the notification signal, a predetermined process is executed at a timing that is a predetermined period in the periodically generated synchronization timing signal.

  On the other hand, the second semiconductor integrated circuit receives a synchronization timing signal and a notification signal and an instruction signal from an external device, and instructs the start of predetermined processing by the input instruction signal. When a notification signal is input, a predetermined process is executed at a timing corresponding to a predetermined cycle in the input synchronization timing signal.

  Thus, according to the first aspect of the present invention, when the first semiconductor integrated circuit is instructed to start the predetermined process by the instruction signal, the notification signal that notifies the start of the predetermined process is instructed. After the notification signal is output, the second semiconductor integrated circuit performs a predetermined process at a timing that is a predetermined period in the periodically generated synchronization timing signal. When the start of the process is instructed and a notification signal is input, the predetermined process is executed at a timing corresponding to the predetermined period in the input synchronization timing signal, so that synchronization of synchronization processes by a plurality of semiconductor integrated circuits is synchronized Can take.

On the other hand, in order to achieve the above object, a second aspect of the present invention provides a clock generating means for generating and outputting a clock signal, and a synchronization timing indicating a timing for performing processing in synchronization with a predetermined processing object. Timing generation means for periodically generating and outputting a signal based on the clock signal, and when an instruction signal for instructing the start of predetermined processing is input from an external device, the timing generation means periodically First processing execution means for executing the predetermined processing at a timing based on the synchronization timing signal generated at the same time, the clock signal output from the first semiconductor integrated circuit, and When a synchronization timing signal is input and the instruction signal is input from the external device, a timing based on the synchronization timing signal is input. And a second semiconductor integrated circuit having a second process execution means for executing the predetermined process, wherein the first semiconductor integrated circuit instructs the start of the predetermined process from the external device. After the instruction signal for input is input, the notification signal for notifying that the start of predetermined processing is instructed from the external device is generated at the timing when the synchronization timing signal is generated by the timing generation unit, Notification means for outputting to the second semiconductor integrated circuit, wherein the first processing execution means executes the predetermined processing at a timing when the notification means generates the notification signal, second process execution means is punished of the predetermined timing based on the sync timing signal which is input after the notification signal inputted from the first semiconductor integrated circuit To run, it is intended.

  Further, according to the first or second aspect of the invention, as in the third aspect of the invention, the processing object is a liquid crystal panel, and the synchronization timing signal displays a screen on the liquid crystal panel. The timing may be indicated.

On the other hand, in order to achieve the above object, a semiconductor integrated circuit according to a fourth aspect of the present invention is synchronized with other semiconductor integrated circuits with respect to a clock generating means for generating and outputting a clock signal and a predetermined processing object. and timing generating means for outputting the periodically generated based on the clock signal synchronized timing signal indicating a timing for performing processing Te, an instruction signal for instructing the start of the predetermined process from the external device is input If the, anda processing execution means for executing the predetermined processing at the timing based on the synchronization timing signal which is periodically generated by the timing generation means, further, the start of the predetermined processing from the external device When the instruction signal for instructing is input, it does not overlap with the synchronization timing signal periodically generated by the timing generation means And a notification means for generating a notification signal for notifying that the start of a predetermined process has been instructed by the external device, and the process execution means, after the notification means generates the notification signal, Ru der which executes the predetermined processing at the timing based on the synchronization timing signal periodically generated by the timing generating means.

According to a fifth aspect of the present invention, there is provided the semiconductor integrated circuit according to the fifth aspect of the present invention, wherein the instruction signal for instructing the start of the synchronization process with the other semiconductor integrated circuit with respect to the predetermined processing object is output from the external device A synchronous timing indicating a timing for performing processing on the predetermined processing object in synchronization with the clock signal generated and output from the other semiconductor integrated circuit, periodically generated based on the clock signal and means to input a signal, if the instruction signal from the external device is input, anda processing execution means for executing the predetermined processing at the timing based on the synchronization timing signal, and further, the other A predetermined process from the external device to the other semiconductor integrated circuit, which is generated and output at a timing that does not overlap the synchronization timing signal in the semiconductor integrated circuit And a means for inputting a notification signal for notifying that the start has been instructed, wherein the processing execution means receives the notification signal input from the other semiconductor integrated circuit when the instruction signal is input from the external device. der which executes the predetermined processing at the timing based on the inputted synchronizing timing signal after the Ru.

  Therefore, by using the semiconductor integrated circuit according to claims 4 and 5, it operates in the same manner as the invention according to claim 1. Therefore, as with the invention according to claim 1, synchronous processing by a plurality of semiconductor integrated circuits is performed. Can be synchronized.

  As described above, according to the present invention, when the first semiconductor integrated circuit is instructed to start the predetermined process by the instruction signal, the notification signal to notify that the start of the predetermined process is instructed. After generating and outputting, and outputting the notification signal, the second semiconductor integrated circuit executes predetermined processing by the instruction signal at predetermined timing in the periodically generated synchronization timing signal. When a start signal is instructed and a notification signal is input, a predetermined process is executed at a timing corresponding to a predetermined period in the input synchronization timing signal. Therefore, synchronization of synchronization processes by a plurality of semiconductor integrated circuits is synchronized. It has an excellent effect that it can be taken.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case of a synchronous processing system that controls display on a panel 18 such as a liquid crystal panel by synchronous processing of two ICs, a master IC and a slave IC, will be described.

  FIG. 1 shows a configuration of a synchronous processing system 10 according to the present embodiment.

The synchronous processing system 10 according to the present embodiment includes a master IC 12 and a slave IC 14, and the master IC 12 controls the clock signal for control ((1) clock in FIG. 1) and the fsync signal (see FIG. 1 (2)) and a display_sync signal ((3) in FIG. 1) for notifying that the start of processing has been instructed is generated and output to the slave IC 14 for synchronization. As described above, the synchronization processing system 10 according to the present embodiment generates the display_sync signal in the master IC 12 ′ constituting the synchronization processing system described in Patent Document 1 shown in FIG. It has a configuration with a function to output to '.

The host 16 controls various settings of the master IC 12 and the slave IC 14, writing of display image data, and display start / stop through a parallel IF (interface) and a serial IF ((4) in FIG. 1). Further, the host 16 sets Display-ON for the master IC 12 and the slave IC 14 when starting display of the panel 18 using the two ICs of the master IC 12 and the slave IC 14. In this case, the timing of the display-ON set by the host 16 and the clock signal generated by the master IC 12 is completely asynchronous, as in the description of the synchronous processing system described in Patent Document 1 shown in FIG. The master IC 12 and the slave IC 14 have a function of receiving data set from the host 16 and executing data processing using the data internally at the timing of processing based on the clock signal.

  FIG. 2 is a block diagram showing functional configurations of the master IC 12 and the slave IC 14.

  The master IC 12 includes a clock signal generation unit 20 that generates a control clock signal, a display timing generation unit 22 that periodically generates an fsync signal that indicates a frame display timing, a host 16, a panel 18, a slave IC 14, and various types. Controls the terminal 24 for inputting / outputting signals, the synchronization notification unit 26 for generating a display_sync signal for notifying that the display start is instructed when the display start is instructed from the host 16, and the display on the panel 18. And a display control processing unit 28 for executing the control processing.

  The clock signal, the fsync signal, and the display_sync signal generated by the clock signal generation unit 20, the display timing generation unit 22, and the synchronization notification unit 26 are output to the slave IC 14 via the terminal 24.

On the other hand, the slave IC 14 includes a terminal 30 for inputting / outputting various signals to / from the host 16, the panel 18, and the master IC 12, and a display control processing unit 32 that executes control processing for controlling display on the panel 18. Yes.

  Next, FIG. 3 shows an example of a timing chart regarding the operations of the master IC 12 and the slave IC 14.

  3 is a control clock signal generated by the master IC 12, and (2) in FIG. 3 is an fsync signal generated by the master IC 12.

  When starting display, the host 16 sets Display-ON (3) in both the master IC 12 and the slave IC 14.

  Next, the host 16 sets display_sync_1st (4) of the master IC 12.

  When the display_sync_1st (4) is set, the synchronization notification unit 26 outputs a High display_sync signal at a timing that does not overlap with fsync.

  Thereafter, the master IC 12 and the slave IC 14 perform the following control.

The display control processing unit 28 and the display control processing unit 32 latch the respective Display_ON signal (5) with the display_sync signal to obtain Display-ON_2nd. ((6) in FIG. 3)
Then, the display control processing unit 28 and the display control processing unit 32 display on the panel 18 at a timing ((7) in FIG. 3) indicated by the fsync signal after the latched Display-ON_2nd becomes High. Perform control processing.

  As described above, according to the present embodiment, a display_sync signal for display notifying that the start of processing is instructed in the master IC 12 is generated at a timing that does not overlap the fsync signal on the master IC 12 side, and is generated in the slave IC 14. In the master IC 12 and the slave IC 14, the display start signal is latched in a three-stage configuration (first stage: latched by the control signal from the host 16, second stage: latched by clock at the timing of the display_sync signal, third stage: fsync The display start timing between the master IC 12 and the slave IC 14 can be synchronized with the fsync signal, and the synchronization processing of the master IC 12 and the slave IC 14 to the panel 18 is synchronized. Can , Flickering of the screen displayed on the panel 18 can be suppressed.

  In this control method, the display can be synchronized with the fsync signal even when the Display-ON setting timing is largely deviated between the master IC 12 and the slave IC 14, and can be synchronized even when the display is OFF.

  In addition to display ON / OFF, it is also possible to use a control signal to be synchronized with a frame.

  In FIG. 3, the case where the display start timing is synchronized with the timing indicated by the fsync signal after Display-ON_2nd becomes High has been described. However, the present invention is not limited to this, for example, As shown in FIG. 4, a disp_on signal is added instead of the display_sync signal.

  For example, as shown in the timing chart of the disp_on signal shown in FIG. 5, the host 18 first sets Display-ON (4) of the master IC 12.

  The master IC 12 latches each Display-ON with the fsync signal, generates a disp_ON signal ((5) in FIG. 5), and outputs it to the slave IC 14.

  In the slave IC, the display control process may be performed on the panel 18 at the timing indicated by the fsync signal after the inputted disp_ON becomes High.

  Further, in the present embodiment, a case has been described in which two ICs are used to perform synchronous control of display of the panel 18 as a processing object. However, the present invention is not limited to this, and two or more are controlled. It is applicable to products that need to be synchronized with each other using the IC.

  In addition, the configuration of the synchronous processing system 10 described in the present embodiment (see FIG. 1) is merely an example, and it is needless to say that the configuration can be appropriately changed without departing from the gist of the present invention.

It is a block diagram which shows the whole structure of the synchronous processing system which concerns on embodiment. It is a block diagram which shows the function structure of the master IC and slave IC which concern on embodiment. 4 is a timing chart regarding operations of a master IC and a slave IC according to an embodiment. It is a block diagram which shows another structure of the synchronous processing system which concerns on embodiment. 6 is a timing chart regarding operations of a master IC and a slave IC having different configurations according to the embodiment. It is a block diagram which shows the structure of the conventional synchronous processing system. It is a timing chart regarding operation | movement of the conventional master IC and slave IC. It is a timing chart when the latch timing which latches data in the conventional master IC and slave IC shifts.

Explanation of symbols

10 synchronous processing system 12 master IC (first semiconductor integrated circuit)
14 Slave IC (second semiconductor integrated circuit)
18 Panel (object to be processed)
22 Display timing generation unit (generation means)
24 terminals (input / output means)
26 Synchronization notification part (notification means)
28 Display control processing unit (first processing execution means, processing execution means)
30 terminals (input means)
32 Display control processing unit (second process execution means, process execution means)

Claims (5)

Clock generating means for generating and outputting a clock signal, for a given object to be processed, the timing to output a synchronization timing signal indicating a timing for performing a process in synchronization with periodically generated based on the clock signal generator means, and, when an instruction signal for instructing the start of a predetermined process from an external apparatus is input, the predetermined processing at the timing based on the synchronization timing signal which is periodically generated by the timing generator A first semiconductor integrated circuit having first processing execution means for executing;
The clock signal output from said first semiconductor integrated circuit, and inputs the synchronization timing signal, if the instruction signal from the external device is input, executes the predetermined processing at the timing based on the synchronization timing signal A second semiconductor integrated circuit having second processing execution means for
In the synchronous processing system with
In the first semiconductor integrated circuit, when an instruction signal for instructing the start of a predetermined process is input from the external device, the first semiconductor integrated circuit does not overlap with the synchronization timing signal periodically generated by the timing generation unit. A notification means for generating a notification signal for notifying that the start of predetermined processing is instructed from the external device and outputting the notification signal to the second semiconductor integrated circuit,
The first process execution unit executes the predetermined process at a timing based on the synchronization timing signal periodically generated by the timing generation unit after the notification unit generates the notification signal.
A second process execution unit of the second semiconductor integrated circuit executes the predetermined process at a timing based on the synchronization timing signal input after the notification signal input from the first semiconductor integrated circuit;
Synchronous processing system . Clock generation means for generating and outputting a clock signal, timing generation for periodically generating and outputting a synchronization timing signal indicating a timing for performing processing in synchronization with a predetermined processing object based on the clock signal And when the instruction signal for instructing the start of the predetermined process is input from the external device, the predetermined process is performed at a timing based on the synchronization timing signal periodically generated by the timing generation unit. A first semiconductor integrated circuit having first processing execution means for executing;
When the clock signal and the synchronization timing signal output from the first semiconductor integrated circuit are input and the instruction signal is input from the external device, the predetermined processing is executed at a timing based on the synchronization timing signal. A second semiconductor integrated circuit having second processing execution means for
In the synchronous processing system with
The first semiconductor integrated circuit receives an instruction signal for instructing the start of a predetermined process from the external device, and then, from the external device at a timing when the synchronization timing signal is generated by the timing generation unit. Notification means for generating a notification signal for notifying that the start of predetermined processing has been instructed and outputting the notification signal to the second semiconductor integrated circuit,
The first process execution unit executes the predetermined process at a timing when the notification unit generates the notification signal,
Second process execution means of said second semiconductor integrated circuit performs the predetermined processing at the timing based on the synchronization timing signal which is input after the notification signal inputted from the first semiconductor integrated circuit,
Synchronization processing system. The processing object is a liquid crystal panel,
The synchronization processing system according to claim 1, wherein the synchronization timing signal indicates a display timing for displaying a screen on the liquid crystal panel. Clock generation means for generating and outputting a clock signal;
A timing generation means for periodically generating and outputting a synchronization timing signal indicating a timing for performing processing in synchronization with another semiconductor integrated circuit on a predetermined processing object based on the clock signal ;
When an instruction signal for instructing the start of a predetermined process from an external device is input, the process for executing the predetermined processing at the timing based on the synchronization timing signals periodically generated by said timing generation means In a semiconductor integrated circuit having execution means ,
When an instruction signal for instructing the start of predetermined processing is input from the external device, the external device has a predetermined timing at a timing that does not overlap with the synchronization timing signal periodically generated by the timing generation unit. A notification means for generating a notification signal notifying that the start of processing has been instructed,
The process execution unit executes the predetermined process at a timing based on the synchronization timing signal periodically generated by the timing generation unit after the notification unit generates the notification signal.
Semiconductor integrated circuit . Means for inputting an instruction signal for instructing the start of synchronization processing with another semiconductor integrated circuit with respect to a predetermined object to be processed, output from an external device;
A clock signal generated and output from the other semiconductor integrated circuit, a synchronization timing signal periodically generated based on the clock signal, and indicating a timing for performing processing in synchronization with the predetermined processing object and the means to enter the,
If the instruction signal from the external device is input, a process execution means for executing the predetermined processing at the timing based on the synchronization timing signal,
In the semiconductor integrated circuit having,
A notification signal that is generated and output at a timing that does not overlap with the synchronization timing signal in the other semiconductor integrated circuit and that notifies the other semiconductor integrated circuit that the start of predetermined processing has been instructed from the external device Has means for inputting
The processing execution means executes the predetermined processing at a timing based on the synchronization timing signal input after the notification signal input from the other semiconductor integrated circuit when the instruction signal is input from the external device. Do
Semiconductor integrated circuit .

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