JP2012060743A - Control circuit of dc/dc converter, dc/dc converter using the same, light emitting device and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an area of a control circuit of a DC/DC converter.SOLUTION: A charging circuit 30 charges a capacitor C2, and a discharging circuit 32 discharges the capacitor C2 in an on state. A comparator 38 generates a release signal S1 whose level is changed corresponding to the voltage Vof the capacitor C2. A logic circuit 40 asserts a fail signal S3 when an abnormality detection signal S2 is asserted, negates the fail signal S3 when the abnormality detection signal S2 is negated at the timing at which the release signal S1 is shifted to a first level, and keeps asserting the fail signal S3 when the abnormality detection signal S2 is asserted at the timing. Also, the logic part 40 controls the discharging circuit 32 corresponding to the release signal S1. An inverting amplifier 46 generates a soft start voltage Vss by inverting the voltage Vof the capacitor C2.

Description

  The present invention relates to a control circuit for a DC / DC converter.

  A DC / DC converter is used to boost or step down a DC voltage such as a battery voltage. The control circuit of the DC / DC converter detects an abnormality occurring in the DC / DC converter, for example, an overvoltage state, an overcurrent state, a temperature abnormality state, etc., and performs circuit protection in the abnormal state. The control circuit includes a timer circuit that monitors the abnormal state, and determines whether or not the abnormal state continues for each predetermined determination period. The control circuit also includes a soft start circuit that generates a soft start voltage that gradually increases with time in order to prevent an inrush current at the time of startup. The control circuit increases the output voltage of the DC / DC converter by following the soft start voltage.

JP-A-9-121535 JP 7-336999 A

  The abnormality detection timer circuit and soft start circuit each require an external capacitor, and thus the number of parts increases. Further, since the control circuit requires two pins (pads) for connecting an external capacitor, the chip size and the package size are increased.

  The present invention has been made in view of these problems, and one of the exemplary purposes of an aspect thereof is to reduce the size of the control circuit of the DC / DC converter.

  One embodiment of the present invention relates to a control circuit for a DC / DC converter. The control circuit includes a capacitor whose potential at the first terminal is fixed, a charging circuit that charges the capacitor, a discharge circuit that can be switched on and off, and that discharges the capacitor in the on state, and the voltage of the capacitor is predetermined. The first level is taken during a period from when the upper threshold voltage of the capacitor is reached to when the upper threshold voltage is lowered to the predetermined lower threshold voltage. During the period until the threshold voltage is reached, the comparator that generates the release signal that takes the second level, the release signal, and the abnormality detection signal that is asserted when an abnormal state is detected are received, and the abnormality detection signal is asserted. Then, when the fail signal is asserted and then the abnormality detection signal is negated at the timing when the release signal transitions to the first level, the fail signal is negated. At that timing, if the abnormality detection signal is asserted, the logic that continues to assert the fail signal, turns on the discharge circuit when the release signal is at the first level, and turns off the discharge circuit when the release signal is at the second level And an inverting amplifier that generates a soft start voltage by inverting the voltage of the capacitor.

  According to this aspect, the slope voltage generated in the abnormality detection timer circuit can be used as the soft start voltage after release from the abnormal state. As a result, the timer circuit and the soft start circuit can be used together, and the size can be reduced.

  The logic unit may include a set priority SR flip-flop in which an abnormality detection signal is input to the set terminal and a release signal is input to the reset terminal.

  The logic unit may further include an OR gate that generates a logical sum of the inverted output signal of the SR flip-flop and the release signal and controls the discharge circuit.

  Another aspect of the present invention is a DC / DC converter. This DC / DC converter includes the above-described control circuit.

  Yet another embodiment of the present invention is a light emitting device. The light-emitting device includes a light-emitting element and the above-described DC / DC converter that supplies a driving voltage to the light-emitting element.

  Yet another embodiment of the present invention is an electronic device. This electronic device includes a liquid crystal panel and the above-described light emitting device provided as a backlight of the liquid crystal panel.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, the circuit area can be reduced.

It is a circuit diagram which shows the structure of an electronic device provided with the drive circuit which concerns on embodiment. 2 is a time chart showing the operation of the drive circuit of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. It includes the case of being indirectly connected through another member that does not affect the connection state.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 1 is a circuit diagram illustrating a configuration of an electronic device 2 including a DC / DC converter according to an embodiment.

  The electronic device 2 is a battery-driven device such as a notebook PC, a digital camera, a digital video camera, a mobile phone terminal, or a PDA (Personal Digital Assistant), and includes a light emitting device 3 and an LCD (Liquid Crystal Display) panel 5. The light emitting device 3 is provided as a backlight of the LCD panel 5.

  The light emitting device 3 includes an LED string 6 that is a light emitting element and a drive circuit 4 thereof.

  The LED string 6 includes a plurality of LEDs connected in series. The drive circuit 4 includes a step-up DC / DC converter, boosts an input voltage (for example, battery voltage) Vin input to the input terminal P1, and outputs an output voltage (drive voltage) Vout from the output terminal P2. One end (anode) of the LED string 6 is connected to the output terminal P2.

  The drive circuit (DC / DC converter) 4 includes a control IC 100 and an output circuit 102. The output circuit 102 includes an inductor L1, a rectifier diode D1, a switching transistor M1, and an output capacitor C1. Since the topology of the output circuit 102 is general, description thereof is omitted.

  The switching terminal P4 of the control IC 100 is connected to the gate of the switching transistor M1. The control IC 100 adjusts the ON / OFF duty ratio of the switching transistor M1 by feedback so that the output voltage Vout necessary for lighting the LED string 6 can be obtained and the drive current corresponding to the target luminance flows to the LED string 6. To do. The switching transistor M1 may be built in the control IC 100.

The first detection resistor R1 is provided on the path of the LED string 6, specifically, between the cathode of the LED string 6 and the ground terminal. The error amplifier EA1 is the voltage drop _{V R1} generated in the first detection resistor R1 amplifies an error control voltage _{V DIM,} to generate an error voltage _{V FB.} The oscillator 60 generates a periodic voltage V _OSC of a triangular wave or a sawtooth wave. The PWM comparator PMW_CMP receives a periodic voltage V _OSC , a soft start voltage Vss described later, and an error voltage V _FB . The PWM comparator PWM_CMP compares the periodic voltage V _OSC with the lower one of the soft start voltage Vss and the error voltage _VFB . The duty ratio of the output (gate pulse signal G1) of the PWM comparator PWM_CMP is adjusted so that the voltage drop V _R1 of the first detection resistor R1 matches the control voltage V _DIM . The driver DR1 drives the switching transistor M1 of the DC / DC converter based on the gate pulse signal G1. A pulse frequency modulator may be used instead of the pulse width modulator.

The first comparator CMP1, the voltage drop _{V R1} of the first detection resistor R1 exceeds the first threshold voltage _{V TH1,} asserts a first overcurrent detection signal OCP1. The second detection resistor R2 is provided on the path of the switching transistor M1 of the DC / DC converter. The second comparator CMP2 is the voltage drop _{V R2} of the second detection resistor R2 asserts the second overcurrent detection signal OCP2 exceeds the second threshold voltage _{V TH2.}

The resistors R3 and R4 divide the drive voltage Vout. The overvoltage detection third comparator CMP3 compares the voltage Vout ′ divided by the resistors R3 and R4 with a predetermined threshold voltage _VTH3 . The third comparator CMP3 asserts the overvoltage detection signal OVP when Vout ′> _VTH3 .

  When at least one of the detection signals OCP1, OCP2, and OVP is asserted, the driver DR1 immediately fixes the gate pulse signal G1 to a low level and turns off the switching transistor M1, thereby stopping the DC / DC switching operation.

  The capacitor C2 is externally attached to the capacitor terminal P5. One end (first terminal) of the capacitor C2 is grounded to fix the potential. The charging circuit 30 charges the capacitor C2. The discharge circuit 32 can be switched between on and off, and discharges the capacitor C2 in the on state. Discharge circuit 32 includes a resistor 34 and a transistor 36 provided in series in the discharge path. When the transistor 36 is on, the discharge circuit 32 is on, and when the transistor 36 is off, the discharge circuit 32 is off.

The comparator 38 has a function of a so-called hysteresis comparator, compares the voltage V _{C2 of the} capacitor C2 with a predetermined upper threshold voltage VH and a predetermined lower threshold voltage VL, and outputs a release signal S1 according to the comparison result. Is generated. Release signal S1 is time for the voltage V _C2 of the capacitor C2 decreases after reaching the upper threshold voltage VH to a predetermined lower threshold voltage VL, take the first level (a high level), The voltage V _{C2 of the} capacitor C2 takes the second level (low level) during the period from when the voltage V _C2 drops to the lower threshold voltage VL until it reaches the upper threshold voltage VH.

  The release signal S1 is used to switch the discharge circuit 32 between the on and off states, and the positive edge of the release signal S1 is used as a timing for re-determining the abnormal state. The logic unit 40 receives the release signal S1 and the abnormality detection signal S2. The abnormality detection signal S2 is a signal that is asserted when any abnormal state is detected in the light emitting device 3, and is generated, for example, by ORing the detection signals OCP1, OCP2, OVP, and the like by the OR gate 39. Is done. In addition to or instead of these detection signals, the OR gate 39 includes a UVLO (Under Voltage Lock Out) signal indicating a low voltage state of a power supply voltage supplied from the outside, a THD (Thermal ShutDown) signal indicating a temperature abnormality, and the like. You may receive.

  When the abnormality detection signal S2 is asserted, the logic unit 40 asserts the fail signal S3 (low level). Thereafter, when the abnormality detection signal S2 is negated at the timing when the release signal S1 transits to the first level (high level), the logic unit 40 negates (fails) the fail signal S3. If the abnormality detection signal S2 is asserted at the re-determination timing at which the release signal S1 transitions to the high level, the logic unit 40 continues to assert the fail signal S3 without negating it.

  The logic unit 40 turns on the discharge circuit 32 when the release signal S1 is at the first level (high level), and turns off the discharge circuit 32 when the release signal S1 is at the second level (low level).

  The logic unit 40 includes an SR flip-flop 42 and an OR gate 44. The abnormality detection signal S2 is input to the set terminal (S) of the SR flip-flop 42, and the release signal S1 is input to the reset terminal (R). The SR flip-flop 42 is configured with set priority logic. When both the signals of the set terminal and the reset terminal are at a high level, the set terminal has priority.

  The inverted output signal #Q (# indicates logic inversion) of the SR flip-flop 42 corresponds to the fail signal S3. The OR gate 44 generates a logical sum of the fail signal S3 and the release signal S1, and controls the discharge circuit 32.

Inverting amplifier 46, resistors Ri, include Rf and an operational amplifier OA1, and generates a soft start voltage Vss by reversing the voltage _{V C2} of the capacitor C2. The switch SW1 is provided between the output terminal of the inverting amplifier 46 and the PWM comparator PWM_CMP. The switch SW1 is turned on after the soft start period, and the soft start voltage Vss is supplied to the inverting input terminal of the PWM comparator PWM_CMP. During the period before the soft start period, the switch SW1 is turned off. The switch SW1 is configured so that the potential of the inverting input terminal of the PWM comparator PWM_CMP does not float in the off state. For example, the switch SW1 may be turned on while the fail signal S3 is at a high level.

  The output circuit 50 outputs the fail signal S3 to a processor (not shown) outside the control IC 100. Output circuit 50 includes an inverter 52 and a transistor 54. The inverter 52 inverts the fail signal S3. The transistor 54 constitutes an open drain type output circuit.

  The above is the configuration of the drive circuit 4. Next, the operation will be described. FIG. 2 is a time chart showing the operation of the drive circuit 4 of FIG. When the abnormality detection signal S2 is asserted at time t0, the inverted output #Q of the SR flip-flop 42 transitions to the low level, and the fail signal S3 is asserted (low level).

When the fail signal S3 becomes low level, the transistor 36 is turned off, the discharge circuit 32 is turned off, the capacitor C2 is charged by the charging circuit 30, and the capacitor voltage V _C2 rises. When the capacitor voltage V _C2 reaches the upper threshold voltage VH at time t1, the release signal S1 is changed to the high level.

Even when the release signal S1 transits to a high level at time t1, since the abnormality detection signal S2 is asserted, the SR flip-flop 42 is not reset by the set priority logic, and the fail signal S3 continues to maintain the low level. When the release signal S1 transitions to a high level, the transistor 36 is turned on, the capacitor C2 is discharged, and the capacitor voltage V _C2 starts to decrease. When the capacitor voltage V _C2 decreases to the lower threshold voltage VL, the release signal S1 transitions to a low level (t2), and the capacitor C2 is charged again. When capacitor voltage _{V C2} at time t3 reaches the upper threshold voltage VH, release signal S1 becomes a high level.

  The control IC 100 repeats the same processing. The abnormality detection signal S2 is negated at time t4. When the release signal S1 transitions to a high level at time t4, the SR flip-flop 42 is reset, and the fail signal S3 transitions to a high level. When the fail signal S3 transits to a high level, the switch SW1 is turned on.

  When the switch SW1 is turned on, the output voltage Vss of the inverting amplifier 46 is supplied to the PWM comparator PMW_CMP. As a result, the duty ratio of the gate pulse signal G1 increases with time, and the output voltage Vout gradually increases.

The above is the operation of the drive circuit 4.
According to the control IC 100, the release signal S1 that is a periodic signal and the soft start voltage Vss can be generated by charging and discharging the single capacitor C2. As a result, it is possible to reduce the number of capacitors that have been conventionally required to two, thereby reducing the circuit area.

Further, since the soft start voltage Vss is generated by inverting the slope of the voltage V _C2 generated in the capacitor C2, when the fail signal S3 is negated, the soft start voltage Vss can be generated immediately. .

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications may exist in each of those constituent elements, each processing process, and a combination thereof. Hereinafter, such modifications will be described.

In the embodiment, the configuration in which the drive current is stabilized by matching the voltage drop V _R1 of the first detection resistor R1 provided on the path of the LED string 6 with the target value V _DIM has been described. Is not limited to this. For example, a constant current source (current driver) that generates a stable drive current may be provided on the path of the LED string 6.

  In the embodiment, a non-insulated switching power supply using an inductor has been described, but the present invention can also be applied to an insulating switching power supply using a transformer.

  In the embodiment, the electronic apparatus has been described as an application of the light emitting device 3, but the application is not particularly limited and can be used for lighting or the like.

  In the present embodiment, the setting of the high level and low level logic signals is merely an example, and can be freely changed by appropriately inverting it with an inverter or the like.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 2 ... Electronic device, 3 ... Light-emitting device, 4 ... Drive circuit, 5 ... LCD panel, 6 ... LED string, C2 ... Capacitor, 30 ... Charge circuit, 32 ... Discharge circuit, 34 ... Resistance, 36 ... Transistor, 38 ... Comparator , 40 ... logic section, 42 ... SR flip-flop, 44 ... OR gate, 46 ... inverting amplifier, 50 ... output circuit, 52 ... inverter, 54 ... transistor, SW1 ... switch, 100 ... control IC, 102 ... output circuit, EA1 ... error amplifier, DR1 ... first driver, CMP1 ... first comparator, CMP2 ... second comparator, CMP3 ... third comparator, R1 ... first detection resistor, R2 ... second detection resistor, L1 ... inductor, C1 ... output capacitor , D1 ... rectifier diode, M1 ... switching transistor, OCP1 ... first overcurrent detection signal, O P2 ... second overcurrent detection signal, OVP ... overvoltage detection signal, S1 ... release signal, S2 ... abnormality detection signal, S3 ... fail signal.

Claims (8)

A control circuit for a DC / DC converter,
A capacitor having a fixed potential at the first terminal;
A charging circuit for charging the capacitor;
A discharge circuit that can be switched on and off, and discharges the capacitor in an on state;
A first level is taken during a period from when the voltage of the capacitor reaches a predetermined upper threshold voltage to when the voltage decreases to a predetermined lower threshold voltage, and the voltage of the capacitor is the lower threshold voltage A comparator that generates a release signal that takes a second level during a period from when the voltage falls to the upper threshold voltage,
The release signal and an abnormality detection signal that is asserted when an abnormal state is detected are asserted, a fail signal is asserted when the abnormality detection signal is asserted, and then the release signal transitions to the first level. When the abnormality detection signal is negated at the timing to perform, the fail signal is negated. When the abnormality detection signal is asserted at the timing, the fail signal is continuously asserted, and the release signal is A logic unit that turns on the discharge circuit when the first level is selected and turns off the discharge circuit when the release signal is the second level;
An inverting amplifier that generates a soft start voltage by inverting the voltage of the capacitor;
A control circuit comprising:   The control circuit according to claim 1, further comprising a switch provided on a path of the soft start voltage on an output terminal side of the inverting amplifier.   3. The control circuit according to claim 2, wherein the switch is turned off while the fail signal is asserted and turned on while the fail signal is negated.   The logic unit includes a set priority SR flip-flop in which the abnormality detection signal is input to a set terminal and the release signal is input to a reset terminal. The control circuit described. The logic unit further includes
5. The control circuit according to claim 4, further comprising an OR gate that generates a logical sum of the inverted output signal of the SR flip-flop and the release signal and controls the discharge circuit.   A DC / DC converter comprising the control circuit according to claim 1. A light emitting element;
The DC / DC converter according to claim 6, wherein a driving voltage is supplied to the light emitting element.
A light emitting device comprising: LCD panel,
The light emitting device according to claim 7 provided as a backlight of the liquid crystal panel;
An electronic device comprising:

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