JP2012060560A - Serial communication apparatus and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a serial communication apparatus including an interface circuit having a transmitter-receiver circuit that communicates with an internal circuit using a predetermined synchronous clock and a PLL circuit that generates the synchronous clock based on a reference clock to be input, thus preventing erroneous operations of the interface circuit and the internal circuit.SOLUTION: A delay circuit 5 delays a reset signal PERST# generated after a frequency of a reference clock REFCLK is stable at 100 MHz by a predetermined delay time Δt to generate an internal reset signal PERST2 and outputs the signal to a link controller 31. A PHY circuit 2 is reset in response to the reset signal PERST#, and the link controller 31 is reset in response to the internal reset signal PERST2. Also, the delay time Δt is set to be longer than a lock-up time previously calculated based on a circuit specification of a PLL circuit 23.

Description

  The present invention relates to a serial communication device that performs high-speed serial data communication in conformity with a standard such as PCI (Peripheral Component Interconnection) Express or USB 3.0 (Universal Serial Data Bus Version 3.0), and a control method thereof.

  PCI Express is positioned as the “third-generation PC interface standard” following PCI, and uses 2.5 Gbps serial signal transmission, a signal connection path that does not have a point-to-point or bus structure, and a protocol. It has features such as data communication and software PCI compatibility. PCI Express is also used for communication between LSIs on a personal computer board, communication between boards, and short-distance communication using a cable (see Non-Patent Document 1).

  FIG. 3 is a block diagram showing the configuration of the endpoint device 1A according to the prior art. In FIG. 3, an endpoint device 1A is a semiconductor integrated circuit of a memory card controller, and communicates with other semiconductor integrated circuits such as a CPU (Central Processing Unit) via a link transmission line compliant with the PCI Express standard. Transmit and receive transmission data packets and reception data packets. The endpoint device 1A includes a card controller 3 including a link controller 31 and a PHY circuit 2. The link controller 31 is an LSI that transmits a PCI Express MAC layer (Media Access Layer) signal. The PHY circuit 2 is an LSI of an interface circuit that transmits a physical coding sublayer signal of the physical layer of PCI Express. The link controller 31 and the PHY circuit 2 are connected via a PIPE transmission line 4 which is a parallel signal transmission line compliant with the PIPE (PHY Interface for the PCI Express Architecture) interface standard (refer to Non-Patent Document 2; hereinafter referred to as PIPE). Are connected to each other.

  In FIG. 3, the PHY circuit 2 includes a transmission / reception circuit 21, a differential detection circuit 22, and a PLL (Phase Locked Loop) circuit. The differential detection circuit 22 inputs reference clocks REFCLKP and REFCLKN supplied from a reference clock generation circuit provided outside the endpoint device 1A. The reference clocks REFCLKP and REFCLKN are low voltage differential signals having a frequency of 100 MHz. The differential detection circuit 22 detects the difference between the input reference clocks REFCLKP and REFCLKN, generates the reference clock REFCLK based on the detected difference, and outputs it to the PLL circuit 23. Furthermore, the PLL circuit 23 generates a signal transmission clock SCLK having a frequency of 2.5 GHz and a synchronous clock PCLK having a frequency of 125 MHz based on the input reference clock REFCLK, and the signal transmission clock SCLK. Is output to the transmission / reception circuit 21, and the synchronous clock PCLK is output to the link controller 31. The transmission / reception circuit 21 packetizes the data received from the link controller 31 into a transmission data packet according to the signal transmission clock SCLK, and transmits the packet to another semiconductor integrated circuit via the transmission terminal Tx. The received data packet is received from the semiconductor integrated circuit, a predetermined receiving process is performed using the signal transmission clock SCLK, and the processed received data packet is transmitted to the link controller 31. Here, the link controller 31 and the transmission / reception circuit 21 transmit / receive data according to the synchronous clock PCLK.

  In FIG. 3, a power-on reset circuit 10 provided outside the endpoint device 1A includes a resistor 11 and a capacitor 12 connected in series between a power supply that outputs a predetermined power supply voltage Vcc and the ground. Configured. The power-on reset circuit 10 generates a global reset signal GBRST that rises later than the power supply voltage Vcc by a predetermined delay time set by the element values of the resistor 11 and the capacitor 12. Output from the connection point between. In the endpoint device 1A according to the related art, the global reset signal GBRST is output to the reset input terminal Reset of the PHY circuit 2 and the reset input terminal RS1 of the link controller 31, and is used to reset the entire endpoint device 1A. . In response to the low-level global reset signal GBRST, the circuits 21 to 23 of the PHY circuit 2 and the circuits in the link controller 31 that are not related to communication with the PHY circuit 2 are reset.

  Further, in FIG. 3, the reset signal PERST # generated in the external circuit of the endpoint device 1A is output to the reset input terminal RS2 of the link controller 31. Here, the high level reset signal PERST # indicates that the power supply voltage Vcc is within the specified voltage and is stable. The PCI Express standard stipulates that the voltage level of the reset signal PERST # becomes high after 100 microseconds or more have elapsed after the reference clock REFCLK has stabilized. Therefore, when the reset signal PERST # becomes high level, the reference clock REFCLK is also in a stable state. In FIG. 3, a circuit related to communication with the PHY circuit 2 among the circuits in the link controller 31 is reset in response to a low level reset signal PERST #.

  Instead of the endpoint device 1A shown in FIG. 3, the endpoint device 1B according to the prior art shown in FIG. 9 is also used. In FIG. 9, the endpoint device 1B further includes a power-on reset circuit 10A as compared with the endpoint device 1A. The power-on reset circuit 10A is configured in the same way as the power-on reset circuit 10, generates a power-on reset signal Ponrst similar to the global reset signal GBRST, and resets the reset input terminal Reset of the PHY circuit 2 and the link controller 31. Output to the input terminal RS2.

  Further, the frequency of the reference clock REFCLK is set to 5 GHz in the PCI Express 2.0 standard, and is set to 8 GHz in the PCI Express 3.0 standard. Furthermore, the frequency of the synchronous clock PCLK is set to 125 MHz when transmitting / receiving 16-bit data, and is set to 250 MHz when transmitting / receiving 8-bit data.

  Furthermore, a method for generating the reset signal PERST # is described in Patent Documents 1 and 2, for example.

  FIG. 4 is a timing chart showing the reference clocks REFCLKP and REFCLKN input to the differential detection circuit 22 of FIG. 3 and the normal reference clock REFCLK output from the differential detection circuit 22, and FIG. 4 is a timing chart showing reference clocks REFCLKP and REFCLKN input to the differential detection circuit 22 of FIG. 3 and an abnormal reference clock REFCLK output from the differential detection circuit 22. FIG. As shown in FIG. 4, the reference clocks REFCLKP and REFCLKN are substantially at the ground level when no differential input is made. At this time, when the differential detection circuit 22 is operating normally, the reference clock REFCLK is in a stopped state. However, when the differential detection circuit 22 detects a slight difference between the reference clocks REFCLKP and REFCLKN when the reference clocks REFCLKP and REFCLKN are substantially at the ground level, as shown in FIG. A large reference clock REFCLK is generated. The PLL circuit 23 may malfunction due to an abnormal reference clock REFCLK.

  Therefore, by configuring the circuit that receives the reference clock REFCLK to have a hysteresis characteristic, when the voltage levels of the reference clocks REFCLKP and REFCLKN are both at the ground level, the difference between the voltage levels is very small. Is controlled so as not to detect the difference. Thereby, during the period when the reference clock REFCLK is stopped, the problem that the abnormal reference clock REFCLK as shown in FIG. 5 is not transmitted to the inside of the endpoint device 1A and the PLL circuit 23 malfunctions can be solved.

  FIG. 6 shows the power supply voltage Vcc, the global reset signal GBRST, the reference clocks REFCLKP and REFCLKN, the reference clock REFCLK, the reset signal PERST #, and the synchronization clock PCLK during normal operation of the endpoint device 1A of FIG. It is a timing chart which shows. In FIG. 6, when the power supply of the endpoint device 1A is turned on at timing tp, in response to this, the voltage level of the global reset signal GBRST becomes high level at timing tg after timing tp. In response to the high level global reset signal GBRST, the resetting of the circuits 21 to 23 in the PHY circuit 2 is released, and the operation starts.

  In FIG. 6, generation of the reference clocks REFCLKP and REFCLKN is started at a predetermined timing t1 after the power is turned on. The reference clocks REFCLKP and REFCLKN are unstable until timing t2 immediately after timing t1, but are stable after timing t2. Further, the PLL circuit 23 generates an unstable synchronous clock PCLK based on the unstable reference clock REFCLK during the period from the timing t1 to the timing t2, and the PLL circuit 23 is locked even after the reference clock REFCLK is stabilized. An unstable synchronous clock PCLK is generated until timing t3. Then, at timing tr after timing t3 when the PLL circuit 23 is locked, the reset signal PERST # is deasserted (set to high level), and the link controller 31 starts communication with the PHY circuit 2.

  Normally, as shown in FIG. 6, since the PLL circuit 23 is normally locked during the period from the timing tp to the timing tr when the reset signal PERST # is asserted (set to the low level), the timing starts from the timing t1. Even if the unstable synchronous clock PCLK up to t3 is output to the link controller 31, since the initialization of the link controller 31 continues, no abnormality caused by the unstable synchronous clock PCLK occurs.

  However, if the PLL circuit 23 does not lock normally during the period when the reset signal PERST # is asserted, and if the lockup time becomes longer than that, it is caused by the unstable synchronous clock PCLK. There was a problem that the card controller 3 malfunctioned. FIG. 7 is a timing chart showing the global reset signal GBRST, the reference clocks REFCLKP and REFCLKN, the reference clock REFCLK, the reset signal PERST #, and the synchronous clock PCLK when the PLL circuit 23 of FIG. 3 is not locked. As shown in FIG. 7, when the PLL circuit is not locked, the correct synchronous clock PCLK is not output to the link controller 31 after the timing tr when the reset signal PERST # is deasserted, so that the card controller 3 malfunctions. Similarly, when the lock-up time of the PLL circuit 23 becomes abnormally longer than the lock-up time defined in the device, the PLL circuit 23 is not locked at the timing tr when the reset signal PERST # is deasserted. As a result, the card controller 3 malfunctions.

  Next, the reason why the PLL circuit 23 does not lock normally will be described. In order for the PLL circuit 23 to lock normally, it is necessary to input a normal reference clock REFCLK. However, as shown in FIG. 6, since the reference clock REFCLK is not stable when the reference clock REFCLK is started (period from timing t1 to timing t2), the PLL circuit 23 performs the locking operation based on the abnormal reference clock REFCLK. Do. At this time, some PHY circuits 2 may malfunction due to an abnormal reference clock REFCLK and may not return to a normal state. For example, if a high-frequency reference clock REFCLK higher than the frequency allowed by the PLL circuit 23 is output to the PLL circuit 23, the PLL oscillation frequency cannot follow the high-frequency reference clock REFCLK. As a result, even if the PLL circuit 23 is locked in an abnormal state and the reference clock REFCLK is stabilized in a normal state, the PLL circuit 23 continues to oscillate abnormally and does not lock normally (see FIG. 8).

  In general, the PLL circuit 23 includes a lock detection circuit. When the lock detection circuit detects that the PLL circuit 23 is locked, the operation of the PHY circuit 2 is started. As a result, the PHY circuit 2 can be prevented from starting to operate until the PLL circuit 23 is locked, and malfunction of the PHY circuit 2 can be prevented. However, when the unstable reference clock REFCLK is output to the PLL circuit 23 for a relatively long time, the lock detection circuit may accidentally detect the lock. As a result, the PHY circuit 2 operates according to the signal transmission clock SCLK and the synchronous clock PCLK output from the PLL circuit 23 whose operation is not stable, and falls into an abnormal state.

  Such a problem cannot be prevented by configuring the circuit that receives the reference clock REFCLK to have a hysteresis characteristic as described above. Further, whether or not such a problem occurs depends on the state of the input reference clock REFCLK and the characteristics of the PHY circuit 2 to be used, and therefore cannot be predicted at the design stage, and can be found by actually making a prototype of the device. Or it may not be known until mass production, which could be a big problem.

  The object of the present invention is to solve the above-described problems, and to transmit / receive a communication circuit that communicates with an internal circuit such as the card controller 3 using a predetermined synchronization clock, and to transmit the synchronization clock based on an input reference clock. An object of the present invention is to prevent malfunction of an interface circuit and an internal circuit in a serial communication apparatus including an interface circuit including a generated PLL circuit and a control method thereof.

The serial communication device according to the first invention is:
In a serial communication device including an interface circuit including a transmission / reception circuit that performs communication with an internal circuit using a predetermined synchronization clock and a PLL circuit that generates the synchronization clock based on an input reference clock,
An external reset signal generated after the frequency of the reference clock is stabilized at a predetermined frequency, a delay circuit that delays a predetermined delay time to generate an internal reset signal and outputs the internal reset signal;
The interface circuit is reset in response to the external reset signal,
The internal circuit is reset in response to the internal reset signal,
The delay time is set longer than a lockup time calculated in advance based on the circuit specifications of the PLL circuit.

  In the serial communication device, the delay circuit delays the external reset signal by the delay time set by counting the reference clock.

In the serial communication device, the external reset signal is a reset signal PERST # conforming to the PCI Express standard.
The reference clock is a reference clock REFCLK compliant with the PCI Express standard.

The serial communication device control method according to the second invention comprises:
Control of a serial communication device including an interface circuit including a transmission / reception circuit that communicates with an internal circuit using a predetermined synchronous clock and a PLL circuit that generates the synchronous clock based on an input reference clock In the method
The serial communication device delays an external reset signal generated after the reference clock frequency is stabilized at a predetermined frequency by a predetermined delay time, generates an internal reset signal, and outputs the internal reset signal to the internal circuit With
The serial communication device control method is as follows:
Resetting the interface circuit in response to the external reset signal;
In response to the internal reset signal, resetting the internal circuit,
The delay time is set longer than a lockup time calculated in advance based on the circuit specifications of the PLL circuit.

  In the control method of the serial communication device, the delay circuit delays the external reset signal by the delay time set by counting the reference clock.

Further, in the control method of the serial communication device,
The external reset signal is a reset signal PERST # conforming to the PCI Express standard,
The reference clock is a reference clock REFCLK compliant with the PCI Express standard.

  According to the serial communication device and the control method thereof according to the present invention, the interface circuit is reset in response to an external reset signal generated after the frequency of the reference clock is stabilized at a predetermined frequency, and the internal circuit is externally reset. The signal is reset in response to an internal reset signal generated by delaying the signal by a predetermined delay time, and the delay time is set longer than the lockup time calculated in advance based on the circuit specifications of the PLL circuit. It is possible to prevent malfunction of the circuit and the internal circuit.

It is a block diagram which shows the structure of the endpoint device 1 which concerns on embodiment of this invention. 2 is a timing chart showing a power supply voltage Vcc, a global reset signal GBRST, a reset signal PERST #, reference clocks REFCLKP and REFCLKN, a reference clock REFCLK, an internal reset signal PERST2, and a synchronous clock PCLK in FIG. It is a block diagram which shows the structure of the endpoint device 1A which concerns on a prior art. 4 is a timing chart showing reference clocks REFCLKP and REFCLKN input to the differential detection circuit 22 of FIG. 3 and a normal reference clock REFCLK output from the differential detection circuit 22. FIG. 4 is a timing chart showing reference clocks REFCLKP and REFCLKN input to the differential detection circuit 22 of FIG. 3 and an abnormal reference clock REFCLK output from the differential detection circuit 22. FIG. 3 is a timing chart showing a power supply voltage Vcc, a global reset signal GBRST, reference clocks REFCLKP and REFCLKN, a reference clock REFCLK, a reset signal PERST #, and a synchronous clock PCLK during normal operation of the endpoint device 1A of FIG. is there. 4 is a timing chart showing a global reset signal GBRST, reference clocks REFCLKP and REFCLKN, a reference clock REFCLK, a reset signal PERST #, and a synchronous clock PCLK when the PLL circuit 23 of FIG. 3 is not locked. 4 is a timing chart showing a global reset signal GBRST, reference clocks REFCLKP and REFCLKN, a reference clock REFCLK, a reset signal PERST #, and a synchronous clock PCLK when the PLL circuit 23 of FIG. 3 oscillates abnormally. It is a block diagram which shows the structure of the endpoint device 1B which concerns on a prior art.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

Embodiment.
FIG. 1 is a block diagram showing a configuration of an endpoint device 1 according to an embodiment of the present invention. FIG. 2 shows a power supply voltage Vcc, a global reset signal GBRST, a reset signal PERST #, and a reference clock shown in FIG. 4 is a timing chart showing REFCLKP and REFCLKN, a reference clock REFCLK, an internal reset signal PERST2, and a synchronous clock PCLK.

  The endpoint device 1 according to the present embodiment delays the reset signal PERST #, which is an external reset signal generated after the frequency of the reference clock REFCLK is stabilized at a predetermined frequency, by delaying the internal reset signal PERST2 by a delay time Δ. The PHY circuit 2 is reset in response to the reset signal PERST #, the link controller 31 is reset in response to the internal reset signal PERST2, and the delay time Δt is generated. Is characterized by being set longer than the lockup time calculated in advance based on the circuit specifications of the PLL circuit 23.

  In FIG. 1, an endpoint device 1 is a semiconductor integrated circuit of a memory card controller, and transmits and receives data packets to and from other semiconductor integrated circuits such as a CPU via a link transmission line compliant with the PCI Express standard. Send and receive data packets. The endpoint device 1 includes a card controller 3 that includes a link controller 31, a PHY circuit 2, and a delay circuit 5. Here, the link controller 31 is an LSI that transmits signals of the MAC layer of the PCI Express. The PHY circuit 2 is an LSI of an interface circuit that transmits a physical coding sublayer signal of the physical layer of PCI Express. The link controller 31 and the PHY circuit 2 are connected to each other via a PIPE transmission line 4 that is a parallel signal transmission line compliant with the PIPE interface standard.

  In FIG. 1, the PHY circuit 2 includes a transmission / reception circuit 21, a differential detection circuit 22, and a PLL circuit. The differential detection circuit 22 receives reference clocks REFCLKP and REFCLKN supplied from a reference clock generation circuit provided outside the endpoint device 1. The reference clocks REFCLKP and REFCLKN are low voltage differential signals having a frequency of 100 MHz. The differential detection circuit 22 detects the difference between the input reference clocks REFCLKP and REFCLKN, generates the reference clock REFCLK based on the detected difference, and outputs the reference clock REFCLK to the clock input terminals of the PLL circuit 23 and the delay circuit 5. To do. Furthermore, the PLL circuit 23 generates a signal transmission clock SCLK having a frequency of 2.5 GHz and a synchronous clock PCLK having a frequency of 125 MHz based on the input reference clock REFCLK, and the signal transmission clock SCLK. Is output to the transmission / reception circuit 21, and the synchronous clock PCLK is output to the link controller 31. The transmission / reception circuit 21 packetizes the data received from the link controller 31 into a transmission data packet according to the signal transmission clock SCLK, and transmits the packet to another semiconductor integrated circuit via the transmission terminal Tx. The received data packet is received from the semiconductor integrated circuit, a predetermined receiving process is performed using the signal transmission clock SCLK, and the processed received data packet is transmitted to the link controller 31. Here, the link controller 31 and the transmission / reception circuit 21 transmit / receive data according to the synchronous clock PCLK.

  Further, in FIG. 1, the reset signal PERST # is output from the outside of the endpoint device 1 to the reset input terminal Reset of the PHY circuit 2. Here, the high level reset signal PERST # indicates that the power supply voltage Vcc is within the specified voltage and is stable. In the PCI Express standard, after the reference clock REFCLK is stabilized (that is, after the frequency of the reference clock REFCLK is stabilized at 100 MHz), the voltage level of the reset signal PERST # becomes high (deasserted) after 100 microseconds have elapsed. )). Therefore, when the reset signal PERST # becomes high level, the reference clock REFCLK is also in a stable state. Each of the circuits 21 to 23 in the PHY circuit 2 is reset when the reset signal PERST # is asserted (at a low level), and reset is released when it is deasserted (at a high level). To start the operation.

  Further, in FIG. 1, the delay circuit 5 receives the reset signal PERST #, and generates a low-level internal reset signal PERST2 in response to the low-level reset signal PERST #. Further, the delay circuit 5 starts counting the reference clock REFCLK at the rising timing of the reset signal PERST #, and generates a high-level internal reset signal PERST2 when the reference clock REFCLK is counted by the number corresponding to the delay time Δt. . That is, the delay circuit 5 delays the reset signal PERST # by a delay time Δt set by counting the reference clock REFCLK and generates an internal reset signal PERST2. Further, the internal reset signal PERST2 is output to the reset input terminal RS2 of the link controller 31. That is, the internal reset signal PERST2 is in the reset state, that is, the asserted state when the reset signal PERST # is asserted, and the delay time Δt timed using the reference clock REFCLK after the reset signal PERST # is deasserted. Deasserted after elapses. As described above, since the frequency of the reference clock REFCLK is stable at 100 MHz at the timing when the reset signal PERST # is deasserted, the delay circuit 5 starts from the timing at which the reset signal PERST # is deasserted. The delay time Δt can be measured by counting.

  Here, the delay time Δt is set to a time longer than the lock-up time of the PLL circuit 23 calculated in advance based on the circuit specifications of the PHY circuit 2 including the PLL circuit 23. In this specification, the lock-up time refers to the frequency of the synchronous clock PCLK output from the PLL circuit 23 when the PLL circuit 23 is locked from the timing at which the normal reference clock REFCLK is output to the PLL circuit 23. This is the period until the timing of convergence to the frequency (in this embodiment, 125 MHz). For example, the lock-up time of the PLL circuit 23 is 50 microseconds, and at this time, the delay time Δt is set to 100 microseconds, for example. In this case, the number of reference clocks REFCLK corresponding to the delay time Δt is 10,000.

  In FIG. 1, a power-on reset circuit 10 provided outside the endpoint device 1 includes a resistor 11 and a capacitor 12 connected in series between a power supply that outputs a predetermined power supply voltage Vcc and the ground. Configured. The power-on reset circuit 10 generates a global reset signal GBRST that rises later than the power supply voltage Vcc by a predetermined delay time set by the element values of the resistor 11 and the capacitor 12. From the connection point between them, the data is output to the reset input terminal RS1 of the link controller 31.

  Further, among the circuits in the link controller 31, circuits that are not related to communication with the PHY circuit 2 are reset in response to a low level global reset signal GBRST input to the reset input terminal RS1. Of the circuits in the link controller 31, the circuit that communicates with the PHY circuit 2 using the synchronous clock PCLK is reset in response to the low-level internal reset signal PERST2 input to the reset input terminal RS2. The

  Next, the operation of the endpoint device 2 will be described with reference to FIG. In FIG. 2, when the power of the endpoint device 1 is turned on at timing tp, a low level global reset signal GBRST and a low level reset signal PERST # are generated. Next, at a timing tg after the timing tp, the voltage level of the global reset signal GBRST becomes a high level. In response to the high level global reset signal GBRST, the reset of the circuits in the link controller 31 that are not related to the communication with the PHY circuit 2 is canceled and the operation is started.

  In FIG. 2, generation of the reference clocks REFCLKP and REFCLKN is started at a predetermined timing t1 after the power is turned on. Until the timing t2 immediately after the timing t1, the reference clocks REFCLKP and REFCLKN are unstable, but after the timing t2, the frequencies of the reference clocks REFCLKP and REFCLKN are stabilized at 100 MHz. Then, at the timing tr after the frequencies of the reference clocks REFCLKP and REFCLKN are stabilized, the reset signal PERST # is deasserted (set to high level). In response to this, the reset of the circuits 21 to 23 in the PHY circuit 2 is released, and the operation starts. At this time, since the frequencies of the reference clocks REFCLKP and REFCLKN are stable at the timing tr, the PLL circuit 23 locks at the timing t4 when the lockup time calculated in advance based on the circuit specifications of the PHY circuit 2 has elapsed. That is, after timing t4, the frequency of the synchronous clock PCLK is stabilized at 125 MHz.

  Further, in FIG. 2, the voltage level of the internal reset signal PERST2 becomes a high level at the timing tr2 when the delay time Δt has elapsed from the timing tr, and in response to this, the PHY circuit 2 of the circuits in the link controller 31 The circuit that performs communication using the synchronous clock PCLK starts operation, and the link controller 31 and the PHY circuit 2 start communication.

  As shown in FIG. 2, since the normal reference clock REFCLK is supplied at the timing tr when the reset signal PERST # is deasserted, the PLL circuit 23 performs the lock operation using the normal reference clock REFCLK at the timing tr. Start. Since the normal reference clock REFCLK is always input to the PLL circuit 23 at the start of the operation of the PLL circuit 23, the PLL circuit 23 has substantially the same lock-up time as described in the circuit specification (standard document) of the PHY circuit 2. Lock in equal time. Further, since the delay time Δt of the internal reset signal PERST2 from the reset signal PERST # is set with a margin based on the lockup time described in the circuit specifications of the PHY circuit 2, the internal reset signal PERST2 At the timing tr2 when is deasserted, the lock operation of the PLL circuit 23 is necessarily completed.

  As described above, devices conforming to the PCI Express standard according to the prior art, such as the endpoint devices 1A and 1B, include a reset input terminal for initializing the entire device (that is, global reset), or A power-on reset circuit 10A for generating a power-on reset signal Ponrst for initializing the entire device at the start of power supply is configured. In the PCI Express standard, the global reset signal GBRST or the power-on reset signal Ponrst is normally output to the reset input terminal Reset of the PHY circuit 2. This is because if the reset signal PERST # is simply output to the reset input terminal Reset of the PHY circuit 2, the lock of the PLL circuit 23 is naturally not completed when the reset signal PERST # is deasserted, and the reset signal PERST # This is because the PCI Express standard that the PLL circuit 23 is required to be locked at the timing tr when is deasserted cannot be observed. That is, in the design of a device that complies with PCI Express according to the prior art, when a general PHY circuit 2 is used, the PHY circuit 2 includes one reset input terminal Reset, and the reset input terminal Reset has a global reset signal. GBRST was output. Also in the PIPE interface standard, only one reset input terminal Reset is defined in the PHY circuit 2, and a global reset signal GBRST is normally output to the reset input terminal Reset. However, in this case, as shown in FIGS. 7 and 8, the PHY circuit 2 malfunctions and an unstable synchronous clock PCLK is output to the card controller 3. As a result, the card controller 3 also malfunctions. .

  On the other hand, according to the present embodiment, the reset signal PERST # that was not conventionally output to the PHY circuit 2 is output to the PHY circuit 2. For this reason, the reset of the PHY circuit 2 is canceled at the timing tr when the reset signal PERST # is deasserted (that is, the timing when the reference clock REFCLK is stable, see FIG. 2), and the unstable reference clock REFCLK. It is possible to prevent malfunction of the PHY circuit 2 due to the above. Further, since the internal reset signal PERST2 is output to the reset input terminal RS2 of the link controller 31, the synchronization clock PCLK is normal at the timing tr2 when the internal reset signal PERST2 is deasserted. For this reason, the link controller 31 malfunctions after the reset is released. Works fine without.

  Therefore, according to the present embodiment, it is possible to realize the endpoint device 1 that operates safely even if the PHY circuit 2 having any circuit specifications is used. Furthermore, no matter what reference clocks REFCLKP and REFCLKN are supplied during a period when the reference clocks REFCLKP and REFCLKN allowed by the PCI Express standard are unstable (periods from timing t1 to timing t2 in FIG. 2), An endpoint device that operates safely can be realized. Therefore, even if any general PHY circuit 2 is used, the endpoint device 1 can be designed without considering the possibility of malfunction. As a result, the choices of the PHY circuit 2 to be used are expanded, and as a result, not only is it easy to use the PHY circuit 2 having the optimum cost and function, but there is a possibility of a failure that cannot be predicted at the design stage. It is mass-produced as it is, and it is possible to prevent problems from occurring after mass production.

  Note that the endpoint device 1 may be configured to further include the power-on reset circuit 10A of FIG. In this case, the power-on reset circuit 10A is configured in the same manner as the power-on reset circuit 10, generates a power-on reset signal Ponrst similar to the global reset signal GBRST, and outputs it to the reset input terminal RS2 of the link controller 31.

  In the present embodiment, the semiconductor integrated circuit of the endpoint device 1 including the PHY circuit 2 compliant with PCI Express has been described. However, the present invention is not limited to this, and PCI compliant with PCI Express, such as a root complex device. It can be widely applied to an Express device or a circuit conforming to the standard of a high-speed serial communication circuit such as USB3.0.

  As described above, according to the serial communication device and the control method thereof according to the present invention, the interface circuit is reset in response to an external reset signal generated after the frequency of the reference clock is stabilized at a predetermined frequency, The internal circuit is reset in response to the internal reset signal generated by delaying the external reset signal by a predetermined delay time, and the delay time is longer than the lockup time calculated in advance based on the circuit specifications of the PLL circuit. Since it is set, malfunction of the interface circuit and the internal circuit can be prevented.

1 ... Endpoint device,
2 ... PHY circuit,
3… Card controller,
4 ... PIPE transmission line,
5 ... delay circuit,
21 ... Transceiver circuit,
22: Differential detection circuit,
23 ... PLL circuit,
31 ... Link controller,
REFCLKP, REFCLKN ... reference clock,
REFCLK: Reference clock,
PCLK: Synchronous clock,
SCLK: Signal transmission clock,
GBRST: Global reset signal,
PERST #: Reset signal.
PERST2: Internal reset signal.

Specification of US Patent Application Publication No. 2007/0156934. Specification of US Pat. No. 7,549,099.

"PCI Express Base Specification Revision 2.0", Peripheral Component Interconnect-Special Interest Group, December 2006. "PHY Interface for the PCI Express Architecture", Version 1.00, Intel, June 2003.

Claims (6)

An interface circuit including a transmission / reception circuit that communicates with an internal circuit using a predetermined synchronization clock and a PLL (Phase Locked Loop) circuit that generates the synchronization clock based on an input reference clock In serial communication devices,
An external reset signal generated after the frequency of the reference clock is stabilized at a predetermined frequency, a delay circuit that delays a predetermined delay time to generate an internal reset signal and outputs the internal reset signal;
The interface circuit is reset in response to the external reset signal,
The internal circuit is reset in response to the internal reset signal,
The serial communication apparatus, wherein the delay time is set longer than a lockup time calculated in advance based on a circuit specification of the PLL circuit.   2. The serial communication apparatus according to claim 1, wherein the delay circuit delays the external reset signal by the delay time set by counting the reference clock. The external reset signal is a reset signal PERST # conforming to the PCI (Peripheral Component Interconnection) Express standard,
The serial communication device according to claim 1, wherein the reference clock is a reference clock REFCLK that conforms to a PCI Express standard. Control of a serial communication device including an interface circuit including a transmission / reception circuit that communicates with an internal circuit using a predetermined synchronous clock and a PLL circuit that generates the synchronous clock based on an input reference clock In the method
The serial communication device delays an external reset signal generated after the reference clock frequency is stabilized at a predetermined frequency by a predetermined delay time, generates an internal reset signal, and outputs the internal reset signal to the internal circuit With
The serial communication device control method is as follows:
Resetting the interface circuit in response to the external reset signal;
In response to the internal reset signal, resetting the internal circuit,
The control method for a serial communication device, wherein the delay time is set longer than a lockup time calculated in advance based on a circuit specification of the PLL circuit.   5. The method according to claim 4, wherein the delay circuit delays the external reset signal by the delay time set by counting the reference clock. The external reset signal is a reset signal PERST # conforming to the PCI Express standard,
6. The method of controlling a serial communication device according to claim 4, wherein the reference clock is a reference clock REFCLK that conforms to the PCI Express standard.

Images