JP2012060072A - Non-volatile semiconductor memory device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device including a variable resistive element which reduces the variation in the resistance values among elements, restrains read-out disturbance in a high-resistance state, and performs stable switching operation at high speed.SOLUTION: A first electrode is achieved by a bit line BL. A second electrode 26 is constituted by a conductive material of which work function is smaller than the first electrode, has a bottom to contact the upper surface of a relay wiring 67, and comprises a cylindrical region projecting vertically upward so as to penetrate a first interlayer insulation film 21, the first electrode (bit line BL), and a second interlayer insulation film 22. A variable resistive element 25 is formed to project vertically upward so as to contact an outer side face of the second electrode 26 to be connected with the upper surface of the relay wiring 67 with a first buffer layer 23 of metal oxide formed on the underlayer of the bottom and to be connected with the first electrode (bit line BL) in the horizontal direction through a second buffer layer 24 of metal oxide formed on the height position of the first electrode (bit line BL).

Description

  The present invention relates to a nonvolatile semiconductor memory device including a variable resistance element that stores information by a change in electrical resistance, and a memory cell that includes a selection transistor having one diffusion region connected to one end of the element, and its manufacture Regarding the method.

  In recent years, various devices such as FeRAM (Ferroelectric RAM), MRAM (Magnetic RAM), PRAM (Phase Change RAM), etc. as next-generation non-volatile random access memory (NVRAM) capable of high-speed operation instead of flash memory Structures have been proposed, and intense development competition is taking place in terms of high performance, high reliability, low cost, and process consistency.

  In contrast to these existing technologies, a resistive random access memory (RRAM) using a variable resistor having a property of reversibly changing electrical resistance by applying electrical stress (voltage pulse); "RRAM" is a registered trademark of Sharp Corporation). An RRAM element (variable resistance element) is usually configured to include two electrodes with a variable resistor interposed therebetween, and a resistance voltage of the element is reversibly changed by applying a predetermined voltage pulse between the two electrodes. The information storage state is changed.

  A non-volatile semiconductor memory device forms a memory cell array by arranging a plurality of memory cells having variable resistance elements in a matrix in the row direction and the column direction, and performs data write, erase, and read operations for each memory cell Peripheral circuits for controlling are arranged. As the memory cell, a “1R type” memory cell in which one memory cell is composed of only one variable resistance element R, one variable resistance element R, and one selection transistor T due to the difference in components. There exist “1T1R type” memory cells and the like.

As the variable resistor material, transition metal element oxides such as a titanium oxide (TiO ₂ ) film, a nickel oxide (NiO) film, a zinc oxide (ZnO) film, and a niobium oxide (Nb ₂ O ₅ ) film can be used. It is known that there is. For example, Non-Patent Document 1 and Non-Patent Document 2 disclose that an element made of each of the above materials exhibits a reversible resistance change.

  In addition, such a variable resistance element exhibiting a reversible resistance change has an impurity level caused by oxygen vacancies formed in a metal oxide in a band gap, so that the conductivity of an n-type or p-type semiconductor can be reduced. Indicates. It has been confirmed that this resistance change is caused by a state change near the electrode interface.

  In order to perform stable resistance switching (stable transition between a low resistance state and a high resistance state) in a variable resistance element configured using a transition metal oxide as a variable resistor material, a variable resistance It is preferable that only one of the interfaces where the body and the two electrodes are in contact be the switching region. More specifically, the materials used for these two electrodes are made different so that the interface with one electrode is a non-switching interface as an ohmic junction and the interface with the other electrode is a switching interface as a Schottky junction, for example. preferable.

  A variable resistance element configured using a transition metal oxide has a very high initial resistance immediately after manufacture. For this reason, in this state, a switching operation may not be stably performed even when a voltage pulse used for a normal rewriting operation (hereinafter referred to as “rewriting voltage pulse” in this paragraph) is applied. As a countermeasure, a voltage pulse (forming voltage pulse) having a larger voltage amplitude and longer pulse width than the rewrite voltage pulse is applied to the variable resistance element in the initial state before use as a memory element, thereby causing resistance switching. Current paths (hereinafter referred to as “filament paths” where appropriate) are formed. By forming the filament path in advance, when a rewrite voltage pulse is applied to the variable resistance element, a rewrite current flows through the filament path, and a stable transition is made to a desired resistance state.

  Note that the process of forming the filament path in the variable resistor is called “forming process”. The filament path formed by this forming process determines the electrical characteristics of the variable resistance element.

  The forming process is a kind of soft breakdown, and the formation path of the filament path, that is, the electrical characteristics of the element is determined by the current control mode from the start of breakdown.

  Theoretically, the current during forming can be controlled by a current control element such as a transistor connected in series with the variable resistance element. Therefore, it seems that the electrical characteristics of the switching element can be arbitrarily controlled by forming the filament path while appropriately controlling the current during forming by the current control element. However, in practice, there is a very steep increase in current amount at the time of breakdown. For example, when a transistor is used as the current control element, a steep current called a spike current that cannot be controlled flows under the influence of the parasitic capacitance of the transistor. As a result, the formed filament path varies between the variable resistance elements, and it becomes difficult to stably manufacture a variable resistance element that realizes a stable switching operation with a low write current value.

  On the other hand, Patent Document 1 and Non-Patent Document 3 have reported methods for improving electrical characteristics by providing a buffer layer (interface oxide) between a metal oxide used as a variable resistor and an electrode. Yes.

JP 2008-306157 A

H. Pagnia et al., "Bistable Switchingin Electroformed Metal-Insulator-MetalDevices", Phys.Stat.Sol. (A), vol.108, pp.11-65, 1988 Baek, I.G. et al., “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses”, IEDM 04, pp. 587-590, 2004 M.Terai et al., "Effect of Bottom Electrode of ReRAM with Ta2O5 / TiO2Stack on RTN and Retention", IEDM 09, pp.775-778, 2009

  In the field of RRAM, there have been some problems that have not yet been found, since the period has not passed since development began. For example, there are variations in the resistance value of the variable resistance element between elements, and read disturb occurs in a high resistance state.

  Read disturb refers to a phenomenon in which the resistance value of the variable resistance element changes due to a bias voltage applied during a read operation. When reading data from a memory cell having a variable resistance element, a bias voltage is applied to the variable resistance element to cause a read current to flow, and the resistance value of the variable resistance element is determined based on the magnitude of the current. Accordingly, a predetermined bias voltage is applied to the variable resistance element in accordance with the read operation regardless of the configuration of the memory cell. If the resistance value of the variable resistance element changes due to the bias voltage applied during this read operation, the recorded information is lost in the worst case. For this reason, it is required to reduce the degree and frequency of read disturb as much as possible.

The inventors of the present application have made a variable resistance element having the structure shown in FIG. 1 through intensive research and found that it is effective in suppressing read disturb in a high resistance state. The variable resistance element 10 shown in FIG. 1 uses HfO _x (hafnium oxide) as the variable resistor 11, TiN as one electrode (first electrode) 13, and Ti as the other electrode (second electrode) 15. Formed.

  In the variable resistance element 10 shown in FIG. 1, in the high resistance state after the erasing pulse voltage is applied from the TiN electrode 13 side, the polarity of the voltage pulse during the erasing operation and the polarity of the voltage pulse during the reading operation are the same. Thus, it has been found that the read disturb in the high resistance state can be reduced. Here, increasing the resistance is referred to as an erasing operation, and decreasing the resistance is referred to as a writing operation, but the calling method may be reversed.

  FIG. 2 is a graph comparing the difference in polarity of the read voltage when the variable resistance element after the erase operation (that is, in the high resistance state) is read. (A) shows the relationship between the cumulative read count and the resistance value when the erasing pulse voltage and the read voltage have opposite polarities, and (b) shows the same polarity. In the case of (a), the read voltage was 0.6V, and in the case of (b), the read voltage was 0.8V.

  According to FIG. 2, in the case of (a), a large change in the resistance value is already observed after the fifth reading. Further, it can be seen that when the number of times exceeds about 700 times, the read resistance value is remarkably unstable. In (a), in order to show that the resistance value fluctuates up and down violently, the resistance value when the number of readings is 1000 times to 10000 times is also displayed.

  On the other hand, in the case of (b), the resistance values were read out from four different elements, but stable resistance values were read out in all cases.

  Here, the work function of Ti is 4.14 eV, which is an ohmic junction, and the work function of TiN is 4.7 eV, which is a Schottky junction serving as a switching interface. That is, based on the results of FIG. 2, it can be seen that, in the erase operation and the read operation, stable reading can be performed by applying a voltage from the electrode having the larger work function serving as the switching interface.

  In order to realize high-speed operation, it is necessary to reduce the load as much as possible to the wiring with voltage fluctuations in order to reduce disturbance caused by signal delay. For this reason, in general, it is desirable to apply the read voltage from the bit line side with a light load rather than the source line side through the selection transistor.

  Furthermore, the inventors of the present application have considered that the cause of variation in characteristics and readout disturbance is caused on the switching region side by intensive research, and contrary to the teaching of Non-Patent Document 3, a metal oxide as a buffer layer is used. And inserted at the interface with the electrode to be a Schottky junction. As a result, it has been found that there is a great effect in reducing variation and suppressing read disturb. This content has been filed separately and has not been published at the time of filing this application (Japanese Patent Application No. 2010-171079).

  FIG. 3 is a schematic cross-sectional structure diagram of a variable resistance element developed by the present inventors. The variable resistance element 10a includes a first electrode 13 on the semiconductor substrate 12 via an insulating film 16 (also TiN here). Then, the first electrode 13 is oxidized to form a metal oxide as the buffer layer 17 on the surface. The buffer layer 17 is made of TiOx (titanium oxide) in the example of FIG.

Then, the variable resistor 11 is formed on the upper layer of the buffer layer 17, and the second electrode 15 is formed on the upper layer. As in the example of FIG. 1, the variable resistor 11 is made of HfO _x (hafnium oxide), and the second electrode 15 is made of Ti. That is, the second electrode 15 is made of a metal material having a work function smaller than that of the first electrode 13, and the interface of the second electrode 15 is an ohmic junction and the interface of the first electrode 13 is a Schottky junction.

  At this time, the buffer layer 17 is formed in the interface of the 1st electrode 13 which shows a Schottky junction, and shows the variation reduction and the suppression effect of read-out disturbance.

  Here, as described above, in order to perform stable reading, it is necessary to apply a voltage from the electrode having the larger work function, that is, the first electrode 13. That is, it is necessary to form a contact electrode that communicates with the first electrode 13 from above so that a voltage can be applied to the first electrode 13.

  At this time, the voltage is applied upward from the first electrode 13 to the second electrode 15 in terms of structure.

  When an attempt is made to realize a 1T1R type memory cell, the source / drain of the selection transistor is formed on the semiconductor substrate 12 (under the insulating film 16). For this reason, it is necessary to apply a voltage applied upward from the first electrode 13 to the second electrode 15 to one of the source / drain of the selection transistor existing at a position deeper than the second electrode 15. That is, also here, a contact electrode connected from the second electrode 15 to the vicinity of the surface of the semiconductor substrate 12 is required.

  That is, in the structure of FIG. 3, in order to realize a configuration in which one of the source / drain of the selection transistor is electrically connected to the second electrode 15 while allowing voltage application from the outside to the first electrode 13. A complicated structure is required, which causes problems such as process complexity and expansion of the device area.

  On the other hand, in order to solve such a problem, a method of inverting the vertical positions of the first electrode 13 and the second electrode 15 is conceivable (see FIG. 4). In this case, a voltage can be easily applied to the first electrode 13 located above from the outside, and the second electrode 15 is formed at a position deeper than that in FIG. It is also easy to electrically connect one of the source / drain of the selection transistor.

  However, in order to realize the structure of FIG. 4, it is necessary to form the buffer layer 17 after the variable resistor 11 is formed. Since both the variable resistor 11 and the buffer layer 17 are made of metal oxide, when the buffer layer 17 is formed after the variable resistor 11 is stacked, oxygen migration occurs at these interfaces, and a desired electrical property is obtained. Another problem is that it becomes difficult to form the variable resistor 11 having characteristics.

  The present invention is based on the above knowledge obtained by the present inventor, and reduces variation in resistance values between elements, suppresses read disturb in a high resistance state, and can perform stable switching operation at high speed. An object of the present invention is to realize a nonvolatile semiconductor memory device including a resistance element by a simple process.

In order to achieve the above object, a nonvolatile semiconductor memory device of the present invention includes a variable resistance element having a first electrode, a second electrode, and a variable resistor sandwiched between the two electrodes on a semiconductor substrate; A non-volatile semiconductor memory device comprising a memory cell having a selection transistor having one of a source and a drain electrically connected to the second electrode,
Above the selection transistor, each wiring layer includes a first wiring, a second wiring, and a relay wiring, and a first interlayer insulating film is provided on the upper surface covering the wiring layer, and the first electrode, Having the second interlayer insulating film in this order from the bottom,
The first electrode is made of a conductive material having a work function larger than that of the second electrode,
The second electrode has a bottom surface that is in contact with the top surface of the relay wiring, and includes a first cylindrical portion that penetrates the first interlayer insulating film, the first electrode, and the second interlayer insulating film. ,
The variable resistor is made of a metal oxide, is in contact with an outer surface of the first cylindrical portion of the second electrode, and includes the first interlayer insulating film, the first electrode, and the second interlayer insulating film. Penetrating and having a second cylindrical part whose bottom surface is higher than the bottom surface of the second electrode,
Between the outer surface of the second cylindrical portion and the first electrode, there is a buffer layer formed of a metal oxide of a material different from that of the variable resistor,
The relay wiring is electrically connected to one of a source and a drain of the selection transistor, the first wiring is electrically connected to a gate electrode, and the second wiring is electrically connected to the other of the source and the drain. And

  In addition to the above features, this nonvolatile semiconductor memory device has another feature that the buffer layer is made of an oxide of the material constituting the first electrode.

  In addition to the above characteristics, this nonvolatile semiconductor memory device has another characteristic in that the variable resistor includes an oxide of Hf or Zr.

  In addition to the above characteristics, this nonvolatile semiconductor memory device has a configuration in which the first electrode includes a conductive material of Ti nitride, Ta nitride, W, Ni, or Co. And

  In addition to the above characteristics, this nonvolatile semiconductor memory device has another feature that the second electrode includes a conductive material of any one of Ti, Ta, Al, Hf, and Zr.

In addition to the above features, the nonvolatile semiconductor memory device includes a memory cell array in which a plurality of the memory cells are arranged in a row direction and a column direction, and a plurality of the first wirings are used as word lines. Two wirings extend as a source line in the row direction, and the plurality of first electrodes extend as bit lines in the column direction.
In the memory cell array, a plurality of the memory cells arranged in the same row are electrically connected to the common word line and the other of the source and drain to the common source line. A plurality of the memory cells connected and arranged in the same column have a configuration in which each of the first electrodes is realized by the common bit line.

According to another aspect of the present invention, there is provided a method for manufacturing a nonvolatile semiconductor memory device, comprising: a variable resistance element having a first electrode, a second electrode, and a variable resistor sandwiched between the two electrodes on a semiconductor substrate; A method of manufacturing a nonvolatile semiconductor memory device including a memory cell having a selection transistor in which one of a source and a drain is electrically connected to two electrodes,
Forming the selection transistor on the semiconductor substrate;
Forming a base interlayer insulating film on an upper layer of the selection transistor;
Forming first, second, and third contact plugs that penetrate the underlying interlayer insulating film and are electrically connected to the drain, source, and gate electrodes of the selection transistor, respectively;
Forming a relay wiring electrically connected to the first contact plug, a first wiring connected to the second contact plug, and a second wiring connected to the third contact plug in an upper layer of the base interlayer insulating film; ,
A first interlayer insulating film is formed on the underlying interlayer insulating film so as to cover the relay wiring, the first wiring, and the second wiring, and the first electrode material film, first layer is further formed thereon. Forming a two-layer insulating film in this order;
Forming a first opening that penetrates the first interlayer insulating film, the first electrode material film, and the second interlayer insulating film and exposes the first electrode material film in a portion of a side surface;
Performing a thermal oxidation process to change the material film of the first electrode exposed in the first opening into a buffer layer;
Depositing a material film of the variable resistor in the first opening so as to be in contact with the buffer layer;
A part of the material film of the variable resistor formed above the relay wiring and a material film formed under the variable resistor are removed to expose the upper surface of the relay wiring and to form a second opening. Forming, and
Depositing the material film of the second electrode having a work function value smaller than that of the material film of the first electrode with a film thickness within a range that does not completely fill the second opening;
Etching the variable resistor material film and the second electrode material film to form the variable resistor and the second electrode.

  According to the nonvolatile semiconductor memory device having the configuration of the present invention, the second electrode having a relatively small work function is electrically connected to the source or the drain of the selection transistor, and the first work function having a larger work function than the second electrode. The electrode is located on the opposite side of the selection transistor with the variable resistor interposed therebetween. A buffer layer is provided between the first electrode and the variable resistor, that is, at the interface with the electrode to be a Schottky junction. This is effective in reducing variation and suppressing read disturb.

  In the case of the configuration of the present invention, it is possible to form the buffer layer at a stage before depositing the material film of the variable resistor. For this reason, by forming the buffer layer after forming the variable resistor, the problem that oxygen in the variable resistor moves through the interface between the two and affects the electrical characteristics is solved.

  Further, the first electrode is formed at a position above the first wiring and the second wiring, and can be easily applied with a voltage from the outside. More specifically, in the read operation, a resistance state can be detected by applying a read voltage to the first electrode side and detecting a current flowing through the first electrode. That is, since it is not necessary to detect the current flowing through the selection transistor, the current can be read without being affected by the load of the selection transistor.

Example of variable resistance element structure effective for suppressing high-resistance read disturb Comparison of resistance value change due to difference in polarity of read voltage when read operation is repeated for variable resistance element in high resistance state Example of schematic cross-sectional structure diagram of variable resistance element provided with buffer layer Another example of schematic cross-sectional structure diagram of variable resistance element provided with buffer layer The figure which shows the circuit structure of the non-volatile semiconductor memory device of this invention Conceptual block diagram of the entire storage device including peripheral circuits Schematic sectional view showing the structure of a memory cell Process sectional drawing of the memory cell which comprises the non-volatile semiconductor memory device of this invention (the 1) Process sectional drawing of the memory cell which comprises the non-volatile semiconductor memory device of this invention (the 2) Process sectional drawing of the memory cell which comprises the non-volatile semiconductor memory device of this invention (the 3) A flowchart showing an outline of a manufacturing process of a nonvolatile semiconductor memory device of the present invention. Process sectional drawing of another embodiment of the memory cell which comprises the non-volatile semiconductor memory device of this invention (the 1) Process sectional drawing of another embodiment of the memory cell which comprises the non-volatile semiconductor memory device of this invention (the 2)

  FIG. 5 shows a circuit configuration of the nonvolatile semiconductor memory device of the present invention. (A) has shown the circuit structure of the memory cell array, (b) is the circuit diagram which expanded the memory cell part.

  The memory cell array 20 includes a plurality of memory cells 1 arranged in a matrix in a row direction (horizontal direction in the drawing) and a column direction (vertical direction in the drawing), and a plurality of word lines (WL1) extending in the row direction. To WLm), a plurality of source lines (SL1 to SLm), and a plurality of bit lines (BL1 to BLn) extending in the column direction. Note that m and n are natural numbers of 2 or more. In the following description, when referring to the word lines without distinguishing the word lines WL1 to WLm, they are referred to as “word lines WL” as a representative. Similarly, the source lines SL1 to SLm are referred to as “source lines SL” and the bit lines BL1 to BLn are referred to as “bit lines BL”.

  As shown in FIG. 5, each memory cell 1 has a 1T1R type structure in which a variable resistance element 2 and a selection transistor 3 are connected in series, and each word line WL and each bit line BL cross each other. Is formed. The memory cells 1 located in the same column are electrically connected to the same bit line BL, and the memory cells 1 located in the same row are electrically connected to the same word line WL and the same source line SL. Has been. Note that the source line SL may be configured such that the source lines SL1 to SLm are electrically connected to each other.

  As with the variable resistance element 10 shown in FIG. 1, the variable resistance element 2 is configured such that one end indicates a Schottky junction and the other end indicates an ohmic junction. In the configuration of the present invention, the end 31 on the Schottky junction side of the variable resistance element 2 is electrically connected to the bit line BL, and the end 33 on the ohmic junction side is electrically connected to one of the source / drain of the selection transistor 3. Connect to. In the present embodiment, the end 33 on the ohmic junction side of the variable resistance element 2 is electrically connected to the drain 41 of the selection transistor 3, and the source 43 of the selection transistor 3 is electrically connected to the source line SL. . The gate 45 of the selection transistor 3 is electrically connected to the word line WL.

  FIG. 6 is a conceptual block diagram of the entire storage device including the memory cell array and its peripheral circuits. The semiconductor memory device includes a word line decoder 51, a bit line decoder 53, a voltage generation circuit 55, a control circuit 57, and a read circuit 59 as peripheral circuits of the memory cell array 20.

  The control circuit 57 controls each memory operation of writing, erasing, and reading of the memory cell array 20 and forming processing. Specifically, the control circuit 57 controls the word line decoder 51 and the bit line decoder 53 based on the address signal input from the address line, the data signal input from the data line, and the control signal input from the control signal line. And control each memory operation and forming process of the memory cell. More specifically, it has functions of an address buffer circuit, a data input / output buffer circuit, and a control input buffer circuit (not shown).

  The voltage generation circuit 55 generates an applied voltage necessary for each operation at the time of writing, erasing, and reading, and supplies the generated voltage to the word line decoder 51 and the bit line decoder 53.

  The word line decoder 51 is connected to one end of each word line WL of the memory cell array 20, and selects a predetermined word line based on an address signal given from the address line in each of write, erase, and read operations. To do. More specifically, by applying a predetermined voltage output from the voltage generation circuit 55 to the selected word line, only the selection transistor 3 connected to the selected word line is turned on.

  The bit line decoder 53 is connected to one end of each bit line BL of the memory cell array 20, and selects a predetermined bit line based on an address signal given from the address line in each of write, erase and read operations. To do. More specifically, a predetermined voltage output from the voltage generation circuit 55 is applied to the selected bit line.

  The read circuit 59 is connected to each bit line BL. At the time of reading, the resistance state of the selected memory cell is detected by detecting the current flowing through the selected bit line separately from the current flowing through the non-selected bit line. In the present embodiment, it is assumed that the read circuit 59 is a current sense circuit that determines the magnitude of the current.

[Memory cell structure]
FIG. 7 is a schematic cross-sectional view showing an example of the structure of the memory cell 1. In FIG. 7, elements corresponding to those in the circuit diagram of FIG. Each cross-sectional view is schematically shown, and the dimensional ratio on the drawing does not necessarily match the actual dimensional ratio.

  For convenience of explanation, the left-right direction in the drawing is the X direction, the up-down direction is the Y direction, and the direction penetrating the drawing is the Z direction. To explain using these notations, the memory cell 1 is formed by stacking each formation film such as the base interlayer insulating film 60 in the vertical direction (Y direction) on the semiconductor substrate 40 arranged on the XZ plane. The

  An element isolation region 47 is provided on the semiconductor substrate 40. A gate insulating film 42 and a gate electrode 45 are formed in this order from the bottom on the upper surface of a part of the active region of the substrate surface separated by the element isolation region 47. On the substrate surface in the same active region outside the gate electrode 45, both diffusion regions of the drain 41 and the source 43 are formed with a separation in the X direction parallel to the substrate surface.

  The selection transistor 3 is formed by the drain 41, the source 43, the gate insulating film 42, the gate electrode 45, and a part of the semiconductor substrate 40 located under the gate insulating film 42.

  A base interlayer insulating film 60 is formed on the select transistor 3. In the underlying interlayer insulating film 60, a contact plug 61 connected to the drain 41, a contact plug 63 connected to the source 43, and a contact plug 65 connected to the gate electrode 45 are embedded separately. The contact plug 61 corresponds to a “first contact plug”, the contact plug 62 corresponds to a “second contact plug”, and the contact plug 63 corresponds to a “third contact plug”.

  A source line SL, a word line WL, and a relay line 67 are separately formed on the upper interlayer insulating film 60. The source line SL is in contact with the contact plug 63 and is extended in the Z direction. The word line WL is in contact with the contact plug 65 and is formed to extend in the Z direction like the source line SL. The relay wiring 67 is formed for each select transistor 3 so as to be in contact with the contact plug 61 and not reach at least the position of the adjacent memory cell in the Z direction. The word line WL corresponds to the “first wiring”, and the source line SL corresponds to the “second wiring”.

  The first interlayer insulating film 21 is formed on the source line SL, the word line WL, the relay wiring 67, and the underlying interlayer insulating film 60.

  A bit line BL also serving as one electrode (first electrode) of the variable resistance element is formed on the first interlayer insulating film 21 and extends in the X direction. As the material of the bit line BL, for example, a conductive material having a relatively large work function such as TiN is used. A second interlayer insulating film 22 is formed above the bit line BL.

  In addition, at the position above the relay wiring 67, the first interlayer insulating film 21, the bit line BL, and the second interlayer insulating film 22 are connected to each other by the variable resistor 25 and the other electrode (second electrode) 26 of the variable resistance element. It is divided in the direction.

  The second electrode 26 and the oxide film 23 are formed in a partial surface region of the relay wiring 67. The oxide film 23 is formed in a part of the surface region of the relay wiring 67 at a position in contact with the side surface in the vicinity of the bottom surface of the second electrode 26.

  The second electrode 26 has a bottom surface that is in contact with the upper surface of the relay wiring 67, and has a cylindrical portion (“first”) penetrating the first interlayer insulating film 21, the first electrode BL, and the second interlayer insulating film 22 in the Y direction. Corresponding to “one cylindrical portion”. And in the position which comprises the side wall part of this cylindrical part, the variable resistor 25 is formed in the outer side of the cylindrical part of the 2nd electrode 26 (corresponding to a "2nd cylindrical part"). . The cylindrical portion of the variable resistor 25 is formed so as to penetrate the first interlayer insulating film 60, the bit line BL, and the second interlayer insulating film 22 in the Y direction, and the height position of the bottom surface is the second electrode 26. It is higher than the bottom. The variable resistor 25 is in contact with the oxide film 23 formed in contact with the upper surface of the relay wiring 67.

  In addition, a buffer layer 24 is formed on the side surface of the variable resistor 25 at a height position where the bit line BL is formed, and the variable resistor 25 and the bit line BL are connected via the buffer layer 24. It is a configuration. The variable resistor 25 is formed up to a position reaching the upper layer of the second interlayer insulating film 22. Further, the second electrode 26 is formed up to the position reaching the upper layer of the variable resistor 25 in the upper layer position of the second interlayer insulating film 22.

The second electrode 26 is configured to be electrically connected to the drain 41 via the relay wiring 67 and the contact plug 61. As the material of the second electrode 26, a conductive material having a work function smaller than that of the material of the first electrode (bit line BL) such as Ta is used. As a material for the oxide film 23 and the buffer layer 24, for example, TiO ₂ is used. As a material of the variable resistor 25, for example, HfO ₂ is used. Examples of other materials that can be used will be described later.

[Production method]
Hereinafter, a method of manufacturing the memory cell shown in FIG. 7 will be described with reference to cross-sectional views of steps in FIGS. 8 to 10 and a flowchart of FIG. Note that step numbers # 1 to # 13 in the following description correspond to the step numbers in the flowchart of FIG.

  In addition, in each process sectional drawing below, the same code | symbol is attached | subjected with respect to the element same as the cross-section figure shown in FIG. In addition, in order to avoid complication of the reference numerals, the same reference numerals are assigned to the film before the forming process such as patterning (for example, the variable resistor material film) and the structure (for example, the variable resistor) after the forming. is doing.

  First, according to a known procedure, the selection transistor 3 is formed on a semiconductor substrate 40 (for example, Si substrate) (# 1). That is, the selection transistor 3 including the gate insulating film 42, the gate electrode 45, the drain 41, and the source 43 is formed on the semiconductor substrate 40 on which the element isolation region 47 is formed.

  Next, after depositing a base interlayer insulating film 60 (for example, a BPSG film) with a film thickness of about 1400 nm on the semiconductor substrate 40 on which the select transistor 3 is formed, the surface is further grown to about 600 nm by CMP. The surface is polished until flattened (FIG. 8A, # 2).

  Next, a contact hole reaching the upper surface of the drain 41, a contact hole reaching the upper surface of the source 43, and a contact hole reaching the upper surface of the gate electrode 45 are formed in the underlying interlayer insulating film 60 using photolithography technology. Then, a barrier film and a contact plug material film (for example, a tungsten film) are formed by the CVD method, and further, the contact plugs 61, 63, and 65 are embedded and formed by performing a molding process by the CMP method (# 3).

  Next, a conductive film for wiring is deposited by sputtering on the underlying interlayer insulating film 60 in which the contact plugs 61, 63, 65 are embedded. As an example of the conductive film for wiring, a material film laminated in the order of Ti (film thickness 15 nm) / AlCu (film thickness 175 nm) / Ti (film thickness 5 nm) / TiN (film thickness 30 nm) is used. Can do.

  Next, the word line WL, the source line SL, and the relay wiring 67 are formed by patterning the wiring conductive film using photolithography technology (FIG. 8B, # 4). The word line WL is electrically connected to the gate electrode 45 through the contact plug 65. Source line SL is electrically connected to source 43 through contact plug 63. The relay wiring 67 is electrically connected to the drain 41 via the contact plug 61.

Next, a first interlayer insulating film 21 (for example, SiO ₂ film) is deposited on the entire surface with a film thickness of about 650 nm by the CVD method. Further, the surface is polished by CMP until the film thickness of the first interlayer insulating film 21 on the relay wiring 67 becomes about 250 nm, thereby flattening the surface (# 5).

  Next, a material film (for example, a TiN film) of the bit line BL (first electrode) is deposited to a thickness of about 100 nm by sputtering. Then, the bit line BL is formed by patterning using a photolithography technique (# 6). As described above, the bit line BL constitutes the first electrode of the variable resistance element 2.

Next, a second interlayer insulating film 22 (for example, SiO ₂ film) is deposited on the entire surface by a CVD method to a thickness of about 200 nm (FIGS. 8C and # 7).

  Next, by patterning using photolithography technology, the upper surface of the relay wiring 67 passes through the second interlayer insulating film 22, the bit line BL, and the first interlayer insulating film 21 at a position above the relay wiring 67. The first opening 80 reaching to is formed (# 8). As a result, the cross section of the bit line BL is exposed in a ring shape at a part of the side wall of the first opening 80 (FIG. 8D).

Next, the conductive material portion exposed by the first opening 80 is thermally oxidized in an atmosphere containing oxygen at about 250 to 450 ° C. Thus, the oxide film 23 is formed on the exposed portion of the relay wiring 67 constituting the bottom surface of the first opening 80, and the buffer layer 24 is formed on the exposed portion of the bit line BL existing on the side wall of the first opening 80. The film is formed with a thickness of about 5 nm (FIGS. 9A and # 9). In the present embodiment, both the oxide film 23 and the buffer layer 24 are realized by a TiO ₂ film.

Next, a variable resistor material film 25 (for example, an HfO ₂ film) is deposited on the entire surface with a film thickness of about 5 nm by sputtering. At this time, it is preferable that the first opening 80 is not completely filled but deposited with a film thickness that can still form the opening 81 (FIG. 9B, # 10).

  Next, a part of the variable resistor material film 25 existing in the first opening 80 and the buffer layer 23 existing immediately below the part are etched using a photolithographic technique, so that the second opening is formed. The part 82 is formed, and the upper surface of the relay wiring 67 is exposed (# 11). As a result, the relay wiring 67 is exposed as the bottom surface of the second opening 82, and the buffer layer 23 and the variable resistor material film 25 are exposed as the side walls stacked from below (FIG. 9C).

  Next, a second electrode material film 26 (for example, a Ta film) is deposited to a thickness of about 100 nm by sputtering (# 12). At this time, the material film is formed with a film thickness that does not completely fill the second opening 82. As a result, the opening 83 is still formed (FIG. 10A). The material of the second electrode material film 26 is required to be a conductive material having a work function smaller than that of at least the bit line BL (that is, the first electrode). Examples of available materials are listed below.

  By this step # 12, the material film of the second electrode 26 is formed on the bottom surface of the second opening 82 that has been formed so far, so that the second electrode material film 26 and the relay wiring 67 come into contact with each other. Both electrical connections are ensured.

  Next, the variable resistor material film 25 and the second electrode material film 26 formed in the upper layer of the second interlayer insulating film 22 at a position outside the first opening 80 are subjected to a patterning process using a photolithography technique ( # 13). Thereby, the variable resistor 25 and the second electrode 26 are formed (FIG. 10B, FIG. 7).

  Thereafter, various peripheral circuits such as a word line decoder 51, a bit line decoder 53, a voltage generation circuit 55, a control circuit 57, and a reading circuit 59 are completed by a known technique.

[Operation method]
Next, erase, write, and read operation methods for the nonvolatile semiconductor memory device including the memory cell 1 having the above structure will be described.

  As described above, in the present embodiment, increasing the resistance of the variable resistance element 2 of the memory cell 1 is referred to as “erasing”, and decreasing the resistance is referred to as “writing”. In the following, a memory cell to be operated is referred to as “target memory cell 1E”, and specific word lines and bit lines connected to the target memory cell 1E are referred to as “word line WLE” and “bit line”, respectively. BLE ".

(Erase operation)
A case where an erase operation is performed on a memory cell, that is, a case where the resistance of the variable resistance element 2 is increased will be described. In this case, the word line decoder 51 selects the word line WLE connected to the target memory cell 1E and applies a predetermined voltage. Further, the source line SL is grounded. As a result, the select transistor of each memory cell arranged in the same row as the target memory cell 1E is turned on.

  Under this state, the bit line decoder 53 selects the bit line BLE connected to the target memory cell 1E and applies a predetermined positive voltage pulse for erasing operation. As described above, the bit line BL also serves as the first electrode of the variable resistance element 2 and is formed of a material having a work function larger than that of the second electrode 26. Therefore, by applying a positive voltage from the bit line BL side, in the target memory cell 1E, a bias is generated such that the end 31 (see FIG. 5B) of the variable resistance element 2 on the Schottky junction side has a high potential. Then, a transition to a high resistance state occurs. Therefore, the target memory cell 1E is in the erased state.

(Write operation)
A case where a write operation is performed on a memory cell, that is, a case where the resistance of the variable resistance element 2 is reduced will be described. Also in this case, as in the erase operation, the word line decoder 51 selects the word line WLE connected to the target memory cell 1E, applies a predetermined voltage, and sets the source line SL to the ground state. As a result, the select transistor of each memory cell arranged in the same row as the target memory cell 1E is turned on.

  During the write operation, since the resistance state of the variable resistance element 2 transitions from the high resistance state to the low resistance state, a large current is expected to flow immediately after or immediately after the transition of the resistance state to the low resistance state. The At this time, there is a risk of destroying the selection transistor 3 in some cases. In order to avoid such a situation, it is preferable to set the voltage applied to the word line WLE within a range in which the current amount can be limited by the selection transistor 3.

  Under this state, the bit line decoder 53 selects the bit line BLE connected to the target memory cell 1E and applies a predetermined negative voltage pulse for the write operation. At this time, in the target memory cell 1E, a bias is generated in which the end 33 (see FIG. 5B) on the ohmic junction side of the variable resistance element 2 has a high potential, and a transition to a low resistance state occurs. Therefore, the target memory cell 1E is in the erased state.

(Read operation)
A case where a read operation is performed on a memory cell, that is, a case where a read current is detected without changing the resistance state of the variable resistance element 2 will be described. In this case, the word line decoder 51 selects the word line WLE connected to the target memory cell 1E, applies a predetermined voltage, and sets the source line SL to the ground state. As a result, the select transistor of each memory cell arranged in the same row as the target memory cell 1E is turned on.

  Under this state, the bit line decoder 53 selects the bit line BLE connected to the target memory cell 1E and applies a predetermined positive voltage pulse for the read operation. At this time, the voltage applied to the word line WLE is set to a value within a range in which the resistance state of the variable resistance element 2 does not transition. As a result, in the target memory cell 1E, a current is generated from the Schottky junction end 31 of the variable resistance element 2 toward the ohmic junction end 33 (see FIG. 5B).

  When the target memory cell 1E is in a high resistance state, a relatively small current flows through the bit line BLE. On the other hand, when the target memory cell 1E is in the low resistance state, a relatively large current flows through the bit line BLE. The read circuit 59 detects the current flowing through the bit line BLE with a sense amplifier, and determines the resistance state. That is, the read circuit 59 does not detect the current flowing from the variable resistance element 2 through the selection transistor 3 to the source line SL, but the current flowing from the bit line BLE toward the end 31 of the variable resistance element 2. Since the detection is configured, the current can be read without being affected by the load of the selection transistor 3.

  As described above, according to the structure of this embodiment, the polarity of the voltage applied in the erase operation and the read operation can be made the same, and the voltage is applied from the bit line BL side with a relatively light load. Thus, by applying a bias that makes the Schottky junction side end 31 positive, read disturb in a high resistance state can be suppressed.

  Further, since the buffer layer 24 made of a metal oxide is inserted between the electrode (here, the bit line BL) serving as a Schottky junction and the variable resistor 25, variation in resistance value between elements is reduced.

  When the memory cell 1 is manufactured, the oxide film 23 and the buffer layer 24 are already formed (# 9) at the time of depositing the variable resistor material film 25 (# 10). For this reason, oxygen contained in the variable resistor does not move toward the buffer layer as in the case of forming the buffer layer after forming the variable resistor. As a result, variation in electrical characteristics between elements is greatly suppressed.

[material]
Hereinafter, usable materials will be described.

  The variable resistor 25 preferably includes an oxide of any element of Hf or Zr. This is because these materials have a large band gap, so that a conductive material having an intermediate work function that can be used in existing semiconductor equipment can be used as the first electrode, and the selection range of the electrode material is expanded. is there.

As an example, the energy positions from the vacuum level at the bottom of the conduction band of HfO ₂ and ZrO ₂ are −2.8 eV and −3.0 eV, respectively.

  The electrode material of the bit line BL (first electrode) and the second electrode 26 is not limited to the above example as long as the former satisfies the relationship that the work function is larger than the latter. .

For example, as the material of the bit line BL (first electrode), TiN (4.7 eV), TaN _x (4.05 to 5.4 eV depending on the stoichiometric composition of nitrogen), W (4. 5 eV), Ni (5.2 eV), Co (4.45 eV), etc. can be used. In addition, the work function value of each material is in parentheses. It is particularly preferable to use TiN or TaN.

  In addition, as a material of the second electrode 26, Ti (4.14 eV), Ta (4.2 eV), Al (4.1 eV) under the restriction that a material having a work function smaller than that of the first electrode is selected. , Hf (3.9 eV), Zr (4.05 eV), etc. can be used.

The buffer layer 24 is formed by oxidizing a part of the bit line BL. For this reason, the material of the buffer layer 24 depends exclusively on the material of the bit line BL. For example, when TiN is used as the bit line BL, the buffer layer 24 is made of TiO ₂ as an example.

The buffer layer 24 preferably contains an oxide of any element of Ti, Ta, Zn, Nb, and W. In view of this, the material of the bit line BL (first electrode) is preferably a conductive material containing Ti, Ta, Zn, Nb, and W. As an example, the energy positions from the vacuum level at the bottom of the conduction bands of TiO ₂ , Ta ₂ O ₅ , ZnO, Nb ₂ O ₅ , and WO ₃ which are oxides of the above-described materials are −3.8 eV, respectively. , −3.7 eV, −4 eV, −4 eV, and −4.2 eV.

[Another embodiment]
Another embodiment will be described below.

  <1> In the above embodiment, the drain 41 of the selection transistor 3 is electrically connected to the second electrode 26 of the variable resistance element. This is discussed on the assumption that the selection transistor 3 is an N-channel type. That is, if the conductivity type is reversed, the names of the source and the drain are reversed.

  <2> In the above embodiment, the first opening 80 is formed in Step # 8 so that the upper surface of the relay wiring 67 is exposed. However, it is not always necessary to expose the upper surface of the relay wiring 67 as long as the opening is formed at least below the bit line BL.

  12 to 13 are a part of each process sectional view when the process according to this another embodiment is followed. In step # 8, the first opening 80a is opened to a position below the bit line BL and above the relay wiring 67 by a distance d (FIG. 12A). Thereafter, as in step # 9, an oxidation process is performed to form the buffer layer 24 in the bit line BL exposed at the side surface of the first opening 80a (FIG. 12B). On the other hand, since the upper surface of the relay wiring 67 is not exposed, the oxide film 23 is not formed in step # 9.

  Next, the variable resistor material film 10 is deposited (FIG. 12C, # 10), and the second opening 28 reaching the upper surface of the relay wiring 67 is formed (FIGS. 13A, # 11). Thereafter, a second electrode material film 68 is deposited to a thickness that does not completely fill the second opening 28 (FIG. 13B, # 12), and the variable resistor 25 and the second electrode 26 are formed by patterning. (FIG. 13 (c), # 13).

  Also in the structure shown in FIG. 13C, a buffer layer 24 is formed at the interface of the first electrode (bit line BL) made of a material having a large work function, as in FIG. It communicates with the variable resistor 25 via the layer 24. The second electrode is in contact with the variable resistor 25 and can be applied with a voltage from the outside.

  <3> The configuration shown in FIG. 4 may include a source line decoder for controlling the voltage applied to the source line SL. At this time, instead of applying a negative voltage pulse to the selected bit line BLE during the write operation, a positive voltage is applied to the source line SL and the non-selected bit line, so that the selected bit line is applied to the source line SL. On the other hand, it may be a relatively negative voltage state.

1: Memory cell (minimum unit of nonvolatile semiconductor memory device)
2: Variable resistance element 3: Selection transistor 10, 10a, 10b: Variable resistance element 11: Variable resistor (HfO _x )
12: Semiconductor substrate 13: First electrode (TiN)
15: Second electrode (Ti)
16: Insulating film 17: Buffer layer 20: Memory cell array 21: First interlayer insulating film 22: Second interlayer insulating film 23: Oxide film 24: Buffer layer 25: Variable resistor (material film)
26: Second electrode (material film)
31: Schottky junction side end of variable resistance element 33: Ohmic junction side end of variable resistance element 40: Semiconductor substrate 41: Drain of selection transistor 42: Gate insulating film of selection transistor 43: Source of selection transistor 45: Selection Transistor gate electrode 47: Element isolation region 51: Word line decoder 53: Bit line decoder 55: Voltage generation circuit 57: Control circuit 59: Read circuit 60: Base interlayer insulating film 61: Contact plug (first contact plug)
63: Contact plug (second contact plug)
65: Contact plug (third contact plug)
67: Relay wiring 80: First opening 81: Opening 82: Second opening 83: Opening BL1-BLn: Bit lines SL1-SLm: Source lines WL1-WLm: Word lines

Claims (7)

A variable resistance element having a first electrode, a second electrode, and a variable resistor sandwiched between the two electrodes on a semiconductor substrate, and a selection in which one of a source or a drain is electrically connected to the second electrode A nonvolatile semiconductor memory device including a memory cell having a transistor,
Above the selection transistor, each wiring layer includes a first wiring, a second wiring, and a relay wiring, and a first interlayer insulating film is provided on the upper surface covering the wiring layer, and the first electrode, Having the second interlayer insulating film in this order from the bottom,
The first electrode is made of a conductive material having a work function larger than that of the second electrode,
The second electrode has a bottom surface that is in contact with the top surface of the relay wiring, and includes a first cylindrical portion that penetrates the first interlayer insulating film, the first electrode, and the second interlayer insulating film. ,
The variable resistor is made of a metal oxide, is in contact with an outer surface of the first cylindrical portion of the second electrode, and includes the first interlayer insulating film, the first electrode, and the second interlayer insulating film. Penetrating and having a second cylindrical part whose bottom surface is higher than the bottom surface of the second electrode,
Between the outer surface of the second cylindrical portion and the first electrode, there is a buffer layer formed of a metal oxide of a material different from that of the variable resistor,
The non-volatile semiconductor, wherein the relay wiring is electrically connected to one of a source and a drain of the selection transistor, the first wiring is electrically connected to a gate electrode, and the second wiring is electrically connected to the other of the source and the drain. Storage device.   The nonvolatile semiconductor memory device according to claim 1, wherein the buffer layer is made of an oxide of a material constituting the first electrode.   The nonvolatile semiconductor memory device according to claim 1, wherein the variable resistor includes an oxide of Hf or Zr.   4. The non-volatile device according to claim 1, wherein the first electrode includes a conductive material of Ti nitride, Ta nitride, W, Ni, or Co. 5. Semiconductor memory device.   5. The nonvolatile semiconductor memory device according to claim 1, wherein the second electrode includes a conductive material of any one of Ti, Ta, Al, Hf, and Zr. . A memory cell array in which a plurality of the memory cells are arranged in a row direction and a column direction, respectively, the plurality of first wirings as word lines and the plurality of second wirings as source lines, respectively, extending in the row direction; A plurality of first electrodes extending in the column direction as bit lines;
In the memory cell array, a plurality of the memory cells arranged in the same row are electrically connected to the common word line and the other of the source and drain to the common source line. The plurality of the memory cells connected and arranged in the same column have a configuration in which each of the first electrodes is realized by the common bit line. Nonvolatile semiconductor memory device. A variable resistance element having a first electrode, a second electrode, and a variable resistor sandwiched between the two electrodes on a semiconductor substrate, and a selection in which one of a source or a drain is electrically connected to the second electrode A method of manufacturing a nonvolatile semiconductor memory device including a memory cell having a transistor,
Forming the selection transistor on the semiconductor substrate;
Forming a base interlayer insulating film on an upper layer of the selection transistor;
Forming first, second, and third contact plugs that penetrate the underlying interlayer insulating film and are electrically connected to the drain, source, and gate electrodes of the selection transistor, respectively;
Forming a relay wiring electrically connected to the first contact plug, a first wiring connected to the second contact plug, and a second wiring connected to the third contact plug in an upper layer of the base interlayer insulating film; ,
A first interlayer insulating film is formed on the underlying interlayer insulating film so as to cover the relay wiring, the first wiring, and the second wiring, and the first electrode material film, first layer is further formed thereon. Forming a two-layer insulating film in this order;
Forming a first opening that penetrates the first interlayer insulating film, the first electrode material film, and the second interlayer insulating film and exposes the first electrode material film in a portion of a side surface;
Performing a thermal oxidation process to change the material film of the first electrode exposed in the first opening into a buffer layer;
Depositing a material film of the variable resistor in the first opening so as to be in contact with the buffer layer;
A part of the material film of the variable resistor formed above the relay wiring and a material film formed under the variable resistor are removed to expose the upper surface of the relay wiring and to form a second opening. Forming, and
Depositing the material film of the second electrode having a work function value smaller than that of the material film of the first electrode with a film thickness within a range that does not completely fill the second opening;
A step of etching the material film of the variable resistor and the material film of the second electrode to form the variable resistor and the second electrode. Method.

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