JP2012054505A - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device in which channel mobility is enhanced and drop in the threshold voltage is minimized by breaking down the relationship of trade-off between channel mobility and threshold voltage.SOLUTION: The method of manufacturing a silicon carbide semiconductor device 1a includes a step for forming a polycrystalline silicon film 18 doped with phosphorus on a silicon carbide epitaxial layer 6 of a silicon carbide substrate 2 having the silicon carbide epitaxial layer 6, and a step for forming a gate insulating film 12 by thermally oxidizing the polycrystalline silicon film 18.

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.

  In order to overcome the physical property limits of power devices using silicon, power devices using silicon carbide have been developed. However, in the case of manufacturing a MOSFET (Metal Oxide Field Effect Transistor) using silicon carbide, when a gate insulating film made of silicon dioxide is formed on the silicon carbide layer, many interface states exist at the silicon carbide / silicon dioxide interface. It is formed. Due to the presence of such an interface state, the channel mobility of the MOSFET is significantly smaller than the mobility in the bulk, and the on-resistance value is increased, which hinders the reduction of the device loss.

In the conventional method for manufacturing a silicon carbide semiconductor device, the surface of the silicon carbide layer is thermally oxidized to form a gate insulating film, and this gate insulating film is annealed in a V group element-containing gas such as NO gas or PH ₃ gas. Thus, the channel mobility is improved by introducing nitrogen or phosphorus into the gate insulating film. (For example, see Patent Document 1)

  In another conventional silicon carbide semiconductor device manufacturing method, a sacrificial layer doped with phosphorus having a substantially uniform concentration profile is formed on the surface of the silicon carbide layer in the in-plane direction, and the surface layer including the sacrificial layer is thermally oxidized. Thus, by forming the gate insulating film, the step on the channel surface is reduced and the channel mobility is improved. (For example, see Patent Document 2)

JP 2005-136386 A (pages 6 to 12, FIG. 3) JP 2009-266871 A (pages 8-11, FIGS. 1-2)

  In the conventional method for manufacturing a silicon carbide semiconductor device described in Patent Document 1, although the channel mobility is improved by annealing in the group V element-containing gas, the threshold voltage is lowered at the same time. When a silicon carbide semiconductor device is used as a power device, it is necessary to ensure high breakdown voltage characteristics, and a threshold voltage of a certain level is necessary to realize this. The method of annealing in the group V element-containing gas has a problem in that channel mobility and threshold voltage are in a trade-off relationship.

  In another conventional method for manufacturing a silicon carbide semiconductor device described in Patent Document 2, a silicon carbide layer is thermally oxidized at a high temperature to form a gate insulating film. An increase in the interface state at the silicon carbide / silicon dioxide interface cannot be avoided, and there is a problem that the effect of improving the channel mobility is insufficient. This method also has a problem in that channel mobility and threshold voltage are in a trade-off relationship.

  An object of the present invention is to provide a silicon carbide semiconductor device that improves channel mobility and suppresses a decrease in threshold voltage and a method for manufacturing the same. To do.

  A method for manufacturing a silicon carbide semiconductor device according to the present invention includes a step of forming a silicon film doped with phosphorus on a silicon carbide layer of a substrate having a silicon carbide layer, and forming a gate insulating film by thermally oxidizing the silicon film And a step of performing.

  A silicon carbide semiconductor device according to the present invention includes a substrate having a silicon carbide layer, and a gate insulating film formed on the silicon carbide layer and formed of silicon dioxide doped with phosphorus. In the device, the phosphorus concentration distribution in the depth direction in the gate insulating film has a peak value near the interface with the silicon carbide layer, and the peak value is the depth of the portion of the gate insulating film doped with phosphorus. Is 2 to 10 times the phosphorus concentration in the bulk near the middle of the shallowest part and the interface between the silicon carbide layer and the gate insulating film.

  According to the method for manufacturing a silicon carbide semiconductor device of the present invention, it is possible to suppress a decrease in threshold voltage while improving channel mobility.

  Moreover, according to the silicon carbide semiconductor device which concerns on this invention, the fall of a threshold voltage can be suppressed, improving a channel mobility.

It is sectional drawing which shows the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 1 of this invention. It is a schematic diagram which shows the distribution of the phosphorus concentration in the cross-sectional depth direction of the silicon carbide semiconductor device in Embodiment 1 of this invention and the conventional silicon carbide semiconductor device. It is the graph which plotted the relationship between the effective channel mobility and threshold voltage of the silicon carbide semiconductor device in Embodiment 1 of this invention and the conventional silicon carbide semiconductor device. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows the silicon carbide semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 3 of this invention. It is sectional drawing which shows a part of manufacturing method of the silicon carbide semiconductor device in Embodiment 3 of this invention.

Embodiment 1 FIG.
First, the structure of silicon carbide semiconductor device 1a in the first embodiment of the present invention will be described. 1 is a cross sectional view showing a silicon carbide semiconductor device 1a according to the first embodiment of the present invention. Here, an n-channel silicon carbide MOSFET will be described as an example of silicon carbide semiconductor device 1a.

  In FIG. 1, an n-type (first conductivity type) silicon carbide epitaxial layer 6 is formed on one surface 3 of an n-type (first conductivity type) and low resistance silicon carbide substrate 2. A p-type (second conductivity type) base region 7 is formed on the surface side of silicon carbide epitaxial layer 6. Further, on the surface side of the base region 7, a pair of n-type (first conductivity type) source regions 8 are formed shallower than the base region 7 with a predetermined distance therebetween. A p-type (second conductivity type) base contact region 11 is formed adjacent to one source region 8.

  On the surface of silicon carbide epitaxial layer 6 including base region 7, source region 8 and base contact region 11, gate insulating film 12 is formed except for part of source region 8 and part of base contact region 11. Is formed. Further, on the gate insulating film 12, a gate electrode 13 is formed in a region facing a region between the pair of source regions 8 and a part of the source region 8. A source electrode 16 is formed so as to extend from a part of the surface of one source region 8 to a part of the surface of the base contact region 11, and a drain electrode 17 is formed on a part of the surface of the other source region 8. Is formed.

  Next, a method for manufacturing silicon carbide semiconductor device 1a in the first embodiment of the present invention will be described. 2 to 7 are cross sectional views showing a part of a method for manufacturing silicon carbide semiconductor device 1a in the first embodiment of the present invention.

  First, an n-type (first conductivity type) low resistance silicon carbide substrate 2 having a plane orientation of one surface 3 of (0001) plane and a 4H polytype is prepared. Then, as shown in FIG. 2, an n-type (first conductivity type) silicon carbide epitaxial layer having a thickness of 1 to 100 μm is formed on one surface 3 of silicon carbide substrate 2 by a CVD (Chemical Vapor Deposition) method. 6 is formed.

  Next, a mask is formed with a resist on the surface of silicon carbide epitaxial layer 6, and p-type (second conductivity type) impurities are ion-implanted from the surface side of silicon carbide epitaxial layer 6. Thereby, p-type (second conductivity type) base region 7 is formed in silicon carbide epitaxial layer 6. A cross-sectional view after removing the resist is shown in FIG.

At this time, the p-type (second conductivity type) impurity to be ion-implanted is, for example, aluminum, boron, or gallium, and the impurity concentration to be ion-implanted is in the range of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ cm ⁻³ . The depth of ion implantation of the p-type (second conductivity type) impurity is about 0.5 to 3 μm that does not exceed the thickness of the silicon carbide epitaxial layer 6.

  Next, a mask is formed with a resist on the surface of silicon carbide epitaxial layer 6, and n-type (first conductivity type) impurities are ion-implanted from the surface side of silicon carbide epitaxial layer 6. As a result, a pair of n-type (first conductivity type) source regions 8 are formed on the surface side of the base region 7 so as to be shallower than the base region 7 at a predetermined distance from each other. Thereafter, the resist is removed.

At this time, the n-type (first conductivity type) impurity to be ion-implanted is, for example, nitrogen, phosphorus, or arsenic, and the impurity concentration to be ion-implanted is in the range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ . The depth of ion implantation of n-type (first conductivity type) impurities is about 0.1 to 2 μm, which is shallower than the thickness of the base region 7.

  Next, a mask is formed with a resist on the surface of silicon carbide epitaxial layer 6, and p-type (second conductivity type) impurities are ion-implanted from the surface side of silicon carbide epitaxial layer 6. As a result, a p-type (second conductivity type) base contact region 11 is formed adjacent to one source region 8 on the surface side of the base region 7. A cross-sectional view after removing the resist is shown in FIG.

At this time, the p-type (second conductivity type) impurity to be ion-implanted is, for example, aluminum, boron, or gallium, and the impurity concentration to be ion-implanted is in the range of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ . The depth of ion implantation of the p-type (second conductivity type) impurity is about 0.1 to 2 μm and is shallower than the thickness of the base region 7.

  Next, the silicon carbide substrate 2 on which the silicon carbide epitaxial layer 6, the base region 7, the source region 8, and the base contact region 11 are formed is subjected to 1300 to 2100 in an inert gas atmosphere such as argon by a heat treatment apparatus. High-temperature annealing is performed in the temperature range. By this high temperature annealing, ion-implanted aluminum, nitrogen, and the like are electrically activated.

  Next, as shown in FIG. 5, phosphorus-doped polycrystalline silicon film 18 is formed on the surface of silicon carbide epitaxial layer 6 including base region 7, source region 8, and base contact region 11. The film thickness of the polycrystalline silicon film 18 doped with phosphorus is preferably 1 nm or more, and more preferably about 20 nm.

The density of interface states generated at the silicon carbide / silicon dioxide interface in the step of forming the gate insulating film 12 described later is about 1 × 10 ¹⁰ to 1 × 10 ¹⁵ cm ⁻² eV ⁻¹ , and the silicon carbide / silicon dioxide interface Since the thickness of the transition region is about 1 to 10 nm, the concentration of phosphorus doped into the polycrystalline silicon film 18 is the surface of the polycrystalline silicon film 18 in order to effectively passivat the interface state with phosphorus. It is substantially constant in the inward direction and the depth direction, and is preferably in the range of 1 × 10 ¹⁶ to 1 × 10 ²² cm ⁻³ .

The polycrystalline silicon film 18 doped with phosphorus is formed by a CVD method using SiH ₄ and PH ₃ as source gases. However, the present invention is not limited to this, and the non-doped polycrystalline silicon film 18 is first formed by the CVD method. Then, phosphorus may be doped by ion implantation.

  Next, the silicon carbide substrate 2 on which the polycrystalline silicon film 18 doped with phosphorus is formed is heated at a temperature in the range of 700 to 1400 ° C., and the polycrystalline silicon film 18 is entirely thermally oxidized to form silicon dioxide. A gate insulating film 12 is formed. For example, when the thickness of the polycrystalline silicon film 18 is about 20 nm, the thickness of the gate insulating film 12 becomes about 50 nm by thermal oxidation. By this step, phosphorus diffuses to the vicinity of the silicon carbide / silicon dioxide interface, and the interface states generated at the silicon carbide / silicon dioxide interface are passivated by phosphorus. A cross-sectional view after the gate insulating film 12 is formed is shown in FIG.

  Next, a polycrystalline silicon film is formed on the gate insulating film 12 by a CVD method and patterned by photolithography and etching techniques to form the gate electrode 13. As shown in FIG. 7, the gate electrode 12 is patterned in such a shape that the pair of source regions 8 are located at both ends, and the base region 7 between the pair of source regions 8 is located at the center.

  Next, leaving the part where the gate electrode 12 is formed and the periphery thereof, a part extending from a part of the surface of one source region 8 to a part of the surface of the base contact region 11, and the other source region 8 The gate insulating film 12 formed on a part of the surface is removed. Then, a source electrode 16 is formed in a portion extending from a part of the surface of one of the source regions 8 to a part of the surface of the base contact region 11 exposed on the surface by removing the gate insulating film 12. A drain electrode 17 is formed on a part of the surface of the other source region 8 exposed to the surface. As a result, the state shown in FIG. 1 is obtained. As the source electrode 16 and the drain electrode 17, for example, nickel, titanium, aluminum, molybdenum, chromium, platinum, tungsten, tantalum, niobium, silicon, titanium carbide, nitrides thereof, or alloys thereof are used.

  Finally, in order to alloy the source electrode 16 and the drain electrode 17 with the silicon carbide in contact, the temperature: 950 to 1000 ° C., the processing time: 20 to 60 seconds, the temperature rising rate: 10 to 25 ° C./second And heat treatment. Thus, the n-channel MOSFET which is silicon carbide semiconductor device 1a in the first embodiment of the present invention shown in FIG. 1 is completed.

  Next, the distribution of phosphorus concentration in gate insulating film 12 and silicon carbide epitaxial layer 6 of silicon carbide semiconductor device 1a manufactured using the method for manufacturing the silicon carbide semiconductor device in the first embodiment of the present invention will be described. FIG. 8 is a schematic diagram showing the phosphorus concentration distribution in the cross-sectional depth direction of silicon carbide semiconductor device 1a in the first embodiment of the present invention and the conventional silicon carbide semiconductor device. In FIG. 8, the vertical axis indicates the depth from the surface of the gate insulating film 12, and the horizontal axis indicates the phosphorus concentration.

Here, as a conventional example, the surface of the silicon carbide epitaxial layer described in the above-mentioned Patent Document 1 is thermally oxidized to form a gate insulating film, and then annealed in a PH ₃ gas, thereby forming a gate insulating film in the gate insulating film. A method of introducing phosphorus, and a surface layer including a sacrificial layer, which is formed by forming a sacrificial layer doped with phosphorus having a substantially uniform concentration profile in the in-plane direction on the surface of the silicon carbide epitaxial layer described in Patent Document 2 above An example of a silicon carbide semiconductor device manufactured using a method of forming a gate insulating film by thermally oxidizing the substrate will be described. In the manufacturing method described in Patent Document 1 and the manufacturing method described in Patent Document 2, the distribution of phosphorus concentration in the gate insulating film and the silicon carbide epitaxial layer is substantially the same. A case where two manufacturing methods are used is collectively shown by a broken line as a conventional example. In FIG. 8, the distribution of phosphorus concentration when the method for manufacturing the silicon carbide semiconductor device in the first embodiment of the present invention is used is shown by a solid line.

  As shown in FIG. 8, in the case of a silicon carbide semiconductor device manufactured using a conventional method for manufacturing a silicon carbide semiconductor device, a small amount of phosphorus exists in the vicinity of the surface of the gate insulating film formed of silicon dioxide. There is almost no phosphorus in the bulk, and phosphorus is concentrated near the silicon carbide / silicon dioxide interface.

In contrast, in the case of silicon carbide semiconductor device 1a manufactured using the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention, a bulk is formed from the vicinity of the surface of gate insulating film 12 formed of silicon dioxide. In the middle, the phosphorus concentration A is substantially constant, and a peak of phosphorus concentration exists in the vicinity of the silicon carbide / silicon dioxide interface. The peak value of the phosphorus concentration near the silicon carbide / silicon dioxide interface is about 2 to 10 times the phosphorus concentration A from the vicinity of the surface of the gate insulating film 12 to the bulk. Note that the phosphorus concentration A from the vicinity of the surface of the gate insulating film 12 to the bulk is slightly lower than the phosphorus concentration doped in the polycrystalline silicon film 18 due to volume expansion caused by thermal oxidation of the polycrystalline silicon film 18. Does not change. Therefore, when the phosphorus concentration of the polycrystalline silicon film 18 is in the range of 1 × 10 ¹⁶ to 1 × 10 ²² cm ⁻³ , the phosphorus concentration A from the vicinity of the surface of the gate insulating film 12 to the bulk is also 1 × 10 ¹⁶ to 1. It becomes the range of * 10 < ²² > cm <^-3> .

Next, an n-channel MOSFET which is silicon carbide semiconductor device 1a manufactured using the method for manufacturing a silicon carbide semiconductor device in the first embodiment of the present invention, and a silicon carbide semiconductor device manufactured using a conventional manufacturing method An experimental result obtained by examining the relationship between the effective channel mobility μ _eff and the threshold voltage V _th with the n-channel MOSFET will be described. FIG. 9 is a graph plotting the relationship between the effective channel mobility and the threshold voltage between silicon carbide semiconductor device 1a in the first embodiment of the present invention and a conventional silicon carbide semiconductor device. In FIG. 9, the vertical axis represents the effective channel mobility μ _eff , and the horizontal axis represents the threshold voltage _Vth .

  Here, as a conventional example, silicon carbide is thermally oxidized to form a gate insulating film and no passivation treatment is performed to improve channel mobility, and silicon carbide is thermally oxidized to perform gate insulation. A case where nitriding is performed by annealing at 1100 to 1300 ° C. in NO gas after forming the film is compared with the case of the method of manufacturing silicon carbide semiconductor device 1a in the first embodiment of the present invention. In FIG. 9, the case where no passivation treatment is performed is indicated by ■, the case where nitriding is performed is indicated by ●, and the case according to the method for manufacturing the silicon carbide semiconductor device in Embodiment 1 of the present invention is indicated by ▲. ing.

As can be seen from FIG. 9, for no passivated, effective channel mobility mu _eff and the threshold voltage V _th has become both low, the case of performing the nitriding treatment, the effective channel mobility mu _eff and the threshold voltage V _th is in a trade-off relationship. In contrast, in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention, both effective channel mobility μ _eff and threshold voltage V _th are higher than those in the above two methods. It turns out that there is no trade-off relationship.

This is because the channel state at the silicon carbide / silicon dioxide interface is passivated with phosphorus, so that the effective channel mobility μ _eff is improved, and phosphorus remains at a high concentration from the surface of the gate insulating film 12 to the bulk. This is because phosphorus remaining in the gate insulating film 12 acts as a fixed charge and the threshold voltage is maintained high.

  In the first embodiment of the present invention, the above configuration has the effect of suppressing the decrease in threshold voltage while improving the channel mobility.

  Silicon can be thermally oxidized at a lower temperature than silicon carbide, and silicon is faster in thermal oxidation than silicon carbide. Therefore, the polycrystalline silicon film 18 is thermally oxidized to form a gate. By forming the insulating film 12, the temperature may be lower than when the gate insulating film 12 is formed by thermally oxidizing the silicon carbide layer, and the time required for forming the gate insulating film 12 can be shortened.

  Further, as described above, since silicon can be thermally oxidized at a lower temperature than silicon carbide, if thermal oxidation is performed at a relatively low temperature at which the thermal oxidation of silicon carbide is difficult to proceed, polycrystalline silicon film 18 is formed. It is possible to prevent the silicon carbide epitaxial layer 6 from being oxidized after all the oxidation. Thereby, the increase in the interface state due to oxidation of silicon carbide epitaxial layer 6 can be suppressed.

  Further, since the speed of thermal oxidation of silicon carbide is slower than that of silicon, even if thermal oxidation is performed at a relatively high temperature, the polycrystalline silicon film 18 is oxidized and then oxidized to the silicon carbide epitaxial layer 6. Can be suppressed. Thereby, the increase in the interface state due to oxidation of silicon carbide epitaxial layer 6 can be suppressed.

  The phosphorus concentration distribution in the depth direction in gate insulating film 12 has a peak value in the vicinity of the interface with silicon carbide epitaxial layer 6, and this peak value is the phosphorus concentration from the vicinity of the surface of gate insulating film 12 to the bulk. By making it 2 to 10 times that of A, the interface state generated at the silicon carbide / silicon dioxide interface can be passivated with phosphorus to improve the channel mobility, and the threshold voltage remains high. Can do.

By doping the polycrystalline silicon film 18 with phosphorus at a concentration of 1 × 10 ¹⁶ to 1 × 10 ²² cm ⁻³ , the interface state generated at the silicon carbide / silicon dioxide interface can be effectively passivated, and the channel Mobility can be improved. Further, this makes it possible to make the phosphorus concentration from the surface of the gate insulating film 12 into the bulk 1 × 10 ¹⁶ to 1 × 10 ²² cm ^−3, and to effectively maintain the threshold voltage at a high level. .

  The phosphorus concentration distribution in the depth direction in the polycrystalline silicon film 18 is from the vicinity of the surface of the polycrystalline silicon film 18 (corresponding to the shallowest portion of the polycrystalline silicon film 18 doped with phosphorus). By doping phosphorus so as to be substantially constant up to the vicinity of the interface with silicon carbide epitaxial layer 6, the threshold voltage can be effectively maintained high.

  In the first embodiment of the present invention, the polycrystalline silicon film 18 is formed. However, a single crystal silicon film or an amorphous silicon film may be formed instead of the polycrystalline silicon film 18. However, from the viewpoint of ensuring insulation of the gate insulating film 12, it is preferable to form a polycrystalline silicon film 18 or a single crystal silicon film that can form a denser film than the amorphous silicon film.

  In the first embodiment of the present invention, polycrystalline silicon film 18 formed on silicon carbide epitaxial layer 6 is all oxidized. However, it is not always necessary to oxidize all, and it suffices that the vicinity of the interface with silicon carbide epitaxial layer 6 is oxidized and the portion where gate electrode 13 is formed is oxidized. For example, the non-oxidized polycrystalline silicon film 18 may remain in a portion that does not significantly affect the operation of the device.

  In the first embodiment of the present invention, phosphorus is doped so that the distribution of phosphorus concentration in the polycrystalline silicon film 18 in the depth direction is substantially constant. However, the distribution of phosphorus concentration in the depth direction is not necessarily constant, and the phosphorus concentration may increase or decrease from the vicinity of the surface to the interface with silicon carbide epitaxial layer 6. Good. Further, the phosphorus concentration need not change monotonously with respect to the depth direction, and may increase or decrease.

  For example, the phosphorus concentration in the vicinity of the interface with the silicon carbide epitaxial layer 6 is higher than the phosphorus concentration in the vicinity of the surface of the polycrystalline silicon film 18 (corresponding to the shallowest portion of the polycrystalline silicon film 18 doped with phosphorus). When the polycrystalline silicon film 18 is formed so as to have a high concentration, the interface state generated at the silicon carbide / silicon dioxide interface can be effectively passivated with phosphorus.

  In this way, when the phosphorus concentration distribution in the depth direction of the polycrystalline silicon film 18 is changed, the peak value of the phosphorus concentration in the depth direction in the gate insulating film 12 to be formed thereafter is the value of the gate insulating film 12. It becomes 2 to 10 times the phosphorus concentration in the bulk near the middle between the surface (corresponding to the shallowest portion of the portion of the gate insulating film 12 doped with phosphorus) and the interface with the silicon carbide epitaxial layer 6. It is better to do so.

  Alternatively, phosphorus may be doped only in a portion of the polycrystalline silicon film 18 close to the interface with the silicon carbide epitaxial layer 6 without doping the entire polycrystalline silicon film 18 with phosphorus. In this case, the thickness of the portion doped with phosphorus in polycrystalline silicon film 18 is preferably 1 nm or more from the interface with silicon carbide epitaxial layer 6, and more preferably about 20 nm.

  In this case, the peak value of the phosphorus concentration distribution with respect to the depth direction in the gate insulating film 12 formed thereafter has a shallowest portion of the portion of the gate insulating film 12 doped with phosphorus and the silicon carbide epitaxial layer 6. It is preferable that the concentration of phosphorus in the bulk near the interface between the gate insulating film 12 and the gate insulating film 12 is 2 to 10 times.

  Even if phosphorus is not doped in the vicinity of the interface between the gate insulating film 12 and the silicon carbide epitaxial layer 6 but phosphorus is doped only in the bulk of the gate insulating film 12, a certain effect can be obtained. In this case, the peak value of the phosphorus concentration distribution in the depth direction in the gate insulating film 12 is between the shallowest portion and the deepest portion of the portion of the gate insulating film 12 doped with phosphorus. It is preferable to be 2 to 10 times the phosphorus concentration in the bulk near the middle.

  In the first embodiment of the present invention, a p-type (second conductivity type) base is implanted into silicon carbide epitaxial layer 6 by ion-implanting a p-type (second conductivity type) impurity into silicon carbide epitaxial layer 6. Region 7 was formed. However, a p-type (second conductivity type) silicon carbide epitaxial layer may be further formed on silicon carbide epitaxial layer 6 to form base region 7.

  In Embodiment 1 of the present invention, gate electrode 13 is formed of polycrystalline silicon. However, the conductivity type of polycrystalline silicon may be n-type or p-type, and may be n-type or p-type polycrystalline silicon carbide. Furthermore, nickel, titanium, aluminum, molybdenum, chromium, platinum, tungsten, tantalum, niobium, silicon, titanium carbide, nitrides thereof, or alloys thereof may be used.

  In Embodiment 1 of the present invention, silicon carbide substrate 2 having a plane orientation of one surface 3 of (0001) and having a 4H polytype is used. However, the plane orientation may be a (000-1) plane, a (11-20) plane, etc., or may be inclined from these plane orientations. Further, the polytype may be 6H or 3C.

  In the first embodiment of the present invention, as an example of silicon carbide semiconductor device 1a, an n-channel silicon carbide MOSFET has been described in which n-type is the first conductivity type and p-type is the second conductivity type. However, the same applies to a p-channel silicon carbide MOSFET in which the p-type is the first conductivity type and the n-type is the second conductivity type.

Embodiment 2. FIG.
FIG. 10 is a cross sectional view showing a part of the method for manufacturing silicon carbide semiconductor device 1a in the second embodiment of the present invention. 10, the same reference numerals as those in FIG. 1 denote the same or corresponding components, and the description thereof is omitted. The first embodiment of the present invention includes a step of forming a polycrystalline silicon film 18 doped with phosphorus, and a step of forming a gate insulating film 12 made of silicon dioxide by thermally oxidizing the polycrystalline silicon film 18. Instead, the difference is that the step of forming phosphorus-doped silicon dioxide film 19 to be a gate insulating film and the step of heat-treating silicon carbide substrate 2 on which phosphorus-doped silicon dioxide film 19 is formed are different. ing.

  A method for manufacturing silicon carbide semiconductor device 1a in the second embodiment of the present invention will be described in detail. In addition, description is abbreviate | omitted here about the part similar to Embodiment 1 of this invention.

  First, a pair of n-type (first conductivity type) source regions 8 is formed on the surface side of the base region 7 shown in FIG. The process until the step of forming the base contact region 11 of the conductivity type is performed and then the step of performing the high temperature annealing is the same as in the first embodiment of the present invention.

  Next, as shown in FIG. 10, phosphorus-doped silicon dioxide film 19 that forms a gate insulating film is formed on the surface of silicon carbide epitaxial layer 6 including base region 7, source region 8, and base contact region 11. . The film thickness of the silicon dioxide film 19 doped with phosphorus is preferably 1 nm or more, and more preferably about 50 nm.

In the step of heat-treating the silicon carbide substrate 2 to be described later, in order to effectively passivat the interface state of the silicon carbide / silicon dioxide interface with phosphorus, the concentration of phosphorus doped into the silicon dioxide film 19 is set to As in the case of Form 1, it is substantially constant in the in-plane direction and the depth direction of the silicon dioxide film 19, and is preferably in the range of 1 × 10 ¹⁶ to 1 × 10 ²² cm ⁻³ .

The silicon dioxide film 19 doped with phosphorus is formed by a CVD method using O ₂ , CO _2, NO _2, etc., and SiH ₄ and PH ₃ as source gases. However, the present invention is not limited to this method. The non-doped silicon dioxide film 19 may be formed by a CVD method and then doped by phosphorus by ion implantation.

  Next, the silicon carbide substrate 2 on which the silicon dioxide film 19 doped with phosphorus is formed is heat-treated at a temperature in the range of 300 to 1400 ° C. By this step, phosphorus diffuses to the vicinity of the silicon carbide / silicon dioxide interface, and the interface state at the silicon carbide / silicon dioxide interface is passivated by phosphorus. In addition, when using the method of doping phosphorus into the silicon dioxide film 19 by ion implantation, it is preferable to set the temperature of the heat treatment here to 1000 ° C. or higher in order to activate the implanted ions.

  Next, the step of forming a gate electrode 13 made of polycrystalline silicon is performed on the silicon dioxide film 19 doped with phosphorus, which becomes a gate insulating film, as shown in FIG. Similar steps are performed to complete silicon carbide semiconductor device 1a shown in FIG. After the completion of the silicon carbide semiconductor device 1a, the phosphorus concentration distribution in the depth direction in the silicon dioxide film 19 doped with phosphorus to be a gate insulating film is as shown in FIG.

  In the second embodiment of the present invention, as described above, as in the first embodiment of the present invention, it is possible to improve the channel mobility and suppress the decrease in the threshold voltage. . In addition, the gate insulating film is not formed by thermal oxidation of silicon or silicon carbide, but the silicon dioxide film 19 to be the gate insulating film is directly formed, so that the controllability of the thickness of the gate insulating film is high.

By doping the silicon dioxide film 19 with phosphorus at a concentration of 1 × 10 ¹⁶ to 1 × 10 ²² cm ⁻³ , it is possible to effectively passivate the interface state of the silicon carbide / silicon dioxide interface, and the channel mobility. Can be improved. In addition, this allows the threshold voltage to be effectively maintained high.

  The distribution of phosphorus concentration in the depth direction in the silicon dioxide film 19 is silicon carbide epitaxial from the vicinity of the surface of the silicon dioxide film 19 (corresponding to the shallowest part of the silicon dioxide film 19 doped with phosphorus). By doping phosphorus so as to be substantially constant up to the vicinity of the interface with the layer 6, the threshold voltage can be effectively maintained high.

  In the second embodiment of the present invention, phosphorus is doped so that the phosphorus concentration distribution in the depth direction in the silicon dioxide film 19 is substantially constant. However, the distribution of phosphorus concentration in the depth direction is not necessarily constant, and the phosphorus concentration may increase or decrease from the vicinity of the surface to the interface with silicon carbide epitaxial layer 6. Good. Further, the phosphorus concentration need not change monotonously with respect to the depth direction, and may increase or decrease.

  For example, the phosphorus concentration in the vicinity of the interface with the silicon carbide epitaxial layer 6 is higher than the phosphorus concentration in the vicinity of the surface of the silicon dioxide film 19 (corresponding to the shallowest part of the silicon dioxide film 19 doped with phosphorus). When the silicon dioxide film 19 is formed so as to be high, the interface state generated at the silicon carbide / silicon dioxide interface can be effectively passivated with phosphorus.

  When the phosphorus concentration distribution in the depth direction of the silicon dioxide film 19 is changed in this way, the peak value of the phosphorus concentration is the surface of the silicon dioxide film 19 (of the portion of the silicon dioxide film 19 doped with phosphorus). It is preferable to be 2 to 10 times the phosphorus concentration in the bulk in the vicinity of the middle between the interface between the silicon carbide epitaxial layer 6 and the shallowest portion.

  Alternatively, phosphorus may be doped only in a portion of the silicon dioxide film 19 close to the interface with the silicon carbide epitaxial layer 6 without doping the entire silicon dioxide film 19 with phosphorus. In this case, the peak value of the phosphorus concentration in the depth direction in the silicon dioxide film 19 is the shallowest part of the silicon dioxide film 19 doped with phosphorus, the silicon carbide epitaxial layer 6 and the silicon dioxide film 19. It is preferable that the concentration be 2 to 10 times the phosphorus concentration in the bulk in the vicinity of the interface with the interface.

  Even if the vicinity of the interface with silicon carbide epitaxial layer 6 is not doped but phosphorus is doped only in the bulk, a certain effect can be obtained. In this case, the peak value of the phosphorus concentration distribution with respect to the depth direction in the silicon dioxide film 19 is the difference between the shallowest portion and the deepest portion of the portion of the silicon dioxide film 19 doped with phosphorus. It is preferable to be 2 to 10 times the phosphorus concentration in the bulk near the middle.

  In the second embodiment of the present invention, portions different from the first embodiment of the present invention are described, and descriptions of the same or corresponding portions are omitted.

Embodiment 3 FIG.
FIG. 11 is a cross sectional view showing a silicon carbide semiconductor device 1b according to the third embodiment of the present invention. In FIG. 11, the same reference numerals as those in FIG. 1 denote the same or corresponding components, and the description thereof is omitted.

  In FIG. 11, n-type (first conductivity type) silicon carbide epitaxial layer 6 is formed on one surface 3 of n-type (first conductivity type) and low resistance silicon carbide substrate 2. On the surface side of silicon carbide epitaxial layer 6, a pair of p-type (second conductivity type) base regions 7 are formed at a predetermined distance from each other. Further, an n-type (first conductivity type) source region 8 is formed shallower than the base region 7 on the surface side of each base region 7. A p-type (second conductivity type) base contact region 11 is formed adjacent to each source region 8.

  Further, a silicon carbide epitaxial additional layer for channel 21 is formed on the surface of silicon carbide epitaxial layer 6 including a part of base region 7 and source region 8, and on channel silicon carbide epitaxial additional layer 21 and the source A gate insulating film 12 is formed on part of the surface of the region 8. Further, on the gate insulating film 12, a gate electrode 13 is formed in a region facing a region between the pair of base regions 7 and a part of the source region 8. Source electrode 16 is formed from a part of the surface of source region 8 to the surface of base contact region 11, and drain electrode 17 is formed on the other surface 22 of silicon carbide substrate 2. An interlayer insulating film 23 is formed on part of the gate insulating film 12 and the gate electrode 13.

  Next, a method for manufacturing silicon carbide semiconductor device 1b in the third embodiment of the present invention will be described. In addition, description is abbreviate | omitted here about the part similar to Embodiment 1 of this invention. 12 to 20 are cross sectional views showing a part of a method for manufacturing silicon carbide semiconductor device 1b in the second embodiment of the present invention.

  First, an n-type (first conductivity type) and low-resistance silicon carbide substrate 2 is prepared. Then, as shown in FIG. 12, n-type (first conductivity type) silicon carbide epitaxial layer 6 is formed on one surface 3 of silicon carbide substrate 2.

  Next, a mask is formed with a resist on the surface of silicon carbide epitaxial layer 6, and p-type (second conductivity type) impurities are ion-implanted from the surface side of silicon carbide epitaxial layer 6. Thereby, a pair of p-type (second conductivity type) base regions 7 separated from each other by a predetermined distance are formed in silicon carbide epitaxial layer 6. FIG. 13 shows a cross-sectional view after removing the resist.

  Next, a mask is formed with a resist on the surface of silicon carbide epitaxial layer 6, and n-type (first conductivity type) impurities are ion-implanted from the surface side of silicon carbide epitaxial layer 6. As a result, n-type (first conductivity type) source regions 8 are formed shallower than the base region 7 on the surface side of the base region 7. Thereafter, the resist is removed.

  Next, a mask is formed with a resist on the surface of silicon carbide epitaxial layer 6, and p-type (second conductivity type) impurities are ion-implanted from the surface side of silicon carbide epitaxial layer 6. As a result, the p-type (second conductivity type) base contact region 11 adjacent to the source region 8 is formed on the surface side of the base region 7. FIG. 14 shows a cross-sectional view after removing the resist.

  Next, the silicon carbide substrate 2 on which the silicon carbide epitaxial layer 6, the base region 7, the source region 8 and the base contact region 11 are formed is annealed at a high temperature by a heat treatment apparatus, and the ion-implanted aluminum or nitrogen is electrically charged. Is activated.

  Next, channel silicon carbide epitaxial additional layer 21 is formed on silicon carbide epitaxial layer 6 including base region 7, source region 8, and base contact region 11. Then, as shown in FIG. 15, the silicon carbide epitaxial additional layer for channel 21 is centered on the silicon carbide epitaxial layer 6 exposed between the pair of base regions 7 by photolithography and RIE (relative ion etching) technology. And patterning into a shape such that a part of each source region 8 is located at both ends.

  Next, at 800 to 1400 ° C., the surface of silicon carbide epitaxial layer 6 including base region 7, source region 8 and base contact region 11 and the surface of channel silicon carbide epitaxial additional layer 21 are thermally oxidized and fluorinated. The thermal oxide film is removed with hydrogen acid.

  Next, as shown in FIG. 16, phosphorus-doped polycrystalline silicon film 18 is formed on part of the surface of source region 8 and the surface of base contact region 11 on channel silicon carbide epitaxial additional layer 21. .

The density of interface states generated at the silicon carbide / silicon dioxide interface in the step of forming the gate insulating film 12 described later is about 1 × 10 ¹⁰ to 1 × 10 ¹⁵ cm ⁻² eV ⁻¹ , and the silicon carbide / silicon dioxide interface Since the thickness of the transition region is about 1 to 10 nm, the concentration of phosphorus doped into the polycrystalline silicon film 18 is the surface of the polycrystalline silicon film 18 in order to effectively passivat the interface state with phosphorus. It is substantially constant in the inward direction and the depth direction, and is preferably in the range of 1 × 10 ¹⁶ to 1 × 10 ²² cm ⁻³ .

The polycrystalline silicon film 18 doped with phosphorus is formed by a CVD method using SiH ₄ and PH ₃ as source gases. However, the present invention is not limited to this, and the non-doped polycrystalline silicon film 18 is first formed by the CVD method. Then, phosphorus may be doped by ion implantation.

  Next, the silicon carbide substrate 2 on which the polycrystalline silicon film 18 doped with phosphorus is formed is heated at a temperature in the range of 700 to 1400 ° C., and the polycrystalline silicon film 18 is entirely thermally oxidized to form silicon dioxide. A gate insulating film 12 is formed. By this step, phosphorus diffuses to the vicinity of the silicon carbide / silicon dioxide interface, and the interface states generated at the silicon carbide / silicon dioxide interface are passivated by phosphorus. A cross-sectional view after the gate insulating film 12 is formed is shown in FIG.

  Next, a polycrystalline silicon film is formed on the gate insulating film 12 by a CVD method and patterned by photolithography and etching techniques to form the gate electrode 13. As shown in FIG. 18, gate electrode 13 is patterned in such a shape that a pair of source regions 8 are located at both ends, and silicon carbide epitaxial layer 6 between source regions 8 is located in the center.

  Next, as shown in FIG. 19, an interlayer insulating film 23 for electrically insulating the source and the gate is formed on the gate electrode 13 and the gate insulating film 12.

  Next, portions of the gate insulating film 12 and the interlayer insulating film 23 from a part of the surface of the source region 8 to the surface of the base contact region 11 are removed. Then, as shown in FIG. 20, source electrodes 16 are respectively formed at portions from the surface of the source region 8 to the surface of the base contact region 11 exposed on the surface by removing the gate insulating film 12. .

  Next, drain electrode 17 is formed on the other surface 22 of silicon carbide substrate 2. As a result, the state shown in FIG. 11 is obtained.

  Finally, heat treatment is performed to alloy the source electrode 16 and the drain electrode 17 with the silicon carbide in contact therewith. Thus, n channel MOSFET which is silicon carbide semiconductor device 1b in the first embodiment of the present invention shown in FIG. 11 is completed.

  In the third embodiment of the present invention, the effects similar to those of the first embodiment of the present invention can be obtained as described above.

  In the third embodiment of the present invention, silicon carbide semiconductor device 1b is manufactured by forming channel silicon carbide epitaxial additional layer 21. However, silicon carbide semiconductor device 1b may be manufactured without forming silicon carbide epitaxial additional layer for channel 21.

  In the third embodiment of the present invention, portions different from the first embodiment of the present invention are described, and descriptions of the same or corresponding portions are omitted.

  The first to third embodiments of the present invention have been described above. These configurations described in the first to third embodiments of the present invention can be combined with each other.

1a, 1b Silicon carbide semiconductor device 2 Silicon carbide substrate 6 Silicon carbide epitaxial layer 7 Base region 8 Source region 11 Base contact region 12 Gate insulating film 18 Polycrystalline silicon film doped with phosphorus 19 Silicon dioxide film doped with phosphorus

Claims (14)

Forming a silicon film doped with phosphorus on the silicon carbide layer of the substrate having the silicon carbide layer;
Forming a gate insulating film by thermally oxidizing the silicon film;
A method for manufacturing a silicon carbide semiconductor device comprising: 2. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the step of forming the silicon film, phosphorus is doped at a concentration of 1 * 10 < ¹⁶ > to 1 * 10 < ²² > cm < ^-3 >.   In the process of forming the silicon film, the phosphorus concentration distribution in the depth direction in the silicon film is substantially constant from the shallowest part of the phosphorus-doped part to the vicinity of the interface with the silicon carbide layer. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein phosphorus is doped into the silicon carbide semiconductor device.   In the step of forming a silicon film, phosphorus is doped so that the phosphorus concentration is higher in the vicinity of the interface with the silicon carbide layer than the shallowest portion of the portion doped with phosphorus in the silicon film. A method for manufacturing a silicon carbide semiconductor device according to claim 2.   5. The silicon carbide semiconductor device according to claim 3, wherein the shallowest portion of the portion doped with phosphorus in the silicon film is near the surface of the silicon film. Manufacturing method. Forming a phosphorus-doped silicon dioxide film to be a gate insulating film on the silicon carbide layer of the substrate having the silicon carbide layer;
Heat-treating the substrate on which the silicon dioxide film is formed;
A method for manufacturing a silicon carbide semiconductor device comprising: The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein in the step of forming the silicon dioxide film, phosphorus is doped at a concentration of 1 × 10 ¹⁶ to 1 × 10 ²² cm ⁻³ .   In the step of forming the silicon dioxide film, the phosphorus concentration distribution in the depth direction in the silicon dioxide film is substantially constant from the shallowest part of the phosphorus-doped part to the vicinity of the interface with the silicon carbide layer. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein phosphorus is doped so that   In the step of forming the silicon dioxide film, phosphorus is doped so that the phosphorus concentration is higher in the vicinity of the interface with the silicon carbide layer than the shallowest part of the silicon dioxide film doped with phosphorus. A method for manufacturing a silicon carbide semiconductor device according to claim 7.   10. The silicon carbide according to claim 8, wherein a portion having the shallowest depth among portions doped with phosphorus in the silicon dioxide film is near the surface of the silicon dioxide film. A method for manufacturing a semiconductor device. A substrate having a silicon carbide layer;
A silicon carbide semiconductor device comprising: a gate insulating film formed of silicon dioxide doped with phosphorus formed on the silicon carbide layer;
The phosphorus concentration distribution in the depth direction in the gate insulating film has a peak value in the vicinity of the interface with the silicon carbide layer,
The peak value is 2 to 10 times the phosphorus concentration in the bulk in the vicinity of the intermediate portion between the shallowest portion of the portion of the gate insulating film doped with phosphorus and the interface. Silicon semiconductor device. The silicon carbide semiconductor device according to claim 11, wherein the phosphorus concentration in the bulk of the gate insulating film is 1 × 10 ¹⁶ to 1 × 10 ²² cm ⁻³ .   The phosphorus concentration distribution in the depth direction in the gate insulating film is substantially constant from the shallowest part to the bulk in the part of the gate insulating film doped with phosphorus. 12. The silicon carbide semiconductor device according to 12.   14. The silicon carbide semiconductor device according to claim 13, wherein the shallowest portion of the portion of the gate insulating film doped with phosphorus is near the surface of the gate insulating film.

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