JP2012044489A - Skew adjusting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a skew adjusting circuit that can supply skew fitted to the operation state of LSI, etc. to plural signals.SOLUTION: A delay adjusting circuit is provided to an integrated circuit having first and second signal lines through which first and second signals are transmitted, first and second buffer circuits to which the first and second signals transmitted through the first and second signal lines are input, and has first and second delay circuits provided at the respective front stages of the first and second buffer circuits, a skew measuring circuit for measuring skew between the first and second signals, and a delay adjusting circuit for determining delay amounts of the first and second delay circuits on the basis of the measured skew measured by the skew measuring circuit and setting the determined delay amounts to the first and second delay circuits.

Description

  The present invention relates to a skew adjustment circuit.

  An integrated circuit device (LSI) has an output buffer that outputs a plurality of signals to an external LSI or to another internal macro. For example, a signal line of a data bus of a plurality of bits is latched by a plurality of latch circuits such as flip-flops in response to a reference clock, and an output of the latch circuit is output via a corresponding output buffer. When a plurality of signals change from the L level to the H level at the same time, a large current flows through the power supply wirings of the plurality of output buffers to generate power supply noise. Conversely, when a plurality of signals simultaneously change from the H level to the L level, a large current flows through the ground wiring of the plurality of output buffers, thereby generating ground noise. Such noise is called simultaneous switching noise (SSN), and becomes particularly large when a plurality of output buffers having a large driving capability are simultaneously switched in the same direction.

  Patent Documents 1, 2, and 3 describe methods for suppressing such simultaneous switching noise. In either case, a predetermined delay is added to a plurality of signals to cause skew in the plurality of signals to suppress simultaneous switching.

JP 2007-129601 A JP 2004-334271 A JP-A-9-181593

  However, since the output timing of a plurality of signals varies depending on various factors, there are cases where noise due to simultaneous switching cannot be suppressed appropriately only by adding a predetermined delay.

  For example, since the operation speed in the LSI differs depending on the operating environment of the LSI and the timing of the internal signal differs, there may be a case where simultaneous switching noise cannot be appropriately reduced by a method in which a fixed delay circuit is inserted into the output signal. In addition, AC specifications in an external LSI that receives an LSI output signal, such as input setup time and hold time, differ depending on the LSI. However, in the method of inserting a fixed delay in an output signal, the AC spec. You may not be satisfied.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a skew adjustment circuit that can provide a plurality of signals with a skew adapted to the operating state of an LSI.

The first aspect of the skew adjustment circuit includes first and second signal lines that propagate the first and second signals, respectively, and first and second signals that propagate through the first and second signal lines. Is a skew adjustment circuit provided in an integrated circuit having first and second buffer circuits, respectively,
First and second delay circuits respectively provided in front stages of the first and second buffer circuits;
A skew measuring circuit for measuring a skew between the first and second signals;
A delay adjustment circuit that determines a delay amount of the first and second delay circuits based on the measured skew measured by the skew measurement circuit, and sets the determined delay amounts in the first and second delay circuits; Have

  According to the first aspect, the skew generated in a plurality of signal lines is measured, and the target skew is generated by delaying the signal of each signal line by the delay amount determined based on the measured skew. Simultaneous switching noise can be appropriately suppressed.

It is a figure which shows the integrated circuit device which has the skew adjustment circuit in this Embodiment. FIG. 2 is a signal waveform diagram illustrating an outline of skew adjustment by the skew adjustment circuit 10 of FIG. 1. It is a figure which shows the skew adjustment circuit in 1st Embodiment. 2 is a diagram showing a selector 26 in the signal change monitoring circuit 25. FIG. 2 is a diagram showing a skew measurement circuit 28 in the signal change monitoring circuit 25. FIG. 2 is a diagram illustrating a delay adjustment circuit 35 in the skew adjustment circuit 10. FIG. It is a figure which shows the structure of target skew value ROM45. It is a figure which shows the relationship between the measurement skew data and target skew data in this Embodiment. It is a figure of the operation | movement flowchart of a skew adjustment circuit. It is a timing chart figure which shows the operation example of a skew adjustment circuit. It is a figure which shows a delay circuit and the relationship between the tap value and delay amount. It is a figure explaining the allowable delay amount. It is a figure which shows the 1st modification of the skew adjustment circuit in 1st Embodiment. 2 is a diagram illustrating an example of an operation state monitoring circuit 50. FIG. It is a figure which shows the specific example of target skew value ROM. It is a figure which shows the 2nd modification of the skew adjustment circuit in 1st Embodiment. It is a figure which shows the delay adjustment circuit in the 2nd modification of 1st Embodiment. 3 is a diagram illustrating a configuration example of a RAM 75. FIG. It is a figure explaining the delay setting value which should be adjusted. It is a figure explaining the delay setting value which should be adjusted. It is a figure which shows the 3rd modification of the skew adjustment circuit in 1st Embodiment. 3 is a diagram illustrating a specific example of a RAM 75. FIG. It is a figure of the skew adjustment circuit in 2nd Embodiment. 6 is a diagram illustrating a specific example of a delay amount ROM 45. FIG. It is a figure which shows the calculation 1 of the delay setting value calculating circuit 381 in this Embodiment. It is a figure which shows the calculation 2 of the delay setting value calculating circuit 381 in this Embodiment. It is a figure which shows the calculation 2 of the delay setting value calculating circuit 381 in this Embodiment. It is a figure which shows the calculation 2 of the delay setting value calculating circuit 381 in this Embodiment. It is a figure which shows the 1st modification of the skew adjustment circuit in 2nd Embodiment. 6 is a diagram illustrating a specific example of a delay amount ROM 45. FIG. It is a figure which shows the 2nd modification of the skew adjustment circuit in 2nd Embodiment. It is a figure which shows the 3rd modification of the skew adjustment circuit in 2nd Embodiment. It is a figure which shows the modification of the skew adjustment circuit of FIG.

  FIG. 1 is a diagram illustrating an integrated circuit device having a skew adjustment circuit according to the present embodiment. FIG. 1 shows a circuit of an output portion of the LSI. In FIG. 1, a plurality of data signals Data # 1 to Data # N are latched by a plurality of flip-flops FF # 1 to FF # N in response to a clock CLK. The plurality of latched data signals are output as output data signals O_Data # 1 to O_Data # N to other external LSIs or to other internal macros via the output buffers OB_1 to OB_N.

  Data signals Data # 1 to Data # N propagate through signal wirings between the plurality of flip-flops and the output buffer, respectively. When the data signal is input to the output buffer, the output buffer drives the output terminal in response to the change from the L level to the H level (Rise) or the change from the H level to the L level (Fall). . At that time, a drive current flows through the power supply VDD and the ground VSS connected to the output buffers OB_1 to OB_N.

  When the timings of changes of the data signals supplied to the output buffers OB_1 to OB_N match, a plurality of output buffers perform the driving operation simultaneously. In that case, if all the changes in the data signal are the same or the changes in many data signals are the same, a large current flows through the power supply VDD and the ground VSS due to the simultaneous drive operation of the output buffer, generating power supply noise or ground noise.

  Therefore, in FIG. 1, the skew adjustment circuit 10 monitors the number and timing of changes in the data signal propagated through each signal wiring, and determines the delay amount of each signal wiring according to the detected number and timing of signal changes. To do. Then, the delay amount of the delay circuits DL_1 to DL_N provided immediately before the output buffers OB_1 to OB_N is set to the determined delay amount, and the timings of the driving operations in the plurality of output buffers OB_1 to OB_N do not match as much as possible. Like that.

  Further, the skew adjustment circuit 10 monitors changes in the operation state of the LSI (process condition, voltage condition, temperature condition), and determines an optimum delay amount according to the operation state. In addition, as the delay amount, a delay amount suitable for the AC specifications of other LSIs to which the output data signals O_Data # 1 to O_Data # N are input, for example, the setup time is selected. Other macros that receive the output data signals O_Data # 1 to O_Data # N can be similarly adapted to the AC specifications.

  FIG. 2 is a signal waveform diagram showing an outline of skew adjustment by the skew adjustment circuit 10 of FIG. In FIG. 1, in response to a clock CLK, a plurality of flip-flops FF # 1 to FF # N latch data signals Data # 1 to Data # N. In the example of FIG. 2, the latch timings coincide. The skew adjustment circuit monitors changes in the outputs of the flip-flops FF # 1 to FF # N, and if signal changes are detected in all or many signal wirings as shown in FIG. The amount Delay # 1 to Delay # N is appropriately controlled to generate an appropriate skew in the data signals FF # 1_Q to FF # N_Q input to the output buffers OB_1 to OB_N.

  In this way, the skew adjustment circuit 10 adjusts the delay amount of the delay circuit provided in the signal wiring, thereby shifting the timing of the propagated data signal to have an appropriate skew. As a result, the simultaneous switching noise due to the simultaneous switching operation by the output buffer is suppressed.

[First Embodiment]
FIG. 3 is a diagram illustrating the skew adjustment circuit according to the first embodiment. FIG. 3 shows the configuration of the output section of the LSI. The final stage flip-flop 1 that latches the two data signals Data_A and Data_B in response to the reference clock Ref_CLK, and the output terminal Q of the flip-flop 1 respectively. It has two connected signal lines SL_A to SL_B and output buffers OB_A to OB_B for inputting signals SG_A to SG_B propagating through the signal lines and outputting them to other external LSIs or to other macros inside the LSIs . In the figure, output buffers OB_A to OB_B also show input buffers for inputting signals in addition to buffer circuits for outputting signals. That is, OB_A to OB_B shown in the figure are input / output buffers.

  In the skew adjustment circuit 10, two signal lines SL_A to SL_B are provided with delay circuits DL_A to DL_B immediately before the output buffers OB_A to OB_B. As described above, by adjusting the delay amount of the delay circuit, an appropriate skew is generated in the signals SG_A to SG_B propagating through the signal lines SL_A to SL_B. This suppresses the generation of noise due to simultaneous switching by shifting the switching timing in the output buffer.

  The control enable signal Cnt_EN is generated by a circuit (not shown). However, when a stable system clock is input and a stable internal reference clock Ref_CLK is generated in the initialization operation of the system of the skew adjustment circuit, the control enable signal Cnt_EN is Become H level. In response to the control enable signal Cnt_EN = H, the skew adjustment operation of the skew adjustment circuit 10 starts.

  The control enable signal Cnt_EN can be configured to be controlled from an upper system to an enable state (H level) and a disable state (L level). With this configuration, the skew adjustment circuit can be stopped after the skew adjustment circuit is automatically operated and the skew adjustment is performed after the initialization operation such as when the power is turned on. In addition, when the temperature of the LSI rises, the control enable signal Cnt_EN can be controlled to be in an enable state, skew adjustment can be performed, and then the disable state can be controlled. By controlling the operation and stop of the skew adjustment circuit in this way, it is possible to avoid generation of useless current consumption.

  The skew adjustment circuit 10 determines the skew between signals in the level change (Rise) from the L level to the H level or the level change (Fall) from the H level to the L level of the signals SG_A to SG_B propagating through the two signal lines. A signal change monitoring circuit 25 for monitoring is provided. If the skew between the signals is small or zero, it causes power supply noise and ground noise due to simultaneous switching in the output buffer.

  The signal change monitoring circuit 25 includes a selector 26 that selects the first and second signals SG_A and SG_B propagating through the first and second signal lines SL_A and SL_B as either data or clock, and the selector 26 And a skew measuring circuit 28 for measuring a skew between data to be output and a clock. The configuration of a skew measurement circuit described later measures skew on the assumption that the clock is earlier than data. Therefore, the skew measurement circuit 28 measures the skew by using one of the first and second signals as data and the other as a clock. If any skew is detected, the skew measurement circuit 28 adds the first and second values in addition to the skew value. It also detects that the other of the signals is early. The skew measuring circuit measures the skew using one of the first and second signals as data and the other as a clock, and if no skew is detected, the skew measurement circuit sends one of the first and second signals as a clock to the other. Is output as data, and the skew is measured again.

  The skew adjustment circuit 10 further includes a delay adjustment circuit 35. The delay adjustment circuit 35 is based on the skew (measurement skew) between the first and second signals measured by the skew measurement circuit 28. The delay amounts of the second delay circuits DL_A and DL_B are determined, and the determined delay amounts are set in the first and second delay circuits DL_A and DL_B. The delay adjustment circuit 35 in the first embodiment refers to the ROM 45 that stores the target skew for the first and second signals SG_A and SG_B propagating through the signal lines SL_A and SL_B that are skew adjustment targets, and the read target The difference between the skew and the measured skew measured by the skew measurement circuit 28 is determined as the delay amount of the delay circuits DL_A and DL_B, and the determined delay amount is set in these delay circuits.

  FIG. 33 is a diagram showing a modified example of the skew adjustment circuit of FIG. In this modified example, similarly to the data Data_A and Data_B, the final data flip-flop 1 captures the data Data_X in synchronization with the reference clock Ref_CLK and propagates the signal lines having the same length as the signal lines SL_A and SL_B of the data Data_A and Data_B The signal change is input to the circuit 25. Although the timing of the reference clock Ref_CLK for capturing the data Data_X and the signal line from the final stage flip-flop 1 to the signal change monitoring circuit 25 are different, a skew equivalent to the data Data_A and Data_B can be measured. Thus, although the skew measurement accuracy is inferior to that of FIG. 3, since the data Data_X is latched by two flip-flops, two signals are input to the signal change monitoring circuit 25 at the same rising edge having skew. . Therefore, skew measurement is easier than using data Data_A and Data_B.

  FIG. 4 is a diagram showing the selector 26 in the signal change monitoring circuit 25. The selector 26 selects one of the signals of the pair of signal lines SL_A and SL_B to be skew adjusted as data and the other as a clock and outputs the selected data to the skew measuring circuit 28. If the skew measurement circuit 28 cannot detect the skew appropriately because the data is earlier than the clock, the selector 26 replaces the signals of the signal lines SL_A and SL_B, and selects the one as the clock and the other as the data. To the skew measurement circuit 28. In this case, the second flag 2nd_Flag indicating the replacement is set to “1” and notified to the skew measurement circuit 28. Thus, the skew measurement circuit 28 can determine which of the first and second signals SG_A and SG_B is output as data or a clock by referring to the second flag 2nd_Flag.

  The selector 26 includes selectors 261 and 262 that select one of the signals SG_A and SG_B of the signal lines SL_A and SL_B as the data 277 and the other as the clock 278 based on the second flag 2nd_Flag. Further, the selector 26 responds to the reference clock Ref_CLK after the AND gate 263 that detects both the signals SG_A and SG_B are “0” (L level) and the control enable signal Cnt_EN is “1” (H level). , A simultaneous rise detection circuit 267 that detects that both signals SG_A and SG_B rise together and sets the simultaneous rise detection signal S_EN to “1”. In addition, a flag generation circuit 268 that generates a second flag 2nd_Flag and a renew_flag renew_Flag, and an AND gate 274 that generates a renew enable signal renew_EN based on the simultaneous rise detection signal S_EN at the first skew measurement and the second skew measurement. 275, an OR gate 276. Further, a skew measurement result dcba_reg (a) and an update completion signal renew_comp are supplied from the delay adjustment circuit 35. Based on these signals, a control signal renew_EN corresponding to the first skew measurement and the second skew measurement, 2nd_Flag and renew_Flag are generated. These specific operations will be described in detail later.

  FIG. 5 is a diagram showing the skew measurement circuit 28 in the signal change monitoring circuit 25. As shown in FIG. 5A, the skew measurement circuit 28 measures the skew between both signals on the assumption that the clock 278 has a timing earlier than the data 277.

  FIG. 5B shows the skew measurement circuit 28, and FIG. 5C shows a signal waveform indicating the operation of the circuit. The skew measurement circuit 28 includes a plurality of latch circuits 281 to 284 that input data 277 to each data input terminal D, and a clock supply circuit 285 that inputs the clock 278 to the clock terminal of the latch circuit while delaying the clock 278. The clock supply circuit 285 has a plurality of buffers, and signals X, Y, and Z of each node are input to the clock terminals of the latch circuits 282, 283, and 284.

  As shown in FIG. 5C, the skew between the clock 278 that is one of both signals SG_A and SG_B and the data 277 is measured skew data 286 (dcba) output from the data output Q of the latch circuits 281 to 284. Is output. In the example of FIG. 5C, the measured skew data dcba = 1100. This measured skew data dcba means that the greater the zero, the greater the skew value. Therefore, the skew value is smaller when measured skew data dcba = 1100 than when dcba = 1000. It should be noted in the delay adjustment circuit described later that the magnitude relation of the measured skew data dcba is opposite to the magnitude relation of the skew value.

  FIG. 6 is a diagram showing the delay adjustment circuit 35 in the skew adjustment circuit 10. Measurement skew holding registers 351 and 352 for holding measured skew data dcba, a target skew value read from the target skew value storage ROM 45 and a measured skew value of the measurement skew holding register 352 are compared, and a skew for detecting a difference between them is detected. The comparison circuit 355 includes a delay setting register 362 in which the detected difference is set as a delay. Based on the delay amount set in the delay setting register 362, the delay circuits DL_A and DL_B delay both signals SG_A and SG_B to generate an appropriate skew. The delay adjustment circuit 35 also includes a timing generation circuit 353 that generates a timing signal in response to the renewal enable signal renew_EN, an address management table 363 that manages an address to the target skew value ROM 45, and a latch that latches read data R_data. Circuit 354. The difference detection in the skew comparison circuit 355 is performed by the exclusive OR circuit 357 and the difference counter 358.

  FIG. 7 is a diagram showing the configuration of the target skew value ROM 45. The address is a signal group that simultaneously operates and is a signal group Gr to be skew-adjusted and a combination of signal pairs, and the corresponding data is a target skew value. This target skew value is in the same format as the measured skew data, and is data n-dcba in the format output by the skew measurement circuit in FIG. Therefore, similarly to the measured skew value and the measured skew data dcba, the target skew value and the target skew data n-dcba in the ROM have a reversed magnitude relationship.

  FIG. 8 is a diagram showing a relationship between measured skew data and target skew data in the present embodiment. As described above, the value of the measured skew data dcba output from the skew measuring circuit 28 is opposite to the magnitude relationship of the measured skew. Similarly, the value of the target skew data dcba output from the ROM 45 is opposite to the target skew magnitude relationship. In the example shown in FIG. 8, the target skew data dcba = 1100 with respect to the measured skew data dcba = 1000. As can be understood from the waveform in FIG. 8, the target skew is smaller than the measured skew. However, in the comparison between the data, the measured skew data dcba = 1000 <target skew data dcba = 1100.

  FIG. 9 is an operation flowchart of the skew adjustment circuit. The outline of the skew adjustment operation of FIGS. 4 to 6 will be described according to this operation flowchart. First, in the initialization operation of the system of the skew adjustment circuit, when a stable system clock is input and a stable internal reference clock Ref_CLK is generated, the control enable signal Cnt_EN becomes H level (S10). In response to the control enable signal Cnt_EN = H, the skew adjustment operation of the skew adjustment circuit 10 starts.

  The selector 26 sets the signal SG_A as data and the signal SG_B as clock according to whether or not the first skew measurement is made (S14). If it is the second time, the signal SG_A is set to the clock and the signal SG_B is set to the data (S16). Specifically, in the first time, the second flag 2nd_Flag = 0, and the selectors 261 and 262 in FIG. 4 select the signal SG_A as the data 277 and the signal SG_B as the clock 278, respectively. If it is the second time, the second flag 2nd_Flag = 1 and the selection opposite to the above is performed.

  When the simultaneous rise detection circuit 267 detects the rise change of the signals SG_A and SG_B, the simultaneous rise detection signal S_EN is set to “1” (S18). That is, when the AND gate 263 detects the L level of both signals SG_A and SG_B, the latch circuit 264 latches it in response to the reference clock Ref_CLK, and then the AND gate 265 detects the H level of both signals SG_A and SG_B. The latch circuit 266 latches it in response to the next reference clock Ref_CLK, and the simultaneous rise detection signal S_EN = 1.

  When the previous skew adjustment is completed, the second flag 2nd_Flag = 0 and the renew flag renew_Flag = 0 are reset by the update completion signal renew_comp = 1. In the case of the first skew measurement, the least significant data dcba_reg (a) of the retained data dcba_reg in the measurement skew retaining register 351 that stores the measured skew data dcba measured by the skew measuring circuit 28 is dcba_reg (a) = 0. If there is, the AND gate 274 sets the renew enable signal renew_EN = 1 in response to S_EN = 1. Alternatively, in the case of the second skew measurement, the AND gate 275 sets the renew enable signal renew_EN = 1 in response to S_EN = 1 regardless of the retained data dcba_reg (a).

  Returning to FIG. 9, when the measured skew data dcba = 1111 detected by the skew measurement circuit 28 (S20), the process proceeds to the second skew measurement (S22). If the measured skew data dcba ≠ 1111 in the first measurement, or if the second skew measurement, the measured skew data dcba holds the data in response to the renew enable signal renew_EN = 1. To do.

  When the renew enable signal renew_EN = 1 in the first and second skew measurements, the delay adjustment circuit 35 in FIG. 6 starts to operate, and the skew comparison circuit 355 holds the target skew value read from the ROM 45. The skew value is compared and the difference is calculated (S28). Further, the determination unit 359 in the skew comparison circuit 355 generates selection signals for the selectors 360 and 361 based on the second flag 2nd_Flag and the comparison result S356. Further, the XOR 357 and the difference counter 358 count the difference between the numbers of “0” between the measured skew data and the target skew data, and obtain a difference value. The difference value S358 is set as a tap value corresponding to the delay amount of the delay circuit in the delay setting register 362 via the selectors 360 and 361 (S30).

  The delay setting register 362 is reset in response to the renewal enable signal renew_EN = 1, and the difference value is set at the timing of the 180 ° phase of the reference clock Ref_CLK that is the output of the inverter 363.

  A logical value table of the discrimination unit 359 is shown in FIG. According to this, at the time of the first skew measurement (2nd_Flag = 0), the case of measured skew data dcba <target skew data dcba, that is, the case of measured skew> target skew is the case of FIG. The difference is set as the delay amount on the signal SG_B side, and the delay amount is set to zero on the late signal SG_A side. When the inequality sign is reversed, contrary to the above, the delay amount zero is set on the signal SG_B side with earlier timing, and the difference amount is set as the delay amount on the signal SG_A side with later timing. In the second skew measurement (2nd_Flag = 1), the signals SG_A and SG_B have an opposite relationship.

  FIG. 10 is a timing chart illustrating an operation example of the skew adjustment circuit. In this operation example, in the first skew adjustment, the skew is measured in the first skew measurement and the delay amount of the delay circuit is set. In the next skew adjustment, the skew cannot be measured in the first skew measurement (dcba = 1111). ) Skew is measured in the second skew measurement.

  At time t0, initialization has already been completed and the control enable signal cnt_EN = 1. Also, the latch circuits 272 and 273 in the selector circuit 26 are reset by the update completion signal renew_comp = 1 with the completion of the previous delay amount setting, and 2nd_Flag = 0 and renew_Flag = 0.

  When the data signals A and B both rise at time t1, the simultaneous rise detection circuit 267 sets LL_Flag = 1, and at time t2, the simultaneous enable signal S_EN = 1 changes in response to the rise of the reference clock Ref_CLK. The skew measurement circuit 28 always measures the skew difference between the two signals, and the data held at time t2 is the measured skew data dcba_reg = 1100 and dcba_reg (a) = 0. The enable signal renew_EN = 1. dcba_reg (a) = 0 means that the timing of the signal B is earlier than that of A, and means that the first measurement is properly performed.

  At time t3, in response to renew_EN = 1, the measurement skew holding register 352 latches dcba_reg = 1100, and at the same time, the output of the AND gate 270 in the flag generation circuit 268 = 1, and the latch circuit 273 causes the renew flag renew_Flag. Set to = 1.

  In the timing generation circuit 353 in the delay adjustment circuit 35 of FIG. 6, the output enable signal xOE = 0 is generated in the ROM 45 at time t5 by the renew flag renew_Flag = 1, and the combination of the signals A and B from the address management table 363 is shown. The address is output, and the target skew data R_data in the ROM 45 is read at time t7.

  After that, the skew comparison circuit 355 in the delay adjustment circuit 35 performs the comparison operation and the difference count operation, and the delay amount corresponding to the difference is stored in the delay setting register 362 at the timing of the update completion signal renew_comp = 1. Is set according to Thereby, the first skew adjustment is completed.

  Next, the rise of the signals A and B at time t10 is detected, and the simultaneous rise detection signal S_EN = 1 is set at time t11. However, due to the renew flag renew_Flag = 1 indicating that the first skew adjustment is in progress, the AND gates 274 and 275 in the selector do not set the renew enable signal renew_EN to “1”.

  Next, at the time t13, the rising edges of the signals A and B are detected. At the time t14, the simultaneous rising edge detection signal S_EN = 1 and the first skew measurement is performed. However, since the measured skew data dcba_reg (a) = 1, The output of the AND gate 274 of the selector remains “0” and the renew enable signal renew_EN is not set to “1”. At time t15, in response to the reference clock Ref_CLK by the measured skew data dcba_reg (a) = 1, the latch circuit 272 loads “1” by the AND gate 269 of the selector 26 to set the second flag 2nd_Flag = 1. This starts the second skew measurement.

  The rise of the signals A and B is detected at time t18, the simultaneous rise detection signal S_EN = 1 at time t19, the renew enable signal renew_EN = 1 by the AND gate 275 of the selector 26, and the time by the AND gate 271 and the latch circuit 273. In response to the next reference clock Ref_CLK at t20, the renew flag renew_Flag = 1. Thereby, the delay control circuit 35 sets the delay amount based on the second measurement skew data and the target skew data read from the ROM 45. This delay amount setting operation is the same as described above.

  FIG. 11 is a diagram illustrating the delay circuit and the relationship between the tap value and the delay amount. The delay circuit DL_ # includes a buffer group 313 including a plurality of buffers for delaying the input data signal Data, and a selector 315 that selects a plurality of nodes in the buffer group 313 based on the setting code S_CODE. FIG. 11 shows a correspondence table between the tap value of the selector and the setting code S_CODE. The smaller the setting code S_CODE, that is, the smaller the tap value, the smaller the delay amount inserted by the delay circuit DL_ #. In this case, the amount of delay increases. Each 4-bit setting code S_CODE for the eight delay circuits DL_0 to DL_7 is set in the delay amount setting register 361 in FIG.

  In the present embodiment, when a simultaneous change in the signals of the signal lines SL_A and SL_B is detected, the skew of the signals is measured, and the delay amount of the delay circuit provided in each signal line is adjusted to reduce the skew between the signals. Adjust appropriately to suppress simultaneous switching by the output buffer. However, this delay amount cannot exceed the allowable delay amount that conforms to the AC specifications of the input circuits of other LSIs or macros that are supplied with the output of the output buffer. Therefore, the delay amount set in the delay amount ROM is set to be less than the allowable delay amount conforming to this AC specification.

  FIG. 12 is a diagram for explaining the allowable delay amount. In the figure, a reference clock Ref_CLK inside the LSI and a system clock S_CLK for a plurality of LSIs are shown. These clocks are synchronized and have the same period T, but there may be a predetermined phase difference dT between the two clocks as shown.

  In FIG. 3, at the output stage of the LSI, the final stage flip-flop 1 latches the data signal in response to the reference clock Ref_CLK. Then, the data signal is output to another LSI or other macro in the subsequent stage through the signal line SL and the output buffer OB. The other LSI or other macro input circuit in the subsequent stage takes in the input signal at the rising edge of the system clock S_CLK, and the setup time Ts and hold time Th are determined as AC specifications for the input circuit.

  In FIG. 12, for data A and data B, the sum TOx of the output delay from the final stage flip-flop and the delay of the output buffer and the allowable delay value satisfying the setup time Ts are shown. The delay value TOx on the output side varies depending on the process conditions, temperature conditions, power supply voltage, etc., so there are maximum and minimum values. Therefore, the cases where the delay values TOx are the maximum and the minimum are respectively shown for the data A and B.

The allowable delay values that satisfy the setup time Ts are as follows for the data A and B, respectively.
Data A = T-T0a_max-Ts + dT
Data B = T-T0b_max-Ts + dT
Since the delay value TOx of data B is larger, the allowable delay value of data B is smaller. Therefore, a delay amount less than the allowable delay value of the data B is set in the delay amount ROM 45. As a result, it is guaranteed that the skew-adjusted output signal is supplied to the subsequent LSI or macro input circuit at a timing that satisfies the setup time Ts.

  The skew measuring circuit 28 measures the skew by selecting one of the two signals SG_A and SG_B as a clock and one of them as data. The skew measuring circuit 28 includes two skew measuring circuits shown in FIG. By providing them, the skew between the two signals can be measured at the same time, regardless of which of the two signals SG_A and SG_B is early. In that case, it is possible to detect which signal timing is earlier by referring to the measurement result dcba of both skew measurement circuits. The skew adjustment circuit of the present embodiment may have two sets of skew measurement circuits as described above.

[First Embodiment (2)]
FIG. 13 is a diagram illustrating a first modification of the skew adjustment circuit according to the first embodiment. 3 is different from the skew adjustment circuit 10 of FIG. 3 in that it has an operation state monitoring circuit 50 and that the target skew value ROM 45 is added to the skew adjustment target signal group Gr and the skew adjustment target signal pair. The target skew value corresponding to the operation speed detected by is stored. The delay circuits DL_A and DL_B are the same as in FIG. 11, the selector 26 is the same as in FIG. 4, the skew measurement circuit 28 is the same as in FIG. 5, and the delay adjustment circuit 35 is also the same as in FIG. However, the address management table 363 in the delay adjustment circuit 35 also adds the operation speed from the operation state monitoring circuit 50 to the address.

  In this modified example, the operation state monitoring circuit 50 monitors the change in the gate speed in the LSI caused by the operation state (process condition, temperature condition, voltage condition variation), and the operation state signal Fast when the speed is high. And an operation state signal Typical in a typical case and an operation state signal Slow in a low speed are output. Since the ROM 45 stores the target skew value corresponding to this operation speed, a delay amount suitable for the operation state can be set in the delay circuit.

  Specifically, compared to the delay amount at a typical speed, the delay amount in the delay circuit DL is increased at a high speed, that is, the number of delay buffers is increased, and the absolute delay time, that is, the absolute delay time is increased. The amount of skew is equivalent to that of a typical speed. On the other hand, when the speed is low, the delay amount in the delay circuit DL is reduced, that is, the number of delay buffers is reduced, and the absolute delay time, that is, the absolute skew is set to a typical speed. Make equal.

  The reasons why the operating speed varies depending on whether the operating speed is high or low are, first, process conditions such as manufacturing variations caused by the target value at the time of manufacturing the device, second, whether the power supply voltage is high or low, Whether the temperature is high or low. As described above, the delay amount of the delay circuit is a value that gives an appropriate skew for simultaneous switching noise reduction and needs to be set to a value less than the allowable delay amount. Therefore, it is desirable to change the number of delay buffers in the delay circuit in accordance with the variation in operation speed.

  FIG. 14 is a diagram illustrating an example of the operation state monitoring circuit 50. The operation state monitoring circuit detects the phase difference between the delay circuit 501 that delays the clock CLK0 having the phase 0 ° and outputs the clock CLK90 having the phase 90 °, and the two clocks CLK0 and CLK90, and the phase difference is 90 °. A delay control circuit 503 for generating a delay control signal 507 for the delay circuit. The delay circuit 501 has the same configuration as the delay circuit shown in FIG. Therefore, the delay control signal 507 is a control signal that selects a signal that has propagated more buffers if the LSI gate speed is high, and a control signal that selects a signal that has propagated less buffers if the gate speed of the LSI is low. Become. In the example of FIG. 14, the delay control signal 507 is decoded by the decoder 505 and converted into three kinds of operation state signals Fast, Typical, and Slow.

  As shown in the delay adjustment circuit 35 of FIG. 6, in this embodiment, the operation state signal output from the operation state monitoring circuit 50 is also output to the address management table 363. The delay adjustment circuit 35 uses the operation state signals Fast, Typical, and Slow as an address when referring to the ROM 45 in addition to the skew adjustment target signal group Gr and the skew adjustment target signal pair.

  FIG. 15 is a diagram showing a specific example of the target skew value ROM 45. In the case of the ROM 45, in addition to the skew adjustment target signal group Gr and the skew adjustment target signal pair, the operation state signals Fast, Typical, and Slow are included as addresses. The data is target skew data n-dcba, which is the target of the signal pair. That is, the data of FIG. 7 is stored for each of the operation state signals Fast, Typical, and Slow.

  However, as shown in FIG. 15, the target skew data when the operation state is the high speed Fast is set to “0” more than the case of the typical speed Typical, and the target skew data when the operation state is the low speed Slow is the typical speed Typical. “0” is set to be smaller than in the case of. That is, the absolute target skew is made almost constant regardless of the operation speed. By referring to the delay amount ROM 45, appropriate target skew data corresponding to the operation state can be read out to the delay adjustment circuit.

  The ROM 45 may be a rewritable memory. If it is a rewritable memory, the optimal target skew value can be rewritten according to the operating environment of the LSI, for example, the AC specifications of other LSIs that input output signals, and optimal skew adjustment is possible. is there.

[First Embodiment (3)]
FIG. 16 is a diagram illustrating a second modification of the skew adjustment circuit according to the first embodiment. As in FIG. 3, the skew adjustment circuit 10 includes a signal change monitoring circuit 25 having a selector 26 and a skew measurement circuit 28, a delay adjustment circuit 37, and delay circuits DL_A and DL_B. The selector 26 and the skew measuring circuit 28 of the signal change monitoring circuit 25 are the same as those shown in FIGS. 4 and 5, and the delay circuit is also the same as that shown in FIG.

  However, unlike FIG. 3, the delay amount to be adjusted according to the measurement skew is stored in the RAM 75 provided outside the LSI, and the delay amount to be adjusted in the RAM 75 is set by an external CPU. . Accordingly, the delay adjustment circuit 37 of the second modification has the configuration of FIG. 17 instead of the configuration of FIG. In addition, a CPU interface 62 that interfaces with an external CPU bus is provided, and an interface operation between the delay adjustment circuit 37 and the CPU is performed.

  The CPU downloads the optimum delay amount to the RAM 75 as appropriate. By making the delay amount of the RAM 75 rewritable in this way, for example, it is possible to dynamically set a delay amount that conforms to the AC specifications of other LSIs or other macros that input signals output from the output buffer. it can.

  Further, the RAM 75 and the CPU may be provided in a common LSI. That is, when the LSI is a system LSI, a CPU and a RAM are provided in the LSI, and these may be used.

  FIG. 17 is a diagram illustrating a delay adjustment circuit according to the second modification of the first embodiment. The delay adjustment circuit 37 includes a measurement skew register 370, a delay setting value register 371, and a delay setting register 373. In the measurement skew register 370, the renew enable signal renew_EN = 1 supplied from the selector 26 is held as a skew valid bit, the second flag 2nd_Flag is held as a determination mode signal, and measurement skew data output from the skew measurement circuit 28 is stored. Retained. When these are held, the skew valid bit is set to valid “1”.

  The CPU monitors the skew valid bit in the measurement skew register 370, and when it becomes “1”, reads the adjustment delay data for the signals A and B from the RAM 75 using the judgment mode signal and the measurement skew data as addresses. The delay setting value register 371 stores the delay switching bit to “1”. In response to the delay switching bit “1”, the delay setting register 373 takes in the delay setting value for the signal A and the delay setting value for the signal B in response to the inversion timing of the reference clock Ref_CLK. As a result, the delay setting value is set in the delay circuits DL_A and DL_B. In response to the delay switching bit “1”, the skew valid bit in the measurement skew register 370 is cleared to “0”.

  FIG. 18 is a diagram illustrating a configuration example of the RAM 75 that stores the delay amount to be adjusted. The addresses of the RAM 75 are the group Gr, signal combination information, measurement skew data, determination mode (first time or second time), and a signal to be set (setting signal). On the other hand, the data stores a delay setting value indicating the delay amount to be set in the setting signal. The right side of the table shows the waveform for which the delay is adjusted according to the delay setting value.

  The delay setting value corresponds to the delay amount to be adjusted by the delay circuits DL_A and DL_B in order to generate the target skew corresponding to the measured skew data, and the data in the RAM 75 is the setting code of the delay circuit of FIG. S_CODE. As shown in FIG. 11, the smaller the setting code S_CODE, the smaller the delay amount to be inserted. Therefore, the delay setting value in the RAM 75 corresponds to the difference between the aforementioned measured skew data and target skew data. Also, the delay setting value is that the signals to be inserted are reversed A and B depending on whether the judgment mode is the first (1st) or the second (2nd).

  19 and 20 are diagrams for explaining delay setting values to be adjusted. FIG. 19 shows waveforms of signals A and B indicating the measured skew and the target skew corresponding to the skew measuring circuit 28. For the measured skew data dcba = 1000, the target skew data dcba = 1100. Therefore, in order to realize this target skew, it can be understood that the delay amount “1” is inserted on the signal B side and the delay amount is zero on the signal A side. The data in the RAM 75 in FIG. 18 is a delay circuit setting code S_CODE to be set for each of the signals A and B, so that the delay amount necessary for realizing the target skew is set.

  FIG. 20 shows a specific example of the RAM 75 and the delay setting value of the delay circuit 28. In the case of the measurement skew and the target skew as shown in FIG. 19, a delay amount of zero should be inserted on the signal A side, and a delay amount “1” should be inserted on the signal B side. Therefore, the delay setting value “0000” is stored for the signal A and the delay setting value “0001” is stored for the signal B in the determination mode “1st” of the RAM 75. As a result, the tap corresponding to the delay setting value “0000” is selected for the delay circuit 28 on the signal A side, and the tap corresponding to the delay setting value “0001” is selected for the delay circuit 28 on the signal B side. By delaying the signal B side by the delay amount “1”, the skew between the signals A and B becomes equal to the target skew.

  Returning to FIG. 18, the determination mode “1st” side also shows delay setting values in the case of dcba = 1100 and dcba = 1110 in addition to the case of the measured skew data dcba = 1000. In the case of the measured skew data dcba = 1100, since the target skew is generated between the signals A and B, the delay setting values to be set are both zero. In the case of the measured skew data dcba = 1110, the delay amount “1” to be inserted into the signal A and the delay amount “0” to be inserted into the signal B are stored as delay setting values, respectively. In the case of the determination mode “2nd”, the signals A and B have an opposite relationship to the determination mode “1st”.

[First Embodiment (4)]
FIG. 21 is a diagram illustrating a third modification of the skew adjustment circuit according to the first embodiment. 16 differs from the skew adjustment circuit 10 of FIG. 16 in that it has an operation state monitoring circuit 50 and that the RAM 75 detects the operation state monitoring circuit 50 in addition to the skew adjustment target signal group Gr and the skew adjustment target signal pair. The delay setting value to be adjusted corresponding to the speed is stored. The delay circuits DL_A and DL_B are the same as in FIG. 11, the selector 26 is the same as in FIG. 4, the skew measurement circuit 28 is the same as in FIG. 5, and the delay adjustment circuit 37 is also the same as in FIG.

  The delay adjustment circuit 37 illustrated in FIG. 17 stores the operation state signal from the operation state monitoring circuit 50 in the measurement skew register 370. Then, the CPU reads the delay setting value in the RAM 75 and stores it in the delay setting value register 371 based on the operation state signal. As described above, the CPU reads the delay setting value corresponding to the determination mode and the measured skew data from the RAM 75.

  FIG. 22 is a diagram showing a specific example of the RAM 75. In this specific example, the delay set values shown in the memory configuration example of FIG. 18 are stored in correspondence with the operation state signals Fast, Typical, Slow. Moreover, the delay setting values in the case of Typical and Fast are doubled and tripled, respectively, as compared with the case where the operation state is Slow. As a result, the target skews having the same length can be generated in the signals A and B regardless of the operating state.

[Second Embodiment]
FIG. 23 is a diagram of a skew adjustment circuit according to the second embodiment. The skew adjustment circuit according to the second embodiment measures the signal skew of the N signal lines SL_A to SL_N, and sets the delay amount of the delay circuits DL_A to DL_N provided in each signal line so as to achieve the target skew. adjust.

  Therefore, the skew adjustment circuit 10 measures the skew between the signal lines SL_A and SL_B, between SL_A and SL_C, and between SL_A and other signals SL_K (K = D to N) using the selector 26 and the skew measurement circuit 28. To have N-1 pieces. The delay adjustment circuit 38 has a delay setting value calculation circuit 381 that reads a target skew corresponding to the signal combination to be adjusted from the ROM 45 and calculates a delay setting value from the measured skew and the target skew. Further, the delay adjustment circuit 38 has a ROM access contention control circuit 382 that performs read control in a round robin manner so that access contention does not occur in order to sequentially read the target skew between the N signals from the ROM 45.

  A case will be described as an example in which skew adjustment is performed for the four signal lines SL_A, B, C, and D. Since there are four signal lines, three sets of selectors 26 and skew measurement circuits 28 are required. Each selector 26 and skew measurement circuit 28 measure the skew between signals A and B, between signals A and C, and between signals A and D. The delay set value calculation circuit 381 in the delay adjustment circuit 38 specifies which signal has the latest timing from the measurement skew. This can be easily identified from the measurement skew between the signals A and B, between the signals A and C, and between the signals A and D and whether the determination is the first time or the second time.

  The ROM 45 stores target skew data for the four signals A, B, C, and D. However, the target skew data is the target skew data when the signal A is the earliest, the signal B is the earliest, the signal C is the earliest, and the signal D is the earliest. Therefore, the delay set value calculation circuit 381 reads out the target skew data from the ROM 45 that makes the signal of the latest timing detected from the measurement skew the earliest. Then, the delay set value calculation circuit 381 reads the timing relationship of the signals A, B, C, D obtained from the measurement skew between the signals A, B, between the signals A, C, and between the signals A, D from the ROM 45. The delay amount of each signal necessary for adjusting to the target skew is calculated, and the delay amount to be adjusted is set in the delay setting register (373 in FIG. 17) as a delay setting value.

  FIG. 24 is a diagram showing a specific example of the ROM 45. The address of the ROM 45 is the signal group Gr that operates simultaneously, the signal combination, and the slowest signal (latest) detected from the measurement skew. On the other hand, the data in the ROM 45 is a target skew between signals that makes the slowest signal the earliest timing. Although only the slowest signal A is shown in FIG. 24, the actual data indicates the target skew between the signals for each of the four cases A, B, C, and D that are the slowest signals. It is necessary to have.

  FIG. 25 is a diagram showing the calculation 1 of the delay set value calculation circuit 381 in the present embodiment. Calculation 1 detects the order of signals on the four signal lines from the determination mode and the measurement skew. There are theoretically 24 orders of the four signals, but FIG. 35 shows 16 orders. For example, (a) is a case where the determination mode is 1st-1st-1st, and in this case, it can be detected that the signal A is the slowest. Furthermore, the order of the other signals B, C, D can be detected by comparing the measurement skews. The same applies to the cases (b), (c), and (d).

  FIG. 26, FIG. 27, and FIG. 28 are diagrams showing the calculation 2 of the delay set value calculation circuit 381 in the present embodiment. Calculation 2 calculates the delay amount to be inserted into each signal so that the slowest signal detected from the measurement result becomes the target skew that makes the earliest. Since the timing relationship of the four signals is known from the measurement skew, the slowest signal among the four signals is made the fastest signal at the target skew. In this case, the adjustment delay amount is set to zero for the slowest signal, and the necessary adjustment delay amount can be easily calculated so that the remaining signal has the target skew.

  26, 27, and 28 show examples of the calculation. (1) in FIG. 26 shows an arithmetic expression for obtaining the delay setting value of each signal when the signal A is the slowest. The signal waveform based on the measurement skew result and the signal waveform based on the target skew are shown on the right side of (1). In this case, the signal A has a set delay value of zero. For the signal B, a delay amount obtained by adding the number of “0” of the measured skew between AB (the amount of delay) and the number of “0” of the target skew between AB is set as the set delay value. For the signal C, a delay amount obtained by adding the number of “0” of the measured skew between ACs (delay amount) and the number of “0” of the target skew between ACs is set as a set delay value. For the signal D, a delay amount obtained by adding the number of “0” of the measured skew between ADs (the delay amount) and the number of “0” of the target skew between the ADs is set as a set delay value.

  (2) in FIG. 27 is an example of calculating the delay set value when the signal B is the slowest. Signal B has a set delay value of zero. The delay values to be set for the remaining signals A, C, and D can be obtained from the arithmetic expressions in the figure.

  First, for the signal A, a delay amount obtained by adding the number of “0” of the target skew between AB to the number of “0” of the measured skew between AB is set as a set delay value. For the signal C, it is necessary to properly use two types of arithmetic expressions depending on the skew relationship between the signals A and C. When the signal A is later than the signal C, add the number of measurement skews “0” between ACs to the number of measurement skews “0” between ABs, and further add the target skew “0” between BCs. The delay amount obtained by adding the numbers is set as the set delay value. Conversely, when signal A is earlier than signal C, the number of measurement skews between ACs is subtracted from the number of measurement skews between ABs and the target skew between BCs is “0”. The delay amount obtained by adding the number of is set delay value. Similarly, for signal D, it is necessary to use two types of arithmetic expressions depending on the skew relationship between signals A and D. When the signal A is later than the signal D, the number of “0” of the measurement skew between AD is added to the number of “0” of the measurement skew between AB, and further, the target skew of “0” of the target skew between BDs The delay amount obtained by adding the numbers is set as the set delay value. Conversely, when the signal A is earlier than the signal D, the number of measurement skews “0” between ADs is subtracted from the number of measurement skews “0” between ABs, and the target skew between BDs is “0”. The delay amount obtained by adding the number of is set delay value.

  Even when the signal C of (3) in FIG. 28 is the slowest and when the signal D of (4) is the slowest, the delay value to be set can be obtained by the same arithmetic expression as in (2) of FIG.

[Second Embodiment (2)]
FIG. 29 is a diagram illustrating a first modification of the skew adjustment circuit according to the second embodiment. 23 differs from the skew adjustment circuit 10 of FIG. 23 in that it has an operation state monitoring circuit 50, and that the target skew value ROM 45 has an operation state monitoring circuit 50 in addition to the skew adjustment target signal group Gr and the latest signal and signal combination. The target skew value corresponding to the operation speed detected by is stored. The delay circuit is the same as in FIG. 11, the selector 26 is the same as in FIG. 4, the skew measurement circuit 28 is the same as in FIG. 5, and the delay adjustment circuit 38 is the same as in FIGS.

  FIG. 30 is a diagram of a specific example of the target skew value ROM 45. In the ROM 45, operation state signals Fast, Typical, and Slow are added in addition to the addresses shown in FIG. In the setting of the target skew with respect to the operation state, the number of zero target skews is smaller in the operation state Slow and the number of zero target skews is larger in the operation state Fast as in FIG.

[Second Embodiment (3)]
FIG. 31 is a diagram illustrating a second modification of the skew adjustment circuit according to the second embodiment. In the skew adjustment circuit 10, the CPU reads RAM data outside or inside the LSI and stores it in the target skew register 383 in the delay adjustment circuit 39 via the CPU interface 62. Further, the skew and discrimination mode data measured by the skew measurement circuit 28 are stored in the measurement skew register 384. These registers 383 and 384 are provided for the number N-1 of data combinations.

  From the selector 26 and the skew measurement circuit 28, N−1 determination modes and measurement skews are stored in the measurement skew register 384. When stored, the skew valid bit in the register is set to “1” as shown in FIG. The CPU constantly monitors the skew effective bit, and when the skew effective bit becomes “1”, reads the target skew data corresponding to the slowest signal detected by the calculation 1 of the delay setting value calculation circuit 381 from the RAM 45. , And stored in the target skew register 383, the delay switching on bit is set to “1” as shown in FIG.

  When the delay switching on bit is set to “1”, the delay set value calculation circuit 381 determines the skew relationship of the current signals A, B, C, and D obtained from the measurement skew and the determination mode according to the target skew. The set delay value of each signal necessary for making the skew relationship of the signals A, B, C, and D is calculated. The calculated set delay value is set in a delay setting register belonging to each delay circuit. When this setting is made, the skew valid bit is reset to “0”.

[Second Embodiment (4)]
FIG. 32 is a diagram illustrating a third modification of the skew adjustment circuit according to the second embodiment. This skew adjustment circuit 10 is different from FIG. 31 in that it has an operation state monitoring circuit 50 and a target skew corresponding to the operation state is stored in the RAM 45 accordingly. Other configurations and operations are the same as those of the second modified example of FIG.

  As described above, according to the second embodiment, the skew of N-1 combinations is measured for the signals of N signal lines to be skew-adjusted, and each signal line is set so as to be the target skew in the memory. A delay amount to be inserted can be obtained by calculation, and a target skew can be generated for signal changes of N signal lines. Thereby, simultaneous switching noise generated when the output buffers are simultaneously switched can be reduced.

  The above embodiment is summarized as follows.

(Appendix 1)
First and second signal lines that propagate the first and second signals, respectively, and first and second signals that receive the first and second signals that propagate through the first and second signal lines, respectively. A skew adjustment circuit provided in an integrated circuit having a buffer circuit of
First and second delay circuits respectively provided in front stages of the first and second buffer circuits;
A skew measuring circuit for measuring a skew between the first and second signals;
A delay adjustment circuit that determines a delay amount of the first and second delay circuits based on the measured skew measured by the skew measurement circuit, and sets the determined delay amounts in the first and second delay circuits; A skew adjustment circuit.

(Appendix 2)
In Appendix 1,
The delay adjustment circuit determines a difference between a target skew and the measurement skew between the first and second signals as a delay amount of the first or second delay circuit.

(Appendix 3)
In Appendix 1 or 2,
And a memory for storing a target skew between the first and second signals,
The delay adjustment circuit reads the target skew with reference to the memory, and determines a difference between the measured skew and the target skew as a delay amount of the first or second delay circuit.

(Appendix 4)
In Appendix 1 or 2,
The delay adjustment circuit sets a set delay amount for generating a target skew between the first and second signals in correspondence with the measured skew and data indicating which of the first and second signals is faster. A skew adjusting circuit that sets the set delay amount read from the memory in the first and second delay circuits.

(Appendix 5)
In Appendix 1 or 2,
The skew measuring circuit includes: a plurality of latch circuits that input one of the first and second signals as data; and the plurality of latch circuits that are used as a clock while delaying the other of the first and second signals. A clock supply circuit for input to the latch circuit,
And a skew adjusting circuit having a selector for selecting the first and second signals as the data and the clock and outputting the selected data and clock to the skew measuring circuit.

(Appendix 6)
In Appendix 5,
The selector detects that the data input is earlier than the clock input when the first and second signals are respectively selected as the data and the clock and output to the skew measurement circuit. In this case, a skew adjustment circuit that selects the first and second signals as the clock and data, respectively, and outputs them to the skew measurement circuit.

(Appendix 7)
First to Nth signal lines that propagate the first to Nth signals, respectively, and the first to Nth signals that receive the first to Nth signals that propagate to the first to Nth signal lines, respectively. A skew adjustment circuit provided in an integrated circuit having a buffer circuit of
First to Nth delay circuits respectively provided in front of the first to Nth buffer circuits;
A skew measuring circuit for measuring a skew between the first and second signals to the first and Nth signals;
A delay adjustment circuit that determines a delay amount of the first to N-th delay circuits based on the measured skew measured by the skew measurement circuit, and sets the determined delay amounts in the first to N-th delay circuits; A skew adjustment circuit.

(Appendix 8)
In Appendix 7,
The delay adjustment circuit detects a signal having the latest timing among the first to N-th signals from the measurement skew, and sets the detected latest timing signal to a target skew having the earliest timing. A skew adjustment circuit for determining a delay amount to be set in the first to Nth delay circuits.

(Appendix 9)
In Appendix 8,
And a memory for storing a target skew corresponding to each of the first to Nth signals, which makes the signal the earliest timing,
The delay adjustment circuit is a skew adjustment circuit that reads the target skew corresponding to the detected signal of the latest timing with reference to the memory.

(Appendix 10)
In Appendix 9,
The skew adjustment circuit is a rewritable memory.

(Appendix 11)
In any one of Supplementary Notes 1, 2, 7, and 8,
And an operation state monitoring circuit for monitoring an operation state of the gate in the integrated circuit device,
The delay adjustment circuit is a skew adjustment circuit that determines the delay amount according to the operation state detected by the operation state monitoring circuit.

(Appendix 12)
In any one of appendices 1-11,
Skew adjustment having a control enable signal for controlling operation enable and operation disable of the monitoring circuit and the delay adjustment circuit, and controlling the start and stop of the operation of the monitoring circuit and the delay adjustment circuit according to the control enable signal circuit.

(Appendix 13)
In Appendix 4 or 5,
A skew adjustment circuit in which the memory is rewritable and the target skew or set delay amount is rewritten.

(Appendix 14)
First and second signal lines that propagate the first and second signals, respectively, and first and second signals that receive the first and second signals that propagate through the first and second signal lines, respectively. The first and second buffer circuits, the third and fourth buffer circuits to which the third signal is input, and the third signal input to the third and fourth buffer circuits. A skew adjustment circuit provided in an integrated circuit having third and fourth signal lines having the same length as the signal line of
First and second delay circuits respectively provided in front stages of the first and second buffer circuits;
A skew measuring circuit for measuring a skew between the third signals propagated through the third and fourth signal lines;
A delay adjustment circuit that determines a delay amount of the first and second delay circuits based on the measured skew measured by the skew measurement circuit, and sets the determined delay amounts in the first and second delay circuits; A skew adjustment circuit.

(Appendix 15)
First and second signal lines that propagate the first and second signals, respectively, and first and second signals that receive the first and second signals that propagate through the first and second signal lines, respectively. A method for adjusting the skew of an integrated circuit having a buffer circuit of
Measuring a skew between the first and second signals;
Based on the measured measurement skew, the delay amounts of the first and second delay circuits provided in the previous stage of the first and second buffer circuits are determined, and the determined delay amounts are determined as the first and second delay circuits. A skew adjustment method set in the second delay circuit.

(Appendix 16)
In Appendix 15,
A skew adjustment method for determining a difference between the target skew and the measurement skew between the first and second signals as a delay amount of the first or second delay circuit.

(Appendix 17)
First to Nth signal lines that propagate the first to Nth signals, respectively, and the first to Nth signals that receive the first to Nth signals that propagate to the first to Nth signal lines, respectively. A skew adjustment method provided in an integrated circuit having a buffer circuit of
Measuring the skew between the first and second signals to the first and Nth signals, respectively;
Based on the measured measurement skew, a delay amount of first to N-th delay circuits provided in a preceding stage of the first to N-th buffer circuits is determined, and the determined delay amount is set to the first to first delay circuits. A skew adjustment method set in the Nth delay circuit.

(Appendix 18)
In Appendix 17,
The signal having the latest timing among the first to N-th signals is detected from the measurement skew, and the first to N-th signals are set so that the detected latest timing signal has the earliest timing. A skew adjustment method for determining a delay amount to be set in a delay circuit.

10: Skew adjustment circuit 25: Signal change monitoring circuit
35, 37: Delay adjustment circuit 45: Delay amount ROM
DL_0 to DL_7: Delay circuit OB_0 to OB_7: Output buffer
SL_0 to SL_7: Signal line SG_0 to SG_7: Signal

Claims (10)

First and second signal lines that propagate the first and second signals, respectively, and first and second signals that receive the first and second signals that propagate through the first and second signal lines, respectively. A skew adjustment circuit provided in an integrated circuit having a buffer circuit of
First and second delay circuits respectively provided in front stages of the first and second buffer circuits;
A skew measuring circuit for measuring a skew between the first and second signals;
A delay adjustment circuit that determines a delay amount of the first and second delay circuits based on the measured skew measured by the skew measurement circuit, and sets the determined delay amounts in the first and second delay circuits; A skew adjustment circuit. In claim 1,
The delay adjustment circuit determines a difference between a target skew and the measurement skew between the first and second signals as a delay amount of the first or second delay circuit. In claim 1 or 2,
And a memory for storing a target skew between the first and second signals,
The delay adjustment circuit reads the target skew with reference to the memory, and determines a difference between the measured skew and the target skew as a delay amount of the first or second delay circuit. In claim 1 or 2,
The delay adjustment circuit sets a set delay amount for generating a target skew between the first and second signals in correspondence with the measured skew and data indicating which of the first and second signals is faster. A skew adjusting circuit that sets the set delay amount read from the memory in the first and second delay circuits. In claim 1 or 2,
The skew measuring circuit includes: a plurality of latch circuits that input one of the first and second signals as data; and the plurality of latch circuits that are used as a clock while delaying the other of the first and second signals. A clock supply circuit for input to the latch circuit,
And a skew adjusting circuit having a selector for selecting the first and second signals as the data and the clock and outputting the selected data and clock to the skew measuring circuit. First to Nth signal lines that propagate the first to Nth signals, respectively, and the first to Nth signals that receive the first to Nth signals that propagate to the first to Nth signal lines, respectively. A skew adjustment circuit provided in an integrated circuit having a buffer circuit of
First to Nth delay circuits respectively provided in front of the first to Nth buffer circuits;
A skew measuring circuit for measuring a skew between the first and second signals to the first and Nth signals;
A delay adjustment circuit that determines a delay amount of the first to N-th delay circuits based on the measured skew measured by the skew measurement circuit, and sets the determined delay amounts in the first to N-th delay circuits; A skew adjustment circuit. In claim 6,
The delay adjustment circuit detects a signal having the latest timing among the first to N-th signals from the measurement skew, and sets the detected latest timing signal to a target skew having the earliest timing. A skew adjustment circuit for determining a delay amount to be set in the first to Nth delay circuits. In claim 7,
And a memory for storing a target skew corresponding to each of the first to Nth signals, which makes the signal the earliest timing,
The delay adjustment circuit is a skew adjustment circuit that reads the target skew corresponding to the detected signal of the latest timing with reference to the memory. In any one of Claims 1, 2, 6, and 7,
And an operation state monitoring circuit for monitoring an operation state of the gate in the integrated circuit device,
The delay adjustment circuit is a skew adjustment circuit that determines the delay amount according to the operation state detected by the operation state monitoring circuit. First and second signal lines that propagate the first and second signals, respectively, and first and second signals that receive the first and second signals that propagate through the first and second signal lines, respectively. The first and second buffer circuits, the third and fourth buffer circuits to which the third signal is input, and the third signal input to the third and fourth buffer circuits. A skew adjustment circuit provided in an integrated circuit having third and fourth signal lines having the same length as the signal line of
First and second delay circuits respectively provided in front stages of the first and second buffer circuits;
A skew measuring circuit for measuring a skew between the third signals propagated through the third and fourth signal lines;
A delay adjustment circuit that determines a delay amount of the first and second delay circuits based on the measured skew measured by the skew measurement circuit, and sets the determined delay amounts in the first and second delay circuits; A skew adjustment circuit.

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