JP2012039091A - Substrate coining electrical inspection device - Google Patents
Substrate coining electrical inspection device Download PDFInfo
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- JP2012039091A JP2012039091A JP2011140932A JP2011140932A JP2012039091A JP 2012039091 A JP2012039091 A JP 2012039091A JP 2011140932 A JP2011140932 A JP 2011140932A JP 2011140932 A JP2011140932 A JP 2011140932A JP 2012039091 A JP2012039091 A JP 2012039091A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
- G01R31/2808—Holding, conveying or contacting devices, e.g. test adapters, edge connectors, extender boards
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
Abstract
Description
本発明は、基板のコイニング電気検査装置に関する。 The present invention relates to a substrate coining electrical inspection apparatus.
一般に、プリント基板（ＰＣＢ）は、様々な電子製品素子を一定の型に沿って簡便に連結させる役割を果たし、デジタルＴＶを始めとした家電製品から先端通信機器まで全ての電子製品に広範囲に使用される部品であって、用途に応じて汎用プリント基板やモジュール用プリント基板、パッケージ用プリント基板などに分類される。 In general, printed circuit boards (PCBs) serve to easily connect various electronic product elements along a certain mold, and are used in a wide range of electronic products from home appliances such as digital TV to advanced communication devices. The components are classified into general-purpose printed circuit boards, module printed circuit boards, package printed circuit boards, and the like according to the application.
最近では、半導体チップの高密度化および信号伝達速度の高速化に対応するための技術であって、半導体チップをプリント基板に直接実装する技術に対する要求が大きくなっており、これにより半導体チップの高密度化に対応できる高密度および高信頼性のプリント基板に対する開発が要求されている。このような仕様に対応して微細回路パターンおよびマイクロビアホールを形成することが可能なプリント基板技術が要求されており、プリント基板製造の生産性を向上させるために、プリント基板を自動製造する装置に関する研究が行われている。 Recently, there is an increasing demand for a technology for dealing with higher density of semiconductor chips and higher signal transmission speed, and for mounting semiconductor chips directly on a printed circuit board. There is a demand for development of high-density and high-reliability printed circuit boards that can cope with higher density. There is a demand for a printed circuit board technology capable of forming a fine circuit pattern and a micro via hole corresponding to such a specification, and relates to an apparatus for automatically manufacturing a printed circuit board in order to improve the productivity of printed circuit board manufacturing. Research is underway.
一般に、プリント基板は、多数の絶縁層と回路層を含み、最外層には半田レジスト層が形成される。この際、半田レジスト層には最外層回路層のパッド部を露出させる開口部が形成され、開口部には半田ボールが形成されることにより、基板と外部素子とを連結する。この際、半田ボールの高さを平坦化するためにコイニング（ｃｏｉｎｉｎｇ）工程を行い、プリント基板の回路連結に対する電気検査を行うことにより、プリント基板を製品化している。 Generally, a printed circuit board includes a large number of insulating layers and circuit layers, and a solder resist layer is formed as the outermost layer. At this time, an opening for exposing the pad portion of the outermost circuit layer is formed in the solder resist layer, and a solder ball is formed in the opening to connect the substrate and the external element. At this time, a coining process is performed in order to flatten the height of the solder ball, and an electrical inspection is performed on the circuit connection of the printed circuit board, thereby commercializing the printed circuit board.
図１は、従来の技術に係る基板のコイニング装置１０を示す断面図、図２は、従来の技術に係る基板の電気検査装置２０を示す断面図である。 FIG. 1 is a sectional view showing a substrate coining apparatus 10 according to the prior art, and FIG. 2 is a sectional view showing a substrate electrical inspection apparatus 20 according to the prior art.
以下、これらの図面を参照して、従来の技術に係る基板のコイニング装置１０および基板の電気検査装置２０を説明する。 Hereinafter, a substrate coining apparatus 10 and a substrate electrical inspection apparatus 20 according to the related art will be described with reference to these drawings.
図１に示すように、従来の基板のコイニング装置１０は、コインヘッド１１を含む。ここで、コインヘッド１１は、圧力が加えられ、基板３０に形成された半田ボール３１を平坦化させる。 As shown in FIG. 1, a conventional substrate coining apparatus 10 includes a coin head 11. Here, the coin head 11 is pressed to flatten the solder balls 31 formed on the substrate 30.
一方、基板のコイニング装置１０によって半田ボール３１のコイニング工程が完了すると、基板３０を基板の電気検査装置２０に投入する。 On the other hand, when the coining process of the solder balls 31 is completed by the substrate coining device 10, the substrate 30 is loaded into the substrate electrical inspection device 20.
図２に示すように、従来の基板の電気検査装置２０はピン２１と治具２２を含む。ここで、ピン２１は、半田ボール３１に直接接触して基板３０に対する電気検査を行い、治具２２は、多数のピン２１を連結し支持する役割を行う。 As shown in FIG. 2, the conventional board electrical inspection apparatus 20 includes a pin 21 and a jig 22. Here, the pins 21 are in direct contact with the solder balls 31 to perform electrical inspection on the substrate 30, and the jig 22 serves to connect and support a large number of pins 21.
ところが、従来の技術に係る基板のコイニング装置１０および基板の電気検査装置２０は、それぞれ別個の装置からなり、互いに異なる工程を行うので、装置間の基板３０の移送などにより、生産性が低下し且つ製造時間が長くなるという問題点があった。また、２種の装置を共に備えなければならないので、基板３０の製造の際に、製造コストが高いという問題点があった。 However, the substrate coining device 10 and the substrate electrical inspection device 20 according to the prior art are composed of separate devices, and perform different processes. Therefore, productivity is reduced due to transfer of the substrate 30 between the devices. In addition, there is a problem that the manufacturing time becomes long. In addition, since both types of apparatuses must be provided, there is a problem in that the manufacturing cost is high when the substrate 30 is manufactured.
また、基板の電気検査装置２０において、ピン２１が半田ボール３１に接触する場合、相対的に強度の弱い半田ボール３１にピン２１の接触圧力によるピン押痕部３２が発生するという問題点があった。これにより、半田ボール３１に外部素子（図示せず）が連結される場合、ピン押痕部３２によって接続不良が発生するという問題点があった。 Further, in the board electrical inspection apparatus 20, when the pin 21 comes into contact with the solder ball 31, there is a problem that the pin indentation portion 32 due to the contact pressure of the pin 21 is generated in the solder ball 31 having relatively low strength. It was. As a result, when an external element (not shown) is coupled to the solder ball 31, there is a problem that a connection failure occurs due to the pin imprint portion 32.
本発明は、上述した従来の技術の問題点を解決するためのもので、その目的は、基板のコイニング工程と電気検査工程を一つの装置で実現する基板のコイニング電気検査装置を提供することにある。 SUMMARY OF THE INVENTION The present invention is to solve the above-described problems of the prior art, and an object of the present invention is to provide a substrate coining electrical inspection apparatus that realizes the substrate coining process and electrical inspection process with a single apparatus. is there.
本発明の他の目的は、基板の電気検査の際にピンの接触圧力によるピン押痕部の発生現象を防止する基板のコイニング電気検査装置を提供することにある。 Another object of the present invention is to provide a coining electrical inspection apparatus for a substrate that prevents the occurrence of pin imprints due to the contact pressure of the pins during electrical inspection of the substrate.
上記目的を達成するために、本発明の好適な実施例に係る基板のコイニング電気検査装置は、基板に形成されたバンプをコイニングする貫通孔付きヘッド部と、前記貫通孔に挿入されて前記ヘッド部と共に前記バンプをコイニングし、前記バンプに接触して前記基板を電気検査するピン部とを含んでなることを特徴とする。 In order to achieve the above object, a coining electrical inspection apparatus for a substrate according to a preferred embodiment of the present invention includes a head portion with a through hole for coining a bump formed on the substrate, and the head inserted into the through hole. And a pin portion for coining the bump together with the portion and for inspecting the substrate in contact with the bump.
ここで、前記ヘッド部が前記バンプに接触する面と、前記ピン部が前記バンプに接触する面とは同じ平面上にあることを特徴とする。 Here, the surface where the head portion contacts the bump and the surface where the pin portion contacts the bump are on the same plane.
また、前記ヘッド部には、多数の前記貫通孔が互いに離隔して設けられたことを特徴とする。 Further, the head portion is provided with a large number of the through holes spaced apart from each other.
また、前記ヘッド部および前記ピン部は、前記基板の両面に位置したことを特徴とする。 The head part and the pin part are located on both sides of the substrate.
また、前記ヘッド部は不導体であり、前記ピン部は導体であることを特徴とする。 Further, the head part is a non-conductor, and the pin part is a conductor.
また、前記ヘッド部は、前記バンプに接触して前記バンプをコイニングするコイニング部、および前記コイニング部同士を連結する連結部を含むことを特徴とする。 The head portion may include a coining portion that contacts the bump and coins the bump, and a connecting portion that connects the coining portions to each other.
また、前記コイニング部が前記バンプに接触する面と、前記連結部の一面とは、同じ平面上にあることを特徴とする。 The surface where the coining portion contacts the bump and the one surface of the connecting portion are on the same plane.
また、前記ヘッド部および前記ピン部による前記バンプのコイニングと、前記ピン部による前記基板の電気検査とは、同時に行われることを特徴とする。 In addition, coining of the bump by the head portion and the pin portion and electrical inspection of the substrate by the pin portion are performed at the same time.
本発明に係る基板のコイニング電気検査装置は、ヘッド部、およびヘッド部の貫通孔に挿入されたピン部を基板のバンプに接触させてコイニング工程を行うと同時に、バンプに接触したピン部を介して基板の電気検査を行うことにより、コイニング工程と電気検査工程を一つの装置で同時に行うことができるため、基板の生産性が向上し且つ基板の製造時間および製造コストが節減されるという利点がある。 The coining electrical inspection apparatus for a substrate according to the present invention performs a coining process by bringing a head portion and a pin portion inserted into a through hole of the head portion into contact with a bump of the substrate, and at the same time via a pin portion in contact with the bump. By performing the electrical inspection of the substrate, the coining process and the electrical inspection process can be performed at the same time with one apparatus, so that the productivity of the substrate is improved and the manufacturing time and manufacturing cost of the substrate are reduced. is there.
また、本発明によれば、ピン部がバンプに当接する面と、ヘッド部がバンプに当接する面とを面一にすることにより、バンプに現れるピン押痕部の発生現象を防止するという利点がある。 In addition, according to the present invention, the surface where the pin portion abuts against the bump and the surface where the head portion abuts against the bump are flush with each other, thereby preventing the occurrence of pin imprints appearing on the bump. There is.
更に、本発明によれば、コイニング部および連結部を含むヘッド部において、コイニング部がバンプに当接する面を連結部の一面と面一にすることにより、アラインメントがずれてもバンプが接触する面に段差がないため、バンプへの段差による押痕現象を防止しないという利点がある。 Furthermore, according to the present invention, in the head portion including the coining portion and the coupling portion, the surface where the coining portion abuts against the bump is flush with the surface of the coupling portion, so that the bump contacts even if the alignment is shifted. Since there is no level difference, there is an advantage that the impression phenomenon due to the level difference on the bump is not prevented.
本発明の目的、特定の利点および新規の特徴は、添付図面に連関する以下の詳細な説明と好適な実施例からさらに明白になるであろう。 Objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and preferred embodiments when taken in conjunction with the accompanying drawings.
これに先立ち、本明細書および請求の範囲に使用された用語または単語は、通常的で辞典的な意味で解釈されてはならず、発明者が自分の発明を最善の方法で説明するために用語の概念を適切に定義することができるという原則に基づき、本発明の技術的思想に符合する意味と概念で解釈されなければならない。 Prior to this, terms or words used in the specification and claims should not be construed in a normal and lexical sense, so that the inventor best describes the invention. Based on the principle that the concept of terms can be appropriately defined, it should be interpreted with a meaning and concept consistent with the technical idea of the present invention.
本発明において、各図面の構成要素に参照番号を付加するにおいて、同一の構成要素については、他の図面上に表示されても、出来る限り同一の番号を付することに留意すべきであろう。なお、本発明を説明するにおいて、関連した公知の技術に対する具体的な説明が本発明の要旨を無駄に乱すおそれがあると判断される場合、その詳細な説明は省略する。 In the present invention, it is to be noted that when reference numerals are added to components in each drawing, the same components are given the same numbers as much as possible even if they are displayed on other drawings. . In the description of the present invention, when it is determined that there is a possibility that a specific description of a related known technique may unnecessarily disturb the gist of the present invention, a detailed description thereof will be omitted.
以下、添付図面を参照して、本発明の好適な実施例を詳細に説明する。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
（基板のコイニング電気検査装置）
図３は、本発明の好適な実施例に係る基板のコイニング電気検査装置１００を示す断面図である。
(Coining electrical inspection equipment for substrates)
FIG. 3 is a cross-sectional view illustrating a substrate coining electrical inspection apparatus 100 according to a preferred embodiment of the present invention.
以下、図３を参照して、本実施例に係る基板のコイニング電気検査装置１００を説明する。 Hereinafter, the substrate coining electrical inspection apparatus 100 according to the present embodiment will be described with reference to FIG.
図３に示すように、本実施例に係る基板のコイニング電気検査装置１００は、バンプ１３１をコイニングするヘッド部１１０、およびバンプ１３１をコイニングし且つ基板１３０を電気検査するピン部１２０を含む。 As shown in FIG. 3, the substrate coining electrical inspection apparatus 100 according to the present embodiment includes a head unit 110 coining the bump 131 and a pin unit 120 coining the bump 131 and electrically testing the substrate 130.
一方、本実施例では、ヘッド部１１０およびピン部１２０が基板１３０の一面に形成されたと説明するが、本発明は、これに限定されず、基板１３０の両面に位置する場合も含むことを予め明かしておく。 On the other hand, in this embodiment, it is described that the head part 110 and the pin part 120 are formed on one surface of the substrate 130. However, the present invention is not limited to this and includes cases where the head portion 110 and the pin portion 120 are located on both surfaces of the substrate 130 in advance. I will make it clear.
ヘッド部１１０は、基板１３０に形成されたバンプ１３１をコイニングする部材である。 The head unit 110 is a member that coins the bumps 131 formed on the substrate 130.
ここで、ヘッド部１１０は、基板１３０の一面または両面に形成されたバンプ１３１をコイニングする部分であって、バンプ１３１に接触しているヘッド部１１０に圧力が加えられると、バンプ１３１の上面が平坦になり、多数のバンプ１３１の高さが均一になれる。この際、ヘッド部１１０には、圧力を加える別途の駆動部（図示せず）が設置できる。 Here, the head part 110 is a part coining a bump 131 formed on one or both surfaces of the substrate 130. When pressure is applied to the head part 110 in contact with the bump 131, the upper surface of the bump 131 is changed. It becomes flat and the height of many bumps 131 can be made uniform. At this time, the head unit 110 may be provided with a separate driving unit (not shown) for applying pressure.
また、ヘッド部１１０は、コイニング部１１２および連結部１１３を含むことができる。 In addition, the head unit 110 may include a coining unit 112 and a connecting unit 113.
ここで、コイニング部１１２は、バンプ１３１に直接接触してバンプ１３１をコイニングするヘッド部１１０の部分であり、連結部１１３は、多数のコイニング部１１２を連結するヘッド部１１０の部分である。また、コイニング部１１２がバンプ１３１に接触する面は、連結部１１３の一面と面一にすることができる。すなわち、コイニング部１１２と連結部１１３とは同一の高さを有するため、ヘッド部１１０がバンプ１３１に接触する面には段差が形成されない。よって、バンプ１３１に接触する面に段差が形成されないため、段差による押痕部の発生現象が防止できる。 Here, the coining portion 112 is a portion of the head portion 110 that directly contacts the bump 131 and coins the bump 131, and the connecting portion 113 is a portion of the head portion 110 that connects a large number of coining portions 112. Further, the surface of the coining portion 112 that contacts the bump 131 can be flush with the one surface of the connecting portion 113. That is, since the coining part 112 and the connection part 113 have the same height, no step is formed on the surface where the head part 110 contacts the bump 131. Therefore, since no step is formed on the surface that contacts the bump 131, the occurrence of a dent portion due to the step can be prevented.
具体的に、バンプ１３１のコイニング工程および電気検査工程を行うとき、アラインメントの誤りによるヘッド部１１０のコイニング部１１２の一部分のみがバンプ１３１上に位置でき、このような場合、ヘッド部１１０に段差が形成されると、段差によるバンプ１３１が損傷するおそれがある。ところが、本実施例のように、コイニング部１１２と連結部１１３が同じ平面上にあるため段差が形成されない場合には、アラインメントがずれてもバンプ１３１の損傷を防止することができる。 Specifically, when performing the coining process and the electrical inspection process of the bump 131, only a part of the coining part 112 of the head part 110 due to an alignment error can be positioned on the bump 131. In such a case, there is a step in the head part 110. If formed, the bump 131 due to the step may be damaged. However, as in this embodiment, since the coining portion 112 and the connecting portion 113 are on the same plane, if the step is not formed, damage to the bump 131 can be prevented even if the alignment is shifted.
一方、ヘッド部１１０のコイニング部１１２には、両面を貫通する貫通孔１１１が設けられる。貫通孔１１１には、ピン部１２０が挿入され、貫通孔１１１は、多数が離隔して設けられてもよい。 On the other hand, the coining part 112 of the head part 110 is provided with a through hole 111 penetrating both surfaces. The pin portion 120 may be inserted into the through hole 111, and a large number of the through holes 111 may be provided apart from each other.
ピン部１２０は、ヘッド部１１０と共にバンプ１３１のコイニング工程を行い、同時に基板１３０の電気検査工程を行う部材である。 The pin part 120 is a member that performs a coining process of the bump 131 together with the head part 110 and simultaneously performs an electrical inspection process of the substrate 130.
ここで、ピン部１２０は、ヘッド部１１０に設けられた貫通孔１１１に挿入できる。この際、ピン部１２０が貫通孔１１１に挿入されてバンプ１３１と接触する面は、ヘッド部１１０がバンプ１３１に接触する面と面一にすることができる。よって、ピン部１２０が挿入されたヘッド部１１０は、一体としてバンプ１３１と接触してバンプ１３１のコイニングを行うことができ、バンプ１３１と接触する面には段差が形成されないため、バンプ１３１に現れるピン押痕部の発生現象を防止することができる。したがって、後でバンプ１３１が外部素子（図示せず）と接続しても、バンプ１３１の押痕部による接続不良現象が減少できる。 Here, the pin portion 120 can be inserted into the through hole 111 provided in the head portion 110. At this time, the surface where the pin portion 120 is inserted into the through hole 111 and contacts the bump 131 can be flush with the surface where the head portion 110 contacts the bump 131. Therefore, the head part 110 into which the pin part 120 is inserted can contact the bump 131 as a whole to perform coining of the bump 131, and no step is formed on the surface in contact with the bump 131, so that it appears on the bump 131. It is possible to prevent the occurrence of pin imprints. Therefore, even if the bump 131 is connected to an external element (not shown) later, the connection failure phenomenon due to the bump portion of the bump 131 can be reduced.
一方、ピン部１２０は、ヘッド部１１０の貫通孔１１１に挿入されてバンプ１３１のコイニングを行うと同時に、バンプ１３１に接触した状態で基板１３０に対する電気検査を行う。この際、ピン部１２０は、バンプ１３１に直接接触してバンプ１３１に電気的信号を送信し、これを受信して、基板１３０の回路層１３２およびビア１３３に電気的欠陥がないか否かを検査することができる。また、ピン部１２０が多数の貫通孔１１１にそれぞれ挿入されることにより、基板１３０に設けられた多数のバンプ１３１に対して同時的に電気検査を行うことが可能である。この際、多数のピン部１２０は、それぞれのバンプ１３１上に接触するので、どの回路的ラインに異常があるかその位置を判別することができる。また、ピン部１２０に制御部（図示せず）を連結することにより、制御部（図示せず）は基板１３０に対して正常的に電気的に導通したか否かを判断することができる。 On the other hand, the pin portion 120 is inserted into the through hole 111 of the head portion 110 to perform coining of the bump 131 and at the same time, performs electrical inspection on the substrate 130 in contact with the bump 131. At this time, the pin unit 120 directly contacts the bump 131 and transmits an electrical signal to the bump 131, receives this signal, and determines whether or not the circuit layer 132 and the via 133 of the substrate 130 have an electrical defect. Can be inspected. In addition, by inserting the pin portions 120 into the large number of through-holes 111, it is possible to simultaneously perform electrical inspection on the large number of bumps 131 provided on the substrate 130. At this time, since a large number of pin portions 120 are in contact with the respective bumps 131, it is possible to determine the position of which circuit line is abnormal. In addition, by connecting a control unit (not shown) to the pin unit 120, the control unit (not shown) can determine whether or not the board 130 is normally electrically connected.
また、基板１３０の両面にピン部１２０およびヘッド部１１０が設置された場合には、基板１３０の一面に位置したピン部１２０が電気的信号を送信し、基板１３の他面に位置したピン部１２０が電気的信号を受信することにより、基板１３０の両面に対する電気的導通検査を行うことも可能である。 In addition, when the pin part 120 and the head part 110 are installed on both surfaces of the substrate 130, the pin part 120 located on one surface of the substrate 130 transmits an electrical signal, and the pin part located on the other surface of the substrate 13. It is also possible to perform an electrical continuity test on both surfaces of the substrate 130 when the 120 receives the electrical signal.
一方、ピン部１２０による電気検査が行われるとき、電気的信号がヘッド部１１０に伝達されないように、ヘッド部１１０は不導体、ピン部１２０は導体で形成することが好ましい。 On the other hand, it is preferable that the head portion 110 is formed of a non-conductor and the pin portion 120 is formed of a conductor so that an electrical signal is not transmitted to the head portion 110 when an electrical inspection is performed by the pin portion 120.
基板１３０は、基板のコイニング電気検査装置１００の対象となる部材である。 The substrate 130 is a member that is a target of the coining electrical inspection apparatus 100 for the substrate.
ここで、基板１３０は、例えば、絶縁層１３４および回路層１３２からなる多層または単層のプリント基板であってもよい。絶縁層１３４は、例えば、プリプレグまたはエポキシ樹脂などで構成されてもよく、回路層１３２は、金、銀、銅、ニッケルなどの電気伝導性金属で構成されてもよい。 Here, the substrate 130 may be, for example, a multilayer or single-layer printed circuit board including the insulating layer 134 and the circuit layer 132. The insulating layer 134 may be made of, for example, a prepreg or an epoxy resin, and the circuit layer 132 may be made of an electrically conductive metal such as gold, silver, copper, or nickel.
また、基板１３０の両面の最外層には、最外層回路層１３２のパッド部１３５を露出させる開口部１３７を有する半田レジスト層１３６が形成され、半田レジスト層１３６の開口部１３７を介して外部に突出するバンプ１３１が形成されてもよい。ここで、バンプ１３１は、例えば、半田ボールの形態を有することができ、後で外部素子（図示せず）と基板１３０とを電気的に連結する役割を果たすことができる。 In addition, a solder resist layer 136 having an opening 137 exposing the pad portion 135 of the outermost circuit layer 132 is formed on the outermost layers on both surfaces of the substrate 130, and is exposed to the outside through the opening 137 of the solder resist layer 136. A protruding bump 131 may be formed. Here, the bump 131 may have a form of a solder ball, for example, and may serve to electrically connect an external element (not shown) and the substrate 130 later.
図４〜図６は、図３に示した基板のコイニング電気検査装置１００の作動方式を説明するための断面図である。 4 to 6 are cross-sectional views for explaining an operation method of the coining electrical inspection apparatus 100 shown in FIG.
以下、図４〜図６を参照して、本実施例に係る基板のコイニング電気検査装置１００の作動方式を説明する。 Hereinafter, with reference to FIGS. 4 to 6, an operation method of the coining electrical inspection apparatus 100 for a substrate according to the present embodiment will be described.
まず、図４に示すように、基板のコイニング電気検査装置１００を基板１３０のバンプ１３１が形成された面に準備する。この際、バンプ１３１は、コイニング工程を経る前なので、円形に近い形状を持つことができる。 First, as shown in FIG. 4, the substrate coining electrical inspection apparatus 100 is prepared on the surface of the substrate 130 on which the bump 131 is formed. At this time, since the bump 131 is not subjected to the coining process, it can have a shape close to a circle.
次に、図５に示すように、ピン部１２０の挿入されたヘッド部１１０に圧力を印加して、バンプ１３１のコイニング工程を行うと同時に、ピン部１２０を介して基板１３０の電気検査工程を行う。 Next, as shown in FIG. 5, pressure is applied to the head part 110 in which the pin part 120 is inserted to perform a coining process of the bump 131, and at the same time, an electrical inspection process of the substrate 130 is performed via the pin part 120. Do.
その後、図６に示すように、基板のコイニング電気検査装置１００から基板１３０を搬出すると、基板１３０のバンプ１３１は、コイニングされて平坦な上面を有し、多数のバンプ１３１は、高さが一定になる。また、基板１３０に対する電気検査をコイニング工程と同時に行うことにより、基板１３０を直ちに製品として出庫することができる。 Thereafter, as shown in FIG. 6, when the substrate 130 is unloaded from the coining electrical inspection apparatus 100 for the substrate, the bumps 131 of the substrate 130 are coined and have a flat upper surface, and the bumps 131 have a constant height. become. Further, by performing electrical inspection on the substrate 130 simultaneously with the coining process, the substrate 130 can be immediately delivered as a product.
以上、本発明を具体的な実施例に基づいて詳細に説明したが、これは、本発明を具体的に説明するためのものに過ぎず、本発明による基板のコイニング電気検査装置は、これに限定されないのは言うまでもない。本発明の技術的思想内で、当該分野における通常の知識を有する者によって多様な変形及び改良が可能であることは明白であろう。本発明の単純な変形ないし変更は、いずれも本発明の範疇内に属するもので、本発明の具体的な保護範囲は、特許請求の範囲によって明らかになるであろう。 The present invention has been described in detail on the basis of specific embodiments. However, this is only for concrete description of the present invention, and the substrate coining electrical inspection apparatus according to the present invention includes the above. It goes without saying that it is not limited. It will be apparent that various modifications and improvements can be made by those having ordinary skill in the art within the technical idea of the present invention. Any simple modifications or alterations of the present invention shall fall within the scope of the present invention, and the specific scope of protection of the present invention will be apparent from the claims.
本発明は、基板のコイニング工程と電気検査工程とを一つの装置で実現する基板のコイニング電気検査装置に適用可能である。 The present invention can be applied to a substrate coining electrical inspection apparatus that realizes a substrate coining process and an electrical inspection process with a single apparatus.
１１０ ヘッド部
１１１ 貫通孔
１１２ コイニング部
１１３ 連結部
１２０ ピン部
１３０ 基板
１３１ バンプ
DESCRIPTION OF SYMBOLS 110 Head part 111 Through-hole 112 Coining part 113 Connection part 120 Pin part 130 Board | substrate 131 Bump
Claims (8)
前記貫通孔に挿入されて前記ヘッド部と共に前記バンプをコイニングし、前記バンプに接触して前記基板を電気検査するピン部とを含んでなることを特徴とする基板のコイニング電気検査装置。 Coining a bump formed on the substrate, and a head portion having a through hole;
A coining electrical inspection apparatus for a substrate, comprising: a pin portion that is inserted into the through hole and coins the bump together with the head portion, and contacts the bump to electrically inspect the substrate.
前記バンプに接触して前記バンプをコイニングするコイニング部と、
前記コイニング部同士を連結する連結部とを含むことを特徴とする請求項１に記載の基板のコイニング電気検査装置。 The head portion is
A coining portion that contacts the bump and coins the bump;
The coining electrical inspection apparatus for a substrate according to claim 1, further comprising a connecting part that connects the coining parts.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2010-0076917 | 2010-08-10 | ||
| KR1020100076917A KR20120014752A (en) | 2010-08-10 | 2010-08-10 | Apparatus for coining-electric inspecting of substrate |
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| Publication Number | Publication Date |
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| JP2012039091A true JP2012039091A (en) | 2012-02-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2011140932A Pending JP2012039091A (en) | 2010-08-10 | 2011-06-24 | Substrate coining electrical inspection device |
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| Country | Link |
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| JP (1) | JP2012039091A (en) |
| KR (1) | KR20120014752A (en) |
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| KR101407036B1 (en) * | 2012-12-28 | 2014-06-12 | 삼성전기주식회사 | Apparatus for manufacturing substrate |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000012587A (en) * | 1998-06-26 | 2000-01-14 | Shinko Electric Ind Co Ltd | Electric characteristic inspection and coining method of solder bumps of circuit board for semiconductor chip mounting |
| JP2006525515A (en) * | 2003-05-01 | 2006-11-09 | セレリティー・リサーチ・インコーポレイテッド | BGA package flattening and inspection method and apparatus |
| JP2009130038A (en) * | 2007-11-21 | 2009-06-11 | Kyocer Slc Technologies Corp | Method for manufacturing wiring board |
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2010
- 2010-08-10 KR KR1020100076917A patent/KR20120014752A/en not_active Application Discontinuation
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- 2011-06-24 JP JP2011140932A patent/JP2012039091A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000012587A (en) * | 1998-06-26 | 2000-01-14 | Shinko Electric Ind Co Ltd | Electric characteristic inspection and coining method of solder bumps of circuit board for semiconductor chip mounting |
| JP2006525515A (en) * | 2003-05-01 | 2006-11-09 | セレリティー・リサーチ・インコーポレイテッド | BGA package flattening and inspection method and apparatus |
| JP2009130038A (en) * | 2007-11-21 | 2009-06-11 | Kyocer Slc Technologies Corp | Method for manufacturing wiring board |
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