JP2012038878A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the breakdown voltage of a semiconductor device including a stack in which a lower semiconductor layer, a buried insulating layer, and an upper semiconductor layer are stacked.SOLUTION: A semiconductor device 10 includes an SOI substrate 50 in which a lower semiconductor layer 20, a buried insulating layer 30, and an upper semiconductor layer 40 are stacked. A recess 66 is formed on a part of the surface on which the lower semiconductor layer 20 contacts the buried insulating layer 30. The relative permittivity in the recess 66 is lower than that of the lower semiconductor layer 20.

Description

  The present invention relates to a semiconductor device having a stacked body and a method for manufacturing the same.

  A semiconductor device having a stacked body in which a lower semiconductor layer, a buried insulating layer, and an upper semiconductor layer are stacked has been developed. In this type of semiconductor device, an element structure that exhibits a specific function is formed in the upper semiconductor layer. An example of the element structure includes a lateral diode, a lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a lateral IGBT (Insulated Gate Bipolar Transistor).

  Patent Document 1 discloses a technique for forming a cavity in a part of a buried insulating layer in order to improve the breakdown voltage of this type of semiconductor device. When a cavity is formed in a part of the buried insulating layer, the relative dielectric constant in the cavity is lowered, and the electric field strength in the cavity is increased. Assuming that the voltage borne in the thickness direction is constant, if the electric field strength in the cavity increases, the voltage borne in the cavity increases and the electric field strength in the upper semiconductor layer relatively decreases. Usually, the breakdown voltage of a semiconductor device is often determined based on the voltage when the electric field strength in the upper semiconductor layer exceeds a critical value. For this reason, if the electric field strength in the cavity increases, the electric field strength in the upper semiconductor layer relatively decreases, and as a result, the breakdown voltage of the semiconductor device improves.

JP-A-6-188438

  In the technique disclosed in Patent Document 1, when it is desired to further improve the breakdown voltage of the semiconductor device, it is necessary to increase the thickness of the embedded insulating layer, increase the depth of the cavity formed in the embedded insulating layer, and increase the voltage borne by the cavity. is there. However, when the buried insulating layer is thickened, the stacked body may be damaged after a thermal load is applied due to a difference in thermal expansion coefficient between the buried insulating layer and the upper and lower semiconductor layers.

  Patent Document 1 discloses a technique for increasing the thickness of a part of a buried insulating layer and forming a cavity in the thick part. If only a part of the buried insulating layer is formed thick, damage due to a difference in thermal expansion may be suppressed. However, in order to make only a part of the buried insulating layer thick, there is a problem that the manufacturing process becomes complicated.

  The technology disclosed in this specification is intended to improve the breakdown voltage of a semiconductor device having a stacked body.

  In the technique disclosed in the present specification, a cavity is not formed in the buried insulating layer, but a recess is formed in a part of the surface of the lower semiconductor layer in contact with the buried insulating layer (the inside of the recess may be a cavity. The recess may be filled with a material having a low relative dielectric constant). Thereby, the electric field strength in the concave portion is increased, the voltage borne by the concave portion is increased, the electric field strength in the upper semiconductor layer is relatively lowered, and as a result, the breakdown voltage of the semiconductor device is improved. According to this technique, it is not necessary to increase the entire thickness of the embedded insulating layer, and it is not necessary to increase the thickness of a part of the embedded insulating layer. For this reason, in the technique disclosed in this specification, damage to the laminate due to the difference in thermal expansion is suppressed, and a complicated manufacturing process is not required.

  The semiconductor device disclosed in this specification includes a stacked body in which a lower semiconductor layer, a buried insulating layer, and an upper semiconductor layer are stacked. A recess is formed in a part of the surface of the lower semiconductor layer in contact with the buried insulating layer. The relative dielectric constant in the recess is lower than the relative dielectric constant of the lower semiconductor layer. In this semiconductor device, a recess having a low relative dielectric constant is formed in a part of the lower semiconductor layer in contact with the buried insulating layer, so that the electric field strength in the recess is increased, resulting in an improvement in the breakdown voltage of the semiconductor device. To do.

  In the upper semiconductor layer of the semiconductor device disclosed in this specification, an element structure that controls a conduction state and a non-conduction state of a current is preferably formed. This element structure preferably includes a first semiconductor region to which a high voltage is applied when in a non-conducting state and a second semiconductor region to which a low voltage is applied when in a non-conducting state. The first semiconductor region is preferably disposed on the center side of the recess when viewed in plan. The second semiconductor region is preferably disposed on the peripheral edge side of the recess when viewed in plan. Here, the second semiconductor region may be disposed so as to overlap the existence range of the recess when viewed in a plan view, or may be arranged around the existence range of the recess. In this specification, in any of the above cases, the second semiconductor region is disposed on the peripheral edge side of the recess. An example of an element structure for controlling the current conduction state and the non-conduction state includes a lateral diode, a lateral MOSFET, and a lateral IGBT. When the element structure is a lateral diode, the first semiconductor region is often referred to as a cathode region, and the second semiconductor region is often referred to as an anode region. When the element structure is a lateral MOSFET, the first semiconductor region is often referred to as a drain region and the second semiconductor region is often referred to as a source region. When the element structure is an IGBT, the first semiconductor region is often referred to as a collector region, and the second semiconductor region is often referred to as an emitter region. In this semiconductor device, when viewed in plan, the positional relationship between the element structure and the recesses is the same, and the breakdown voltage is improved.

  As described above, when the first semiconductor region is disposed on the central portion side of the concave portion and the second semiconductor region is disposed on the peripheral portion side of the concave portion when viewed in plan, the concave portion is in the central portion rather than the peripheral portion. It is desirable to form deeply. When the concave portion has such a form, the fluctuation of the pressure resistance becomes small with respect to the variation in the depth of the concave portion. Accordingly, variations due to manufacturing tolerances of the recesses can be compensated, and thus a semiconductor device having such recesses can be manufactured with a high yield.

  The method for manufacturing a semiconductor device disclosed in this specification includes a trench formation step and a recess formation step. In the trench formation step, a stacked body in which a lower semiconductor layer, a buried insulating layer, and an upper semiconductor layer are stacked is prepared, and a trench penetrating the upper semiconductor layer and the buried insulating layer is formed. In the recess forming step, an etching material is supplied through the trench, and a recess is formed in a part of the surface of the lower semiconductor layer that is in contact with the buried insulating layer. According to this manufacturing method, it is possible to form a recess centered on the trench when viewed in plan. The position of the recess formed in the lower semiconductor layer can be accurately controlled.

  The method for manufacturing a semiconductor device disclosed in this specification preferably further includes an element structure forming step of forming an element structure for controlling a current conduction state and a non-conduction state in the upper semiconductor layer. The element structure preferably includes a first semiconductor region to which a high voltage is applied when in a non-conductive state and a second semiconductor region to which a low voltage is applied when in a non-conductive state. The first semiconductor region is disposed on the center side of the recess when viewed in plan. The second semiconductor region is disposed on the peripheral edge side of the recess when viewed in plan. The element structure forming step may be performed prior to the trench forming step, may be performed between the trench forming step and the concave portion forming step, or may be performed after the concave portion forming step.

  In the method for manufacturing a semiconductor device disclosed in the present specification, a high-speed etching is performed in which a high-speed etching layer is formed on the surface of the lower semiconductor layer in contact with the buried insulating layer prior to the recess formation step. It is desirable to further include a layer forming step. When the high-speed etching layer is formed, the etching in the lateral direction proceeds rapidly using the high-speed etching layer in the recess forming step, so that a recess that widens in the lateral direction can be formed.

  In the technique disclosed in this specification, since the relative dielectric constant in the recess formed in a part of the surface of the lower semiconductor layer in contact with the buried insulating layer is low, the electric field strength in the recess is high. As a result, the breakdown voltage of the semiconductor device is improved. According to this technique, it is not necessary to increase the entire thickness of the buried insulating layer, and it is not necessary to increase the thickness of a part of the buried insulating layer. For this reason, in the technique disclosed in the present specification, damage to the laminate due to the difference in thermal expansion is suppressed, and the manufacturing process is also simple.

FIG. 1 is a flowchart for manufacturing the semiconductor device of this embodiment. FIG. 2 schematically shows a cross-sectional view of the manufacturing process of the semiconductor device of this embodiment (1). FIG. 3 schematically shows a cross-sectional view of the manufacturing process of the semiconductor device of this embodiment (2). FIG. 4 schematically shows a cross-sectional view of the manufacturing process of the semiconductor device of this embodiment (3). FIG. 5 schematically shows a cross-sectional view of the manufacturing process of the semiconductor device of this embodiment (4). FIG. 6 schematically shows a cross-sectional view of the manufacturing process of the semiconductor device of this embodiment (5). FIG. 7 schematically shows a cross-sectional view of the manufacturing process of the semiconductor device of this example (6). FIG. 8 schematically shows a cross-sectional view of the manufacturing process of the semiconductor device of this example (7). FIG. 9 schematically shows a cross-sectional view of the manufacturing process of the semiconductor device of this embodiment (8). FIG. 10 schematically shows a cross-sectional view of the manufacturing process of the semiconductor device of this example (9). FIG. 11 schematically shows a cross-sectional view of a semiconductor device having a tapered recess used in the simulation. FIG. 12 schematically shows a cross-sectional view of a semiconductor device having a rectangular recess used in the simulation. FIG. 13 shows a simulation result regarding the breakdown voltage of a semiconductor device having a tapered recess. FIG. 14 shows a simulation result regarding the breakdown voltage of a semiconductor device having a rectangular recess. FIG. 15 shows a simulation result regarding the breakdown voltage of a semiconductor device having a tapered recess. FIG. 16 shows a simulation result regarding the breakdown voltage of a semiconductor device having a rectangular recess. FIG. 17 shows the electric field strength distribution in the horizontal direction of a semiconductor device having a tapered recess. FIG. 18 shows the electric field strength distribution in the horizontal direction of a semiconductor device having a rectangular recess.

The features of the technology disclosed in this specification will be summarized and described.
(First feature) It is desirable that the shape of the recess is deep at the center and shallow at the periphery. The depth between the central portion and the peripheral portion may be continuously decreased from the central portion toward the peripheral portion, may be changed in stages, or a combination thereof. More preferably, it is desirable that the deepest portion of the recess is below the first semiconductor region (for example, the cathode region, the drain region, and the collector region).
(Second feature) The high-speed etching layer formed in the lower semiconductor layer is a layer having a higher etching rate than the remaining lower semiconductor layer. In one example, the high-speed etching layer is preferably a layer that contains more crystal defects than the remaining lower semiconductor layer. This high-speed etching layer is desirably formed by implanting ions that do not affect the conductivity type, typically rare gas ions, into the surface layer portion of the lower semiconductor layer using an ion implantation technique.

  Hereinafter, a method for manufacturing the semiconductor device 10 and features of the semiconductor device 10 will be described with reference to the drawings. In the semiconductor device 10 described below, silicon is used as the semiconductor material, but other semiconductor materials such as silicon carbide, gallium nitride, and gallium arsenide semiconductor materials may be used instead of this example. Good.

(Manufacturing method of the semiconductor device 10)
FIG. 1 schematically shows a flow chart of a method of manufacturing the semiconductor device 10, and FIGS. 2 to 10 schematically show cross-sectional views of the manufacturing process of the semiconductor device 10 manufactured along the flow chart.

  First, as shown in FIG. 2, a lower semiconductor layer 20 of p-type single crystal silicon is prepared. Next, by utilizing an ion implantation technique, rare gas ions (for example, argon ions) are implanted into the surface layer portion of the lower semiconductor layer 20 to form a large amount of crystal defects in the surface layer portion of the lower semiconductor layer 20. As will be described later, the reason for forming a large amount of crystal defects is to make the etching rate of the surface layer portion of the lower semiconductor layer 20 faster than that of the remaining lower semiconductor layer 20. Therefore, hereinafter, the layer in which a large amount of crystal defects are formed is referred to as a high-speed etching layer 22. Instead of forming the high-speed etching layer 22 having a large amount of crystal defects, a polycrystalline layer or an amorphous layer may be formed on the surface of the lower semiconductor layer 20. In this case, the polycrystalline layer or the amorphous layer becomes a high-speed etching layer, and the layer including the polycrystalline layer or the amorphous layer is referred to as the lower semiconductor layer 20.

  Next, as shown in FIG. 3, a silicon oxide buried insulating layer 30 and an n-type single crystal silicon upper semiconductor layer 40 are bonded to the surface of the lower semiconductor layer 20 by using a bonding technique. Thereby, the SOI substrate 50 in which the lower semiconductor layer 20, the buried insulating layer 30, and the upper semiconductor layer 40 are stacked in this order is completed.

  Next, as shown in FIG. 4, a mask 52 is patterned on the surface of the upper semiconductor layer 40, and phosphorus is implanted into a part of the surface layer portion of the upper semiconductor layer 40 using an ion implantation technique. The implanted phosphorus is introduced into a region corresponding to the formation region of the cathode region 42.

  Next, as shown in FIG. 5, a mask 54 is patterned on the surface of the upper semiconductor layer 40, and boron is implanted into a part of the surface layer portion of the upper semiconductor layer 40 using an ion implantation technique. Boron to be implanted is introduced into a region corresponding to a region where the anode region 44 is formed. The anode region 44 is formed so as to make a round around the cathode region 42 in plan view.

  Next, as shown in FIG. 6, using the heat treatment technique, phosphorus and boron introduced into the surface layer portion of the upper semiconductor layer 40 are activated to form the cathode region 42 and the anode region 44. A part of the upper semiconductor layer 40 between the cathode region 42 and the anode region 44 becomes the drift region 43. Thereby, the element structure (42, 43, 44) constituting the lateral diode is formed in the upper semiconductor layer 40.

  Next, as shown in FIG. 7, a mask 56 is patterned on the surface of the upper semiconductor layer 40. Next, by using RIE (Reactive Ion Etching) technology, the upper semiconductor layer 40 and the buried insulating layer 30 exposed from the opening are removed, and a trench 62 reaching the lower semiconductor layer 20 is formed. The trench 62 is formed in a positional relationship overlapping with a part of the cathode region 42 in plan view.

  Next, as shown in FIG. 8, a thermal oxide film 64 is formed on the inner wall of the trench 62 using a thermal oxidation technique.

  Next, as shown in FIG. 9, an etching material (for example, hydrogen fluoride) is introduced through the trench 62 by using a wet etching technique, and the surface of the lower semiconductor layer 20 in contact with the embedded insulating layer 30 is contacted. A recess 66 is formed. At this time, the high-speed etching layer 22 is formed in the surface layer portion of the lower semiconductor layer 20, and the high-speed etching layer 22 has an etching rate about 2 to 4 times faster than the remaining lower semiconductor layer 20. . For this reason, the formed recess 66 can have a form in which the surface layer portion of the lower semiconductor layer 20 is widened in the horizontal direction. It is desirable that the existence range of the recess 66 is widened to the side of the anode region 44 rather than the cathode region 42 in plan view. More preferably, the range of existence of the recess 66 extends laterally toward the anode region 44 side from the intermediate point between the cathode region 42 and the anode region 44 (intermediate point of the drift region 43) when viewed in plan. Is desirable. More preferably, it is desirable that the existence range of the recess 66 reaches the boundary between the anode region 44 and the drift region 43 in a plan view. The withstand voltage of the semiconductor device 10 is improved as the existence range of the recess 66 is expanded to the side.

  Finally, as shown in FIG. 10, an aluminum cathode electrode 72 and an anode electrode 74 are formed on the surface of the upper semiconductor layer 40 by using a vapor deposition technique. The cathode electrode 72 is in contact with the cathode region 42, and the anode electrode 74 is in contact with the anode region 44. Through these steps, the semiconductor device 10 in which the lateral diode is formed in the upper semiconductor layer 40 is completed.

  In the semiconductor device 10 described above, since the concave portion 66 is formed on the surface of the lower semiconductor layer 20 in contact with the buried insulating layer 30, the relative dielectric constant in the concave portion 66 (air is about 1.0). Is lower than the relative dielectric constant of the lower semiconductor layer 20 (single crystal silicon, which is about 11.9). For this reason, the electric field strength applied to the recess 66 is increased. In the semiconductor device 10, when the lateral diode is in a reverse bias state, a high voltage is applied to the cathode region 42, and a low voltage (typically ground voltage) is applied to the anode region 44 and the lower semiconductor layer 20. Therefore, the voltage in the thickness direction between the cathode region 42 and the lower semiconductor layer 20 is borne by the upper semiconductor layer 40, the buried insulating layer 30, and the recess 66. In the semiconductor device 10, the concave portion 66 is formed, and the electric field strength applied to the concave portion 66 is high. Therefore, the electric field strength applied to the upper semiconductor layer 40 is relatively small. Usually, the breakdown voltage of the semiconductor device 10 is often determined based on the voltage when the electric field strength in the upper semiconductor layer 40 exceeds a critical value. For this reason, if the electric field strength in the recess 66 is increased, the electric field strength in the upper semiconductor layer 40 is relatively decreased, and as a result, the breakdown voltage of the semiconductor device 10 is improved.

Hereinafter, characteristics and modifications of the above manufacturing method will be listed.
(1) As described above, during reverse bias, a high voltage is applied to the cathode region 42 and a low voltage (typically ground voltage) is applied to the anode region 44 and the lower semiconductor layer 20. For this reason, a large voltage must be borne at a short distance between the cathode region 42 and the lower semiconductor layer 20 below the cathode region 42. According to the manufacturing method, the recess 66 can be reliably formed below the cathode region 42. For this reason, since the recessed part 66 can be reliably formed in a required place, the semiconductor device 10 having a high yield and a high breakdown voltage can be manufactured.
(2) According to the above manufacturing method, by using the high-speed etching layer 22, it is possible to form the concave portion 66 spreading in the lateral direction. For example, in the case where the high-speed etching layer 22 is not formed, the depth of the concave portion 66 becomes deeper when an attempt is made to form the concave portion 66 spreading in the lateral direction by using an isotropic wet etching technique. When the depth of the recess 66 is increased, there is a problem that the rigidity of the SOI substrate 50 is weakened. On the other hand, in the manufacturing method described above, by using the high-speed etching layer 22, it is possible to form the recess 66 having a shape that expands in the lateral direction while keeping the depth shallow.
(3) As will be described in the following simulation, if the recess 66 has a deep shape at the center and a shallow shape at the periphery, the fluctuation in the breakdown voltage of the semiconductor device 10 with respect to variations in the depth of the recess 66 Is small. In the above manufacturing method, since the recess 66 is formed by using an isotropic wet etching technique, it is possible to form the recess 66 deep at the center and shallow at the periphery. Therefore, the semiconductor device 10 manufactured by the above manufacturing method has a characteristic that the withstand voltage fluctuation is small with respect to the variation in the depth of the recess 66.
(4) In the manufacturing method described above, the inside of the concave portion 66 is hollow, but instead, for example, the concave portion 66 may be filled with silica beads. The silica beads may be supplied from the trench 62 into the recess 66 in a state of being mixed with a volatile liquid using, for example, an inkjet technique. By filling the recess 66 with silica beads, the rigidity of the SOI substrate 50 can be increased.

(Simulation study on the form of the recess 66)
The effect of the shape of the recess 66 on the pressure resistance was examined by simulation. 11 and 12 show the form of the recess 66 used in the simulation. The recess 66 shown in FIG. 11 has a depth that varies between the cathode region 42 and the anode region 44, and has a form that is deep below the cathode region 42 and shallow below the anode region 44 (hereinafter, this is described below). The form is called a taper type). The depth of the recess 66 continuously decreases from the cathode region 42 side toward the anode region 44 side. The recess 66 shown in FIG. 12 has a constant depth between the cathode region 42 and the anode region 44 (this form is hereinafter referred to as a rectangular shape). In the simulation, the impurity concentration of the lower semiconductor layer 20 is fixed at 3.8 × 10 ¹⁸ cm ⁻³ , and the lateral length L40 of the upper semiconductor layer 40 is fixed at 40 μm.

  13 and 14, the thickness T30 of the buried insulating layer 30 is set to 4 μm, the thickness T40 of the upper semiconductor layer 40 is set to 15 μm, and the breakdown voltage when the tapered recess 66 is shown in FIG. FIG. 14 shows the breakdown voltage when the rectangular recess 66 is provided. 15 and 16, the thickness T30 of the buried insulating layer 30 is set to 1 μm, the thickness T40 of the upper semiconductor layer 40 is set to 7.5 μm, and FIG. 15 has a tapered recess 66. FIG. 16 shows the breakdown voltage when the rectangular recess 66 is provided. The variation parameters are the depth T66 of the deepest portion of the recess 66 and the impurity concentration of the upper semiconductor layer 40. In addition, when the depth T66 of the recessed part 66 is "0", the case where the recessed part 66 is not formed is shown.

As shown in FIGS. 13 and 15, in the semiconductor device 10 having the tapered recess 66, the impurity concentration of the upper semiconductor layer 40 is 3.5 × 10 ¹⁴ cm ⁻³ and 5.0 × 10 ¹⁴ cm ^−3. , 7.0 × 10 ¹⁴ cm ⁻³ , the withstand voltage is improved by forming the tapered recess 66. Similarly, as shown in FIGS. 14 and 16, even in the semiconductor device 10 having the rectangular recess 66, the impurity concentration of the upper semiconductor layer 40 is 3.5 × 10 ¹⁴ cm ⁻³ and 5.0 × 10 ^14. In both cases of cm ⁻³ and 7.0 × 10 ¹⁴ cm ⁻³ , the withstand voltage is improved by forming the rectangular recess 66.

However, as shown in FIGS. 14 and 16, in the semiconductor device 10 having the rectangular recess 66, the impurity concentration of the upper semiconductor layer 40 is high (5.0 × 10 ¹⁴ cm ⁻³ , 7.0 × 10). ¹⁴ cm ⁻³ ), it can be seen that the pressure resistance rapidly decreases as the depth T66 of the recess 66 increases. On the other hand, as shown in FIGS. 13 and 15, in the semiconductor device 10 having the tapered recess 66, it can be seen that the withstand voltage is relatively maintained even when the depth T 66 of the recess 66 increases.

  To summarize these results, the semiconductor device 10 having the tapered recess 66 shows a tendency that the withstand voltage variation is small with respect to the variation of the depth T66 of the recess 66. In particular, when the impurity concentration of the upper semiconductor layer 40 is high, the semiconductor device 10 having the tapered recess 66 is more resistant to fluctuations in the depth T66 of the recess 66 than the semiconductor device 10 having the rectangular recess 66. The tendency for small fluctuations is remarkable.

  FIG. 17 schematically shows the horizontal electric field strength distribution of the upper semiconductor layer 40 in the vicinity of the bonding surface between the upper semiconductor layer 40 and the buried insulating layer 30 in the semiconductor device 10 having the tapered recess 66. FIG. 18 schematically shows the horizontal electric field strength distribution of the upper semiconductor layer 40 in the vicinity of the bonding surface between the upper semiconductor layer 40 and the buried insulating layer 30 in the semiconductor device 10 having the rectangular recess 66.

  As shown in FIG. 18, in the semiconductor device 10 having the rectangular recess 66, the electric field strength of the portion 44 </ b> A (see FIG. 12) immediately below the anode region 44 is lower than the portion 42 </ b> A (see FIG. 12) directly below the cathode region 42. It shows a tendency to be significantly higher than the electric field strength. For this reason, in the semiconductor device 10 having the rectangular recess 66, the electric field strength tends to concentrate on the portion 44A immediately below the anode region 44. On the other hand, as shown in FIG. 17, in the semiconductor device 10 having the tapered recess 66, both the portion 44 </ b> A (see FIG. 11) immediately below the anode region 44 and the portion 42 </ b> A (see FIG. 11) directly below the cathode region 42. The electric field strength is shared, and the electric field concentration in the portion 44A (see FIG. 11) immediately below the anode region 44 is relaxed. When the electric field is concentrated in the portion 44A immediately below the anode region 44 that is close to the pn junction formed by the anode region 44 and the drift region 43, breakdown due to the impact ionization phenomenon is likely to occur. For this reason, in the semiconductor device 10 having the tapered recess 66, the electric field concentration in the portion 44A immediately below the anode region 44 is alleviated, so that the fluctuation of the breakdown voltage with respect to the variation in the depth T66 of the recess 66 is suppressed to be small. Inferred.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

10: Semiconductor device 20: Lower semiconductor layer 22: High-speed etching layer 30: Buried insulating layer 40: Upper semiconductor layer 42: Cathode region 44: Anode region 50: SOI substrate 66: Recess

Claims (6)

A semiconductor device having a laminate in which a lower semiconductor layer, a buried insulating layer, and an upper semiconductor layer are laminated,
A recess is formed in a part of the surface of the lower semiconductor layer that contacts the buried insulating layer,
A semiconductor device in which a relative dielectric constant in the recess is lower than a relative dielectric constant of the lower semiconductor layer. In the upper semiconductor layer, an element structure for controlling a conduction state and a non-conduction state of current is formed,
The element structure includes a first semiconductor region to which a high voltage is applied when in a non-conductive state and a second semiconductor region to which a low voltage is applied when in a non-conductive state,
The first semiconductor region is disposed on a central portion side of the recess when viewed in plan,
The semiconductor device according to claim 1, wherein the second semiconductor region is disposed on a peripheral edge side of the recess when viewed in a plan view.   The semiconductor device according to claim 2, wherein the concave portion is deeper in a central portion than in a peripheral portion. A method for manufacturing a semiconductor device,
Preparing a stacked body in which a lower semiconductor layer, a buried insulating layer, and an upper semiconductor layer are laminated, and forming a trench that penetrates the upper semiconductor layer and the buried insulating layer;
A recess forming step of supplying an etching material through the trench and forming a recess in a part of a surface of the lower semiconductor layer in contact with the buried insulating layer. An element structure forming step of forming an element structure for controlling a conduction state and a non-conduction state of current in the upper semiconductor layer;
The element structure has a first semiconductor region to which a high voltage is applied when in a non-conductive state and a second semiconductor region to which a low voltage is applied when in a non-conductive state,
The first semiconductor region is disposed on a central portion side of the recess when viewed in plan,
The method of manufacturing a semiconductor device according to claim 4, wherein the second semiconductor region is disposed on a peripheral edge side of the recess when viewed in plan.   6. The high-speed etching layer forming step of forming a high-speed etching layer for increasing the etching rate on the surface of the lower semiconductor layer in contact with the buried insulating layer prior to the recess forming step. The manufacturing method of the semiconductor device as described in any one of.

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