JP2012038372A - Driving method for resistance change element, and nonvolatile storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving method for a resistance change element capable of operating with good endurance characteristics.SOLUTION: The driving method includes: a writing step of applying a writing voltage pulse having a first polarity to the element so as to change a resistance state of a transition metal oxide layer 3 from a high resistance state to a low resistance state; an erasing step of applying an erasing voltage pulse having a second polarity different from the first polarity, so as to change the resistance state of the transition metal oxide layer 3 from the low resistance state to a high resistance state; a breaking step of applying an initial voltage pulse having the second polarity prior to the first time writing step, so as to form a conductive path in the transition metal oxide layer 3 to decrease a resistance value in the initial state; and an additional processing step, after the breaking step and prior to the first time writing step, of applying an additional process voltage pulse having a voltage value equal to or larger than that of the erasing voltage pulse and having the second polarity, so as to further decrease the resistance value of the transition metal oxide layer 3 after breaking.

Description

  The present invention relates to a resistance change element driving method in which a resistance value changes according to an applied electric pulse, and a nonvolatile memory device that implements the method.

  In recent years, with the advancement of digital technology in electronic devices, in order to store data such as images, the capacity of nonvolatile resistance change elements (hereinafter simply referred to as “resistance change elements”) is increased, the writing power is reduced, There is an increasing demand for faster writing / reading time and longer life. In response to such demands, it is said that there is a limit to the response in miniaturization of existing flash memories using floating gates.

As a first conventional technique that may be able to meet the above requirements, perovskite materials (for example, Pr _(1-x) Ca _x MnO ₃ [PCMO], LaSrMnO ₃ [LSMO], GdBaCo _x O _y [GBCO] Etc.) have been proposed (see Patent Document 1). This technique is designed to store data by applying a voltage pulse (wave voltage with short duration) of different polarity to a perovskite material to increase or decrease its resistance value, and to correspond the data to a changing resistance value. Is.

In addition, as a second conventional technique that makes it possible to switch the resistance value using voltage pulses of the same polarity, transition metal oxides (NiO, V ₂ O, ZnO, Nb ₂ O ₅ , TiO ₂ , WO ₃ , Alternatively, there is a variable resistance element that utilizes a change in the resistance value of the transition metal oxide film by applying a voltage pulse having a different pulse width to the CoO film (see Patent Document 2). In the variable resistance element using the transition metal oxide film, a configuration in which cross-point type memory cell arrays using diodes are stacked is also realized.

US Pat. No. 6,204,139 JP 2004-363604 A

However, it has been found that the first prior art has a problem that the operation stability and reproducibility are insufficient. Furthermore, since an oxide crystal having a perovskite structure such as Pr _0.7 Ca _0.3 MnO ₃ usually requires a high temperature of 650 ° C. to 850 ° C. for crystallization, when introduced into a semiconductor manufacturing process, other materials There is also a problem of deterioration.

  In the second prior art, the initial pulse application condition necessary for the resistance change operation is described. However, reference is made to the stabilization of data in a repetitive operation (endurance operation) of a plurality of data rewrite operations. Not.

  The present invention has been made in view of such circumstances, and a main object of the present invention is to provide a method of driving a resistance change element capable of stably changing the resistance of the resistance change element, and a nonvolatile memory device that implements the method. It is to provide.

  Furthermore, the present invention relates to a method for driving a resistance change element that can be manufactured at a low temperature, a resistance change element driving method capable of stably changing the resistance of the resistance change element, and a nonvolatile memory device that implements the method It is also intended to provide.

  In order to solve the above-described problem, a driving method of a variable resistance element according to one aspect of the present invention includes a first electrode, a second electrode, and the first electrode and the second electrode interposed between the two electrodes. In the driving method of driving a resistance change element including a transition metal oxide layer whose resistance value increases or decreases according to an electric pulse applied therebetween, the transition metal oxide layer is applied to the first electrode. A first transition metal oxide layer to be connected and a second transition metal oxide layer having a higher oxygen content than that of the first transition metal oxide layer and connected to the second electrode are stacked. The transition state of the transition metal oxide layer is changed from the high resistance state to the low resistance state by applying a write voltage pulse having a first polarity between the first electrode and the second electrode. The changing writing process and the first polarity An erasing process for changing the resistance state of the transition metal oxide layer from a low resistance state to a high resistance state by applying an erasing voltage pulse having a second polarity between the first electrode and the second electrode; The transition voltage is applied by applying a break voltage pulse having the second polarity having a voltage value equal to or higher than the erase voltage pulse between the first electrode and the second electrode before the first writing process. A break process in which a conductive path is formed in the metal oxide layer to reduce a resistance value in an initial state to a first resistance value larger than a resistance value in the high resistance state; and a first writing after the break process Before the process, the break process is performed by applying an additional processing voltage pulse having the second polarity having a voltage value greater than or equal to the erase voltage pulse between the first electrode and the second electrode. And having an additional processing step for the first resistance value of the transition metal oxide layer to a lower second resistance value.

  As a result, the resistance value of the resistance change element is further reduced by an additional processing process added after the break process, and the resistance change element can stably and repeatedly transition between the high resistance state and the low resistance state. Therefore, better endurance characteristics can be obtained.

  In the additional processing step, the resistance value of the transition metal oxide layer is set to the second resistance value by applying a plurality of additional processing voltage pulses between the first electrode and the second electrode. Also good.

Further, in the resistance change element driving method according to the invention, the first transition metal oxide layer is a tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9). It is preferable that the second transition metal oxide layer is made of tantalum oxide having a composition represented by TaO _y (where 2.1 ≦ y). Thus, a resistance change element driving method that can be manufactured at a low temperature and that can stably change the resistance of the resistance change element is realized.

  In addition, the nonvolatile memory device of one embodiment of the present invention includes a first electrode, a second electrode, and an electric pulse that is interposed between the first electrode and the second electrode and is applied between the electrodes. A resistance change element comprising a transition metal oxide layer whose resistance value increases or decreases, and a pulse voltage application unit that applies a predetermined pulse voltage to the resistance change element, the transition metal oxide layer comprising: The first transition metal oxide layer and the second transition metal oxide layer having a higher oxygen content than the first transition metal oxide layer are stacked, and the pulse voltage application unit Is a writing process for changing the resistance state of the transition metal oxide layer from a high resistance state to a low resistance state by applying a write voltage pulse having a first polarity between the first electrode and the second electrode. And a first polarity different from the first polarity. An erasing process for changing the resistance state of the transition metal oxide layer from a low resistance state to a high resistance state by applying an erasing voltage pulse having the following polarity between the first electrode and the second electrode; By applying a break voltage pulse having the second polarity having a voltage value equal to or higher than the erase voltage pulse between the first electrode and the second electrode before the second writing process, the transition metal oxide layer And a voltage value greater than or equal to the erase voltage pulse after the break process and before the first write process. The resistance value of the transition metal oxide layer after the break process is further reduced by applying an additional processing voltage pulse having the second polarity having the second polarity between the first electrode and the second electrode. And executes an additional process to the second resistance value.

  As a result, since the additional processing process is executed after the break process by the pulse voltage application unit, the resistance value of the resistance change element after the break process is further reduced, and the resistance change element is stably placed in the high resistance state and the low resistance state. The resistance state can be repeatedly changed, and a better endurance characteristic can be obtained.

In the nonvolatile memory device according to the invention, the first transition metal oxide layer is composed of a tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9). The second transition metal oxide layer is preferably composed of tantalum oxide having a composition represented by TaO _y (where 2.1 ≦ y). Accordingly, a nonvolatile memory device that implements a resistance change element driving method that can be manufactured at a low temperature and that can stably change the resistance of the resistance change element is realized.

  The nonvolatile memory device according to the invention preferably further includes a current control element electrically connected to the first electrode or the second electrode. This current control element may be a selection transistor or a bidirectional diode.

  According to the resistance change element driving method of the present invention, it is possible to stably change the resistance of the resistance change element. Further, according to the nonvolatile memory device of the present invention that implements this driving method, a memory device capable of stable operation can be realized.

The schematic diagram which showed an example of the structure of the resistance change element of Embodiment 1 of this invention The flowchart which shows the procedure of the drive method of the resistance change element of Embodiment 1 of this invention. The graph which shows an example of the change of the resistance state of the transition metal oxide layer with which the resistance change element of Embodiment 1 of this invention with which a break process and an additional process process are provided is provided. The graph which shows an example of the change of the resistance state of the transition metal oxide layer after repeating 1 million times of writing and erasing The figure which shows an example of a structure of the circuit which operates the resistance change element of Embodiment 1 of this invention, and the operation example in the case of writing data in the said resistance change element The figure which shows the change of the resistance value of the resistance change layer in the case of writing in and erasing data in the resistance change element of Embodiment 1 of this invention, and the break process performed before the 1st write, and an additional process. The figure which shows an example of the structure in the case of reading an example of the structure of the circuit which operates the resistance change element of Embodiment 1 of this invention, and the said resistance change element The figure which shows the relationship between the electric current value of the electric current which flows through the circuit provided with the resistance change element of Embodiment 1 of this invention, and the resistance value of a resistance change layer in the case of data reading The graph which shows an example of the change of the resistance state of the transition metal oxide layer with which the resistance change element of the comparative example 1 is equipped The graph which shows an example of the change of the resistance state of the transition metal oxide layer with which the resistance change element of the comparative example 2 after a break process and an additional process process is provided The graph which shows an example of the change of the resistance state of the transition metal oxide layer with which the resistance change element of the comparative example 2 after repeating writing and erasing 1 million times is provided. The graph which shows an example of the change of the resistance state of the transition metal oxide layer with which the resistance change element of the comparative example 3 is provided The graph which shows the change of the resistance state of the transition metal oxide layer of a resistance change element by the difference in the conditions of an additional process The figure which shows the quality of the endurance characteristic of the variable resistance element by the difference in the condition of the additional process The block diagram which shows an example of a structure of the non-volatile memory device of Embodiment 2 of this invention. The block diagram which shows an example of a structure of the non-volatile storage device of Embodiment 3 of this invention

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
[Configuration of variable resistance element]
First, the configuration of the variable resistance element according to Embodiment 1 of the present invention will be described.

  FIG. 1 is a schematic diagram showing an example of the configuration of the variable resistance element according to Embodiment 1 of the present invention. As shown in FIG. 1, the resistance change element 10 of the present embodiment includes a substrate 1, a first electrode 2 formed on the substrate 1, and a transition metal oxide formed on the first electrode 2. A layer 3 and a second electrode 4 formed on the transition metal oxide layer 3 are provided. The first electrode 2 and the second electrode 4 are electrically connected to the transition metal oxide layer 3.

  The substrate 1 is composed of, for example, a silicon substrate. Furthermore, the substrate 1 may be configured by a semiconductor circuit including transistors, wirings, and the like. The second electrode 4 includes, for example, one of Au (gold), Pt (platinum), Ir (iridium), Pd (palladium), Cu (copper), and Ag (silver) or a material thereof. You may comprise using an alloy. The first electrode 2 may be made of tantalum nitride (TaN) or the like.

The transition metal oxide layer 3 is a resistance change layer which is interposed between the first electrode 2 and the second electrode 4 and whose resistance value increases or decreases in accordance with an electric pulse applied between the two electrodes. The first transition metal oxide layer 3a connected to the electrode 2 and the second transition metal oxide layer connected to the second electrode 4 having a higher oxygen content than the first transition metal oxide layer 3a 3b is laminated. The transition metal oxide layer 3 is, for example, an oxygen-deficient first tantalum oxide layer that is an example of the first transition metal oxide layer 3a and a second transition metal oxide layer 3b that is an example of the second transition metal oxide layer 3b. A structure in which two tantalum oxide layers are stacked may be employed. Here, the oxygen-deficient tantalum oxide layer refers to a tantalum oxide layer in which the oxygen content is less than the stoichiometric composition (here, Ta ₂ O ₅ ). The oxygen content of the second transition metal oxide layer is higher than the oxygen content of the first transition metal oxide layer, and the resistance value of the second transition metal oxide layer is also the first transition metal oxide layer. Higher than the resistance value.

When the composition of the first transition metal oxide layer 3a is TaO _x (first tantalum oxide layer), x is 0.8 or more and 1.9 or less, and the second transition metal oxide layer When the composition of 3b is TaO _y (first tantalum oxide layer) and y is 2.1 or more, the resistance value of the transition metal oxide layer 3 can be stably changed at high speed. It was. Therefore, x and y are preferably within the above range.

  If the thickness of the transition metal oxide layer 3 is 1 μm or less, a change in the resistance value is recognized. However, when a large-scale memory device is configured, it is preferably 200 nm or less. This is because when the photolithography process and the etching process are used in the patterning process, it is easy to process and the voltage value of the voltage pulse required to change the resistance value of the transition metal oxide layer 3 can be lowered. is there. On the other hand, the thickness of the transition metal oxide layer 3 is preferably at least 5 nm or more from the viewpoint of more reliably avoiding breakdown (dielectric breakdown) during voltage pulse application.

  In addition, the thickness of the second transition metal oxide layer 3b is disadvantageous in that the initial resistance value becomes too high if it is too large, and if it is too small, there is a disadvantage that a stable resistance change cannot be obtained. 1 nm or more and about 8 nm or less are preferable.

  When operating the variable resistance element 10 configured as described above, the first electrode 2 and the second electrode 4 are electrically connected to different terminals of the power supply 5. The power source 5 functions as an electric pulse applying device for driving the variable resistance element 10, and an electric pulse (voltage) having a predetermined polarity, voltage, and time width between the first electrode 2 and the second electrode 4. Pulse) can be applied between the first electrode 2 and the second electrode 4.

  In the following, it is assumed that the polarity of the voltage pulse applied between the electrodes is specified by the potential of the second electrode 4 with respect to the first electrode 2.

  The second electrode 4 disposed so as to be in contact with the second transition metal oxide layer 3b is, for example, Au (gold), Pt (platinum), Ir (iridium), Pd (palladium), Cu (copper). And one or more of materials having a standard electrode potential higher than the standard electrode potential of the transition metal M constituting the first transition metal oxide layer and the second transition metal oxide layer, such as Ag (silver) The first electrode 2 is preferably made of a material (for example, W, Ni, TaN, etc.) having a standard electrode potential smaller than the standard electrode potential of the material constituting the second electrode 4.

That is, when a tantalum oxide to the transition metal oxide, the standard electrode potential V ₁ of the first electrode 2, the standard electrode potential V ₂ of the second electrode 4, and a standard electrode potential V _Ta of tantalum, V _Ta It is preferable that the relationship of <V ₂ and V ₁ <V ₂ is satisfied.

Further, it is more preferable to satisfy the relationship of V ₁ ≦ V _Ta <V ₂ .

  With such a configuration, it is possible to stably cause a resistance change phenomenon in the second transition metal oxide layer 3b in contact with the second electrode 4.

  In addition, the variable resistance element 10 may have an upside down structure.

[Method of manufacturing variable resistance element]
Next, a method for manufacturing the variable resistance element 10 will be described.

First, the first electrode 2 having a thickness of 0.2 μm is formed on the substrate 1 by sputtering. Thereafter, a tantalum oxide (TaO _x ) layer is formed on the first electrode 2 by a so-called reactive sputtering method in which a Ta target is sputtered in argon (Ar) gas and oxygen (O ₂ ) gas. . Here, the oxygen content in the tantalum oxide layer can be easily adjusted by changing the flow ratio of oxygen gas to argon gas. The substrate temperature can be set to room temperature without any particular heating.

Next, the surface of the tantalum oxide layer formed as described above is modified by oxidizing it. Thereby, a region (second region: TaO _y , y> x) having a higher oxygen content than a region (first region: TaO _x ) where the tantalum oxide layer was not oxidized on the surface of the tantalum oxide layer. Is formed. The first region (TaO _x ) and the second region (TaO _y ) correspond to the first transition metal oxide layer 3a and the second transition metal oxide layer 3b, respectively. The transition metal oxide layer 3 is constituted by the first transition metal oxide layer 3a and the second transition metal oxide layer 3b. Note that the second transition metal oxide layer 3b may be formed by sputtering in an argon (Ar) gas and an oxygen (O ₂ ) gas using a TaO _y target.

  Next, the variable resistance element 10 is obtained by forming the second electrode 4 having a thickness of 0.2 μm by sputtering on the transition metal oxide layer 3 formed as described above.

  As described above, the variable resistance element 10 in the present embodiment is manufactured by a sputtering method or the like, and can be manufactured at a low temperature.

In addition, the magnitude | size and shape of the 1st electrode 2, the 2nd electrode 4, and the transition metal oxide layer 3 can be adjusted with a mask and lithography. In the present embodiment, the size of the second electrode 4 and the transition metal oxide layer 3 is 0.5 μm × 0.5 μm (area 0.25 μm ² ), and the first electrode 2 and the transition metal oxide layer 3 are The size of the contacting portion was also 0.5 μm × 0.5 μm (area 0.25 μm ² ).

In the present embodiment, the composition of the first transition metal oxide layer 3a is the first tantalum oxide layer (TaO _x (x = 1.54)), and the second transition metal oxide layer 3b The composition is the second tantalum oxide layer (TaO _y (y = 2.47)). Furthermore, the thickness of the transition metal oxide layer 3 is 50 nm, the thickness of the first transition metal oxide layer 3a is 45 nm, and the thickness of the second transition metal oxide layer 3b is 5 nm.

  In the present embodiment, the oxygen content in the first tantalum oxide layer and the second tantalum oxide layer is described as x = 1.54 and y = 2.47. The resistance change element according to the present invention is not limited to this, and the resistance of the present embodiment is as long as the range of x is 0.8 ≦ x ≦ 1.9 and the range of y is 2.1 ≦ y. Similar to the change characteristic, stable resistance change can be realized.

[Operation of variable resistance element]
Next, the operation of the variable resistance element 10 obtained by the manufacturing method described above will be described.

  Hereinafter, a case where the resistance value of the transition metal oxide layer 3 is a predetermined high value (for example, about 100 kΩ) is referred to as a high resistance state, and a case where the resistance value is also a predetermined low value (for example, about 10 kΩ) is low resistance. It is called a state.

  Using the power source 5, a write voltage pulse, which is a voltage pulse having a negative polarity and smaller than a predetermined first threshold voltage (absolute value), is applied to the transition metal oxide layer 3 in a high resistance state. By applying between the second electrodes 4, the resistance value of the transition metal oxide layer 3 decreases, and the transition metal oxide layer 3 changes from the high resistance state to the low resistance state. Hereinafter, this is referred to as a writing process.

  On the other hand, the first electrode 2 and the second electrode 4 are supplied with the erase voltage pulse, which is a voltage pulse having a positive polarity and larger than a predetermined second threshold voltage, to the transition metal oxide layer 3 in the low resistance state using the power source 5. By applying in between, the resistance value of the transition metal oxide layer 3 increases, and the transition metal oxide layer 3 changes from the low resistance state to the high resistance state. Hereinafter, this is referred to as an erasing process.

  Even when a negative voltage pulse having the same polarity as the write voltage pulse is applied between the first electrode 2 and the second electrode 4 when the transition metal oxide layer 3 is in a low resistance state, the transition metal The oxide layer 3 remains unchanged in the low resistance state. Similarly, when the transition metal oxide layer 3 is in a high resistance state, even if a positive voltage pulse having the same polarity as the erase voltage pulse is applied between the first electrode 2 and the second electrode 4, The transition metal oxide layer 3 remains in a high resistance state.

  The resistance change element 10 operates by executing the above writing process and erasing process on the resistance change element 10. In addition, there is a case where so-called overwrite (overwriting) in which a writing process or an erasing process is continuously performed is performed.

  In the present embodiment, the break process and the additional process are executed before the first writing process. Here, the break process means that the resistance value of the transition metal oxide layer 3 is initially set by applying a positive polarity break voltage pulse having the same polarity as the erase voltage pulse between the first electrode 2 and the second electrode 4. A process of greatly reducing the resistance value (the initial value after being manufactured and shipped, that is, the resistance value after being manufactured and not yet subjected to the writing process) to the first resistance value. . Note that this break process is a process in which a path having good conductivity (conductive path) is locally formed in the transition metal oxide layer 3 unlike a breakdown that means a dielectric breakdown of an insulator or the like. It is considered that the resistance of the conductive path changes during writing and erasing. The first resistance value is preferably larger than the resistance value in the high resistance state. This is because it is expected that the conductive path can be prevented from becoming too large during the break process, and the endurance characteristics can be further improved. The additional process is a positive voltage pulse having the same polarity as the erase voltage pulse, and an additional process voltage pulse having a voltage value higher than that of the erase voltage pulse is applied between the first electrode 2 and the second electrode 4. This means a process of further reducing the resistance value of the transition metal oxide layer 3 from the first resistance value to a second resistance value lower than the first resistance value. Here, the second resistance value may be the same resistance value as in the high resistance state. In addition, it is guessed that this additional process process has given some change to the conductive path formed in the break process.

  Conventionally, in order to develop a change in resistance state in a variable resistance element having a structure in which a variable resistance material is sandwiched between upper and lower electrodes, a “break-in” process (hereinafter referred to as a special electrical stimulus) is applied between the upper and lower electrodes in the manufacturing process. , Called a forming step). Specifically, for example, in order to operate a resistance change element having the potential to change its resistance state by a voltage pulse having a pulse width of 100 ns at a voltage of 2 V, for example, a size different from this (normally, And a step of applying voltage pulses having different pulse widths (usually a larger pulse width) a plurality of times (for example, applying an electrical pulse of 1 μs at ± 3 V about 100 times) corresponds to the forming step. The break process and the additional process in the present embodiment are performed before the first writing process after the resistance change element is manufactured and shipped, and electric pulses having the same polarity are continuously applied. Thus, the step of applying to the variable resistance element is different from the above forming step.

  In the present embodiment, when the first resistance value after the break process is R1, and the second resistance value after the additional process is R2, R1> R2 is satisfied. By satisfying this relationship, a stable resistance changing operation can be realized as described later.

  The operation of the variable resistance element 10 according to Embodiment 1 of the present invention described above is shown in a flowchart in FIG. First, when the resistance value of the transition metal oxide layer 3 is the initial resistance value R0, that is, before the first writing process is performed, a break process is executed by a break voltage pulse of the voltage value V0 (S101). At this time, a conductive path is formed in the transition metal oxide layer 3, and the resistance value decreases from the initial resistance value R0 to the first resistance value R1. Further, an additional processing step is executed by the additional processing voltage pulse of the voltage value V1 (S102). At this time, the resistance value of the transition metal oxide layer 3 further decreases from the first resistance value R1 to the second resistance value R2 that is lower than the first resistance value R1.

  The second resistance value R2 may be higher than the high resistance state of the variable resistance element or may be the same resistance value.

  Thereafter, step S103 is repeated to repeat the writing process and the erasing process. Specifically, a writing process (S103A) using a writing voltage pulse having a voltage value Vw and an erasing process (S103B) using an erasing voltage pulse having a voltage value Ve are repeated. Here, when step S103A is executed, the resistance value of the transition metal oxide layer 3 changes from the high resistance value RH to the low resistance value RL. When step S103B is executed, the resistance value of the transition metal oxide layer 3 is It changes from the low resistance value RL to the high resistance value RH.

  When the first writing process (S103A) is performed, the resistance value of the transition metal oxide layer 3 is the second resistance value R2 as described above. The resistance value of the metal oxide layer 3 changes from the second resistance value R2 to the low resistance value RL. In the subsequent writing process (S103A) after the second time, as described above, the resistance value of the transition metal oxide layer 3 changes from the high resistance value RH to the low resistance value RL.

  3A and 3B are graphs showing an example of a change in resistance state of the transition metal oxide layer 3 in which the thickness of the second transition metal oxide layer 3b is 5.0 nm. FIG. 3A shows a state in which the resistance value of the transition metal oxide layer 3 changes from the initial resistance value through a break process and an additional processing process, and the transition metal oxide layer 3 when the subsequent writing process and erasing process are repeatedly performed. The state of resistance change. FIG. 3B shows a state of resistance change of the transition metal oxide layer 3 after the writing process and the erasing process are repeatedly executed 1 million times after the break process and the additional processing process are completed. In this example, the voltage value V0 of the break voltage pulse in the break process is set to + 4.5V which is equal to or higher than the voltage value Ve (+ 2.5V) of the erase voltage pulse, the pulse width is 100 μs, and the voltage value V1 of the additional processing voltage pulse is The erase voltage pulse has a voltage value Ve (+2.5 V) or more of +4.5 V and a pulse width of 500 μs. The voltage value Vw of the write voltage pulse is −1.9 V and the pulse width is 100 ns, and the voltage value Ve of the erase voltage pulse is greater than the absolute value of the voltage value Vw (−1.9 V) of the write voltage pulse. Is +2.5 V and the pulse width is 100 ns.

  Referring to FIG. 3A, in the break process, when the break voltage pulse is applied 11 times, the resistance value of the transition metal oxide layer 3 rapidly decreases from the initial resistance value of about 36 MΩ to about 560 kΩ which is 1/10 or less. ing. Thereafter, in the additional process, the resistance value of the transition metal oxide layer 3 is reduced from about 560 kΩ to about 70 kΩ by applying the additional process voltage pulse 20 times (that is, a plurality of additional process voltage pulses). As the number of additional processing voltage pulses applied increases, the resistance value slightly increases or decreases, but gradually decreases gradually. After the break process and the additional process, the resistance value of the transition metal oxide layer 3 in the writing process and the erasing process changes relatively stably between about 8 kΩ and about 50 kΩ to 120 kΩ.

  Referring to FIG. 3B, the resistance value of the transition metal oxide layer 3 in the writing process and the erasing process changes relatively stably between about 8 kΩ and about 40 kΩ to 100 kΩ. It can be seen that the change in the resistance state of the layer 3 is stable immediately after the break process and the additional process process are completed, and after the writing process and the erasing process are repeated one million times. In this way, by applying the voltage pulse between both electrodes so that the first resistance value R1 after the break process and the second resistance value R2 after the additional process process satisfy R1> R2, the resistance change element 10 can be stably operated.

  Next, a case where the resistance change element 10 is used as a memory and 1-bit data writing / reading processing is performed will be described. Hereinafter, a case where the transition metal oxide layer 3 is in the low resistance state is associated with “1”, and a case where the transition metal oxide layer 3 is in the high resistance state is associated with “0”.

  FIG. 4 is a diagram illustrating an example of a configuration of a circuit that operates the resistance change element 10 according to the first embodiment of the present invention and an operation example when data is written to the resistance change element 10. As shown in FIG. 4, this circuit includes a resistance change element 10, a first terminal 11, and a second terminal 12. The second electrode 4 of the resistance change element 10 is electrically connected to the first terminal 11, and the first electrode 2 is electrically connected to the second terminal 12.

  FIG. 5 shows a case where data is written to the variable resistance element 10 according to the first embodiment of the present invention (writing process), a case where data is erased (erasing process), a break process and an additional processing process performed before the first writing. It is a figure which shows the change of the resistance value of the transition metal oxide layer 3 in. In the writing process, the erasing process, the break process, and the additional processing process, as shown in FIG. 4, the second terminal 12 is grounded (ground: GND), and a voltage pulse is supplied to the first terminal 11. The voltage pulse is specified with reference to the first electrode 2 and the ground point.

  When the variable resistance element 10 is in the initial state (when the resistance value of the transition metal oxide layer 3 is at the initial resistance value R0), a positive break voltage pulse (voltage value V0) is supplied to the first terminal 11. Then, as shown in FIG. 5, the resistance value of the transition metal oxide layer 3 decreases from the initial resistance value R0 to the first resistance value R1, and the positive additional processing voltage pulse (voltage value V1) is the first. When supplied to one terminal 11, the resistance value of the transition metal oxide layer 3 decreases from the first resistance value R1 to the second resistance value R2. Next, when a negative write voltage pulse (voltage value Vw) is supplied to the first terminal 11, the resistance value of the transition metal oxide layer 3 is lower than the second resistance value R2, as shown in FIG. It decreases to the resistance value RL (first writing). As a result, 1-bit data representing “1” is written. Next, when a positive first erase voltage pulse (voltage value Ve) is supplied to the first terminal 11, the resistance value of the transition metal oxide layer 3 increases from the low resistance value RL to the high resistance value RH. (First erase). As a result, 1-bit data representing “0” is written.

  Note that the resistance value of the transition metal oxide layer 3 is the highest in the initial resistance value R0, and the high resistance value RH is higher than the low resistance value RL. Therefore, the relationship of R0> RH> RL is established. In the present embodiment, the first resistance value R1 after the initial process and the second resistance value R2 after the additional processing process are in a relationship of R1> R2.

  Thereafter, when the resistance value of the transition metal oxide layer 3 is the high resistance value RH, when a negative write voltage pulse (voltage value Vw) is supplied to the first terminal 11, the transition metal oxide layer 3 The resistance value changes from the high resistance value RH to the low resistance value RL. On the other hand, when the resistance value of the transition metal oxide layer 3 is the low resistance value RL, when a positive erase voltage pulse (voltage value Ve) is supplied to the first terminal 11, the transition metal oxide layer 3 The resistance value changes from the low resistance value RL to the high resistance value RH.

  Also in this circuit, the variable resistance element 10 functions as a memory that operates stably and at high speed even after the break process, immediately after the additional process, and after repeating the writing process and the erasing process one million times.

  FIG. 6 is a diagram illustrating an example of a configuration of a circuit that operates the resistance change element 10 according to the first embodiment of the present invention and an operation example in the case of reading data written in the resistance change element 10. As shown in FIG. 6, when reading data, the second terminal 12 is grounded (ground: GND), and a read voltage is supplied to the first terminal 11. This read voltage is specified with reference to the first electrode 2 and the ground point, and is a voltage that does not change the resistance of the resistance change element 10 even when supplied to the resistance change element 10.

  FIG. 7 is a diagram showing the relationship between the current value of the current flowing through the circuit including the resistance change element 10 according to the first embodiment of the present invention and the resistance value of the transition metal oxide layer 3 when reading data. . When a read voltage is supplied to the first terminal 11, a current corresponding to the resistance value of the transition metal oxide layer 3 flows through the circuit. That is, as shown in FIG. 7, when the transition metal oxide layer 3 has the low resistance value RL, the current having the current value Ia flows through the circuit, and when the transition metal oxide layer 3 has the high resistance value RH, the current having the current value Ib flows through the circuit. Flowing.

  As shown in FIG. 6, when the second terminal 12 is grounded and, for example, a read voltage of +0.5 V is supplied to the first terminal 11, the current flowing between the first terminal 11 and the second terminal 12 By detecting the value, it is determined whether the transition metal oxide layer 3 is in a high resistance state or a low resistance state. Specifically, if the detected current value is Ia, it is determined that the transition metal oxide layer 3 has the low resistance value RL. As a result, it can be seen that the data written in the resistance change element 10 is “1”. On the other hand, if the detected current value is Ib, it is determined that the transition metal oxide layer 3 has the high resistance value RH. As a result, it can be seen that the data written in the variable resistance element 10 is “0”. In this way, the data written in the variable resistance element 10 is read.

  The resistance change element 10 of the present embodiment does not change its resistance value even when the power is turned off. Therefore, a nonvolatile memory device can be realized by using the variable resistance element 10.

  Hereinafter, three examples are shown as comparative examples for the present embodiment. In addition, since the structure of the resistance change element of the following comparative examples 1-3 is the same as that of the resistance change element 10 of this Embodiment (The thickness of the 2nd transition metal oxide layer 3b is 5.0 nm), it demonstrates. Is omitted.

[Comparative Example 1]
FIG. 8 is a graph showing an example of a change in the resistance state of the transition metal oxide layer included in the resistance change element of Comparative Example 1. In the comparative example 1, unlike the case of the above embodiment, the break process and the additional process are not performed. That is, a writing process in which a writing voltage pulse having a voltage value of −1.9 V and a pulse width of 100 ns is applied between both electrodes to the transition metal oxide layer having an initial resistance value, and a voltage value of +2.5 V and a pulse width of 100 ns The erasing process of applying the erasing voltage pulse between both electrodes is only executed repeatedly.

  As shown in FIG. 8, in Comparative Example 1, the resistance value of the transition metal oxide layer remains the initial resistance value, and no change in the resistance state is observed. Therefore, the variable resistance element in the state of Comparative Example 1 cannot be used for the memory.

[Comparative Example 2]
9A and 9B are graphs showing an example of changes in the resistance state of the transition metal oxide layer included in the variable resistance element of Comparative Example 2. In this comparative example 2, unlike the case of the above-described embodiment, only the break process is performed and the additional process process is not performed. That is, as a break process, an initial voltage pulse having a voltage value of +4.5 V and a pulse width of 100 μs is applied twice between both electrodes, whereby the resistance value of the transition metal oxide layer is increased from an initial resistance value of about 38 MΩ to about 280 kΩ. After a significant decrease, a writing process in which a writing voltage pulse having a voltage value of −1.9 V and a pulse width of 100 ns is applied between both electrodes, and an erasing voltage pulse having a voltage value of +2.5 V and a pulse width of 100 ns are applied to both electrodes. The erasing process applied between them is repeatedly executed.

  As shown in FIG. 9A, in Comparative Example 2, after the break voltage pulse is applied, the transition metal oxide layer shows a relatively stable resistance change as in the case of the above embodiment. As shown, after the writing process and the erasing process are performed 1 million times, the resistance value of the transition metal oxide layer rises to about the initial resistance value, and the resistance state is maintained even when the writing voltage pulse and the erasing voltage pulse are applied. Change is not seen. Therefore, the variable resistance element in the state of Comparative Example 2 cannot be used for a memory that requires endurance characteristics about one million times. The difference between the present embodiment and Comparative Example 2 is the difference in the presence or absence of an additional processing process, and it can be seen that the additional processing process greatly affects the endurance characteristics.

[Comparative Example 3]
FIG. 10 is a graph showing an example of a change in the resistance state of the transition metal oxide layer included in the resistance change element of Comparative Example 3. In the comparative example 3, the break process and the additional process process are performed. However, unlike the above-described embodiment, the voltage values of the write voltage pulse and the erase voltage pulse are in a relationship of | Ve | <| Vw |. Specifically, the voltage value of the write voltage pulse is set to -2.5V, and the voltage value of the erase voltage pulse is set to + 1.9V. The voltage pulse also has a pulse width of 100 ns.

  As shown in FIG. 10, in Comparative Example 3, the resistance value of the resistance change layer is decreased from the initial resistance value by applying a break voltage pulse between both electrodes, and further resistance is applied by applying an additional processing voltage pulse. The value is further reduced. After that, the resistance value is further decreased by the first writing process, but no change in the resistance state is observed after repeating the writing process and the erasing process. Therefore, the variable resistance element in the state of Comparative Example 3 cannot be used for the memory.

  As can be seen from these comparative examples 1 to 3, when the break process is not executed, and when the voltage value Ve of the erase voltage pulse and the voltage value Vw of the write voltage pulse are not in a relationship of | Ve | ≧ | Vw | Cannot realize an operable resistance change element. Further, when the additional process is not performed even though the break process is performed, even when the voltage value Ve of the erase voltage pulse and the voltage value Vw of the write voltage pulse are in a relationship of | Ve | ≧ | Vw | A variable resistance element with good endurance characteristics cannot be realized.

[Additional process and resistance change operation]
We examined how the additional processing process affects the endurance characteristics. FIG. 11 shows that the resistance value of the transition metal oxide layer 3 of the resistance change element 10 according to the first embodiment of the present invention changes the number of voltage pulses applied in the additional process from the resistance value at the end of the break process. It is a graph which shows how it changes in the case of. In the first embodiment of the present invention, the voltage value of the additional processing voltage pulse is +4.5 V and the pulse width is 500 μs. For comparison, the voltage value is +3.0 V, +3.5 V, and +4.0 V. A change in resistance value due to a voltage pulse having a width of 500 μs is also shown. Note that the cumulative pulse application time indicated by the horizontal axis of the graph of FIG. 11 is the pulse width of 500 μs of the additional processing voltage pulse × number of times of pulse application. The unit of cumulative pulse application time is expressed in ms.

  Referring to FIG. 11, it can be seen that the manner of change from the resistance value at the end of the break process differs depending on the voltage value of the additional processing voltage pulse. When the voltage value of the additional processing voltage pulse is +3.0 V, the resistance value of the transition metal oxide layer 3 varies considerably every time the pulse is applied, but the resistance at the end of the break process even when the cumulative pulse application time is 50 ms. The value has not changed much. When the voltage value of the additional processing voltage pulse is +3.5 V, the resistance value is higher than the resistance value at the end of the break process until the cumulative pulse application time is about 15 ms, but gradually decreases when the cumulative pulse application time is 15 ms or more. is doing. When the voltage value of the additional processing voltage pulse is +4.0 V and +4.5 V, the resistance value of the transition metal oxide layer 3 rapidly decreases when the cumulative pulse application time is about 5 ms, and when the cumulative pulse application time is 5 ms or more, the resistance value The way of lowering is saturated.

  FIG. 12 shows the result of examining the endurance characteristics by changing the voltage value of the additional processing voltage pulse and the cumulative pulse application time of each voltage value. When a plurality of resistance change elements are subjected to resistance change operation under each condition in FIG. 12, the endurance characteristics are good in all resistance change elements under the conditions indicated by ○, and the endurance characteristics are good under the conditions indicated by Δ. Resistance change elements and defective resistance change elements, and under the conditions indicated by x, the endurance characteristics were defective in all the resistance change elements. Compared with the result of the change in resistance value in FIG. 11, it can be seen that the endurance characteristics become better as the resistance value decreases in the additional process. Therefore, by executing the additional processing step using a plurality of additional processing voltage pulses rather than one additional processing voltage pulse, the accumulated pulse application time is increased, and better endurance characteristics can be obtained.

  Here, the mechanism of the resistance value change of the transition metal oxide layer 3 in the break process and the additional process of the variable resistance element 10 will be described again with reference to FIG.

  In the break process (S101) in which a positive polarity break voltage pulse having a voltage value equal to or higher than the erase voltage pulse is applied to the second electrode 4, the resistance value of the transition metal oxide layer 3 is changed from the initial resistance value R0 to the first resistance value R0. The resistance value decreases to R1.

  First, the mechanism of the change from the initial resistance value R0 to the first resistance value R1 by this break voltage pulse will be qualitatively described. By applying a break voltage pulse, oxygen ions in a minute portion of the second transition metal oxide layer 3b abruptly change at the interface of the second electrode 4 (interface between the second electrode 4 and the second transition metal oxide layer 3b). ) Moving from the vicinity to the first transition metal oxide layer 3a side, an oxygen concentration is smaller than the oxygen concentration of the second transition metal oxide layer 3b, so that a small-sized conductive path with low resistance is formed. The Thereafter, oxygen ions having a negative charge move in the conductive path formed in the second transition metal oxide layer 3b by the positive electric field generated by the positive polarity break voltage pulse applied to the second electrode 4 and move to the second electrode 4. Accumulated at the interface. That is, by applying a break voltage pulse having a voltage value equal to or higher than the erase voltage pulse, formation of a conductive path in the second transition metal oxide layer 3b and accumulation of oxygen ions at the interface of the second electrode 4 are almost simultaneously performed. It is thought to happen.

  Since the amount of oxygen ions accumulated at the interface of the second electrode 4 is considerably smaller than the initial oxygen concentration of the second transition metal oxide layer 3b, comparing the initial resistance value R0 and the first resistance value R1, The ratio R1 / R0 of resistance values is 1/10 or less. Further, the magnitude of the first resistance value R1 is often higher than the resistance value RH of the transition metal oxide layer 3 when an erase voltage pulse is applied in the erase process. The reason is that since the voltage of the break voltage pulse is larger than the voltage of the erase voltage pulse, the amount of oxygen ions accumulated at the interface of the second electrode 4 by the positive electric field is greater when the break voltage pulse is applied. This is because it is considered to be larger than that at the time of application.

  Next, in the additional processing step (S102) in which a positive polarity additional processing voltage pulse having a voltage value equal to or higher than the erase voltage pulse is applied to the second electrode 4, the resistance value of the transition metal oxide layer 3 is the first resistance. The value R1 decreases to the second resistance value R2.

  The mechanism of the resistance change from the first resistance value R1 to the second resistance value R2 is unknown at present, but is presumed as follows. Oxygen ions having a negative charge move in the conductive path formed in the second transition metal oxide layer 3b by the positive electric field generated by the positive additional processing voltage pulse, and are accumulated at the interface of the second electrode 4 to form the transition metal. The resistance value of the oxide layer 3 is expected to be higher than the first resistance value R1. However, in actuality, the second resistance value R2 is smaller than the first resistance value R1. This change is well explained by assuming that the size of the conductive path formed in the break process is increased by an additional process. In other words, the effect of increasing the conductive path size and decreasing the resistance value is superior to increasing the amount of oxygen ions accumulated at the interface of the second electrode 4 and increasing the resistance value, and the transition metal oxide layer 3 This resistance value is considered to have decreased to a second resistance value R2 that is smaller than the first resistance value R1. Also, as shown in FIG. 11, when the voltage value or pulse width of the additional processing voltage pulse is sufficiently large, the value of the current flowing through the conductive path or the time during which the current flows increases, and the conductive path size increases and the resistance increases. The value is estimated to decrease.

  Next, in step S103 in which the writing process and the erasing process are repeated, the resistance value of the transition metal oxide layer 3 is changed to RL by the writing process (S103A) by the writing voltage pulse, and the transition metal oxide layer is changed by the erasing process (S103B). The resistance value of 3 changes to RH.

  The mechanism of this resistance change will be qualitatively explained. By applying a negative write voltage pulse, oxygen ions are transferred to the second electrode 4 in the conductive path formed in the second transition metal oxide layer 3b in the break process (S101) and the additional process (S102). The resistance value of the transition metal oxide layer 3 decreases to RL as it moves away from the interface. On the other hand, by applying a positive erasing voltage pulse, oxygen ions move in the direction toward the second electrode 4 in the conductive path formed in the second transition metal oxide layer 3 b, and the second electrode 4. And the resistance value of the transition metal oxide layer 3 increases to a high resistance value RH. Since the erase voltage pulse is smaller than the voltage of the additional processing voltage pulse, the high resistance value RH after the erasing process is smaller than the second resistance value R2 after the additional processing process (S102). In addition, since the voltage value and pulse width of the erase voltage pulse and the write voltage pulse are smaller than the additional processing voltage pulse, the size of the conductive path does not change even when repeatedly applied, and the resistance value RL is relatively stable. It is possible to repeatedly change the high resistance value RH.

  Next, a qualitative description will be given of the difference in endurance characteristics between when the break process (S101) and the additional process (S102) are performed and when the additional process (S102) is omitted and only the break process (S102) is performed. To do.

  When the amount of oxygen ions moving in the conductive path is exactly the same in the erasing process and the writing process, even if the erasing process and the writing process are repeated many times, it is stably between the low resistance value RL and the high resistance value RH. Change. However, it is very difficult in practice to make the amount of oxygen ions moving in the erasing process and the writing process exactly the same. Therefore, for example, when the amount of oxygen ion movement in the erasing process is slightly larger than the amount of oxygen ion movement in the writing process, the oxygen ions accumulated at the interface of the second electrode 4 in the initial erasing process and writing process. Although the amount can be almost ignored, if the erase process and the write process are performed many times such as 1 million times, the amount of oxygen ions accumulated at the interface of the second electrode 4 cannot be ignored. In that case, as the size of the conductive path is smaller, the increase in the resistance value due to the amount of accumulated oxygen ions becomes more significant. It has been stated that the size of the conductive path is larger when the break process and the additional process are performed than when only the break process is performed. Therefore, when the additional process is omitted and only the break process is performed, the resistance value increases faster with the number of repetitions because the size of the conductive path is smaller. It is thought that it will stop showing.

  As described above, according to the driving method of the variable resistance element in the first embodiment, the break process for reducing the initial resistance value of the transition metal oxide layer is performed before the first writing process, and thereafter In addition, by performing an additional processing process for further reducing the resistance value, when the writing process and the erasing process are repeated after those processes, the transition metal oxide layer has a low resistance value and a high resistance value. A good endurance characteristic of stably repeating the change between the two is obtained.

(Embodiment 2)
The second embodiment is a nonvolatile memory device including the variable resistance element described in the first embodiment. The configuration and operation of this nonvolatile memory device will be described below.

[Configuration of non-volatile storage device]
FIG. 13 is a block diagram showing an example of the configuration of the nonvolatile memory device 200 according to Embodiment 2 of the present invention. As illustrated in FIG. 13, the nonvolatile memory device 200 includes a memory cell array 201 including a resistance change element, an address buffer 202, a control unit 203, a row decoder 204, a word line driver 205, a column decoder 206, And a bit line / plate line driver 207. The bit line / plate line driver 207 includes a sense circuit, and can measure a current flowing in the bit line or the plate line and a generated voltage.

  As shown in FIG. 13, the memory cell array 201 includes two word lines W1 and W2 extending in the vertical direction, two bit lines B1 and B2 extending in the horizontal direction across the word lines W1 and W2, Corresponding to each intersection of two plate lines P1, P2 extending in the lateral direction provided corresponding to the bit lines B1, B2 on a one-to-one basis, and word lines W1, W2 and bit lines B1, B2 in a matrix form Select transistors T211, T212, T221, T222, and memory cells MC211, MC212, provided in a matrix corresponding to the four select transistors T211, T212, T221, T222 in a one-to-one correspondence. MC221 and MC222 are provided.

  Note that the number or number of these components is not limited to the above. For example, the memory cell array 201 includes four memory cells as described above, but this is an example, and a configuration including five or more memory cells may be employed.

  In the above configuration example, the plate line is arranged in parallel with the bit line, but the plate line may be arranged in parallel with the word line. The plate line is configured to apply a common potential to the connected transistors. However, the plate line includes a source line selection circuit and a driver having the same configuration as the row decoder 204 and the word line driver 205, and the selected source line and The non-selected source line may be driven with a different voltage (including polarity).

  The memory cells MC211, MC212, MC221, and MC222 described above correspond to the resistance change element 10 described with reference to FIG. 4 in the first embodiment. The configuration of the memory cell array 201 will be further described with reference to FIG. 4. The selection transistor T211 and the memory cell MC211 are provided between the bit line B1 and the plate line P1, and the source of the selection transistor T211 and the memory The terminals 11 of the cells MC211 are arranged in series to be connected. More specifically, the selection transistor T211 is connected to the bit line B1 and the memory cell MC211 between the bit line B1 and the memory cell MC211. The memory cell MC211 is connected between the selection transistor T211 and the plate line P1. Are connected to the selection transistor T211 and the plate line P1. The gate of the selection transistor T211 is connected to the word line W1.

  The connection state of the other three selection transistors T212, T221, T222 and the three memory cells MC212, MC221, MC222 arranged in series with the selection transistors T212, T221, T222 is the selection transistor T211 and the memory. Since it is the same as that of the cell MC211, description is abbreviate | omitted.

  With the above configuration, when a predetermined voltage (activation voltage) is supplied to the respective gates of the selection transistors T211, T212, T221, and T222 via the word lines W1 and W2, the selection transistors T211, T212, T221, and The drain and source of T222 become conductive.

  The address buffer 202 receives an address signal ADDRESS from an external circuit (not shown), outputs a row address signal ROW to the row decoder 204 based on the address signal ADDRESS, and outputs a column address signal COLUMN to the column decoder 206. . Here, the address signal ADDRESS is a signal indicating the address of the selected memory cell among the memory cells MC211, MC212, MC221, and MC222. The row address signal ROW is a signal indicating a row address among the addresses indicated by the address signal ADDRESS, and the column address signal COLUMN is a signal similarly indicating a column address.

  The control unit 203 selects any one of the break mode, the additional processing mode, the write mode, the erase mode, and the read mode according to the mode selection signal MODE received from the external circuit. Hereinafter, in the case of voltage application, each voltage is applied with reference to the plate line.

  In the break mode, the control unit 203 outputs a control signal CONT instructing “break voltage application” to the bit line / plate line driver 207. Following this break mode, an additional processing mode is selected.

  In the additional processing mode, the control unit 203 outputs a control signal CONT instructing “application of additional processing voltage” to the bit line / plate line driver 207. These break mode and additional processing mode are modes that are selected before the first writing is performed.

  In the write mode, the control unit 203 outputs a control signal CONT instructing “application of write voltage” to the bit line / plate line driver 207 in accordance with the input data Din received from the external circuit.

In the read mode, the control unit 203 outputs a control signal CONT instructing “read voltage application” to the bit line / plate line driver 207. In this read mode, the control unit 203 further receives a signal I _READ output from the bit line / plate line driver 207, and outputs output data Dout indicating a bit value corresponding to the signal I _READ to an external circuit. This signal I _READ is a signal indicating the current value of the current flowing through the plate lines P1 and P2 in the read mode.

  Further, in the erase mode, the control unit 203 confirms the write state of the memory cells MC211, MC212, MC221, and MC222, and sends a control signal CONT instructing “application of erase voltage” to the bit line / plate according to the write state. Output to the line driver 207.

  The row decoder 204 receives the row address signal ROW output from the address buffer 202, and selects one of the two word lines W1 and W2 according to the row address signal ROW. The word line driver 205 applies an activation voltage to the word line selected by the row decoder 204 based on the output signal of the row decoder 204.

  The column decoder 206 receives the column address signal COLUMN output from the address buffer 202, and selects one of the two bit lines B1 and B2 in accordance with the column address signal COLUMN. One of the two plate lines P1 and P2 corresponding to the bit line is selected.

When the bit line / plate line driver 207 receives a control signal CONT instructing “break voltage application” from the control unit 203, the bit line / plate line driver 207 applies a break voltage V _BREAK (break voltage pulse) between each bit line and each plate line.

When the bit line / plate line driver 207 receives a control signal CONT instructing “application of additional processing voltage” from the control unit 203, the additional processing voltage V _ADD (additional processing voltage pulse) is applied between each bit line and each plate line. ) Is applied.

When the bit line / plate line driver 207 receives the control signal CONT instructing “application of write voltage” from the control unit 203, the bit line / plate line driver 207 determines the bit line selected by the column decoder 206 based on the output signal of the column decoder 206. A write voltage V _WRITE (write voltage pulse) is applied between the selected plate lines.

When the bit line / plate line driver 207 receives a control signal CONT instructing “reading voltage application” from the control unit 203, the bit line / plate line driver 207 determines the bit line selected by the column decoder 206 based on the output signal of the column decoder 206. Similarly, a read voltage V _READ is applied between the selected plate lines. Thereafter, the bit line / plate line driver 207 outputs a signal I _READ indicating the value of the current flowing through the plate line to the control unit 203.

Further, when the bit line / plate line driver 207 receives the control signal CONT instructing “application of erase voltage” from the control unit 203, the bit line / plate line driver 207 determines the bit line selected by the column decoder 206 based on the output signal of the column decoder 206. Similarly, an erase voltage V _RESET (erase voltage pulse) is applied between the selected plate lines.

Here, the voltage value of the break voltage V _BREAK is set to +4.5 V, for example, and the pulse width is set to 100 μs. Further, the voltage value of the additional processing voltage V _ADD is set to, for example, +4.5 V, and the pulse width is set to 500 μs. The voltage value of the write voltage V _WRITE is set to, for example, −1.9 V, and the pulse width is set to 100 ns. The voltage value of the read voltage V _READ is set to +0.5 V, for example. Furthermore, the voltage value of the erase voltage V _RESET is set to +2.5 V, for example, and the pulse width is set to 100 ns.

  Functionally, the control unit 203 and the bit line / plate line driver 207 constitute a pulse voltage application unit that applies a predetermined pulse voltage to a selected memory cell (resistance change element). Such a pulse voltage application unit includes at least (1) applying a write voltage pulse having a first polarity to a memory cell, thereby changing the resistance state of the transition metal oxide layer 3 of the memory cell to a high resistance state. (2) by applying an erasing voltage pulse having a second polarity different from the first polarity to the memory cell, thereby changing the transition metal oxide layer 3 of the memory cell. An erase process for changing the resistance state from the low resistance state to the high resistance state, and (3) a break voltage pulse having a second polarity having a voltage value equal to or higher than the erase voltage pulse is stored in the memory before the first write process. A break process for reducing the initial resistance value of the transition metal oxide layer 3 of the memory cell by applying to the cell; and (4) after the first break Before the writing process, by applying an additional processing voltage pulse having a second polarity having a voltage value equal to or higher than the erase voltage pulse to the memory cell, the transition metal oxide layer 3 of the memory cell after the breaking process is applied. It is a process part which performs the additional process process which reduces the resistance value of.

[Operation of non-volatile storage device]
Hereinafter, an operation example of the nonvolatile memory device 200 configured as described above is described with respect to the break mode, the additional processing mode (the mode selected before the first write), the write mode (in the memory cell). Each mode of input data Din), erase mode (mode for erasing data written in memory cells), and read mode (mode for outputting (reading) data written to memory cells as output data Dout) This will be explained separately. Here, the break process in the first embodiment corresponds to the break mode, the additional process process corresponds to the additional process mode, the write process corresponds to the write mode, and the erase process corresponds to the erase mode.

  For convenience of explanation, it is assumed that the address signal ADDRESS is a signal indicating the address of the memory cell MC211.

[Break mode]
The control unit 203 outputs a control signal CONT indicating “break voltage application” to the bit line / plate line driver 207 before executing the first writing. When the bit line / plate line driver 207 receives a control signal CONT for instructing “break voltage application” from the control unit 203, the bit line / plate line driver 207 applies a break voltage V _BREAK (break voltage pulse) to each bit line and Set to ground.

As a result, a break voltage V _BREAK , that is, a break voltage pulse having a voltage value of +4.5 V and a pulse width of 100 μs is applied to all the memory cells. Here, the break voltage pulse is applied once to a plurality of times until the resistance value of the transition metal oxide drops to the first resistance value R1 in each memory cell. The first resistance value R1 is preferably larger than the resistance value RH in the high resistance state. This is because it is expected that the conductive path can be prevented from becoming too large during the break process, and the endurance characteristics can be further improved. After applying each break voltage pulse, the resistance value of the variable resistance element is read in the read mode to check whether the break process is completed. Here, the break voltage pulse having the same voltage is applied a plurality of times to cause a break, but the break voltage pulse voltage may be gradually increased from a predetermined voltage to cause a break.

  Thereby, the break process in the first embodiment is executed by the pulse voltage application unit, and the resistance value of the transition metal oxide layer 3 is decreased from the initial resistance value R0 to the first resistance value R1 in all the memory cells.

[Additional processing mode]
The control unit 203 outputs a control signal CONT indicating “application of additional processing voltage” to the bit line / plate line driver 207 before executing the first writing. When the bit line / plate line driver 207 receives the control signal CONT instructing “application of additional processing voltage” from the control unit 203, the bit line / plate line driver 207 applies an additional processing voltage V _ADD (additional processing voltage pulse) to each bit line, Ground each plate wire.

As a result, an additional processing voltage V _ADD , that is, an initial voltage pulse having a voltage value of, for example, +4.5 V and a pulse width of 500 μs is applied to all the memory cells. Here, the initial voltage pulse is applied until the resistance value of the transition metal oxide layer 3 basically decreases in all memory cells from the first resistance value R1 to the second resistance value R2 which is lower than the first resistance value R1. The The second resistance value R2 may be set by experimentally checking in advance. Further, the cumulative application time of the additional processing pulse is set to a time during which the resistance value of the transition metal oxide layer 3 is reduced from the first resistance value R1 to the second resistance value R2 lower than the first resistance value R1, for example. You may set to 10 ms. As a result, the additional process in the first embodiment is performed by the pulse voltage application unit, and the resistance value of the transition metal oxide layer 3 is lower than the first resistance value R1 in all the memory cells. It decreases to the resistance value R2.

[Write mode]
The control unit 203 receives input data Din from an external circuit. Here, when the input data Din is “1”, the control unit 203 outputs a control signal CONT indicating “application of write voltage” to the bit line / plate line driver 207. On the other hand, the control unit 203 does not output the control signal CONT when the input data Din is “0”.

When the bit line / plate line driver 207 receives the control signal CONT indicating “application of write voltage” from the control unit 203, the write voltage V _{WRITE is} applied between the bit line B1 selected by the column decoder 206 and the selected plate line P1. (Write voltage pulse) is applied.

  At this time, an activation voltage is applied to the word line W1 selected by the row decoder 204 by the word line driver 205. For this reason, the drain and the source of the selection transistor T211 are in a conductive state.

As a result, a write voltage V _WRITE , that is, a write voltage pulse having a voltage value of −1.9 V and a pulse width of 100 ns is applied to the memory cell MC211. Thereby, the write process in the first embodiment is executed by the pulse voltage application unit, and the resistance value of the transition metal oxide layer 3 of the memory cell MC211 changes from the high resistance state to the low resistance state. On the other hand, no write voltage pulse is applied to the memory cells MC221 and MC222, and no activation voltage is applied to the gate of the select transistor T212 connected in series with the memory cell MC212, so that the resistance of the memory cells MC212, MC221 and MC222 The state does not change.

  In this way, only the memory cell MC211 can be changed to the low resistance state, whereby 1-bit data indicating “1” corresponding to the low-resistance state is written into the memory cell MC211 (the 1-bit data is Remembered).

  When writing to the memory cell MC211 is completed, a new address signal ADDRESS is input to the address buffer 202, and the operation in the write mode of the nonvolatile memory device 200 is repeated for the memory cells other than the memory cell MC211. It is.

[Read mode]
The control unit 203 outputs a control signal CONT instructing “application of read voltage” to the bit line / plate line driver 207.

When the bit line / plate line driver 207 receives the control signal CONT instructing “application of read voltage” from the control unit 203, the read voltage V between the bit line B1 selected by the column decoder 206 and the selected plate line P1. _{Apply READ} .

  At this time, an activation voltage is applied to the word line W1 selected by the row decoder 204 by the word line driver 205. For this reason, the drain and the source of the selection transistor T211 are in a conductive state.

Therefore, as the write voltage V _READ, for example, the measured voltage of the voltage value + 0.5V, is applied to the memory cell MC211. Thus, a read current indicating a current value corresponding to the resistance value of the memory cell MC211 flows from the bit line B1 to the plate line P1 via the memory cell MC212. The write voltage V _READ is a sufficiently low voltage that does not change the resistance value of the memory cell even when applied to the memory cell.

  Note that no measurement voltage is applied to the memory cells MC221 and MC222, and no activation voltage is applied to the gate of the selection transistor T212 connected in series with the memory cell MC212. Current does not flow.

Next, a sense amplifier (not shown) connected to the bit line compares the current value of the read current flowing through the bit line B1 with the current value flowing through the reference resistance value, and _generates a signal I _READ indicating the result. Output to the control unit 203.

The control unit 203 outputs output data Dout corresponding to the current value indicated by the signal I _READ to the outside. For example, when the current value indicated by the signal I _READ corresponds to the current value of the current flowing when the memory cell MC211 is in the low resistance state, the control unit 203 outputs the output data Dout indicating “1”.

  In this way, a current corresponding to the resistance value of the memory cell MC211 flows only in the memory cell MC211 and the current flows out from the bit line B1 to the plate line P1. Thereby, 1-bit data indicating “1” is read from the memory cell MC211.

  Note that the resistance value of the memory cell MC211 may be measured by a voltage in a process in which the voltage precharged in the memory cell MC211 decays with a time constant corresponding to the resistance value of the memory cell MC211.

  When reading from the memory cell MC211 is completed, a new address signal ADDRESS is input to the address buffer 202, and the operation in the read mode of the nonvolatile memory device 200 is repeated for memory cells other than the memory cell MC211.

[Erase mode]
In the erase mode, first, the control unit 203 acquires the resistance value state (memory state) of the memory cell MC211 by executing the read mode. When it is determined that bit data indicating “1” is stored in the memory cell MC211 (when it is determined that the memory cell MC211 is in the low resistance state), the control unit 203 indicates “application of erase voltage”. A control signal CONT is output to the bit line / plate line driver 207. On the other hand, when it is determined that the bit data indicating “0” is stored in the memory cell MC211 (when it is determined that the memory cell MC211 is in the high resistance state), the control unit 203 does not output the control signal CONT. .

When the bit line / plate line driver 207 receives the control signal CONT indicating “application of erase voltage” from the control unit 203, the bit line / plate line driver 207 erases the erase voltage V _RESET between the bit line B1 selected by the column decoder 206 and the selected plate line P1. (Erase voltage pulse) is applied.

  At this time, an activation voltage is applied to the word line W1 selected by the row decoder 204 by the word line driver 205. For this reason, the drain and the source of the selection transistor T211 are in a conductive state.

As a result, an erase voltage V _RESET , that is, an erase voltage pulse having a voltage value of +2.5 V and a pulse width of 100 ns is applied to the memory cell MC211. Thereby, the erasing process in the first embodiment is performed by the pulse voltage application unit, and the transition metal oxide layer 3 of the memory cell MC211 changes from the low resistance state to the high resistance state. On the other hand, the erase voltage pulse is not applied to the memory cells MC221 and MC222, and the activation voltage is not applied to the gate of the select transistor T212 connected in series with the memory cell MC212, so that the resistances of the memory cells MC212, MC221 and MC222 The state does not change.

  In this way, only the memory cell MC211 can be changed from the low resistance state to the high resistance state. Thereby, 1-bit data indicating “1” corresponding to the low resistance state stored in the memory cell MC211 is reset to “0” corresponding to the high resistance state.

  When the reset of the memory cell MC211 is completed, a new address signal ADDRESS is input to the address buffer 202, and the operation in the reset mode of the nonvolatile memory device 200 is repeated for the memory cells other than the memory cell MC211. .

  By operating as described above, the nonvolatile memory device 200 can realize a stable high-speed operation.

(Embodiment 3)
The third embodiment is a cross-point type nonvolatile memory device including the variable resistance element described in the first embodiment. Here, the cross-point type nonvolatile storage device is a storage device in a mode in which an active layer is interposed at an intersection (a three-dimensional intersection) between a word line and a bit line.

  Hereinafter, the configuration and operation of the nonvolatile memory device according to Embodiment 3 will be described.

[Configuration of non-volatile storage device]
FIG. 14 is a block diagram showing an example of the configuration of the nonvolatile memory device 100 according to Embodiment 3 of the present invention. As shown in FIG. 14, the cross-point type nonvolatile memory device 100 includes a memory cell array 101 including a resistance change element, an address buffer 102, a control unit 103, a row decoder 104, a word line driver 105, A column decoder 106 and a bit line driver 107 are provided. The bit line driver 107 includes a sense circuit, and can measure a current flowing through the bit line and a generated voltage.

  As shown in FIG. 15, the memory cell array 101 includes a plurality of word lines W1, W2, W3,... Formed in parallel to each other and extending in the lateral direction, and these word lines W1, W2, W3,. A plurality of bit lines B1, B2, B3,... Are formed so as to intersect and extend in parallel with each other in the vertical direction. Here, the word lines W1, W2, W3,... Are formed in a first plane parallel to the main surface of the substrate (not shown), and the bit lines B1, B2, B3,. It is formed in a second plane located above or below one plane and substantially parallel to the first plane. Therefore, the word lines W1, W2, W3,... And the bit lines B1, B2, B3,... Are three-dimensionally crossed, and a plurality of memory cells MC11, MC12, MC13, MC21, MC22 correspond to the three-dimensional intersections. , MC23, MC31, MC32, MC33,... (Hereinafter referred to as “memory cells MC11, MC12,...”).

  Each memory cell MC includes resistance change elements connected in series and current control elements D11, D12, D13, D21, D22, D23, D31, D32, D33,. The resistance change elements are connected to the bit lines B1, B2, B3,..., And the current control elements are connected to the resistance change elements and the word lines W1, W2, W3,. As the resistance change element, the resistance change element 10 according to the first embodiment can be used. As the current control element, an MIM (Metal Insulator Metal) diode, an MSM (Metal Semiconductor Metal) diode, a varistor, or the like can be used.

  The address buffer 102 receives an address signal ADDRESS from an external circuit (not shown), outputs a row address signal ROW to the row decoder 104 based on the address signal ADDRESS, and outputs a column address signal COLUMN to the column decoder 106. . Here, the address signal ADDRESS is a signal indicating the address of the selected memory cell among the memory cells MC12, MC21,. The row address signal ROW is a signal indicating a row address among the addresses indicated by the address signal ADDRESS, and the column address signal COLUMN is a signal similarly indicating a column address.

  Hereinafter, in the case of voltage application, each voltage is applied with reference to the bit line.

  The control unit 103 includes a break mode, an additional processing mode (a mode selected before the first writing), a writing mode (the above writing process and erasing process) according to the mode selection signal MODE received from the external circuit. And one of the read modes is selected.

  In the break mode, the control unit 103 outputs a break voltage pulse to the word line driver 105.

  Further, in the additional processing mode, the control unit 103 outputs an additional processing voltage pulse to the word line driver 105.

  In the write mode, the control unit 103 outputs a write voltage pulse or an erase voltage pulse to the word line driver 105 according to the input data Din received from the external circuit.

Further, in the read mode, the control unit 103 outputs a read voltage to the word line driver 105. In this read mode, the control unit 103 further receives a signal I _READ output from the bit line driver 107, and outputs output data Dout indicating a bit value corresponding to the signal I _READ to an external circuit. This signal I _READ is a signal indicating the current value of the current flowing through the word lines W1, W2, W3,.

  The row decoder 104 receives the row address signal ROW output from the address buffer 102, and selects any one of the word lines W1, W2, W3,... According to the row address signal ROW. The word line driver 105 applies an activation voltage to the word line selected by the row decoder 104 based on the output signal of the row decoder 104.

  The column decoder 106 receives the column address signal COLUMN output from the address buffer 102, and selects any one of the bit lines B1, B2, B3,... According to the column address signal COLUMN.

  The bit line driver 107 sets the bit line selected by the column decoder 106 to the ground state based on the output signal of the column decoder 106.

  Note that this embodiment is a single-layer cross-point nonvolatile memory device, but a multi-layer cross-point nonvolatile memory device may be formed by stacking memory cell arrays.

  Further, the positional relationship between the resistance change element and the current control element may be interchanged. That is, the bit line may be connected to the resistance change element, and the word line may be connected to the current control element.

  Further, the bit line and / or the word line may also serve as an electrode in the resistance change element.

  In the present embodiment, similarly to the second embodiment, functionally, a predetermined pulse voltage is applied to the selected memory cell (resistance change element) by the control unit 103 and the word line driver 105. A pulse voltage application unit is configured. Such a pulse voltage application unit includes at least (1) applying a write voltage pulse having a first polarity to a memory cell, thereby changing the resistance state of the transition metal oxide layer 3 of the memory cell to a high resistance state. (2) by applying an erasing voltage pulse having a second polarity different from the first polarity to the memory cell, thereby changing the transition metal oxide layer 3 of the memory cell. An erase process for changing the resistance state from the low resistance state to the high resistance state, and (3) a break voltage pulse having a second polarity having a voltage value equal to or higher than the erase voltage pulse is stored in the memory before the first write process. A break process for reducing the initial resistance value of the transition metal oxide layer 3 of the memory cell by applying to the cell; and (4) after the first break Before the writing process, by applying an additional processing voltage pulse having a second polarity having a voltage value equal to or higher than the erase voltage pulse to the memory cell, the transition metal oxide layer 3 of the memory cell after the breaking process is applied. It is a process part which performs the additional process process which reduces the resistance value of.

[Operation of non-volatile storage device]
Hereinafter, an operation example of the nonvolatile memory device 100 configured as described above will be described separately for each of the initial mode, the write mode, and the read mode. Note that a known method can be used as a method for selecting a bit line and a word line, a method for applying a voltage pulse, and the like, and thus detailed description thereof is omitted.

  Hereinafter, a case where writing / reading is performed on the memory cell MC22 will be described as an example.

[Break mode]
In the break mode, a break voltage pulse is applied to all memory cells. That is, each bit line is grounded by the bit line driver 107, and each word line and the control unit 103 are electrically connected by the word line driver 105. Then, the control unit 103 applies a break voltage pulse to each word line. Here, the voltage value of the break voltage pulse is set to +4.5 V, and the pulse width is set to 100 μs. Here, the break voltage pulse is applied once to a plurality of times until the resistance value of the transition metal oxide layer is lowered to the first resistance value R1 in each memory cell. The first resistance value R1 is preferably larger than the resistance value RH in the high resistance state. This is because it is expected that the conductive path can be prevented from becoming too large during the break process, and the endurance characteristics can be further improved. After applying each break voltage pulse, the resistance value of the variable resistance element is read in the read mode to check whether the break process is completed.

  Here, the break voltage pulse having the same voltage is applied a plurality of times to cause a break, but the break voltage pulse voltage may be gradually increased from a predetermined voltage to cause a break.

  By the operation as described above, the break process in the first embodiment is executed by the pulse voltage application unit, and the resistance value of the transition metal oxide layer is changed from the initial resistance value R0 to the first resistance value R1 in all the memory cells. Decrease.

[Additional processing mode]
In the additional processing mode, an additional processing voltage pulse is applied to all memory cells. That is, each bit line is grounded by the bit line driver 107, and each word line and the control unit 103 are electrically connected by the word line driver 105. Then, an additional processing voltage pulse is applied to each word line by the control unit 103. Here, the voltage value of the additional processing voltage pulse is set to +4.5 V, for example, and the pulse width is set to 500 μs. Here, the initial voltage pulse is applied until the resistance value of the transition metal oxide layer 3 basically decreases in all memory cells from the first resistance value R1 to the second resistance value R2 which is lower than the first resistance value R1. The The second resistance value R2 may be set by experimentally checking in advance. Further, the cumulative application time of the additional processing pulse is set to a time during which the resistance value of the transition metal oxide layer 3 is reduced from the first resistance value R1 to the second resistance value R2 lower than the first resistance value R1, for example. You may set to 10 ms.

  By the operation as described above, the additional processing step in the first embodiment is performed by the pulse voltage application unit, and the resistance value of the transition metal oxide layer is lower than the initial resistance value R0 in all the memory cells. Decreases to the resistance value R2.

[Write mode]
When 1-bit data representing “1” is written (stored) in the memory cell MC22, the bit line driver 107 grounds the bit line B2, and the word line driver 105 electrically connects the word line W2 and the control unit 103. Is done. Then, the control unit 103 applies a write voltage pulse to the word line W2. Here, the voltage value of the write voltage pulse is set to -1.9 V, and the pulse width is set to 100 ns.

  By the operation as described above, the write process in the first embodiment is performed by the pulse voltage application unit, and the write voltage pulse is applied to the resistance change element of the memory cell MC22. Therefore, the resistance change element of the memory cell MC22 is A low resistance state corresponding to “1” is obtained.

  On the other hand, when 1-bit data representing “0” is written (stored) in the memory cell MC22, the bit line driver 107 grounds the bit line B2, and the word line driver 105 connects the word line W2 and the control unit 103 to each other. Electrically connected. Then, the control unit 103 applies an erase voltage pulse to the word line W2. Here, the voltage value of the erase voltage pulse is set to +2.5 V, and the pulse width is set to 100 ns.

  By the operation as described above, the erasing process in the first embodiment is executed by the pulse voltage application unit, and the write voltage pulse is applied to the resistance change element of the memory cell MC22, so that the transition metal oxide layer of the memory cell MC22 3 enters a high resistance state corresponding to “0”.

[Read mode]
When reading data written in the memory cell MC22, the bit line B2 is grounded by the bit line driver 107, and the word line W2 and the control unit 103 are electrically connected by the word line driver 105. Then, the control unit 103 applies a read voltage to the word line W2. Here, the voltage value of the read voltage is set to + 0.5V.

  When a read voltage is applied to memory cell MC22, a current having a current value corresponding to the resistance value of transition metal oxide layer 3 of memory cell MC22 flows between bit line B2 and word line W2. Control unit 103 detects the current value of this current, and detects the resistance state of memory cell MC22 based on the current value and the read voltage.

  If the transition metal oxide layer 3 of the memory cell MC22 is in a low resistance state, it can be seen that the data written in the memory cell MC22 is “1”. On the other hand, in the high resistance state, it can be seen that the data written in the memory cell MC22 is “0”.

  By operating as described above, the nonvolatile memory device 100 can realize stable high-speed operation.

  In the above description, the bit line is grounded and a predetermined voltage pulse is applied to the word line. However, different voltage pulses are applied to the bit line and the word line, respectively, and the potential difference is a predetermined voltage. You may comprise so that it may become.

(Other embodiments)
In each of the above embodiments, the transition metal oxide layer 3 has a laminated structure of tantalum oxide, but the present invention is not limited to this. For example, a stacked structure of hafnium (Hf) oxide or a stacked structure of zirconium (Zr) oxide may be used.

In the case of adopting a hafnium oxide laminated structure as the transition metal oxide layer 3, the composition of the first hafnium oxide to be the first transition metal oxide layer 3a is HfO _x, and the second transition metal oxide When the composition of the second hafnium oxide to be the layer 3b is HfO _y , x is about 0.9 to 1.6 and y is about 1.8 to 2.0. The film thickness of the object is preferably 3 nm or more and 4 nm or less.

Further, in the case of adopting a zirconium oxide laminated structure as the transition metal oxide layer 3, the composition of the first zirconium oxide to be the first transition metal oxide layer 3a is ZrO _x, and the second transition metal When the composition of the second zirconium oxide to be the oxide layer 3b is ZrO _y , x is about 0.9 to 1.4 and y is about 1.9 to 2.0. The film thickness of the zirconium oxide is preferably 1 nm or more and 5 nm or less.

  When the transition metal oxide layer 3 is a hafnium oxide, the first hafnium oxide is formed on the first electrode 2 by a so-called reactive sputtering method using an Hf target and sputtering in argon gas and oxygen gas. A physical layer is formed. The second hafnium oxide layer can be formed by exposing the surface of the first hafnium oxide layer to a plasma of argon gas and oxygen gas after forming the first hafnium oxide layer. The oxygen content of the first hafnium oxide layer can be easily adjusted by changing the flow ratio of oxygen gas to argon gas during reactive sputtering. The substrate temperature can be set to room temperature without any particular heating.

The thickness of the second hafnium oxide layer can be easily adjusted by the exposure time of the argon gas and oxygen gas to the plasma. When the composition of the first hafnium oxide layer is represented as HfO _x and the composition of the second hafnium oxide layer is represented as HfO _y , 0.9 ≦ x ≦ 1.6, 1.8 <y, and the second hafnium Stable resistance change characteristics can be realized when the thickness of the oxide layer is in the range of 3 nm to 4 nm.

When the transition metal oxide layer 3 is a zirconium oxide, the first zirconium oxide layer is formed on the first electrode 2 by a so-called reactive sputtering method using a Zr target and sputtering in argon gas and oxygen gas. Form. The second zirconium oxide layer can be formed by exposing the surface of the first zirconium oxide layer to a plasma of Ar gas and O ₂ gas after forming the first zirconium oxide layer. The oxygen content of the first zirconium oxide layer can be easily adjusted by changing the flow ratio of oxygen gas to argon gas during reactive sputtering. The substrate temperature can be set to room temperature without any particular heating.

The film thickness of the second zirconium oxide layer can be easily adjusted by the exposure time of the argon gas and oxygen gas to the plasma. When the composition of the first zirconium oxide layer is expressed as ZrO _x and the composition of the second zirconium oxide layer is expressed as ZrO _y , 0.9 ≦ x ≦ 1.4, 1.9 <y, the second zirconium Stable resistance change characteristics can be realized when the thickness of the oxide layer is in the range of 1 nm to 5 nm.

  In each of the above embodiments, a stable resistance changing operation can be realized as described above. However, in rare cases, writing in the writing process or erasing process may fail. In such a case where writing fails, a stable operation can be realized for a long time by executing an initial process of applying an initial voltage pulse between both electrodes and then repeating the writing process and the erasing process. It becomes possible.

  In the embodiment described above, the transition metal oxide as the variable resistance layer has been described with respect to tantalum oxide, hafnium oxide, and zirconium oxide. However, the transition metal oxide layer sandwiched between the upper and lower electrodes is described. As the main resistance change layer that exhibits resistance change, an oxide layer such as tantalum, hafnium, zirconium, or the like may be included, and in addition to this, for example, a trace amount of other elements may be included. It is also possible to intentionally include a small amount of other elements by fine adjustment of the resistance value, and such a case is also included in the scope of the present invention. For example, if nitrogen is added to the resistance change layer, the resistance value of the resistance change layer increases and the reactivity of resistance change can be improved.

Therefore, in the resistance change element using the oxygen-deficient transition metal oxide M as the resistance change layer, the resistance change layer is MO _x (where the configuration of the transition metal oxide in the stoichiometric configuration is MO _s . An oxygen-deficient first transition metal oxide layer having a composition represented by 0 <x <s) and a second transition metal having a composition represented by MO _y (where x <y) In the case of the structure including the oxide layer, the oxygen-deficient first transition metal oxide layer and the second transition metal oxide layer include predetermined impurities in addition to the transition metal oxide having the corresponding composition. (For example, an additive for adjusting the resistance value) is not prevented from being included.

  In addition, when a resistive film is formed by sputtering, an unintended trace element may be mixed into the resistive film due to residual gas or outgassing from the vacuum vessel wall. Naturally, it is also included in the scope of the present invention when mixed into the film.

  The variable resistance element driving method and the nonvolatile memory device of the present invention are useful as a variable resistance element driving method and a nonvolatile memory device used in various electronic devices such as a personal computer or a portable phone, respectively.

DESCRIPTION OF SYMBOLS 1 Substrate 2 1st electrode 3 Transition metal oxide layer 3a 1st transition metal oxide layer 3b 2nd transition metal oxide layer 4 2nd electrode 5 Power supply 10 Resistance change element 11 1st terminal 12 2nd terminal 100 Nonvolatile Memory storage device 101 memory cell array 102 address buffer 103 control unit 104 row decoder 105 word line driver 106 column decoder 107 bit line driver W1, W2, W3 word line B1, B2, B3 bit line MC11, MC12, MC13, MC21, MC22, MC23, MC31, MC32, MC33 Memory cells D11, D12, D13, D21, D22, D23, D31, D32, D33 Current control element (bidirectional diode)
DESCRIPTION OF SYMBOLS 200 Nonvolatile memory device 201 Memory cell array 202 Address buffer 203 Control part 204 Row decoder 205 Word line driver 206 Column decoder 207 Bit line / plate line driver MC211, MC212, MC221, MC222 Memory cells T211, T212, T221, T222 Selection transistor

Claims (9)

A first electrode, a second electrode, a transition metal oxide layer interposed between the first electrode and the second electrode, the resistance value of which increases or decreases in response to an electrical pulse applied between the two electrodes; In a driving method for driving a variable resistance element comprising:
The transition metal oxide layer has a first transition metal oxide layer connected to the first electrode and an oxygen content higher than that of the first transition metal oxide layer, and is connected to the second electrode. And the second transition metal oxide layer is laminated.
A writing process of changing a resistance state of the transition metal oxide layer from a high resistance state to a low resistance state by applying a writing voltage pulse having a first polarity between the first electrode and the second electrode;
By applying an erase voltage pulse having a second polarity different from the first polarity between the first electrode and the second electrode, the resistance state of the transition metal oxide layer is changed from a low resistance state to a high resistance state. An erasing process that changes to a state,
Before the first writing process, the transition metal is applied by applying a break voltage pulse having the second polarity having a voltage value equal to or higher than the erase voltage pulse between the first electrode and the second electrode. A break process in which a conductive path is formed in the oxide layer and a resistance value in an initial state is lowered to a first resistance value larger than a resistance value in the high resistance state;
After the break process and before the first write process, an additional processing voltage pulse having the second polarity having a voltage value equal to or higher than the erase voltage pulse is applied between the first electrode and the second electrode. And an additional processing step of causing the first resistance value of the transition metal oxide layer after the break step to be a lower second resistance value by applying to the resistance change element.   2. The resistance process of the transition metal oxide layer is caused to have a second resistance value by applying a plurality of the additional processing voltage pulses between the first electrode and the second electrode in the additional processing step. 2. A driving method of a resistance change element according to 1. The first transition metal oxide layer is made of tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9), and the second transition metal oxide layer is The method for driving a resistance change element according to claim 1, wherein the resistance change element is made of tantalum oxide having a composition represented by TaO _y (where 2.1 ≦ y). A first electrode, a second electrode, a transition metal oxide layer interposed between the first electrode and the second electrode, the resistance value of which increases or decreases in response to an electrical pulse applied between the two electrodes; A variable resistance element comprising:
A pulse voltage application unit that applies a predetermined pulse voltage to the variable resistance element;
The transition metal oxide layer is formed by laminating a first transition metal oxide layer and a second transition metal oxide layer having an oxygen content higher than that of the first transition metal oxide layer. And
The pulse voltage application unit is
A writing process of changing a resistance state of the transition metal oxide layer from a high resistance state to a low resistance state by applying a writing voltage pulse having a first polarity between the first electrode and the second electrode;
By applying an erase voltage pulse having a second polarity different from the first polarity between the first electrode and the second electrode, the resistance state of the transition metal oxide layer is changed from a low resistance state to a high resistance state. An erasing process that changes to a state,
Before the first writing process, the transition metal oxidation is performed by applying a break voltage pulse having the second polarity having a voltage value equal to or higher than the erase voltage pulse between the first electrode and the second electrode. A break process in which a conductive path is formed in the physical layer to reduce the initial resistance value to the first resistance value;
After the break process and before the first write process, an additional processing voltage pulse having the second polarity having a voltage value equal to or higher than the erase voltage pulse is applied between the first electrode and the second electrode. A non-volatile memory device that performs an additional processing step of applying a voltage to the second resistance value of the transition metal oxide layer after the break step to a lower second resistance value.   The pulse voltage application unit applies the plurality of additional processing voltage pulses between the first electrode and the second electrode in the additional processing step, thereby reducing the resistance value of the transition metal oxide layer to the second voltage. The nonvolatile memory device according to claim 4, wherein a resistance value of the non-volatile memory device is set. The first transition metal oxide layer is made of tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9),
The non-volatile property according to claim 4, wherein the second transition metal oxide layer is composed of a tantalum oxide having a composition represented by TaO _y (where 2.1 ≦ y). Storage device.   The nonvolatile memory device according to claim 4, wherein the variable resistance element further includes a current control element electrically connected to the first electrode or the second electrode.   The nonvolatile memory device according to claim 4, wherein the current control element is a selection transistor.   The nonvolatile memory device according to claim 4, wherein the current control element is a diode.

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