JP2012033748A - Semiconductor surface light emitting element, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor surface light emitting element and a method of manufacturing the same capable of improving characteristics.SOLUTION: A semiconductor surface light emitting element has: a photonic crystal layer 6 formed by forming a plurality of holes H in a basic layer 6A made of a first compound semiconductor having a zinc blende structure periodically, and growing a buried layer 6B having a zinc blende structure and made of a second compound semiconductor in the hole H; and an active layer 4 that supplies light to the photonic crystal layer 6. A main surface of the basic layer 6A is a (001) plane. A lateral face of the hole H has two different {100} planes.

Description

  The present invention relates to a semiconductor surface light emitting device and a method for manufacturing the same.

  A photonic crystal is a nanostructure whose refractive index changes periodically, and the wavelength of light passing through the nanostructure can be controlled. As a next generation semiconductor surface light emitting device, a photonic crystal surface emitting laser (hereinafter referred to as PCSEL) using a two-dimensional photonic crystal (hereinafter referred to as 2DPC) has been proposed. PCSEL has the characteristics that its optical characteristics are determined by the size and shape of the microstructure and does not depend on the material. Conventional semiconductor light emitting devices such as large area, single mode, two-dimensional polarization control, and emission angle control It has new characteristics that are difficult to realize by itself, and has the potential to open up the possibilities of high-power semiconductor lasers.

In actual production of 2DPC, a wafer bonding technique is used, and the following problems (1) to (3) are present.
(1) It is difficult to produce a large area 2DPC. That is, when the wafer to be bonded has a warp, when there is dust between the wafers, or when there are large irregularities on the wafer surface, these wafers cannot be bonded well.
(2) The 2DPC layer includes a cavity, has a large coupling coefficient κ, and is not suitable for increasing the area. The reason is that in order to distribute light uniformly in the 2DPC layer, the normalized coupling coefficient κL in the in-plane direction with respect to the electrode length L is preferably about 1 to 2, but the 2DPC layer includes a cavity. This is because the value of κ is a value of 1000 cm ⁻¹ or more, and the value of L is limited to several tens of μm.
(3) Since defects are formed at the interface between the bonded wafers, there are difficulties in life and reliability.

As a 2DPC manufacturing means for solving the above problems, there is a regrowth type PCSEL utilizing crystal regrowth, and this has the following advantages.
(1) It is easy to produce a large area 2DPC. That is, when regrowth is used, there is no need to bond crystals.
(2) When the 2DPC layer is completely embedded, the coupling coefficient κ is reduced to about 1/10 of the coupling coefficient when the wafers are bonded, so that the area can be easily increased.
(3) Since the interface of the 2DPC layer is embedded with an epi layer, there are few defects and the reliability is improved.
(4) Since the 2DPC layer does not include cavities, it has excellent heat dissipation and is suitable for high output.

  From the above viewpoint, the regrowth type PCSEL is superior to the bonded type PCSEL in aiming at the practical use of the high output PCSEL.

  Patent Document 1 proposes that a hexagonal convex portion is embedded in a semiconductor layer as a photonic crystal that does not generate a cavity in crystal regrowth. In this case, the side surface is the (1-100) plane with respect to the main surface (0001) plane of the convex portion.

  In Patent Document 2, the crystal growth of a zinc blende structure using a (111) substrate having a polar surface or an (n11) substrate having 2 semipolar surfaces (2 ≦ n ≦ 6 is desirable) is repeated. Growth embedding is performed, and lateral growth is used as the means.

JP 2009-206157 A JP 2010-114384 A

  However, when the inventors of the present invention have made a hole in the zinc flash structure semiconductor layer and regrown the crystal in the hole, the surface morphology of the compound semiconductor layer formed thereon is not sufficient, and the crystal inside It was discovered that a large dislocation occurred. That is, since the crystallinity of the formed semiconductor layer is not sufficient, the characteristics of the semiconductor surface light emitting element are not sufficient.

  This invention is made | formed in view of such a subject, and it aims at providing the semiconductor surface light emitting element which can improve a characteristic, and its manufacturing method.

  In order to solve the above-described problem, a semiconductor surface light emitting device according to the present invention is formed by periodically forming a plurality of holes in a basic layer made of a first compound semiconductor having a zinc flash structure, and having a zinc flash structure in the hole. A photonic crystal layer obtained by growing a buried layer made of a second compound semiconductor, and an active layer that supplies light to the photonic crystal layer, and the main surface of the basic layer is (001) And the side surface of the hole includes two different {100} planes, or a plane obtained by rotating these planes at a rotation angle of ± 15 degrees or less around the normal of the main surface. It is characterized by including.

  If the side surface of the hole is formed by four different {110} planes, the buried layer grown perpendicular to the (110) and (-1-10) side surfaces has (110) and (-1-10) Facet When these facets come into contact with each other at the center, it was found that the crystals were disturbed and the final crystallinity was deteriorated. That is, the surface morphology of the semiconductor layer formed on the photonic crystal layer is rough, and many dislocations are generated inside. Further, when (110) and (−1-10) are included in the side surface of the hole, Facet that appears in the early stage of the regrowth embedding process (for example, (113), (−1-13), that is, (113) A surface) Multiple Facet competition occurs above and partially regrowth. There is also a mechanism that this region becomes the nucleus of dislocation formation.

  On the other hand, when the shape of the side surface of the hole is that of the present invention, the ratio of (110) and (-1-10) exposure to the side surface is reduced, and the dislocation formation mechanism is suppressed as described above. It is considered that the crystallinity of the internal semiconductor layer is improved. When the crystallinity of the semiconductor layer is improved in this manner, the durability due to temperature and heat increases, so that the lifetime can be increased, and the leakage current and internal resistance are reduced, so that the light emission efficiency can be improved. . That is, the characteristics of the semiconductor surface light emitting device can be improved by setting the shape of the hole to that of the present invention.

The first compound semiconductor is GaAs, and the second compound semiconductor is AlGaAs. When these zinc-blende compound semiconductors are used, the material characteristics are well known, and the formation thereof is easy.
In addition, the manufacturing method of the semiconductor surface light emitting element for manufacturing the above-described semiconductor surface light emitting element includes a step of forming the hole and a step of growing the buried layer. In addition, before the step of performing the growth, an alignment mark including a {110} plane or a plane obtained by rotating {110} by a rotation angle within ± 10 degrees around the normal of the main surface by etching, You may include the process of forming in the semiconductor substrate in which a base layer is formed. According to this method, when the above-described element is formed, the regrowth surface is roughened by forming dislocations in the regrowth layer of the alignment mark, and can be used as a reference position for optical exposure.

  According to the semiconductor surface light emitting device of the present invention, since the crystallinity of the semiconductor layer constituting the semiconductor surface light emitting device is improved, it is possible to improve characteristics such as light emission output and lifetime.

It is a perspective view of the semiconductor surface light emitting element which shows a semiconductor surface light emitting element partially broken. It is a top view of basic layer 6A formed on the wafer. It is a front view of a wafer. It is a figure which shows the structure of the shape of a hole. It is sectional drawing of a semiconductor surface light emitting element. It is a top view of basic layer 6A formed on the wafer concerning a comparative example. It is a figure which shows the concept of crystallinity deterioration. It is a figure which shows the detailed structure of the shape of a hole. It is a figure shown about the shape of various holes. FIG. 5 is a diagram for explaining a first manufacturing method of a photonic crystal layer. FIG. 6 is a diagram for explaining a second manufacturing method of the photonic crystal layer.

  Hereinafter, the semiconductor surface light emitting device and the manufacturing method thereof according to the embodiment will be described. Note that the same reference numerals are used for the same elements, and redundant description is omitted.

  FIG. 1 is a perspective view of a semiconductor surface light emitting device, with the semiconductor surface light emitting device partially cut away.

  The semiconductor surface light emitting device includes a lower clad layer 2, a lower light guide layer 3, an active layer 4, an upper light guide layer 5, a photonic crystal layer 6, an upper clad layer 7, and a contact layer 8 that are sequentially formed on a semiconductor substrate 1. It has. On the back side of the semiconductor substrate 1, an electrode E <b> 1 is provided on the entire surface, and an electrode E <b> 2 is provided in the center portion of the contact layer 8.

The materials / thicknesses of these compound semiconductor layers are as follows. Note that an intrinsic semiconductor having an impurity concentration of 10 ¹⁵ / cm ³ or less has no conductivity type. In addition, the density | concentration when an impurity is added is 10 < ¹⁷ > -10 < ²⁰ > / cm < ³ >. Further, the following is an example of the present embodiment. If the configuration includes the active layer 4 and the photonic crystal layer 6, the material system, the film thickness, and the layer configuration have flexibility. The numerical values in parentheses are those used in the experiments at the time of alignment mark creation described later, the growth temperature of AlGaAs by the MOCVD method is 500 ° C. to 850 ° C., and the experiments adopt 550 to 700 ° C., TMA (trimethylaluminum) as the Al source during growth, TMG (trimethylgallium) and TEG (triethylgallium) as the gallium source, AsH _{3 (} arsine) as the As source, Si ₂ H ₆ (as the source for N-type impurities) Disilane), DEZn (diethyl zinc) was used as a raw material for P-type impurities.
Contact layer 8: P-type GaAs / 50 to 500 nm (200 nm)
Upper clad layer 7: P-type AlGaAs (Al _0.4 Ga _0.6 As) /1.0 to 3.0 μm (2.0 μm)
Photonic crystal layer 6:
Basic layer 6A: GaAs / 50 to 200 nm (100 nm)
Buried layer 6B: AlGaAs (Al _0.4 Ga _0.6 As) / 50 to 200 nm (100 nm)
Upper light guide layer 5:
Upper layer: GaAs / 10-200 nm (50 nm)
Lower layer: p-type or intrinsic AlGaAs / 10 to 100 nm (50 nm)
Active layer 4 (multiple quantum well structure):
AlGaAs / InGaAs MQW / 10 to 100 nm (30 nm)
Lower light guide layer 3: AlGaAs / 0 to 300 nm (150 nm)
Lower clad layer 2: N-type AlGaAs / 1.0 to 3.0 μm (2.0 μm)
Semiconductor substrate 1: N-type GaAs / 80 to 350 μm (150 μm)

  When a current is passed between the upper and lower electrodes E1, E2, a current flows in a region R immediately below the electrode E2, this region emits light, and the laser beam LB is output in a direction perpendicular to the substrate.

  FIG. 2 is a plan view of the basic layer 6A formed on the wafer. In the plan view, for the purpose of clarifying the understanding, a plurality of holes H are described which are much larger than the actual scale, and the number thereof is smaller than the actual scale. FIG. 3 is a front view of the wafer.

  The main surface of the wafer (substrate) is the (001) plane, and in the drawing, the main surface (001) of the basic layer 6A is exposed on the surface. The a-axis, b-axis, and c-axis of the zinc-blende structure crystal are shown in the drawing as the X-axis, Y-axis, and Z-axis, respectively. The directions of the X axis, the Y axis, and the Z axis are [100], [010], and [001], respectively.

  An orientation flat (hereinafter referred to as orientation flat) OF is formed at one end of the wafer, and the orientation flat OF is perpendicular to the [110] direction. The orientation flat OF has a (-1-10) plane. A plurality of holes H (H1 to H10) are formed in the basic layer 6A, and each hole H has a depth in the thickness direction of the semiconductor substrate.

  The outline of the hole H in the planar shape is a triangle, and each side of the triangle is inclined 45 degrees with respect to the direction [1-10] in which the orientation flat OF extends. That is, the three side surfaces of the hole H have a (−100) plane, a (010) plane, and a (hk0) plane, respectively. As crystallographically equivalent planes, the (-100) plane and the (010) plane can be represented as {100} planes.

  FIG. 4 is a diagram showing the shape of the hole H.

    An angle (acute angle) formed by the (0-10) plane and the (hk0) plane is defined as θ. In the figure, the plane orientation of the (hk0) plane is a plane orientation parallel to the vector V [h1, k1, 0] where h1 = −sin θ and k1 = cos θ.

  In the plan view of FIG. 2, the positions of the centers of gravity of the holes H in the XY plane are arranged at regular intervals along the [1-10] direction, and also along the [110] direction along the regular intervals. Are lined up. In the drawing, the case where the former interval (for example, between H1 and H2) is shorter than the latter interval (for example, between H1 and H6) is shown, but the present invention is not limited to this. Further, another hole H4 is arranged on an extension line along the [110] direction of the midpoint position of the former interval (for example, between H1 and H2).

In the embodiment, the interval in the [1-10] direction of the center of gravity of the hole H is 335 nm, and the interval in the [110] direction is 580 nm. The shape of the hole is a triangle, and the length of each side is 120 nm, 160 nm, and 200 nm, respectively, and the area is 9.6 × 10 ³ nm ² . In addition, the line group which connects the gravity center position of the hole H can comprise a square lattice, a rectangular lattice, and a triangular lattice, and may be a random arrangement | positioning.

  Since the buried layer 6B shown in FIG. 1 is buried in the hole H of the basic layer 6A, its side surface is in contact with the side surface of the hole H, and its plane orientation matches the plane orientation of the side surface of the hole H. Yes.

  As described above, the above-described semiconductor surface light-emitting device has a plurality of holes H periodically formed in the basic layer 6A made of the first compound semiconductor (GaAs) having the zinc flash structure, and the zinc H structure having the zinc flash structure. A photonic crystal layer 6 formed by growing a buried layer 6B made of a second compound semiconductor (AlGaAs) is provided. Of course, since the photonic crystal is formed, the refractive index of the first compound semiconductor is different from that of the second compound semiconductor.

  FIG. 5 is a cross-sectional view of a semiconductor surface light emitting device. This example shows a cross section parallel to the orientation flat.

  As described above, the semiconductor surface light emitting device includes the lower cladding layer 2, the lower light guide layer 3, the active layer 4, the upper light guide layer 5, the photonic crystal layer 6, and the upper cladding layer that are sequentially formed on the semiconductor substrate 1. 7 and a contact layer 8 are provided. Here, the active layer 4 supplies light to the photonic crystal layer 6, and includes upper and lower semiconductor layers 4A and 4C and a central semiconductor layer 4B sandwiched between them. The relationship of these energy band gaps is the same as that of a normal laser, and is set so as to have a multiple quantum well structure in which a 4B QW (quantum well) layer is sandwiched between 4A and 4C guide layers. The photonic crystal layer 6 is used to generate laser light by light resonance. That is, this semiconductor surface light emitting device is a photonic crystal surface emitting laser, but if the laser oscillation does not occur, the structure can be used as a light emitting diode.

  FIG. 6 is a plan view of the basic layer 6A formed on the wafer according to the comparative example. If the semiconductor surface light emitting device shown in FIGS. 1 to 5 is an example, the device of the comparative example is different from the example only in the shape of the holes H (H1 to H10). That is, each side surface of the hole H is constituted by a {110} plane. More specifically, the respective sides are (110), (1-10), (-1-10), and (-110).

  FIG. 7 is a diagram showing the concept of crystallinity degradation.

  In the comparative example, the buried layer grown perpendicular to the side surfaces (110) and (-1-10) has deteriorated crystallinity due to the above-described dislocation generation mechanism. That is, the surface morphology of the semiconductor layer formed on the photonic crystal layer is rough, and many dislocations are generated inside.

  On the other hand, in the present invention, the main surface of the basic layer 6A is the (001) plane, and two of the side surfaces of the hole H are {100} planes, and (110), (−1-10) on the side surfaces. The percentage of surface exposure is reduced. Therefore, since the above-mentioned dislocation generation mechanism is suppressed, it is theoretically considered that crystallinity is improved.

  FIG. 8 is a diagram showing a detailed configuration of the hole shape.

  In the triangle circumscribing the outline of the hole H in the XY plane, the dimensions of two orthogonal sides are L1 and L2. A triangle similar to this triangle is assumed, and one corner is inscribed. The inscribed triangle has the same center of gravity G as the circumscribed triangle, and the rotational position in the XY plane is also the same. In this case, the separation distance in the direction parallel to one side ((010) plane) orthogonal to the triangle of the corresponding side is ΔL11, ΔL12, and the separation distance in the direction parallel to the other side (−100) plane is ΔL21, ΔL22. And

  This is a case where (ΔL11 + ΔL12) / L1 is less than 29% and (ΔL21 + ΔL22) / L2 is less than 29%, and the maximum value of the area of the hole in the XY plane (area of the outermost surface) is When the area of the circumscribed triangle is 50% or more, the shape of the hole is recognized as a triangle, and the side surface of the hole H is recognized as including two {100} planes.

  FIG. 9 is a diagram showing various hole shapes.

The dotted line in the figure indicates the {100} plane. FIG. 9A shows the shape of the hole in the above-described embodiment. (B) is a part in which one side of (A) is missing and the embedded layer 6B has a recess (concave surface). (C) is one in which part of the two sides of (A) is missing and the buried layer 6B has a recess (concave surface). In (D), a part of the three sides of (A) is missing, and the embedded layer 6B has a recess (concave surface). Note that there may be a plurality of concave portions shown in (B) to (D), or the concave portions may be replaced with convex portions. (E) is a case where a part of the center of the buried layer 6B of (A) is missing. There may be a plurality of regions lacking (E).
(F) is a case where the hypotenuse of (A) is a curved line (curved surface).

  Also in these cases, it is considered that the crystallinity is improved because the mechanism of dislocation formation due to the above (110) and (-1-10) is suppressed.

  (G) shows a case where the planar shape of the hole is a quadrangle (trapezoid) and the side surface has two {100} planes, and these {100} planes are opposed and parallel to each other. . (H) shows a case in which the planar shape of the hole is a parallelogram and the side surface has two {100} planes, but these {100} planes are opposed and parallel. (I) shows a case where a part of the bottom of the trapezoid shown in (G) is missing and a part of the buried layer 6B has a V-groove.

  Also in these cases, it is considered that the crystallinity is improved because the mechanism of dislocation formation due to the above (110) and (-1-10) is suppressed.

  As described above, in the above-described embodiment, the side surface of the hole H includes two different {100} surfaces. When the shape of the side surface of the hole is that of the present invention, the ratio of exposure of the (110) and (−1-10) planes to the side surface is reduced, and the above-described dislocation generation mechanism is suppressed. It is believed that the crystallinity of the layer is improved. When the crystallinity of the semiconductor layer is improved in this manner, the durability due to temperature and heat increases, so that the lifetime can be increased, and the leakage current and internal resistance are reduced, so that the light emission efficiency can be improved. . That is, the characteristics of the semiconductor surface light emitting device can be improved by adopting the hole-shaped configuration described above.

  The first compound semiconductor is GaAs, and the second compound semiconductor is AlGaAs. When these zinc-blende compound semiconductors are used, the material characteristics are well known, and the formation thereof is easy.

  In addition, it is thought that the same effect is acquired even when the above-mentioned hole H is rotated by a rotation angle within ± 15 degrees around the normal line of the main plane (001) in the XY plane. In this case, the side surface of the hole H includes a surface obtained by rotating two different {100} planes around the normal of the main surface (001) with a rotation angle of ± 15 degrees or less.

  FIG. 10 is a diagram for explaining a first manufacturing method of the photonic crystal layer.

  An N-type cladding layer (AlGaAs) 2, a guide layer (AlGaAs) 3, a multiple quantum well structure (InGaAs / AlGaAs) 4, an optical guide on an N-type (first conductivity type) semiconductor substrate (GaAs) 1 A layer (GaAs / AaGaAs) or spacer layer (AlGaAs) 5 and a basic layer (GaAs) 6A to be a photonic crystal layer are epitaxially grown sequentially using MOCVD (metal organic chemical vapor deposition).

  In order to take alignment after epitaxial growth, a SiN layer AG is formed on the basic layer 6A by PCVD (plasma CVD), and then a resist R is formed on the SiN layer AG (C). Further, the resist R is exposed and developed (D), the SiN layer AG is etched using the resist R as a mask, and a part of the SiN layer AG is left to form an alignment mark (E). The remaining resist is removed (F).

  Next, a resist R2 is applied to the basic layer 6A, a two-dimensional fine pattern is drawn on the resist R2 by an electron beam drawing apparatus, and developed to form a two-dimensional fine pattern on the resist R2 (H). Thereafter, using the resist R2 as a mask, a two-dimensional fine pattern having a depth of about 100 nm is transferred onto the basic layer 6A by dry etching (forming a hole H) (I), and the resist is removed (J). The depth of the hole H is 100 nm.

  Thereafter, regrowth is performed using the MOCVD method.

  In the regrowth process, the buried layer (AlGaAs) 6B is grown in the hole H, and then the P-type cladding layer (AlGaAs) 7 and the P-type contact layer (GaAs) 8 are sequentially epitaxially grown (K). Next, a resist R3 having a square hole H is formed on the P-type contact 8 (L), the resist R3 is patterned (M), and an electrode E is deposited on the resist R3 (N). The electrode material is removed leaving only the electrode (Cr / Au) E2 by lift-off (O). Then, the back surface of the N-type semiconductor substrate 1 is polished to form an N-type electrode (AuGe / Au) E1 (P).

  FIG. 11 is a diagram for explaining a second manufacturing method of the photonic crystal layer.

  An N-type cladding layer (AlGaAs) 2, a guide layer (AlGaAs) 3, a multiple quantum well structure (InGaAs / AlGaAs) 4, an optical guide on an N-type (first conductivity type) semiconductor substrate (GaAs) 1 A layer (GaAs / AaGaAs) or spacer layer (AlGaAs) 5 and a basic layer (GaAs) 6A to be a photonic crystal layer are epitaxially grown sequentially using MOCVD (metal organic chemical vapor deposition).

  Next, a resist R2 is applied on the basic layer 6A (B), a two-dimensional fine pattern is drawn with an electron beam drawing apparatus, and developed to form a two-dimensional fine pattern on the resist (C). At this time, squares with sides of 120 nm surrounded by the (110) plane are arranged at 330 nm intervals at the alignment mark position of the photomask to be used, and the area of the entire region is 100 μm × 100 μm. As will be described later, this pattern is used as a reference for alignment of optical exposure after regrowth.

  Thereafter, a two-dimensional fine pattern having a depth of about 100 nm is transferred onto the basic layer 6A by dry etching (D), and the resist is removed (E). Since the position of the mark is also etched, a pattern (alignment mark) is formed at this position. This pattern has side surfaces surrounded by four {110} planes, but may be rotated slightly (within ± 10 degrees). In this pattern, it was observed that the regrowth surface was rough because dislocations were formed by regrowth. Therefore, the rough surface can be used as a reference for alignment in optical exposure after regrowth. Thereafter, regrowth is performed using the MOCVD method. Thus, before the step of performing the regrowth of the buried layer, the {110} plane or {110} was rotated by a rotation angle within ± 10 degrees around the normal line of the main surface (001) by etching. By forming the alignment mark including the surface in an appropriate location (outside area of the light emitting element formation scheduled area) of the semiconductor substrate on which the basic layer 6A is formed, the normal alignment mark forming process can be omitted. .

In the regrowth step, the buried layer (AlGaAs) 6B is grown in the hole H, and then the P-type cladding layer (AlGaAs) 7 and the P-type contact layer (GaAs) 8 are sequentially epitaxially grown (F). Next, a resist R3 having a square hole H is formed on the P-type contact 8 (G), the resist R3 is patterned by optical exposure (H), and an electrode E is deposited on the resist R3 (I). Then, the electrode material is removed by lifting off, leaving only the electrode (Cr / Au) E2 (J). Then, the back surface of the N-type semiconductor substrate 1 is polished to form an N-type electrode (AuGe / Au) E1 (K). According to this method, when the above-described element is formed, by forming a pattern surrounded by the {110} plane before the regrowth, the reference position for alignment of the optical exposure after the regrowth is formed. Can be used as
The depth of the hole H may be shallower than the basic layer 6A or slightly deeper. The (001) wafer may be an off-substrate.

  In addition, although the manufacturing method by the electron beam exposure method was demonstrated in the embodiment as the manufacturing method of the hole H, you may use other microfabrication techniques, such as optical exposures, such as nanoimprint, interference exposure, FIB, and a stepper.

6A: basic layer, 6B: buried layer, H: hole.

Claims (4)

A photonic crystal in which a plurality of holes are periodically formed in a basic layer made of a first compound semiconductor having a zinc flash structure, and a buried layer made of a second compound semiconductor having a zinc flash structure is grown in the hole. Layers,
An active layer for supplying light to the photonic crystal layer;
With
The main surface of the basic layer is a (001) plane,
The side surface of the hole includes two different {100} planes, or includes a plane obtained by rotating these planes at a rotation angle of ± 15 degrees or less around the normal of the main surface.
A semiconductor surface light emitting device. The first compound semiconductor is GaAs;
The second compound semiconductor is AlGaAs;
2. The semiconductor surface light emitting device according to claim 1, wherein: In the manufacturing method of the semiconductor surface light emitting element which manufactures the semiconductor surface light emitting element of Claim 1 or 2,
Forming the hole;
Growing the buried layer;
A method for manufacturing a semiconductor surface light emitting device, comprising: Before the step of performing the growth, an alignment mark including a {110} plane or a plane obtained by rotating {110} at a rotation angle within ± 10 degrees around the normal of the main surface by etching is used as the base layer. 4. The method of manufacturing a semiconductor surface light emitting device according to claim 3, further comprising a step of forming the semiconductor substrate on the semiconductor substrate on which the semiconductor surface is formed.

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