JP2012033576A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent peeling and breaking of a surface layer, in a semiconductor device in which a via hole is formed in a substrate and the surface layer.SOLUTION: A semiconductor device comprises: a substrate 10; a surface layer 20 that is provided on the substrate 10 and is composed of a different material than that of the substrate 10; and an electrode pad 50 provided on the surface layer 20. A via hole 30 is formed in the substrate 10 and the surface layer 20. In the via hole 30, a metal layer 32 electrically connected to the electrode pad 50 is provided. Around the opening of the via hole 30, a groove 22 is formed in the surface layer 20 so as to surround the via hole 30.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  2. Description of the Related Art There is known a semiconductor device in which a surface layer (for example, a semiconductor layer or an insulating layer) is formed on a substrate and a via hole penetrating the substrate and the surface layer is formed. An electrode pad is formed in the opening of the via hole on the surface layer, and a metal layer is formed in the back surface of the substrate and in the via hole. The electrode pad and the metal layer are in contact with each other in the vicinity of the opening of the via hole and are electrically connected to each other. (For example, see Patent Document 1).

JP 2005-322811 A

  The electrode pad and the metal layer have a large thermal expansion coefficient and are easily expanded and contracted, but the substrate and the surface layer have a small thermal expansion coefficient and are difficult to expand and contract. For this reason, the stress generated by the expansion and contraction of the electrode pad and the metal layer is transmitted to the substrate and the surface layer, and the surface layer may be peeled off or broken.

  The present invention has been made in view of the above problems, and an object of the present invention is to suppress separation and destruction of a surface layer in a semiconductor device in which via holes are formed in a substrate and a surface layer.

  The semiconductor device includes a substrate, a surface layer made of a material different from the substrate provided on the substrate, and an electrode pad provided on the surface layer, and via holes are formed in the substrate and the surface layer. A metal layer electrically connected to the electrode pad is provided in the via hole, and a groove is formed in the surface layer around the via hole so as to surround the via hole. ing.

  The said structure WHEREIN: The said groove | channel can be set as the structure which has penetrated the said surface layer.

  In the above configuration, the substrate may include a SiC substrate, and the surface layer may include a nitride semiconductor layer.

  In the above configuration, the substrate may include a GaAs substrate, and the surface layer may include an insulating layer.

  The said structure WHEREIN: The said groove | channel can be set as the structure currently formed inside the area | region in which the said electrode pad was provided.

  The said structure WHEREIN: The said groove | channel can be set as the structure currently formed in the outer side of the area | region in which the said electrode pad was provided.

  In the above configuration, a source electrode provided on the surface layer and a lead-out wiring portion provided on the surface layer and connecting the source electrode and the electrode pad may be provided.

  The said structure WHEREIN: The said lead-out wiring part can be set as the structure containing the air bridge provided in the said groove | channel.

  The method of manufacturing the semiconductor device includes a step of forming a groove in the surface layer so as to surround a via hole formation region in a surface layer of a material different from the substrate provided on the substrate, and the via hole formation region in the surface layer. A step of forming an electrode pad thereon, a step of forming a via hole penetrating the substrate and the surface layer and opening in the via hole forming region, and a metal electrically connected to the electrode pad in the via hole Forming a layer.

  According to the present invention, in a semiconductor device in which via holes are formed in a substrate and a surface layer, peeling and destruction of the surface layer can be suppressed.

FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to a comparative example. FIG. 2 is a diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 3 is a diagram illustrating the configuration of the semiconductor device according to the first embodiment. FIG. 4 is a diagram for explaining the force acting on the semiconductor device. FIG. 5 is a diagram illustrating a configuration of a semiconductor device according to a modification of the first embodiment. FIG. 6 is a diagram illustrating the method of manufacturing the semiconductor device according to the second embodiment. FIG. 7 is a diagram illustrating the configuration of the semiconductor device according to the second embodiment. FIG. 8 is a diagram illustrating a configuration of a semiconductor device according to a modification of the second embodiment.

(Comparative example)
First, a semiconductor device according to a comparative example will be described.

  FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a comparative example. A surface layer 20 is formed on the upper surface of the substrate 10, and a via hole 30 penetrating the substrate 10 and the surface layer 20 is formed. An electrode pad 50 is formed in the opening of the via hole 30 on the surface layer 20. The lower surface of the substrate 10 and the inside of the via hole 30 are metallized, and a metal layer 32 is formed. The electrode pad 50 and the metal layer 32 are in contact with each other in the vicinity of the opening of the via hole 30 on the upper side of the substrate 10 and are electrically connected to each other. In the following description, of the two main surfaces of the substrate 10, the main surface on which the surface layer 20 is formed is referred to as an upper surface, and the opposite main surface is referred to as a lower surface.

  Here, each of the electrode pad 50 and the metal layer 32 is formed of a material having a large thermal expansion coefficient and easily expanding and contracting. On the other hand, the substrate 10 and the surface layer 20 are each formed of a material having a small coefficient of thermal expansion and difficult to expand and contract. For this reason, stress is generated inside the electrode pad 50 and the metal layer 32 in accordance with the temperature change, and the force is transmitted to the substrate 10 and the surface layer 20, so that the surface layer 20 may be peeled off or broken. . Specifically, peeling is likely to occur at the boundary portion (A) between the substrate 10 and the surface layer 20 inside the via hole 30, and the surface layer 20 (B) near the outer peripheral edge of the electrode pad 50 is likely to be broken. It has become.

  2A to 2E are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. As shown in FIG. 2A, a surface layer 20 is formed on the upper surface of the substrate 10. As the substrate 10, for example, a substrate made of SiC can be used. The surface layer 20 includes, for example, a nitride semiconductor layer, and includes, for example, a 300 nm buffer layer made of AlN, a 1 μm channel layer (electron transit layer) made of i-GaN, and 20 nm made of n-AlGaN. The electron supply layer and the 5 nm cap layer made of n-GaN are sequentially stacked. For the nitride semiconductor layer, GaN, AlN, InN, InGaN, AlGaN, InAlN, InAlGaN, or the like can be used.

  First, as shown in FIG. 2B, a part of the surface layer 20 is etched to expose the substrate 10 and form a groove 22. The groove 22 is formed so as to surround the planned via hole formation region 26 in the surface layer 20. Next, as illustrated in FIG. 2C, the gate electrode 40, the source electrode 42, and the drain electrode 44 are formed on the surface layer 20. As the electrode material, for example, a laminate of Ti and Al or a laminate of Ta and Al can be used. Subsequently, the insulating layer 24 is formed so as to cover the electrode and the surface layer 20, and the surfaces of the source electrode 42, the drain electrode 44, and the via hole forming region 26 are exposed by etching. As the insulating layer 24, for example, a SiN insulating film can be used.

  Next, as shown in FIG. 2D, a metal layer is formed on the drain electrode 44 and on the region from the source electrode 42 to the via hole formation region 26. The metal layer can be formed by, for example, Au plating. The metal layer formed on the via hole formation region 26 becomes the electrode pad 50. A metal layer 52 is formed on the drain electrode 44, and a metal layer 54 is formed on the source electrode 42. The metal layer formed on the insulating layer 24 between the source electrode 42 and the electrode pad 50 becomes a lead-out wiring portion 56 that electrically connects the source electrode 42 and the electrode pad 50.

  Next, as shown in FIG. 2E, the via hole 30 is formed by etching the lower portion of the electrode pad 50 from the lower surface of the substrate 10. The via hole 30 can be formed by, for example, inductively coupled plasma (ICP) type dry etching using a fluorine-based gas. Subsequently, metallization is performed on the lower surface of the substrate 10 and the inside of the via hole 30 to form a metal layer 32. The metal layer 32 can be formed by first forming a seed layer 34 containing, for example, Ni, and forming a plating layer 36 containing, for example, Au on the seed layer 34. The semiconductor device according to Example 1 is completed through the above steps.

  FIG. 3A is a schematic cross-sectional view of the semiconductor device according to the first embodiment, and FIG. 3B is a schematic plan view. A surface layer 20 is provided on the substrate 10, and a gate electrode 40, a source electrode 42, a drain electrode 44, and an electrode pad 50 are provided on the surface layer 20. A via hole 30 penetrating the substrate 10 and the surface layer 20 is formed, and a metal layer 32 electrically connected to the electrode pad 50 is provided in the via hole 30. A groove 22 is formed around the opening of the via hole 30 in the surface layer 20 so as to surround the via hole 30. In FIG. 3B, the groove 22 and the via hole 30 are indicated by dotted lines. As shown in FIG. 3B, the outer peripheral end of the electrode pad 50 is located inside the groove 22. That is, the groove 22 is formed outside the region where the electrode pad 50 is provided.

  FIG. 4 is a diagram for explaining the action of force in the semiconductor device according to the first embodiment. Similar to the comparative example, the electrode pad 50 and the metal layer 32 are easily expanded and contracted by heat, and the substrate 10 and the surface layer 20 are not easily expanded and contracted by heat. When the temperature of the semiconductor device rises, the metal layer 32 in the via hole 30 expands, and forces in the direction of arrow a (direction parallel to the surface of the substrate 10) and the direction of arrow b (direction perpendicular to the surface of the substrate 10). Is added to the point A which is the boundary between the substrate 10 and the surface layer 20. When the temperature of the semiconductor device rises, the electrode pad 50 expands, and the total force in the direction of arrow a and the direction of arrow c (the direction parallel to the surface of the substrate 10) is the outer peripheral edge of the electrode pad 50. Applied to the nearby surface layer 20 (point B).

  Here, since the grooves 22 are formed in the surface layer 20, the force in the direction along the surface of the substrate 10 (arrows a and c in the figure) is released at the end (point B) of the surface layer 20. The Thereby, since the force added with respect to A point and B point in a figure is relieve | moderated, peeling of the surface layer 20 in A point and destruction of the surface layer 20 in B point can be suppressed. As described above, according to the semiconductor device according to the first embodiment, peeling and destruction of the surface layer 20 can be suppressed in the semiconductor device in which the via hole 30 is formed in the substrate 10 and the surface layer 20.

  FIG. 5 is a diagram illustrating a configuration of a semiconductor device according to a modification of the first embodiment. Unlike the first embodiment (FIG. 3A), an air bridge 58 is formed in a region where the lead-out wiring portion 56 intersects the groove 22. Due to the air bridge 58, the lead-out wiring part 56 is configured to float from the substrate 10 in the groove 22. Other configurations are the same as those of the first embodiment, and detailed description thereof is omitted. Also in this configuration, peeling and destruction of the surface layer 20 can be suppressed as in the first embodiment.

  Example 2 is an example in which the groove is formed inside the electrode pad.

  6A to 6E are diagrams illustrating a method for manufacturing a semiconductor device according to the second embodiment. Detailed description of portions common to the first embodiment will be omitted. As shown in FIG. 6A, the surface layer 20 is formed on the upper surface of the substrate 10.

  First, as shown in FIG. 6B, the substrate 10 is exposed by etching a part of the surface layer 20, and a groove 22 is formed so as to surround the via hole formation planned region 26. Next, as shown in FIG. 6C, the gate electrode 40, the source electrode 42, and the drain electrode 44 are formed on the surface layer 20. Subsequently, the insulating layer 24 is formed so as to cover the electrode and the surface layer 20, and a part thereof is removed by etching. Here, unlike the first embodiment, in the etching process of the insulating layer 24, the surfaces of the source electrode 42, the drain electrode 44, and the via hole 30 formation region 26 are exposed, and the groove 22 and the surrounding surface layer 20 are also exposed. Let's make it.

  Next, as shown in FIG. 6D, the electrode pad 50, the metal layer 52, the metal layer 54, and the lead-out wiring portion 56 are formed. Next, as shown in FIG. 2 (e), the lower portion of the electrode pad 50 is etched from the lower surface of the substrate 10 to form a via hole 30, and metallized on the lower surface of the substrate 10 and inside the via hole 30. The metal layer 32 is formed. Through the above process, the semiconductor device according to the second embodiment is completed.

  FIG. 7A is a schematic cross-sectional view of the semiconductor device according to the second embodiment, and FIG. 7B is a schematic plan view. Unlike Example 1 (FIGS. 3A and 3B), the outer peripheral end of the electrode pad 50 is located outside the groove 22. That is, the groove 22 is formed inside the region where the electrode pad 50 is provided. Other configurations are the same as those of the first embodiment, and detailed description thereof is omitted.

  According to the semiconductor device according to the second embodiment, as in the first embodiment, the stress caused by the expansion and contraction of the metal layer 32 and the electrode pad 50 is relieved by the grooves 22 formed in the surface layer 20, and the peeling of the surface layer 20 and Destruction can be suppressed.

  FIG. 8 is a diagram illustrating a configuration of a semiconductor device according to a modification of the second embodiment. Unlike the second embodiment (7 (a)), an air bridge 58 is formed in the lead-out wiring portion 56, and the portion floats from the insulating layer 24. Other configurations are the same as those of the first embodiment, and detailed description thereof is omitted. Also in this configuration, peeling and destruction of the surface layer 20 can be suppressed as in the second embodiment.

  In Examples 1 and 2, the example in which the substrate 10 is a SiC substrate and the surface layer 20 is a nitride semiconductor layer has been described. However, the present invention is not limited to the above configuration. For example, a Si substrate or a GaAs substrate may be used for the substrate 10, and a semiconductor layer or an insulating layer other than the nitride semiconductor layer may be used for the surface layer 20.

  For example, when a GaAs substrate is used as the substrate 10, peeling is likely to occur between an insulating layer (for example, a silicon nitride (SiN) insulating film) formed on the GaAs substrate as a surface layer and the GaAs substrate. The present invention is particularly suitable for such a configuration.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

DESCRIPTION OF SYMBOLS 10 Substrate 20 Surface layer 22 Groove 24 Insulating layer 30 Via hole 32 Metal layer 40 Gate electrode 42 Source electrode 44 Drain electrode 50 Electrode pad 56 Lead-out wiring part 58 Air bridge

Claims (9)

A substrate,
A surface layer made of a material different from that of the substrate provided on the substrate;
An electrode pad provided on the surface layer,
Via holes are formed in the substrate and the surface layer,
In the via hole, a metal layer electrically connected to the electrode pad is provided,
A groove is formed in the surface layer around the opening of the via hole so as to surround the via hole.   The semiconductor device according to claim 1, wherein the groove penetrates the surface layer.   The semiconductor device according to claim 1, wherein the substrate includes a SiC substrate, and the surface layer includes a nitride semiconductor layer.   The semiconductor device according to claim 1, wherein the substrate includes a GaAs substrate, and the surface layer includes an insulating layer.   The semiconductor device according to claim 1, wherein the groove is formed inside a region where the electrode pad is provided.   The semiconductor device according to claim 1, wherein the groove is formed outside a region where the electrode pad is provided. A source electrode provided on the surface layer;
The semiconductor device according to claim 1, further comprising a lead-out wiring portion provided on the surface layer and connecting the source electrode and the electrode pad.   The semiconductor device according to claim 7, wherein the lead-out wiring portion includes an air bridge provided on the groove. Forming a groove in the surface layer so as to surround a via hole forming region in a surface layer of a material different from the substrate provided on the substrate;
Forming an electrode pad on the via hole forming region in the surface layer;
Forming a via hole penetrating through the substrate and the surface layer and opening in the via hole forming region;
Forming a metal layer electrically connected to the electrode pad in the via hole;
A method for manufacturing a semiconductor device, comprising:

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