JP2012033090A - Memory device and ink information transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a recovery period with respect to data corruption due to static electricity or the like, which is generated during a data retention period or a data read period of a buffer memory.SOLUTION: A memory device includes a buffer memory 210 for storing data sent from an upper device, a parity generating circuit 228 for generating first parity data and second parity data that is related to the first parity data according to a predetermined rule based on a written data when the data is written on the buffer memory 210, a parity comparison part 234 for comparing the first parity data with the second parity data during a retention period in which the data written on the buffer memory 210 is retained, and an output part 216 for outputting a data retransmission request to the upper device when the relation by the predetermined rule is invalid as a result of the comparison by the parity comparison part 234.

Description

  The present invention relates to a memory device, an ink information transfer device, and the like.

  Patent Document 1 discloses an image forming apparatus in which recording characteristic data and check data for confirming the correctness or normal / abnormal operation of the recording head are stored in a detachable recording head. ing. In the technique described in Patent Document 1, when the recording head is mounted, the main body side reads the check data from the recording head and determines whether the recording head is valid or operates normally. Judge whether or not.

JP-A-6-64157

  In the image forming apparatus disclosed in Patent Document 1, no consideration is given to checking for errors that occur when the main body apparatus writes recording characteristic data to the recording head. For example, when the distance between the control unit of the main unit and the recording head is large, the recording characteristic data is usually transferred from the main unit to the recording head via a buffer memory. Here, it is assumed that data is destroyed due to static electricity, excessive noise, or the like during the holding period in which the recording characteristic data is temporarily held in the buffer memory. In this case, since the buffer memory itself cannot detect the data destruction, the data read from the buffer memory is transferred to the recording head, and the data error is detected for the first time by the data error detection in the recording head. Become.

  However, when an error is detected for the first time, it is unclear whether the data error occurred at the time of reception or whether the data output from the buffer memory itself was destroyed. Thus, for example, the recording head repeatedly sends a data retransmission request to the buffer memory, for example, an allowable number of times. If the problem cannot be solved even by repeating the data retransmission, it was found that the data itself stored in the buffer memory was destroyed. The same data is rewritten to the buffer memory.

  In this way, if data is destroyed due to static electricity or the like while data is held in the buffer memory, it takes a considerable amount of time before the same data is rewritten from the main unit to the buffer memory. Cost. That is, it takes time to recover the data error (error recovery), and during the recovery period, for example, other processing in the image forming apparatus may be stopped. A similar problem occurs when data is destroyed due to static electricity or the like when data is read from the buffer memory.

  According to at least one aspect of the present invention, it is possible to shorten a recovery period for data destruction caused by static electricity or the like that occurs during a data holding period or a data read period of a buffer memory.

  (1) According to one aspect of the memory device of the present invention, a buffer memory for storing data sent from a host device, and when the data is written to the buffer memory, the first is based on the written data. A parity generation circuit that generates parity data and second parity data related to the first parity data according to a predetermined rule; and a holding period in which the written data is held in the buffer memory. As a result of the comparison by the parity comparison unit that compares the first parity data and the second parity data and the comparison by the parity comparison unit, when the relationship according to the predetermined rule is not established, An output unit for outputting a data retransmission request.

  In this aspect, the memory device itself has a function of generating the first parity data and the second parity data when writing data to the buffer memory, and compares the generated first parity with the second parity during the data holding period. In addition, when a relationship according to a predetermined rule at the beginning of generation is not established between both parity data, a configuration is adopted in which a data retransmission request is output to a higher-level device. In this aspect, the memory device itself can detect the occurrence of data corruption during the data holding period. Therefore, it is possible to take measures against data destruction earlier than in the prior art, and therefore it is possible to reduce the time required for recovery against data destruction.

  For example, the parity generation circuit generates 1-bit first parity data and second parity data for each bit under the rule that the values of the parity data to the buffer memory do not match. If static electricity, excessive noise, or the like is input to the memory device during the data holding period and the value of either the first parity data or the second parity data is inverted, the first parity data and the second parity data Each value of is in a matching state. In this case, it can be estimated that there is a high possibility that the data held in the buffer memory is garbled.

  When the parity comparison unit detects a match between the values of both parity data, the output unit outputs a data retransmission request (request signal requesting retransmission of the same data) to the higher-level device. Therefore, the corrupted data in the buffer memory can be quickly recovered.

  (2) In another aspect of the memory device of the present invention, the buffer memory has a memory cell array, and the memory cell array stores at least m for temporarily storing data sent from the host device. A data storage area of row n columns (each of m and n is an integer of 2 or more), a first parity memory area for storing the first parity data, and a second parity memory area for storing the second parity data The parity generation circuit has the first parity data and the second parity that are vertical parity data by an operation based on each of the data in the same column of the data written to the data storage area. Generate each of the data.

  In this aspect, the memory cell array in the buffer memory has a first parity memory area for storing the first parity data and a second parity memory area for storing the second parity data in addition to the data storage area. For example, when SRAM is used as the buffer memory, there is no particular problem in securing the first parity memory area and the second parity memory area by adding word lines and memory cells in the vicinity of the data storage area. Is easy.

  For example, when the data storage area has a storage capacity of m rows and n columns (each of m and n is an integer of 2 or more), the data written in the data storage area (or held in the data storage area) Data), an operation based on each of the data in the same column (vertical parity operation) is executed. For example, the addition of the data in the same column by the binary method can be executed, and the vertical parity bit as a result of the addition can be set as, for example, the first parity data. Further, for example, the value of the first parity data can be inverted by an inverter or the like to obtain the second parity data. Each of the first parity data and the second parity data is stored in each of the first parity memory area and the second parity memory area.

  In this aspect, for example, 1-bit vertical parity data can be easily generated without difficulty for each data string of data written to the data storage area. Also, since vertical parity is generated for each data string, vertical parity data is generated by the number of bits of write data, and the total number of vertical parity data increases, making it easy to detect data corruption. . In addition, regarding the possibility of data destruction, even when there is a variation in the two-dimensional memory area, vertical parity data is generated for each data string (that is, with a spread along the row direction of the write data). Since vertical parity data is arranged), the possibility of detecting data corruption in an area where data destruction is likely to occur increases.

  (3) In another aspect of the memory device of the present invention, s bits (s is an integer of 1 or more) of lateral parity data is added to the data sent from the host device for every n bits of data. The data storage area has a storage capacity of at least m rows (n + s) columns, and performs a parity check based on each of the s-bit horizontal parity data added to each n-bit data. And a horizontal parity check unit.

  In this aspect, s-bit horizontal parity data is added to each n-bit data in the data sent from the host device. In order to support this data structure, the data storage area has a storage capacity of at least m rows (n + s) columns. In this aspect, a horizontal parity check unit is provided. The horizontal parity check unit executes a parity check based on each of the s-bit horizontal parity data added to each row, for example, when receiving data or writing data to the buffer memory.

  In this aspect, in addition to the detection of data destruction during the data holding period based on the above-described vertical parity data, data errors caused by data reception or data writing to the buffer memory based on the horizontal parity data are detected. Detection is also performed. The combined use of the vertical parity check and the horizontal parity check increases the reliability of data error detection.

  (4) In another aspect of the memory device of the present invention, when the data is read from the buffer memory, the parity generation circuit generates third parity data based on the read data, and compares the parity The comparison unit compares the third parity data with the second parity data, and the output unit determines that the higher-level device is not established when the relationship according to the predetermined rule is not established as a result of the comparison by the parity comparison unit. In response, a data retransmission request is output.

  As described above, even when data is read from the buffer memory, there is a possibility that data destruction due to static electricity or the like occurs. Therefore, in this aspect, a parity check for detecting data corruption is executed even when data is read from the buffer memory. That is, in this aspect, the third parity data is newly generated based on the read data, the generated third parity data is compared with the second parity data generated at the time of data write, A configuration is adopted in which a data retransmission request is output to a higher-level device when a rule relationship is not established.

  If data destruction due to static electricity or the like does not occur during data reading, the generated third parity data should be the same as the first parity data generated during data writing. As described above, for example, since the first parity data and the second parity data are generated so as to have different values, normally, the values of the third parity data and the second parity data should also be different. It is. Here, if data destruction occurs during the read period and the value of either the third parity data or the second parity data is inverted, the value of the third parity data matches the value of the second parity data, Therefore, data destruction at the time of reading can be detected. Also in this case, since a rapid data recovery process can be executed, the recovery period for data destruction caused by static electricity or the like that occurs during the data read period in the buffer memory can be shortened.

  (5) In another aspect of the memory device of the present invention, the buffer memory includes a memory cell array having a data storage area for temporarily storing data sent from the host device, and the memory cell array A first parity memory for storing the first parity data; and a second parity memory for storing the second parity data, provided separately from the memory cell array.

  In this aspect, the first parity memory that stores the first parity data and the second parity memory that stores the second parity data are provided separately from the memory cell array. The first parity memory (the same applies to the second parity memory) can be constituted by, for example, at least one flip-flop. For example, each of the plurality of flip-flops, for example, is arranged with a two-dimensional spread in an IC chip, or is arranged according to the degree of possibility of data destruction. By doing so, it is possible to increase the possibility of detecting data corruption while reducing the capacity of the parity memory.

  (6) In one aspect of the ink information transfer device of the present invention, an ink information storage unit comprising a nonvolatile memory for storing ink information relating to ink contained in the ink container, and a host for generating and outputting the ink information The ink information output from the apparatus and the host device is written to the buffer memory, the written ink information is held, the written ink information is read from the buffer memory, and the read ink information is read from the buffer memory. Including any one of the above memory devices to be supplied to an ink information storage unit, and when the host device receives a data retransmission request from the memory device after outputting the ink information to the memory device, Ink information having the same contents as the previously output ink information is output again to the memory device.

  In this aspect, when data corruption is detected in the memory device that relays the transferred ink information, a data retransmission request is output to the host device. Therefore, retransmission of the same data from the host device and rewrite of the retransmitted data to the buffer memory in the memory device can be executed early and efficiently. As a result, even if data destruction occurs, the time from when the ink information is first output from the host device until the correct ink information is stored in the non-volatile memory in the ink information storage unit is compared with the conventional case. And can be significantly shortened.

The figure which shows an example of a structure of the printing apparatus (here inkjet-type color printer) which has an ink information transfer apparatus. 2A and 2B are diagrams for explaining the operation procedure of the memory device (ASIC) according to the first embodiment. The figure which shows the specific structural example of ASIC as a memory device. Diagram for explaining the operation to detect data destruction due to static electricity or noise 5A to 5C are diagrams for more specifically explaining the parity generation operation and the parity comparison operation. FIG. 5A and FIG. 5B are timing charts showing the data write operation and data read operation of the ASIC shown in FIG. FIGS. 7A and 7B are diagrams showing the operation of the ink information transfer apparatus employing the memory device according to the first embodiment in comparison with the operation of the conventional example. 8A and 8B are diagrams showing the operation timing of the ink information transfer apparatus according to the first embodiment in comparison with the operation timing of the conventional example. The figure which shows the other example of a memory device (ASIC)

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

(First embodiment)
FIG. 1 is a diagram illustrating an example of a configuration of a printing apparatus (here, an inkjet color printer) having an ink information transfer apparatus. The ink information transfer device includes an SOC (system on chip) 100 as a host device, an ASIC (for example, an IC including a buffer memory 210 formed of SRAM) 200 as a memory device that relays transferred ink information, and And an ink information storage unit CSIC (an IC including a nonvolatile memory 310 such as an EEPROM) 300.

  The SOC 100 as the host device includes a CPU 102, a head drive unit 112, and a system bus BUS. The CPU 102 determines an R / W control unit 104 that controls reading (R) of data from the ink information storage unit CSIC300 and writing (W) of data to the ink information storage unit CSIC300, and determines that the ink remaining amount is low. It has a register 108 that stores a near-end threshold value that is a threshold value, an ink consumption calculation unit 110, and a determination unit 106 that determines the degree of ink remaining. For example, the determination unit 106 can instruct the display unit 114 to display a sentence, an icon, or the like for notifying the user that the ink remaining amount is low.

  The ink information storage unit CSIC300 is provided in a detachable ink container unit (liquid container unit) 400. In addition to the CSIC 300, the ink container part (liquid container part) 400 is provided with, for example, ink cartridges 10a to 10d for each color of cyan (C), magenta (M), yellow (Y), and black (K or Bk). ing. For example, although the ink information storage unit CSIC300 can be provided for each of the ink cartridges 10a to 10d, only one ink information storage unit CSIC300 is shown in FIG. 1 for convenience of explanation.

  Each of the ink cartridges 10 a to 10 d is held by a holder 31. The holder 31 is supported by the carriage 25. The carriage 25 can move along the guide shaft 26. The carriage 25 is fixed with heads 20a to 20d corresponding to CMYK inks. Ink of each color stored in each of the ink cartridges 10 a to 10 d is supplied to the heads 20 a to 20 d via the ink tube 32. Characters and images can be printed on the printing paper 9 by ejecting ink from the heads 20a to 20d. Each of the heads 20a to 20d is driven by a head driving unit 112 included in the SOC 100.

  When the removable ink container part (liquid container part) 400 is attached to the printing apparatus main body, various data (current inks) stored in the ink capacity memory (nonvolatile memory such as EEPROM) 310 in the CSIC 300 are provided. Capacity data, ink cartridge model number data, etc.) are read out, and the read out various data are sent to the SOC 100 via the ASIC 200. Various data received by the SOC 100 is stored in, for example, the determination unit 106 and the ink consumption 110 provided in the CPU 102.

  When printing is performed, for example, the ink consumption calculation unit 110 calculates the ink consumption based on the number of driving times of each of the heads 20a to 20d. Since the amount of ink consumed per head drive is known, the amount of ink consumed for each color can be calculated based on the number of times each head is driven. Since the ink capacity in each of the ink cartridges 10a to 10d before printing is known, the remaining amount of each ink after printing is uniquely determined if the consumption amount of each ink is obtained. When the ink consumption calculation unit 110 obtains the capacity of each ink (ink remaining amount after printing), the obtained ink capacity data is supplied to the determination unit 106 and the R / W control unit 104. When the determination unit 106 compares the near-end threshold value with the obtained ink capacity and detects that the remaining ink amount is equal to or less than the threshold value, the determination unit 106 causes the display unit 114 to display predetermined notification information.

  Further, the R / W control unit 104, for example, every time ink capacity data is obtained by the ink consumption calculation unit 110, the ink capacity data (broadly defined ink information) is transmitted via the ASIC 200 as a memory device. The data is transmitted to the CSIC 300 serving as an ink capacity storage unit. The CSIC 300 receives the transmitted ink capacity data, and writes the ink capacity data into the ink capacity memory 310 constituted by a non-volatile memory (such as an EEPROM). Data indicating the remaining amount of ink is constantly updated and held in the ink capacity memory 310, which is a non-volatile memory, so that the latest ink remaining amount information disappears even if the power is turned off due to, for example, a sudden power failure. There is nothing. In other words, the SOC 100 can read the latest ink remaining amount information from the ink capacity memory 310 after the power supply is restored, so that even if the power is unexpectedly turned off, the SOC 100 determines the remaining amount of ink of each color. Accurately grasp.

  As described above, ink capacity data (ink information in a broad sense) transmitted from the SOC 100 is temporarily stored in the buffer memory 210 in the ASIC 200 serving as a memory device, and then transferred to the CSIC 300.

  Here, when data destruction occurs due to static electricity, excessive noise, or the like in the holding period in which the ink capacity data is temporarily stored in the buffer memory 210 in the ASIC 200 or the reading period in which the ink capacity data is read. Is assumed. Conventionally, since the data destruction can be detected only by the CSIC 300, it was not possible to take an early measure against the data destruction.

  Therefore, in this embodiment, the ASIC 200 itself as a memory device is provided with a monitor function for detecting that data destruction has occurred. This point will be described below with reference to FIG.

  2A and 2B are diagrams for explaining the operation procedure of the memory device (ASIC) of the present embodiment. 2A shows an operation procedure of the comparative example, and FIG. 2B shows an operation procedure of the memory device (ASIC 200) of the present embodiment. As described above, the ASIC 200 as a memory device is located between the SOC 100 and the CSIC 300, receives data (for example, ink capacity data) transmitted from the SOC 100, temporarily holds the data, and then stores the data in the CSIC 300. Forward to.

  First, the operation of the comparative example shown in FIG. The ASIC 200 shown in FIG. 2A receives data (step S1), writes the received data to the buffer memory 210 (step S2), and at this time, executes a parity check at reception (step S3). The data written in the buffer memory 210 is held for a predetermined period (step S4), then the held data is read (step S5), and the read data is transmitted to the CSIC 300 (step S6). .

  Here, it is assumed that static electricity, excessive noise, or the like is input during the data retention period (accumulation period) or read period (readout period), and a part of the data is destroyed. In this case, the ASIC 200 cannot detect data corruption. Therefore, as a result, a data error is detected for the first time by data error detection in the CSIC 300 or the like. However, when an error is detected for the first time, it is unclear whether the data error occurred during reception or whether the data output from the ASIC 200 has been destroyed.

  Therefore, the CSIC 300 first transmits a data retransmission request (retransmission request 1) to the ASIC 200. In the above example, since the data itself is damaged, the data error is not resolved even by the retransmission of the data, the data retransmission request 2 is transmitted, and then the data retransmission request 3 is output. Since the problem is not solved by repeating the retransmission of data, it is detected at this point that there is an abnormality in the data itself sent from the ASIC 200.

  The CSIC 300 transmits a re-data write request to the SOC 100 which is the most upstream device. In response to this, the SOC 100 retransmits data having the same content as the previously transmitted data to the ASIC 200, and the ASIC 200 accumulates the retransmitted data for a predetermined period and then transmits it to the CSIC 300. In the case of this comparative example, since it is impossible to detect at an early stage that there is an abnormality in the data itself sent from the ASIC 200, it takes time to recover the data error.

  On the other hand, the ASIC 200 of the present embodiment shown in FIG. 2B has a function of detecting that data has been damaged, and therefore can transmit a data retransmission request to the SOC 100, which is a higher-level device, at an early stage. it can. Therefore, the time required for data error recovery is significantly shortened.

  That is, in the example according to the present embodiment shown in FIG. 2B, parity data for data destruction detection is newly generated when data is written (step S3 '). Then, in the data holding period, a parity check using newly generated parity data is executed (step S7). Further, a parity check at the time of data reading is executed even during the read period of the retained data (step S9).

  In this step S9, for example, parity data based on the read data is generated, and the generated parity data is compared with the parity data generated at the time of writing, whereby it is possible to detect data corruption at the time of reading. Become. In step S7 or step S9, when the result of the parity check is NG, the ASIC 200 immediately transmits a data retransmission request to the SOC 100, which is the host device.

  As described above, in the example according to the present embodiment shown in FIG. 2B, it is detected at an early stage that data destruction due to static electricity or the like has occurred. Therefore, the time required to recover the data error is significantly shortened compared to the comparative example shown in FIG.

  Next, a specific configuration example and operation of the ASIC 200 as a memory device will be described with reference to FIGS. FIG. 3 is a diagram illustrating a specific configuration example of the ASIC as the memory device.

  The ASIC 200 performs a parity check based on the lateral parity added to the buffer memory 210 composed of SRAM, the input interface (input I / F) 212, and the input data SDA (corresponding to the ink capacity information in FIG. 1). A lateral parity check unit 213 to be executed, an input / output interface (input / output I / F) 214, and an output interface (output I / F or output unit) 216 that outputs a data retransmission request RQ to the SOC that is the host device. A parity generation circuit 228 that generates vertical parity data for detecting data corruption, a first parity memory 230 that stores the generated first parity data, and a second parity memory that stores the generated second parity data 232 and the first parity data and the second parity data are compared. Has a parity comparison unit 234 detects an error (whether data destruction), and output interface (input-output I / F) 236, an output interface (output I / F) 238, a.

  Here, the buffer memory 210 includes a column decoder 220, a row decoder-222, a memory cell array 224, and a read / write circuit 226. The memory cell array 224 has a data storage area 223 for storing data SDA. Also, a first parity memory 230 and a second parity memory 232 described later can be provided in the memory cell array 224 (this configuration is assumed in the example of FIG. 3).

  An operation clock SCK and a reset signal XRST are input to the input interface (input I / F) 212. The input / output interface (input / output I / F) 214 executes input or output of data (SDA) and horizontal parity data added to the data SDA. The output interface (output I / F or output unit) 216 transmits a data retransmission request RQ to the SOC 100 when data corruption is detected based on the comparison result of the parity comparison unit 234. Further, the input / output interface (input / output I / F) 236 transmits SDA (with horizontal parity) to the CSIC 300. Further, the output interface (output I / F) 238 transmits an operation clock SCK and a reset signal XRST to the CSIC 300.

  FIG. 4 is a diagram for explaining an operation of detecting data destruction due to static electricity or noise. The data SDA written and held in the data storage area 223 in the memory cell array 224 is, for example, data of 8 rows (A0 to A7) × 8 columns (C1 to C8). Further, 1-bit horizontal parity data for detecting a communication error is added to the data SDA for each row of data (8-bit data).

  In the example of FIG. 4, odd parity is employed. That is, the value of the horizontal parity data is determined so that the number of “1” included in the 8-bit bit string is an odd number. When 1-bit data corruption occurs along with data communication, the number of “1” included in the 8-bit bit string becomes an even number, so that a data error can be detected. Detection of a data error accompanying communication is executed by the horizontal parity check unit 213 shown in FIG.

  In addition, data destruction due to static electricity or noise in the data holding period and the data read period can be detected using vertical parity data.

  As shown in the lower part of FIG. 4, the vertical parity data is composed of primary parity data that is first parity data and inverted parity data that is second parity data. The vertical parity data can be obtained by an operation (vertical parity operation) based on each of the data in the same column among the data written to the memory cell array 224. For example, the addition of the data in the same column by the binary method is executed, and the vertical parity bit as the addition result is set as, for example, first parity data (normal parity data). Also, the second parity data (inverted parity data) can be generated by inverting the value of the first parity data (normal parity data) with an inverter or the like. Such a vertical parity operation is executed by the parity generation circuit 228 shown in FIG.

  The first parity data (normal parity data) is stored in the first parity memory (or first parity memory area) 230. The second parity data (inverted parity data) is stored in the second parity memory (or second parity memory area) 232. The parity comparison unit 234 compares the first parity data (normal parity data) and the second parity data (inverted parity data), and outputs a check result signal Chk.

  As described above, in the example of the present embodiment shown in FIG. 3 and FIG. 4, the ASIC 200 itself as the memory device has the first parity data (primary parity data) and the second parity data (when the data is written to the buffer memory 210). For example, in the data holding period, the parity comparison unit 234 always compares the first parity data and the second parity data. A relationship according to a predetermined rule at the beginning of generation is established between both parity data. That is, in the example of FIG. 4, the rule that the second parity data is obtained by inverting the value of the first parity data is applied, and therefore the values (1 or 0) of both parity data do not match. The relationship is established.

  When data corruption occurs due to static electricity or the like, the relationship according to a predetermined rule at the beginning of generation does not hold between both parity data. That is, a phenomenon occurs in which the values of both data match. In this case, the check result signal Chk becomes an active level, and a data error is detected.

  That is, for example, the occurrence of data destruction in the data holding period can be detected by the ASIC 200 itself as a memory device. Therefore, it is possible to take measures against data destruction earlier than in the prior art, and therefore it is possible to reduce the time required for recovery against data destruction.

  That is, when a data error is detected, retransmission of the same data from the SOC 100, which is the host device, and rewrite of the retransmitted data to the buffer memory 210 are executed. As a result, the corrupted data can be quickly recovered.

  Further, as described above, even when data is read from the buffer memory 210, there is a possibility of data destruction due to static electricity or the like. Therefore, in this embodiment, a parity check for detecting data corruption is executed even when data is read from the buffer memory 210.

  In this case, the parity generation circuit 228 performs vertical parity calculation based on the read data to generate third parity data, and the generated third parity data is stored in the first parity memory (first parity memory area). ) 230 (for example, the first parity data is overwritten). The parity comparison unit 234 compares the third parity data with the second parity data generated at the time of data write, and when the relationship according to a predetermined rule (here, the relationship that the two data do not match) is not established. The check result signal Chk changes to the active level.

  That is, if data destruction due to static electricity or the like does not occur at the time of reading, the generated third parity data should be the same as the first parity data generated at the time of data writing. As described above, for example, the first parity data and the second parity data are generated so as to have different values. Therefore, normally, the values of the third parity data and the second parity data should be different from each other. It is.

  Here, if data destruction occurs during the read period and the value of either the third parity data or the second parity data is inverted, the value of the third parity data matches the value of the second parity data, Therefore, data destruction at the time of reading can be detected. Also in this case, since a rapid data recovery process can be executed, the recovery period for data destruction caused by static electricity or the like that occurs during the data read period in the buffer memory 210 can be shortened.

  FIG. 5A to FIG. 5C are diagrams for more specifically explaining the parity generation operation and the parity comparison operation. FIG. 5A shows the operation in the data holding period, FIG. 5B shows the operation in the data read period, and FIG. 5C shows the vertical parity generation operation.

  As shown in FIG. 5A, data SDA, a write enable signal WE, and a reset signal XRST are input to the write circuit 226a. At the time of writing, the write enable signal WE is at an active level. The inverters INV1 to INV8 are provided to invert the level of the first parity data (normal parity data) to generate inverted parity data. The parity generation circuit 228 performs vertical parity calculation based on data written to the memory cell array 224, and generates first parity data (normal parity data) and second parity data (inverted parity data).

  The parity generation circuit 228 includes, for example, a cumulative adder (accumulator) as shown in FIG. The cumulative adder (accumulator) includes an adder 229 that adds data in the same column and a register 231 that stores the addition result. A cumulative adder (accumulator) is provided for each data string. In the example of FIG. 5C, when the data in the A0 row C1 column is X and the data in the A1 row C2 column is Y, the adder 229 performs an X + Y operation (binary addition operation), and the result Is stored in the register 231. Similarly, cumulative addition is executed each time data is written, and when the data in the A7 row is written, the addition result of the data in the same column of the data in the A0 to A7 rows is stored in the register 231. Has been.

  The addition result is the first parity data (positive parity data). Also, the second parity data is generated by inverting the level of the first parity data (normal parity data) by the inverter INV1.

  According to this example, for example, 1-bit vertical parity data can be easily generated for each data string without difficulty. In addition, since vertical parity is generated for each data string, vertical parity data is generated for the number of bits of data (here, 8 bits), and the total number of vertical parity data increases. It becomes easy to detect destruction. Also, regarding the possibility of data destruction, even when there is a variation in the two-dimensional memory area, vertical parity is generated for each data string (that is, the data is vertically expanded along the row direction of the write data). (Parity is arranged), the possibility of detecting data corruption in an area where data destruction is likely to occur is increased.

  In the example shown in FIG. 5B, a write enable signal WE and a reset signal XRST are input to the read circuit 226b. At the time of reading, the write enable signal WE is at an inactive level. The read data SDA is output from the read circuit 226b.

  The parity generation circuit 228 performs vertical parity calculation based on the data read from the memory cell array 224 to generate third parity data (normal parity data). Note that generation of inverted parity data based on the read data is not performed. Therefore, the second parity memory 232 stores the second parity data generated at the time of writing as it is. The parity comparison unit 234 compares the third parity data (positive parity data) with the second parity data generated at the time of writing. When the coincidence of both data is detected, the check result signal Chk becomes an active level.

  5A and 5B, the first parity memory (first parity memory area) 230 that stores the first parity data and the second parity memory that stores the second parity data. The (second parity memory area) 232 is provided in the memory cell array 224, for example. For example, when an SRAM is used as the buffer memory, the memory cell array 224 is expanded, and word lines and memory cells are added in the vicinity of the data storage area 223 for storing the data SDA, so that the first parity memory area and the second parity memory area are stored. There is no particular problem in securing the memory area. Therefore, this configuration is easy to realize.

  For example, if the data storage area has a storage capacity of m rows and n columns (each of m and n is an integer of 2 or more), the vertical direction based on each of the data in the same column in the written data SDA. Parity operation is performed. As described above, each of the generated first parity data and second parity data is stored in each of the first parity memory (first parity memory area) 230 and the second parity memory (second parity memory area) 232. Is done.

  In the example shown in FIGS. 5A and 5B, the parity check at the time of data reception (or data write) using the horizontal parity data, the vertical period in the data holding period and the data read period Parity check using parity is also used. Therefore, the reliability of data error detection is increased.

  In the example shown in FIG. 4, the horizontal parity bit is 1 bit, but the horizontal parity bit is not limited to this, and the horizontal parity bit can be s bits (s is an integer of 1 or more). In this case, the data storage area 223 provided in the memory cell array 224 has a size for storing at least m rows (n + s) columns of data.

  FIG. 6 is a timing chart showing an operation at the time of data writing and an operation at the time of data reading of the ASIC shown in FIGS. 5 (A) and 5 (B). In FIG. 6, a period T1 between times t1 and t3 is a data write period. During the period from time t1 to time t2, the write command, data SDA, and horizontal parity (indicated as 1P in the figure) are written to the memory cell array 224. The period from time t2 to time t3 is the vertical parity write period T2. In this period T 2, vertical parity data is generated, and the generated vertical parity data is written to the first parity memory 230 and the second parity memory 232.

  A period T3 from time t3 to time t5 is a data holding period after writing. In this data holding period T3, data corruption due to static electricity or the like is checked. This period T3 can also be referred to as a monitor period after writing.

  A period T4 from time t5 to time t7 is a data read period. During the period from time t5 to t6, the read command, data SDA, and horizontal parity (1P) are read from the memory cell array 224. A period T5 from time t6 to time t7 is a write period of the normal parity data (third parity data) at the time of reading. That is, in this period T5, third parity data (primary parity data) is generated, and the generated third parity data is overwritten on the first parity memory 230.

  A period T6 from time t7 to t8 is a post-read monitoring period. In the post-read monitoring period T6, the presence or absence of data destruction during the data SDA read period is checked.

  When it is detected that data corruption has occurred during the data SDA read period, the data read from the buffer memory 210 may already be transmitted to the CSIC 300 at the next stage. In this case, for example, the ASIC 200 may transmit a notification signal indicating that a data error has occurred to the CSIC 300, and the data received by the CSIC 300 may be discarded by the notification signal.

  FIG. 7 is a diagram showing the operation of the ink information transfer apparatus employing the memory device of the present embodiment in comparison with the operation of the conventional example. FIG. 7A shows the operation of the comparative example, and FIG. 7B shows the operation of the ink information transfer apparatus according to the present embodiment. As shown in FIG. 1, the ink information transfer device (data transfer system) includes an SOC 100 as a host device, a memory device (ASIC) 200 having a buffer memory 210, and a CSIC 300 as an ink information storage unit. Is done.

  As shown in FIG. 7A, conventionally, first, data is written to the ASIC 200 (step ST1). In ASIC 200, a parity check at the time of reception using horizontal parity data is executed (step ST2). If the check result is NG, the first count is incremented and the process returns to step ST1. If the check result is OK, the data read from the ASIC 200 is sent to the CSIC 300, and the data is written to the CSIC 300 (step ST4). In CSIC 300, a parity check at the time of reception using horizontal parity is executed (step ST5). If the check result is NG, the second count is incremented and the process returns to step ST4. When the value of the second count exceeds the allowable range, the third count is incremented (step ST7), and the process returns to step ST1.

  On the other hand, as shown in FIG. 7B, in the ink information transfer apparatus according to the present embodiment, data is first written to the ASIC 200 (step ST1), and the ASIC 200 stores the horizontal parity data. The parity check at the time of reception used is executed (step ST2). If the check result is NG, the first count is incremented and the process returns to step ST1. If the check result is OK, a parity check is performed in the data holding period or data read period using vertical parity data (step ST4). If the check result is NG, the process increments and returns to step ST1, and step ST1 and step ST2 are executed again (retry operation for error recovery).

  If the result of the parity check is OK in step ST4, the data read from the ASIC 200 is sent to the CSIC 300, and the data is written to the CSIC 300 (step ST5). In CSIC 300, a parity check at the time of reception using horizontal parity is executed (step ST6). If the check result is NG, the second count is incremented, and then, for example, it is determined whether the result of the parity check using vertical parity data is NG or OK (step ST8). If OK, the process returns to step ST5. If NG, the process returns to step ST1.

  If the result of the parity check in step ST6 is OK, a parity check using vertical parity data is executed (step ST9). If the check result in step ST9 is NG, the process returns to step ST1. Note that the above operation example is an example, and the present invention is not limited to this operation.

  FIGS. 8A and 8B are diagrams illustrating the operation timing of the ink information transfer apparatus according to the present embodiment in comparison with the operation timing of the conventional example. Here, it is assumed that a part of data is damaged due to static electricity or the like in the data holding period after data is written to the ASIC 200.

  In the conventional example shown in FIG. 8A, three retry processes are executed in the period from time t5 to time t10. This number is managed by the second count shown in the operation flow of FIG. Since the data error is not resolved by the third retry, the data is retransmitted from the SOC 100, which is the most upstream host device, at time t11, the write operation of the data to the ASIC 200 is executed, and then at time t13. Data output from the ASIC 200 is written to the CSIC 300. The number of retries at times t11 to t14 is managed by the third count shown in the operation flow of FIG. As a result, in the conventional example of FIG. 8A, it takes time from time t1 to time t14 before correct data is written to the ASIC 200.

  In contrast, in the example according to the present embodiment shown in FIG. 8B, the ASIC 200 itself can detect data corruption based on the parity check result Chk. Therefore, rewriting of the same data to the ASIC 200 is executed at time t3. Therefore, in the example according to this embodiment shown in FIG. 8B, the time until the correct data is written to the ASIC 200 is the time from time t1 to time t6. Therefore, the time required for error recovery of data is remarkably reduced as compared with the conventional example.

(Second Embodiment)
FIG. 9 is a diagram illustrating another example of the memory device (ASIC). In the example shown in FIG. 9, a first parity memory (flip-flops FF1, FF3, FF5) that stores first parity data and a second parity memory (flip-flops FF2, FF4, FF6) that stores second parity data are included. The memory cell array 224 for storing the data SDA is provided separately.

  The first parity memory and the second parity memory can be configured by at least one flip-flop. For example, each of the plurality of flip-flops (FFs) is distributed and arranged with a two-dimensional spread, for example, in an IC chip, or is distributed according to the degree of possibility of data destruction. If such measures are taken, it is possible to increase the possibility of detecting data corruption while reducing the capacity of the parity memory.

  When static electricity or noise is superimposed on the power supply line (VDD), the higher the ground line resistance, the greater the rise of the ground potential. Therefore, data corruption of the flip-flop (FF) at that location is likely to occur. In the example of FIG. 9, resistors R1 and R2 are interposed in the ground line. Therefore, data corruption is most likely to occur in the flip-flops FF1 and FF2, and then data corruption is most likely to occur in the flip-flops FF3 and FF4.

  For example, in the data holding period, the parity comparison unit 234 constantly compares the data values of FF1 and FF2, compares the data values of FF3 and FF4, and compares the data values of FF5 and FF6. For example, when data coincidence is detected for any one of them, the check result signal Chk changes to the active level. The check result signal Chk can be used as an error detection signal.

  As described above, according to at least one embodiment of the present invention, the recovery period for data destruction caused by static electricity or the like that occurs during the data holding period or the data read period of the buffer memory is remarkably shortened compared to the conventional example. can do.

  Although several embodiments have been described above, it is easily understood by those skilled in the art that many modifications can be made without substantially departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings.

9 printing paper, 10a-10d ink cartridge,
20a to 20d head, 25 carriage, 26 guide shaft, 31 holder,
32 ink tube, 104 control unit, 106 determination unit, 108 register,
110 ink consumption calculation unit, 112 head drive unit, 114 display unit,
210 Buffer memory, 213 Horizontal parity check section,
220 column decoder,
224 memory cell array (memory cell array area),
226 read / write circuit, 226a write circuit, 226b read circuit,
228 parity generation circuit, 229 adder, 230 first parity memory,
231 registers, 232 second parity memory,
234 Parity comparison unit, 300 ink information storage unit,
310 Nonvolatile memory

Claims (6)

A buffer memory that stores data sent from the host device;
Parity for generating first parity data and second parity data related to the first parity data according to a predetermined rule based on the written data when the data is written to the buffer memory A generation circuit;
A parity comparison unit that compares the first parity data and the second parity data in a holding period in which the written data is held in the buffer memory;
As a result of comparison by the parity comparison unit, when the relationship according to the predetermined rule is not established, an output unit that outputs a data retransmission request to the higher-level device;
A memory device comprising: The memory device according to claim 1,
The buffer memory has a memory cell array, and the memory cell array temporarily stores at least m rows and n columns (m and n are integers of 2 or more) for temporarily storing data sent from the host device. ) Data storage area, a first parity memory area for storing the first parity data, and a second parity memory area for storing the second parity data,
The parity generation circuit generates the first parity data and the second parity data, which are vertical parity data, by performing an operation based on each of the data in the same column among the data written in the data storage area. A memory device characterized by that. The memory device according to claim 2,
In the data sent from the host device, s bits (s is an integer of 1 or more) horizontal parity data is added for each n bits of data,
The data storage area has a storage capacity of at least m rows (n + s) columns;
The memory device further includes a lateral parity check unit that performs a parity check based on each of the s-bit lateral parity data added to each n-bit data. The memory device according to any one of claims 1 to 3,
The parity generation circuit generates third parity data based on the read data when the data is read from the buffer memory;
The parity comparison unit compares the third parity data with the second parity data, and the output unit, as a result of the comparison by the parity comparison unit, the relationship according to the predetermined rule is not established, A memory device that outputs a data retransmission request to the host device. The memory device according to claim 1,
The buffer memory is
A memory cell array having a data storage area for temporarily storing data sent from the host device;
A first parity memory that is provided separately from the memory cell array and stores the first parity data;
And a second parity memory for storing the second parity data, which is provided separately from the memory cell array. An ink information storage unit comprising a non-volatile memory for storing ink information relating to the ink contained in the ink container;
A host device that generates and outputs the ink information;
The ink information output from the host device is written to a buffer memory, the written ink information is held, the written ink information is read from the buffer memory, and the read ink information is stored in the ink information The memory device according to any one of claims 1 to 5, comprising:
When the host device receives the data retransmission request from the memory device after outputting the ink information to the memory device, the upper device outputs the ink information having the same content as the previously output ink information. The ink information transfer device is characterized in that the information is output again.

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