JP2012185724A - System, host device, and error detecting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system, a host device, an error detecting method and the like capable of detecting a failure of a circuit for detecting an imperfect contact of a terminal.SOLUTION: The system comprises a host device 10 and a storage device 20. The storage device 20 includes: a nonvolatile storage section 60, an access control section 36 performing an access control to the nonvolatile storage section 60; and a detecting circuit 32 for detecting at least one floating state of a power supply terminal TV and a ground terminal TG. The host device 10 includes: a switching circuit 50 that switches a supply/non-supply of a detecting object voltage for detecting the floating state of either of a power supply voltage VDD and a ground voltage VSS; and a determination section 70 for determining, when the detecting object voltage is set to the non-supply, whether the detecting circuit 32 is normal or not based on a signal from the storage device 20.

Description

  The present invention relates to a system, a host device, an error detection method, and the like.

  As a nonvolatile memory, EEPROM, FERAM, and the like are known. These memories transmit / receive data to / from the host device and read / write the data. For example, an ink cartridge is attached to an ink jet printer. Some ink cartridges are provided with a storage device having a nonvolatile memory (for example, Patent Document 1). The nonvolatile memory stores various information such as ID, manufacturing information, and ink remaining amount, and the storage device transmits and receives such information to and from the printer.

JP 2004-299405 A Japanese Patent Laid-Open No. 10-011558 Japanese Patent Laid-Open No. 2001-222689 JP 2001-202479 A JP-A-6-325222

  However, when an abnormality occurs in the power supply of the storage device, there is a possibility that data stored in the non-volatile memory may be destroyed because the data is not read / written normally. For example, a storage device of an ink cartridge and a printer are generally connected by contact of a terminal, and power is supplied from the printer to the storage device via the terminal. At this time, if the contact of the power supply terminal becomes defective during access to the nonvolatile memory, data stored in the nonvolatile memory may be destroyed by reading / writing.

  For example, Patent Documents 2 to 5 disclose a method in which an IC card side detects a terminal contact failure in a system in which an IC card and a reader / writer are connected by contact of terminals. In Patent Documents 2 to 5, when the reader / writer recognizes that a contact failure has been detected, the reader / writer performs processing corresponding thereto.

  However, this method does not take into account the case where no contact failure is detected due to failure of the IC card or the like. For example, when a circuit for detecting a contact failure of a power supply terminal is broken, there is a possibility that even if there is a contact failure of the power supply terminal, the power supply wraps around from other signal terminals and appears to be operating normally. If the memory is accessed in this state, for example, the retention of stored data (garbled data) may occur in the nonvolatile memory.

  According to some aspects of the present invention, it is possible to provide a system, a host device, an error detection method, and the like that can detect a failure of a circuit that detects contact failure of a terminal.

  One embodiment of the present invention is a system including a host device and a storage device, and the storage device includes a nonvolatile storage unit, and an access control unit that performs read or write access control on the nonvolatile storage unit. A detection circuit that detects a floating state of at least one of a power supply terminal connected to the host-side power supply terminal and a ground terminal connected to the host-side ground terminal, and the host device includes the host-side power supply terminal A switching circuit for switching supply / non-supply of the detection target voltage for detecting the floating state among the power supply voltage supplied to the host and the ground voltage supplied to the host-side ground terminal, and the detection target voltage is set to non-supply If the detection circuit is normal, it is determined whether the detection circuit is normal or not based on a signal from the storage device Relating to a system having a tough, the.

  According to one aspect of the present invention, the floating state of at least one of the power supply terminal and the ground terminal is detected, and supply / non-supply of the detection target voltage for detecting the floating state of the power supply voltage and the ground voltage is switched. When the detection circuit is operating normally, if the detection target voltage is set to non-supply, the signal from the storage device becomes abnormal, so the host device determines whether the detection circuit is operating normally. Can be determined. As a result, it is possible to detect a failure of a circuit that detects a contact failure of a terminal.

  In the aspect of the invention, the access control unit stops the access control when the detection circuit detects the floating state, and the determination unit sets the detection target voltage to non-supply. In this case, it may be determined whether the detection circuit has normally detected the floating state based on a signal from the access control unit in which the access control is stopped.

  In this way, it is possible to determine whether or not access control has been stopped based on a signal from the access control unit, so that it is possible to determine whether or not the detection circuit is normal.

  In the aspect of the invention, the host device includes a communication control unit that performs communication control with the access control unit, and the communication control unit is configured to store the nonvolatile memory via the access control unit. Performing the access control to a unit, receiving transmission data from the access control unit according to the access control, and the determination unit determines whether the received transmission data and the access control are stopped The determination of normality / non-normality may be performed by comparing with determination data for the purpose.

  In this way, it is possible to determine whether or not the access control is stopped based on the transmission data from the access control unit, and it is possible to detect whether the detection circuit is normal or abnormal based on the determination result. .

  In the aspect of the invention, the determination unit may determine whether the access control is stopped when the detection target voltage is supplied. If the determination unit determines that the access control is not stopped, the detection unit It may be determined whether or not the access control is stopped when the target voltage is set to non-supply, and it is determined that the detection circuit is normal when it is determined that the access control is stopped.

  In the aspect of the invention, when the determination unit determines that the access control is stopped when the detection target voltage is supplied, the determination unit determines that the detection target voltage is set to non-supply. It is not necessary to perform.

  In this way, the fact that the floating state is not detected in the supply state of the detection target voltage can be used as a condition for normal / unnormal determination. Further, when the access control is abnormal in the supply state, the determination in the non-supply state can be omitted.

  In one embodiment of the present invention, the storage device includes a first signal terminal connected to a first host-side signal terminal to which a first signal from the host device is supplied, and the first signal terminal. And a first diode element provided between the power supply terminal and the power supply terminal in the floating state, a high level voltage of the first signal is applied to the power supply terminal. It may be supplied via the first diode element.

  In the aspect of the invention, the first signal may be a reset signal, and the reset signal may be set to a high level when the access control unit performs the access control.

  In one embodiment of the present invention, the storage device includes a second signal terminal connected to a second host-side signal terminal to which a second signal from the host device is supplied, and the second signal terminal. And a second diode element provided between the ground terminal and the ground terminal, and when the ground terminal is in the floating state, a low level voltage of the second signal is applied to the ground terminal. It may be supplied via the second diode element.

  In this way, even when the power supply terminal or the ground terminal is in a floating state, the dropped power supply voltage or ground voltage is supplied to the storage device. Therefore, if the detection circuit is abnormal, the nonvolatile storage unit At first glance it may be possible to access normally. According to one embodiment of the present invention, whether a detection circuit is normal or abnormal can be determined, so that memory access in a floating state can be suppressed.

  According to another aspect of the present invention, at least one of a power supply terminal connected to a host-side power supply terminal and a ground terminal connected to a host-side ground terminal is performed while performing read or write access control to a nonvolatile storage unit. Supply / non-supply of the detection target voltage for detecting the floating state among the power supply voltage supplied to the host-side power supply terminal and the ground voltage supplied to the host-side ground terminal when detecting the floating state of This is related to an error detection method for determining whether the detection circuit is normal or not based on a signal from the access control unit when the detection target voltage is set to non-supply.

  Another aspect of the present invention includes a switching circuit and a determination unit. A storage device to which a power supply voltage and a ground voltage are supplied from a host device includes a nonvolatile storage unit and the nonvolatile storage unit. An access control unit that performs read or write access control on the power supply, a power supply terminal connected to the host-side power supply terminal, and a detection circuit that detects a floating state of at least one of the ground terminals connected to the host-side ground terminal. The switching circuit is configured to supply or not supply a detection target voltage in which the floating state is detected among the power supply voltage supplied to the host-side power supply terminal and the ground voltage supplied to the host-side ground terminal. A switching circuit for switching between and an access control unit when the detection target voltage is set to non-supply The detection circuit is related to determining the host device whether a non-normal or normal on the basis of al of the signal.

1 is a configuration example of a system according to the present embodiment. 3 shows a detailed configuration example of a host device. The flowchart example which shows operation | movement of the system of this embodiment. 3 shows a detailed configuration example of a storage device. An example of system operation when the power supply terminal is floating. 2 is a configuration example of an ink cartridge. FIG. 7A and FIG. 7B are configuration examples of the substrate. 2 is a detailed configuration example of a system according to the present embodiment. The signal waveform example in the case of reading data from a memory | storage device. The flowchart example of a read process of a printer. 7 is a flowchart example of storage device access control processing. An example of a signal waveform when data is written to a storage device. The flowchart example of the write process of a printer. 4 is a detailed flowchart example of a write process of a storage device. 3 shows a detailed configuration example of a detection circuit. 16A to 16C are detailed configuration examples of the VSS detection circuit. 17A and 17B are explanatory diagrams of a ferroelectric memory.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration FIG. 1 shows a configuration example of a system according to this embodiment. The system includes a host device 10 and a storage device 20. In the following, a case where the host device 10 is an ink jet printer main body and the storage device 20 is a storage device provided in an ink cartridge will be described as an example. However, the present embodiment is not limited to this. For example, the host device 10 may be a memory card reader / writer, and the storage device 20 may be a memory card.

  The host device 10 is connected to the storage device 20 via a terminal, and performs communication control with the storage device 20 and failure detection of the detection circuit 32 of the storage device 20. Specifically, the host device 10 includes a power supply circuit 40, a switching circuit 50, a determination unit 70, a communication control unit 80, a host side power supply terminal TVH, a host side ground terminal TGH, a host side clock terminal TKH, a host side data terminal TDH, A host-side reset terminal TRH is included.

  The power supply circuit 40 generates a power supply voltage VDD (high-potential-side power supply voltage in a broad sense) and a ground voltage VSS (low-potential-side power supply voltage), and outputs the generated voltages VDD and VSS to the host device 10 and the storage device 20. Supply.

  The switching circuit 50 switches whether the power supply voltage VDD (high potential side power supply voltage in a broad sense) and the ground voltage VSS are supplied to the storage device 20 or not. In the case of non-supply, the power supply terminal TVH and the power supply circuit 40 or the ground terminal TGH and the power supply circuit 40 are disconnected to bring the power supply terminal TVH and the ground terminal TGH into a floating state. The non-contact of the terminal is simulated by this floating state.

  The communication control unit 80 performs communication with the storage device 20 via the clock terminal TKH, the data terminal TDH, and the reset terminal TRH. For example, the communication control unit 80 controls read / write (reading or writing) with respect to the storage device 20, reception of read data, transmission of write data, conversion processing between data and a communication format, and control of the storage device 20. Command issuance and communication error detection processing. The communication control unit 80 controls the switching circuit 50.

  The determination unit 70 determines whether the detection circuit 32 of the storage device 20 is normal or abnormal (failure) based on the received data from the storage device 20. Specifically, the determination unit 70 performs determination based on the communication result in the supply state of VDD and VSS and the communication result in the non-supply state. The received data from the storage device 20 is not limited to data read from the nonvolatile memory 60 of the storage device 20, but may be data or bits used for communication control.

  The storage device 20 is connected to the host device 10 via a terminal, and performs memory access, detection of terminal contact failure, and the like according to control from the host device 10. Specifically, the storage device 20 includes a detection circuit 32, an access control unit 36, a nonvolatile memory 60 (a nonvolatile storage unit in a broad sense), a power supply terminal TV, a ground terminal TG, a clock terminal TK, a data terminal TD, and a reset. Including terminal TR. Hereinafter, a case where the nonvolatile storage unit is the nonvolatile memory 60 will be described as an example, but the present embodiment is not limited to this. For example, the nonvolatile storage unit may be a magnetic drive such as a hard disk drive or an optical drive such as a DVD.

  The power supply terminal TV, the ground terminal TG, the clock terminal TK, the data terminal TD, and the reset terminal TR are respectively a host-side power supply terminal TVH, a host-side ground terminal TGH, a host-side clock terminal TKH, a host-side data terminal TDH, It is electrically connected to the host side reset terminal TRH. For example, each terminal is composed of a metal terminal, and the terminals are electrically connected by being in physical contact. When the terminals are connected, the power supply terminal TV, the ground terminal TG, the clock terminal TK, the data terminal TD, and the reset terminal TR are respectively supplied with the power supply voltage VDD, the ground voltage VSS, the system clock SCK, and the data signal from the host device 10. SDA and reset signal XRST are supplied.

  The detection circuit 32 detects an abnormality in the power supplied to the storage device 20 and outputs a detection signal (information on the detection result) to the access control unit 36. Specifically, the detection circuit 32 detects the floating state (open state, non-contact state) of the power supply terminal TV and the floating state of the ground terminal TG. The floating state occurs, for example, due to foreign matter insertion between terminals or poor contact between terminals. The detection circuit 32 detects these floating states based on voltages from the power supply terminal TV and the ground terminal TG. The detection circuit 32 may further detect a voltage drop of the power supply voltage VDD.

  The access control unit 36 performs access control to the nonvolatile memory 60, data transmission / reception (data communication) with the host device 10, and the like. Specifically, the access control unit 36 reads or writes data stored in each address of the nonvolatile memory 60 or writes data to each address of the nonvolatile memory 60 in synchronization with the system clock SCK. Perform the operation (write operation). The access control unit 36 may perform sequential access to the nonvolatile memory 60 or may perform random access.

  Further, when the detection circuit 32 detects a floating state of the terminal, the access control unit 36 stops access to the nonvolatile memory 60 and data transmission / reception with the host device 10. This prevents the stored data from being destroyed by uncertain memory access.

  The nonvolatile memory 60 is composed of, for example, an EEPROM such as FERAM (ferroelectric memory) or flash memory. The nonvolatile memory 60 may include a memory array, a column selection circuit, and a row selection circuit. The nonvolatile memory 60 stores the ID and manufacturing information written at the time of manufacturing, and information written from the host device 10. For example, in the case of an ink cartridge, the nonvolatile memory 60 stores manufacturing date information, ink color information, and the like as manufacturing information, and stores ink remaining information as information written from the host device 10.

2. Host Device FIG. 2 shows a detailed configuration example of the host device 10 described above. The host device includes a power supply circuit 40, a switching circuit 50, a determination unit 70, a memory 71 (storage unit), a data comparison unit 72, a communication control unit 80, and terminals TVH, TGH, TKH, TDH, and TRH. The switching circuit 50 includes a first switch element SW1, a second switch element SW2, and a switch control unit 55.

  The switch element SW1 is provided between the VDD output node of the power supply circuit 40 and the power supply terminal TVH. The switch element SW2 is provided between the VSS output node of the power supply circuit 40 and the ground terminal TGH. When the switch elements SW1 and SW2 are turned off, the terminals TVH and TGH enter a floating state.

  The switch control unit 55 performs on / off control of the switch elements SW <b> 1 and SW <b> 2 based on the on / off control signal from the communication control unit 80. Specifically, when the host device 10 performs a failure detection operation of the detection circuit 32 of the storage device 20, the switch control unit 55 switches on and off the switch elements SW1 and SW2, and the host device 10 performs normal operation. When performing, the switch elements SW1 and SW2 are always turned on.

  The memory 71 stores write data written to the nonvolatile memory 60 and read data read from the nonvolatile memory 60. The memory 71 stores determination data for determining whether or not the access to the nonvolatile memory 60 has been normally performed. For example, the ink cartridge ID and serial number are stored as determination data. Alternatively, write data, communication control data such as SOF, and logically inverted data thereof may be used as the determination data.

  The data comparison unit 72 compares the data received by the communication control unit 80 with the determination data (known data in a narrow sense) and outputs the comparison result to the determination unit 70. The determination unit 70 performs determination based on the comparison result.

3. Operation Next, the operation of the system when the failure determination of the detection circuit 32 is performed will be described. The failure determination is performed, for example, at the initial operation after turning on the power to the ink jet printer or at the time of replacing the ink cartridge.

  FIG. 3 shows an example of a flowchart. As shown in FIG. 3, when the failure determination operation is started, the switch elements SW1 and SW2 are turned on, and the voltages VDD and VSS are supplied to the storage device 20 (S1). Data is written to the nonvolatile memory 60, and the written data is read from the nonvolatile memory 60 (S2). The determination unit 70 of the host device compares the write data with the read data received from the storage device 20 via the communication control unit 80 (S3). If the write data does not match the read data (S4, NO), it is determined that there is a communication error, and the process ends.

  If the write data matches the read data (S4, YES), the switch elements SW1 and SW2 are turned off, and the voltages VDD and VSS are set in a floating state (S5). Data is written to the nonvolatile memory 60, and the written data is read from the nonvolatile memory 60 (S6). The determination unit 70 of the host device compares the write data with the read data received from the storage device 20 via the communication control unit 80 (S7). If the write data and the read data do not match (S8, YES), it is determined that the floating state is normally detected by the detection circuit 32 and that the detection circuit 32 is not faulty (S9). If the write data and the read data match (S8, NO), it is determined that the detection circuit 32 has failed.

  In the above description, the case where the failure determination is performed by verifying the write data has been described, but the present embodiment is not limited to this. For example, only a read operation for reading an ID or the like stored in the non-rewritable area of the nonvolatile memory 60 may be performed to determine whether or not the read ID is correct. Alternatively, only the write operation is performed with respect to the nonvolatile memory 60, and the access control unit 36 returns an OK / NG flag (described later) attached to the write data to the host device 10 to check whether or not the bit is correct. You may judge.

  For example, when the detection circuit 32 has not failed, when the detection circuit 32 detects a floating state, data transmission / reception from the access control unit 36 to the communication control unit 80 is stopped, and the signal from the access control unit 36 is, for example, all-zero data. Become. In this case, when the communication control unit 80 reads the ID, it becomes zero data. When the communication control unit 80 writes, the OK / NG flag returned from the access control unit 36 becomes low level (NG). As a result, it can be seen that the detection circuit 32 has not failed.

  In the present embodiment, all-zero data may be used as the determination data. For example, if the received data is all zero when power is not supplied, the detection circuit 32 can be determined to be normal.

  Here, the case where the data transmission / reception of the access control unit 36 is stopped when the floating state is detected has been described as an example. However, the present embodiment is not limited to this. For example, the access control unit 36 may transmit some notification signal to the host device 10 when a floating state is detected.

  As described above, as shown in FIG. 1, the system according to the present embodiment includes the host device 10 and the storage device 20. The storage device 20 includes a nonvolatile storage unit (nonvolatile memory 60), an access control unit 36, and a detection circuit 32. The access control unit 36 performs read or write (read / write) access control with respect to the nonvolatile storage unit. The detection circuit 32 detects a floating state of at least one of the power supply terminal TV connected to the host-side power supply terminal TVH and the ground terminal TG connected to the host-side ground terminal TGH.

  The host device 10 includes a switching circuit 50 and a determination unit 70. The switching circuit 50 switches supply / non-supply of a detection target voltage for detecting a floating state among the power supply voltage VDD supplied to the host-side power supply terminal TVH and the ground voltage VSS supplied to the host-side ground terminal TGH. The determination unit 70 determines whether the detection circuit 32 is normal or abnormal based on a signal from the storage device 20 when the detection target voltage is set to non-supply.

  In this way, it is possible to detect a failure of the detection circuit 32 that detects contact failure of the terminals. That is, the switching circuit 50 makes the detection target voltage non-supplied, so that a floating state of the terminal can be created. Then, whether or not the detection circuit 32 is operating normally in the non-supply state can be detected. For example, if a write operation is performed in a state where VDD is dropped due to wraparound from a signal line as will be described later with reference to FIG. 15 or the like without detecting a contact failure of the power terminal TV, the written data is retained over time. (Data corruption) may occur. In this regard, according to the present embodiment, since the failure of the detection circuit 32 can be detected, memory access in a poor contact state can be suppressed.

  In the present embodiment, the detection circuit 32 may detect the floating state of only one of the terminals TV and TG. In this case, the detection target voltage is a voltage supplied to one of the terminals. Alternatively, the detection circuit 32 may detect the floating state of both the terminals TV and TG. In this case, the detection target voltages are both the voltages VDD and VSS.

  In this embodiment, the access control unit 36 stops access control when the detection circuit 32 detects a floating state. The determination unit 70 determines whether the detection circuit 32 has normally detected the floating state based on a signal from the access control unit whose access control has been stopped when the detection target voltage is set to non-supply. To do.

  In this way, it is possible to determine whether or not access control is stopped based on a signal from the access control unit 36. That is, when it is determined that the access control is not stopped, it can be determined that the detection circuit 32 has failed.

  In the present embodiment, failure detection may be performed based on signals other than the signals (XRST, SCK, SDA) from the access control unit 36. For example, the storage device 20 may have another control terminal (not shown), and failure detection may be performed based on the signal level of the signal from the control terminal in the VDD non-supply state.

  In the present embodiment, the host device 10 includes a communication control unit 80 that performs communication control with the access control unit 36. The communication control unit 80 performs access control on the nonvolatile storage unit via the access control unit, and receives transmission data from the access control unit according to the access control. The determination unit 70 compares the received transmission data with the determination data for determining whether or not the access control is stopped, and performs normal / unnormal determination.

  For example, as shown in FIG. 3, in the case of write access, the transmission data is read data, and the determination data is write data. Alternatively, as shown in FIG. 10, in the case of ID data read access, the transmission data is ID data, and the determination data is the same ID data. Alternatively, as shown in FIG. 13, in the case of write access, the transmission data is an OK / NG flag, and the determination data is “1” corresponding to the OK flag or “0” corresponding to the NG flag.

  In this way, whether or not access control is stopped can be determined based on transmission data from the access control unit, and a failure of the detection circuit 32 can be detected based on the determination result.

  In the present embodiment, as shown in S1 to S4 in FIG. 3, the determination unit 70 determines whether or not access control is normal when the detection target voltage is supplied. As shown in S5 to S8, when it is determined to be normal, it is determined whether or not the access control is stopped when the detection target voltage is set to non-supply. As shown in S9, when it is determined that the detection has been stopped, it is determined that the detection circuit 32 is normal.

  In this embodiment, as shown in S4, when the determination unit 70 determines that the access control is abnormal when the detection target voltage is supplied, the detection target voltage is set to non-supply. No judgment is made in case.

  In this way, the failure determination condition can be that the floating state is not detected in the supply state of the detection target voltage. Further, when the access control is abnormal in the supply state, the error determination can be performed by omitting the determination in the non-supply state.

4). Storage Device FIG. 4 shows a detailed configuration example of the storage device 20 described above. The storage device includes a detection circuit 32, an access control unit 36, a nonvolatile memory 60, and terminals TV, TG, TK, TD, and TR. The access control unit 36 includes a mask processing unit 34 and a transmission / reception unit 38 (reception unit or transmission unit).

  The mask processing unit 34 performs mask processing of the system clock SCK based on the detection signal from the detection circuit 32. Here, the system clock SCK is a clock used for controlling the storage device 20. For example, the SCK is a clock for generating a clock for read / write access control of the nonvolatile memory and for transmitting and receiving data between the host device 10 and the storage device 20. The system clock SCK may be supplied from the host device 10 or may be generated inside the storage device 20.

  When a power supply abnormality is detected by the detection circuit 32, the mask processing unit 34 masks the system clock SCK from the clock terminal TK. That is, the system clock SCK is not supplied to the access control unit 36, the transmission / reception unit 38, and the like. For example, the SCK is not supplied by fixing the system clock after mask processing to a low level (first logic level) or a high level (second logic level). In this case, the operation of the storage device 20 is stopped. That is, no read / write operation with respect to the nonvolatile memory 60 or data transmission / reception with the host device 10 is performed. On the other hand, when the power supply abnormality is not detected by the detection circuit 32, the mask processing unit 34 does not mask the system clock SCK and supplies SCK to the components of the storage device 20. In this case, the storage device 20 performs a normal operation.

  The transmission / reception unit 38 performs data transmission / reception between the host device 10 and the storage device 20 based on the system clock from the mask processing unit 34. Then, the transmission / reception unit 38 outputs the received data to the access control unit 36, and the access control unit 36 writes the data in the nonvolatile memory 60. The transmission / reception unit 38 transmits the data read from the nonvolatile memory 60 by the access control unit 36 to the host device 10. More specifically, the transmission / reception unit 38 receives the data signal SDA from the host device 10 via the data terminal TD. The received data signal SDA includes, for example, a command such as a read command and a write command, an address signal, and a data signal. The transmission / reception unit 38 transmits the data read from the nonvolatile memory 60 by the access control unit 36 to the host device 10 via the data terminal TD.

  An operation example of the present embodiment when the power supply terminal TV is in a floating state will be described with reference to FIG. FIG. 5 shows an example in which the host device 10 starts memory access after the floating state is detected. The same applies to the case where the ground terminal TG is in a floating state.

  As shown in B1 of FIG. 5, when the power supply terminal TV is in a floating state, the detection signal FLTO from the detection circuit 32 becomes a low level as shown in B2. As shown in B3, the system clock SCK is inputted after the reset signal XRST is released, and as shown in B4, the mask signal QMS becomes low level at the first falling edge of SCK. The mask signal QMS is an internal signal of the mask processing unit 34. As shown in B5, the internal system clock MSCK after the masking process outputs SCK until the first falling edge of SCK, and then outputs a low level. The internal system clock MSCK is an internal signal of the storage device 20. As shown in B6, when reset by the reset signal XRST, the holding state of the mask signal QMS is released and the QMS becomes high level as shown in B7.

  In this manner, when the power supply terminal TV is in a floating state, the internal system clock MSCK supplied to the access control unit 36 and the transmission / reception unit 38 is masked, and memory access and data transmission / reception are prohibited. When the power supply terminal TV and the ground terminal TG are not in a floating state, the detection signal FLTO and the mask signal QMS are not at a low level, and the internal system clock MSCK is not masked. That is, the system clock SCK from the host device 10 is supplied to the access control unit 36 and the transmission / reception unit 38, and normal operation is performed.

5. Liquid Container and Substrate Next, the substrate provided with the storage device 20 and the liquid container provided with the substrate will be described. In the following, a case where the host device is an ink jet printer, the liquid container is an ink cartridge, and the substrate is a circuit board provided in the ink cartridge will be described as an example. However, the present embodiment is not limited thereto. Not. For example, the host device may be a memory card reader / writer, and the substrate may be a circuit board provided on the memory card.

  FIG. 6 shows a detailed configuration example of the ink cartridge. An ink chamber (not shown) for containing ink is formed inside the ink cartridge 200 (liquid container in a broad sense) shown in FIG. The ink cartridge 200 is provided with an ink supply port 240 that communicates with the ink chamber. The ink supply port 240 is for supplying ink to the print head unit when the ink cartridge 200 is installed in the printer.

  The ink cartridge 200 includes a sensor 210 and a circuit board 220 (substrate in a broad sense). The sensor 210 is for detecting the remaining amount of ink in the ink chamber. The sensor 210 is composed of, for example, a piezoelectric element and is fixed inside the ink cartridge 200. The circuit board 220 is provided with the storage device 20 of the present embodiment. The circuit board 220 is realized by a printed circuit board, for example, and is provided on the surface of the ink cartridge 200. The circuit board 220 is provided with terminals such as a power supply terminal TV. When the ink cartridge 200 is attached to the printer, the terminals and the terminals on the printer side come into contact with each other, whereby power and data are exchanged.

  7A and 7B show a detailed configuration example of the circuit board 220. FIG. As shown in FIG. 7A, a terminal group having a plurality of terminals is provided on the surface of the circuit board 220 (surface connected to the printer). This terminal group includes a ground terminal TG, a power supply terminal TV, a first sensor driving terminal TSN, a reset terminal TR, a clock terminal TK, a data terminal TD, and a second sensor driving terminal TSP. Each terminal is realized by, for example, a metal terminal formed in a rectangular shape (substantially rectangular shape). Each terminal is connected to the storage device 20 or the sensor 210 via a wiring pattern layer or a through hole (not shown) provided on the circuit board 220.

  As shown in FIG. 7B, the storage device 20 of this embodiment is provided on the back surface of the circuit board 220 (the surface on the back side of the surface connected to the printer). The storage device 20 can be realized by, for example, a semiconductor storage device having a ferroelectric memory. The storage device 20 stores various data related to the ink or the ink cartridge 200, for example, data such as ink consumption and ink color. The ink consumption data is data indicating the total amount of ink consumed for the printing of the ink stored in the ink cartridge 200. The ink consumption data may be information indicating the amount of ink in the ink cartridge 200 or information indicating the ratio of the consumed ink amount.

6). Detailed Configuration Example of System FIG. 8 shows a detailed configuration example of the printer system. The printer system includes a printer 10 (host device) and an ink cartridge 200 (liquid container). The printer 10 includes a main control unit 300 and a sub control unit 310. The ink cartridge 200 includes a storage device 20 and a sensor 210. In the following, a case where one ink cartridge is mounted on the printer will be described as an example. However, in the present embodiment, a plurality of ink cartridges may be mounted on the printer.

  The sub control unit 310 supplies the power supply voltage VDD and the ground voltage VSS to the storage device 20. The sub-control unit 310 performs data reading / writing with respect to the storage device 20 and sensor processing using the sensor 210. Specifically, the sub control unit 310 includes a switching circuit 50, a communication processing unit 312, and a sensor processing unit 314.

  The communication processing unit 312 performs communication processing between the storage device 20 and the main control unit 300. Specifically, a reset signal XRST, a system clock SCK, and a data signal SDA are supplied to the storage device 20, and serial communication processing with the storage device 20 is performed using these signals. In the present embodiment, the communication processing unit 312 and the storage device 20 may perform parallel communication processing. In addition, the communication processing unit 312 performs communication processing with the main control unit 300 by exchanging commands and data signals via the bus BS. For example, the communication processing unit 312 determines connection or disconnection between the ink cartridge 200 and the printer 10 and a communication error with the storage device 20, and transmits these determination results to the main control unit 300.

  The communication processing unit 312 detects a failure of the detection circuit 32 of the ink cartridge 200 and controls the switching circuit 50. Specifically, the communication processing unit 312 includes the determination unit 70, the memory 71, and the data comparison unit 72 described above with reference to FIG.

  The sensor processing unit 314 performs a remaining ink level determination process by the sensor 210. The sensor processing unit 314 applies the sensor driving signal DS from the main control unit 300 to the electrode of the sensor 210 via the sensor driving terminal TSNH or TSPH. The sensor processing unit 314 determines whether the remaining amount of ink is greater than or less than the threshold based on a signal obtained by applying the sensor drive signal DS to the sensor 210. The determination result is transmitted to the main control unit 300 via the communication processing unit 312.

  The main control unit 300 controls the printer 10. For example, the memory access is controlled, the power supply voltage VDH and the ground voltage VSH are supplied to the sub-control unit 310, and the remaining ink level is determined (calculation processing). More specifically, the main control unit 300 includes a control circuit 302 and a drive signal generation circuit 304.

  The control circuit 302 transmits commands and data to the communication processing unit 312 via the bus BS, and controls communication processing between the communication processing unit 312 and the storage device 20. Specifically, when the connection of the ink cartridge 200 is detected by the communication processing unit 312, data such as the remaining amount of ink stored in the storage device 20 is read, and the ink remaining amount newly calculated based on the data is read. Are written in the storage device 20. In addition, the control circuit 302 controls the drive signal generation circuit 304 and supplies the sensor drive signal DS to the sensor 210. Then, the control circuit 302 determines the remaining amount of ink based on the determination result of the remaining amount of ink from the sensor processing unit 314 and the estimated ink consumption amount due to printing. When it is determined that the ink has run out, the ink running information may be displayed on a display unit (not shown).

  Next, the storage device 20 of the ink cartridge 200 will be described. The storage device 20 includes a memory control circuit 30 (control unit) and a ferroelectric memory 60 (nonvolatile memory in a broad sense). The memory control circuit 30 includes a detection circuit 32, a mask processing unit 34, an ID comparison unit 41, a command interpretation unit 42, an address counter 44, a read / write control unit 46, a data transmission / reception unit 38 (transmission / reception unit), a counter control unit 48, A duplicate data generation unit 51, an inverted data generation unit 52, and a data determination unit 54 are included. The same components as those described above with reference to FIG. 4 and the like are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The ID comparison unit 41 compares the ID data (identification data) received from the sub-control unit 310 with the ID number assigned to the storage device 20 (for example, a number corresponding to the color of the ink). It is determined whether or not it is an access target.

  The command interpretation unit 42 interprets SOF (communication start data), command data, and EOF (communication end data) received from the sub-control unit 310, and determines the type of access such as access start, read and write, and access end. To do. The address counter 44 counts the system clock SCK and outputs a count value for designating an address (for example, a word line) of the ferroelectric memory 60. The read / write control unit 46 performs read / write control on the ferroelectric memory 60 based on the access type interpreted by the command interpretation unit 42 and the count value of the address counter 44. The counter control unit 48 (sequencer) counts the system clock SCK and controls memory access based on the count value and command interpretation by the command interpretation unit 42.

  The duplicate data generation unit 51 copies the original data read from the ferroelectric memory 60 to generate mirror data (replica data). The inversion data generation unit 52 inverts each bit value of the original data read from the ferroelectric memory 60 (for example, inversion of 0 to 1 and 1 to 0) to generate inversion data. The data determination unit 54 determines the data consistency by performing a parity check of the original data and the mirror data and an exclusive OR operation of the original data and the inverted data.

  The ferroelectric memory 60 (ferroelectric memory cell array) is composed of a plurality of ferroelectric memory cells arranged along word lines and bit lines. The ferroelectric memory 60 can include a row address decoder, a column address decoder, a sense amplifier, etc. (not shown).

7). Communication processing (read control)
The storage device 20 stops the memory access when detecting the floating state of the power supply terminal TV or the like. Since the printer 10 cannot directly recognize that the floating state has been detected, the printer 10 recognizes it through communication processing with the storage device 20. This communication process is performed when detecting a failure in the detection circuit 32 or detecting a contact failure during normal operation.

  This communication process will be described in detail with reference to FIGS. FIG. 9 schematically shows an example of a signal waveform when data is read from the storage device 20. In the following, the direction of data transmission / reception is indicated by arrows. That is, an arrow from H to C indicates that the sub-control unit 310 is the transmission side and the storage device 20 is the reception side, and an arrow from C to H indicates that the storage device 20 is the transmission side and the sub-control unit 310 is the transmission side. Indicates the receiving side.

  As shown in A1 of FIG. 9, when the communication process is started, the reset signal is changed from the low level to the high level. As shown in A2, the system clock SCK is supplied to the storage device 20. As indicated by A3, first, SOF (Start Of Frame) data is transmitted to the storage device 20 as the data signal SDA. As indicated by A4, ID data and read command data are transmitted to the storage device 20 as operation codes. As the ID data, original ID data ID and inverted ID data / ID obtained by inverting each bit value of the original ID data (hereinafter, the inverted data is indicated by a slash symbol /) are transmitted to the storage device 20. Original command data CM and inverted command data / CM are transmitted as command data.

  As indicated by A5, the read data from the storage device 20 is transmitted to the sub-control unit 310. As read data, upper 8 bits UD1 of 16-bit original data, its inverted data / UD1, lower 8 bits LD1 of original data, and its inverted data / LD1 are transmitted. Also, mirror data Ud1 of UD1, its inverted mirror data / Ud1, mirror data Ld1 of LD1, and its inverted mirror data / Ld1 are transmitted. UD1, LD1, Ud1, and Ld1 are data read from the storage device 20. On the other hand, the inverted data / UD1, / LD1, / Ud1, and / Ld1 are data generated by the inverted data generation unit 52. As indicated by A6, the reading and transmission of the unit read data are repeated. As shown in A8, when the transmission of the read data is completed, the reset signal is set to the low level.

  As described above, by multiplexing data with original data and inverted data, it is possible to prevent the storage device 20 from operating erroneously. For example, it is possible to prevent destruction of data in the nonvolatile memory by receiving an erroneous command due to a communication failure and performing erroneous writing or reading on the nonvolatile memory.

  Further, when a floating state of the power terminal TV or the like is detected, read / write control and data transmission / reception are not performed. At this time, for example, a low level is output as read data transmitted to the printer 10. The printer 10 can determine whether the detection circuit 32 is operating normally by detecting this low level.

  Further, when the floating state of the power supply terminal TV or the like is detected, the original data and the inverted data are not in a logically inverted relationship. The printer 10 side may determine whether the detection circuit 32 is operating normally by verifying the inverted data.

  FIG. 10 shows a flowchart example of the read process of the printer 10. As shown in FIG. 10, when the reading process is started, SOF data is transmitted (S50), ID data is transmitted (S51), a read command is transmitted (S52), and unit read data is received (S53). A data determination process for unit read data is performed. If the result of the data determination is an error (S54, NO), an error process is performed (S55), and the communication process is terminated. If the result of the data determination is normal (S54, YES), it is confirmed whether all the read data has been received (S56). If all are received (S56, YES), error processing is performed (S57), and the communication processing is terminated. If not all have been received (S56, NO), unit read data is received (S53).

  In the data determination process (S54), for example, exclusive OR of original data and inverted data, exclusive OR of mirror data and inverted mirror data, and exclusive OR of original data and inverted mirror data are calculated. . When reading or data transmission / reception is performed normally, each bit of these exclusive ORs is 1. In the data determination process, a communication error or a memory cell error is determined based on the calculation result.

  In the error process (S55), for example, an error display that prompts the user to reset or replace the ink cartridge 200 is performed in the VDD / VSS supply state and the normal operation in failure detection. In the error process (S57), an error is displayed when VDD or VSS is not supplied in failure detection. In normal operation, no error is displayed because it is normal.

  FIG. 11 shows a flowchart example of the access control processing of the storage device 20. As shown in FIG. 11, when communication processing is started, SOF data is received (S102), and ID data is received (S104). It is determined whether or not the received ID data is normal. If it is abnormal, the communication process is terminated (S106, NO). If it is normal (S106, YES), it is determined whether or not the ID data match (S108). If they do not match, the communication process ends (S108, NO). If they match (S108, YES), command data is received (S110). Then, it is determined whether or not the received command data is normal. If the command data is abnormal (S112, NO), the communication process is terminated. If normal (S112, YES), the command type is determined (S114).

  If it is a read command, a read process is performed (S120), and the communication process is terminated. In the read process, reading and transmission of original data and the like, and generation and transmission of inverted data are performed. If it is a write command, a write process to be described later with reference to FIG. 14 is performed (S116). If it is a write lock command, write lock processing is performed (S118). In the write lock process, a process of setting a part (or all) of the rewritable area of the ferroelectric memory 60 as a non-writable area is performed. Specifically, address data is received following the write lock command. Then, the area designated by the received address data is set as the write lock area. For example, the write lock area is set for each row of the ferroelectric memory 60 by setting a write flag in the control register.

8). Communication processing (write control)
FIG. 12 schematically shows an example of a signal waveform when data is written to the storage device 20. As indicated by D 1 in FIG. 12, SOF data, ID data ID, inverted ID data / ID, write command data CM, and inverted write command data / CM are transmitted to the storage device 20. Then, as shown by D2, the upper 8 bits UD1 of the 16-bit original data, its inverted data / UD1, the lower 8 bits LD1 of the original data, and its inverted data / LD1 are transmitted as write data. Further, the mirror data Ud1 of UD1, its inverted mirror data / Ud1, the mirror data Ld1 of LD1, and its inverted mirror data / Ld1 are transmitted to the storage device 20.

  As shown in D3, the storage device 20 determines whether the transmitted data is normal, and an OK / NG flag is transmitted to the printer 10 based on the determination result. For example, when it is determined that the data is normal, a high-level OK flag is transmitted, and when it is determined that the data is abnormal, a low-level NG flag is transmitted. Then, as shown at D4, the transmission of the write data (unit write data) and the transmission of the OK / NG flag are repeated. As shown in D5, when transmission of the write data is completed, EOF (End Of Frame) data is transmitted to the storage device 20.

  In this embodiment, when the floating state of the power supply terminal TV or the like is detected, the storage device 20 outputs, for example, a low level as the data signal SDA. Accordingly, the printer 10 receives the low level (NG) as the OK / NG flag, and can determine whether the detection circuit 32 is operating normally.

  FIG. 13 shows a flowchart example of the write process of the printer 10. As shown in FIG. 13, when the writing process is started, SOF data is transmitted (S202), ID data is transmitted (S204), and write command data is transmitted (S206). Then, a process of transmitting unit write data is performed (S208), and an OK / NG flag is received (S210). It is determined whether the received OK / NG flag is an OK flag or an NG flag. If it is an NG flag (S212, NO), an error process is performed and the communication process is terminated (S214). If it is an OK flag (S212, YES), it is determined whether or not all the write data has been transmitted. If all have been transmitted (S216, YES), the EOF data is transmitted (S218). An error process is performed (S220), and the communication process is terminated. If not all have been transmitted (S216, NO), a process of transmitting unit write data is performed (S208).

  In the error process (S214), for example, an error display that prompts the user to reset or replace the ink cartridge 200 is performed in the VDD / VSS supply state and the normal operation in failure detection. In the error process (S220), an error is displayed when VDD or VSS is not supplied in failure detection. In normal operation, no error is displayed because it is normal.

  FIG. 14 shows a detailed flowchart example of the write processing of the storage device 20. When the write process is started, a process of receiving unit write data is performed (S302). It is determined whether or not the received write data is normal. If it is abnormal (S304, NO), an NG flag is transmitted and the communication process is terminated (S306). If normal (S304, YES), an OK flag is transmitted (S308), and write data is written to the target area of the nonvolatile memory 60 (S310). It is determined whether or not EOF data has been received. If it has been received (S312: YES), the communication processing is terminated. If not (S302, NO), processing for receiving unit write data is performed (S302: NO). S302).

9. FIG. 15 shows a detailed configuration example of the detection circuit 32 that detects the floating state of the terminals. A storage device 20 illustrated in FIG. 15 includes input cells ICEL1 and ICEL2, a detection circuit 32, an access control unit 36, and a nonvolatile memory 60.

  The detection circuit 32 detects at least one of a floating state of the power supply line NV supplied with VDD and a floating state of the ground line NG supplied with VSS. Specifically, the detection circuit 32 includes a VSS detection circuit 134 and a VDD detection circuit 135.

  The VSS detection circuit 134 detects the NG floating state using the voltage of the system clock SCK (first signal in a broad sense) as a reference voltage. On the other hand, the VDD detection circuit 135 detects the NV floating state using the voltage of the reset signal XRST (second signal in a broad sense) as a reference voltage. XRST is set high during system operation.

  The input cell ICEL1 buffers the reset signal XRST and supplies it to the access control unit. ICEL1 includes a resistance element RS1, diode elements DD1, DS1, and a buffer BF2. The input cell ICEL2 buffers the data signal SDA and supplies it to the access control unit. ICEL2 includes a resistance element RS2, diode elements DD2, DS2, and a buffer BF2. These resistance elements and diode elements are for protecting the internal circuit from electrostatic breakdown. Note that an input cell may be provided in the SCK.

  Now, it is assumed that the ground terminal TG is in a floating state due to insertion of a foreign object or the like. When a low level is supplied to the terminal TD, a current flows from the ground line NG to the terminal TD via the diode element DS2. The voltage of NG is a voltage that is increased from VSS by the forward voltage of the diode element DS2. The VSS detection circuit 134 detects this voltage increase.

  On the other hand, it is assumed that the power supply terminal TV is in a floating state due to insertion of foreign matter or the like. A high level is supplied to the terminal TR, and a current flows from the terminal TR to the power supply line NV via the diode element DD1. Therefore, the voltage of NV is a voltage that drops from VDD by the forward voltage of the diode element DD1. The VDD detection circuit 135 detects this voltage drop.

  A detailed configuration example of the VSS detection circuit 134 will be described with reference to FIGS. The VSS detection circuit 134 includes N-type transistors NT1 to NT3 (first conductivity type transistor in a broad sense), P-type transistors PT1 and PT2 (second conductivity type transistor in a broad sense), and inverters INV1 and INV2. Here, the enable signal EN is, for example, the reset signal XRST, and is set to a high level during normal operation.

  As shown in FIG. 16A, when the ground voltage VSS is supplied to the ground terminal TG, the drain current Id1 of the transistor PT1 is equal to the drain current Id2 of the transistor PT2. By designing the differential pair so that the voltage at the node N1 is equal to or lower than the logical threshold of the inverter INV1, that is, the INV1 outputs a high level, the output signal Q2 becomes a low level.

  As shown in FIG. 16B, it is assumed that the ground terminal TG is in a floating state and the data signal SDA (third signal in a broad sense) is at a low level. At this time, since the voltage of the ground line NG increases as described above, Id1> Id2, and the voltage of the node N1 increases. Therefore, the output signal Q2 of the inverter INV2 becomes high level. On the other hand, it is assumed that SDA is at a high level as shown in FIG. At this time, since there is no current path from the ground line NG to VSS, the voltage of NG rises. Therefore, the output signal Q2 of the inverter INV2 becomes high level.

  The VDD detection circuit 134 can be configured similarly. That is, the N-type and P-type transistors are interchanged, and VDD and VSS are interchanged.

  According to the above, as shown in FIG. 15, the storage device 20 is connected to the first host-side signal terminal (host-side reset terminal TRH) to which the first signal (reset signal XRST) from the host device 10 is supplied. It has a first signal terminal (reset terminal TR) to be connected and a first diode element DD1 provided between the first signal terminal and the power supply terminal TV. When the power supply terminal TV is in a floating state, the high-level voltage (VDD) of the first signal is supplied to the power supply terminal TV via the first diode element DD1.

  In the present embodiment, the first signal is the reset signal XRST. The reset signal XRST is set to a high level when the access control unit performs access control.

  In the present embodiment, the storage device 20 is connected to the second host side signal terminal (host side data terminal TDH) to which the second signal (data signal SDA) from the host device 10 is supplied. A signal terminal (data terminal TD); and a second diode element DS2 provided between the second signal terminal and the ground terminal TG. When the ground terminal TG is in a floating state, the low-level voltage (VSS) of the second signal is supplied to the ground terminal TG via the second diode element DS2.

  According to the present embodiment, VDD and VSS are supplied to the storage device 20 even when the power supply terminal TV or the ground terminal TG has a poor contact. Can be accessed. Since VDD or the like is dropped by the diode element, there is a possibility of causing an access failure or destruction of stored data. In this regard, according to the present embodiment, since a failure of the detection circuit 32 can be detected, memory access in a poor contact state can be prohibited.

10. Ferroelectric Memory The above-described ferroelectric memory will be described in detail with reference to FIGS. 17 (A) and 17 (B). FIG. 17A shows a configuration example of a ferroelectric memory cell. This ferroelectric memory cell includes a ferroelectric capacitor CS and an N-type transfer transistor TT (first conductivity type transistor in a broad sense).

  A node NC is connected to one end of the ferroelectric capacitor CS, and a plate line PL is connected to the other end. A word line WL is connected to the gate electrode of the transistor TT, a bit line BL is connected to the source electrode (drain electrode), and a node NC is connected to the drain electrode (source electrode). It is not limited to the 1T1C (1 Transistor 1 Capacitor) type, and may be a 2T2C (2 Transistor 2 Capacitor) type, an FET type, or the like.

  FIG. 17B is an explanatory diagram showing a write operation with respect to the ferroelectric memory cell. As shown in FIG. 17B, when logic “1” is written in the memory cell, a selection voltage is applied to the word line WL, a power supply voltage VCC (eg, VDD) is applied to the bit line BL, 0V (for example, VSS) is applied to the plate line PL. Thereby, the remanent polarization of the ferroelectric capacitor CS becomes “negative”. Thus, a state in which the remanent polarization is “negative” can be defined as a state in which, for example, logic “1” is stored.

  On the other hand, when logic “0” is written in the memory cell, a selection voltage is applied to the word line WL, 0 V is applied to the bit line BL, and VCC is applied to the plate line PL. Thereby, the remanent polarization of the ferroelectric capacitor CS becomes “positive”. Thus, a state where the remanent polarization is “positive” can be defined as a state where, for example, logic “0” is stored.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. Further, the configurations and operations of the host device, the storage device, and the like are not limited to those described in this embodiment, and various modifications can be made.

10 host device, 20 storage device, 30 memory control circuit, 32 detection circuit,
34 mask processing unit, 36 access control unit, 38 transmission / reception unit, 40 power supply circuit,
41 ID comparison unit, 42 command interpretation unit, 44 address counter,
46 read / write control unit, 48 counter control unit, 50 switching circuit,
51 replicate data generation unit, 52 inverted data generation unit, 54 data determination unit,
55 switch control unit, 60 non-volatile memory, 70 determination unit, 71 memory,
72 data comparison unit, 80 communication control unit, 134 VSS detection circuit,
135 VDD detection circuit, 200 ink cartridge, 210 sensor,
220 circuit board, 240 ink supply port, 300 main control unit, 302 control circuit,
304 drive signal generation circuit, 310 sub-control unit, 312 communication processing unit,
314 sensor processing unit,
BL bit line, CS ferroelectric capacitor, DD1, DS2 diode element,
NG ground line, NV power line, PL plate line,
SCK system clock, SDA data signal, SW1, SW2 switch element,
TD data terminal, TDH host side data terminal, TG ground terminal,
TGH Host side ground terminal, TK clock terminal,
TKH Host side clock terminal, TR reset terminal,
TRH host-side reset terminal, TV power supply terminal, TVH host-side power supply terminal,
VDD power supply voltage, VSS ground voltage, WL word line, XRST reset signal

Claims (10)

A system including a host device and a storage device,
The storage device
A non-volatile storage unit;
An access control unit that performs read or write access control on the nonvolatile storage unit;
A detection circuit for detecting a floating state of at least one of a power supply terminal connected to the host-side power supply terminal and a ground terminal connected to the host-side ground terminal;
Have
The host device is
A switching circuit for switching supply / non-supply of the detection target voltage from which the floating state is detected among the power supply voltage supplied to the host-side power supply terminal and the ground voltage supplied to the host-side ground terminal;
A determination unit that determines whether the detection circuit is normal or abnormal based on a signal from the storage device when the detection target voltage is set to non-supply;
The system characterized by having. In claim 1,
The access control unit
When the floating state is detected by the detection circuit, the access control is stopped,
The determination unit
When the detection target voltage is set to non-supply, it is determined whether or not the detection circuit has normally detected the floating state based on a signal from the access control unit in which the access control is stopped. A system characterized by In claim 2,
The host device is
A communication control unit that performs communication control with the access control unit;
The communication control unit
Performing the access control to the nonvolatile storage unit via the access control unit, receiving transmission data from the access control unit according to the access control,
The determination unit
A system for performing the normality / non-normality determination by comparing the received transmission data with determination data for determining whether or not the access control is stopped. In claim 2 or 3,
The determination unit
When the detection target voltage is supplied, it is determined whether or not the access control is normal. If it is determined that the detection target voltage is normal, the access control when the detection target voltage is set to non-supply is stopped. And determining that the detection circuit is normal when it is determined that the detection circuit has been stopped. In claim 4,
The determination unit
When it is determined that the access control is abnormal when the detection target voltage is supplied, the system does not perform determination when the detection target voltage is set to non-supply. In any one of Claims 1 thru | or 5,
The storage device
A first signal terminal connected to a first host-side signal terminal to which a first signal from the host device is supplied;
A first diode element provided between the first signal terminal and the power supply terminal;
Have
When the power supply terminal is in the floating state, a high-level voltage of the first signal is supplied to the power supply terminal via the first diode element. In claim 6,
The first signal is:
Reset signal,
The reset signal is
The system is set to a high level when the access control unit performs the access control. In any one of Claims 1 thru | or 7,
The storage device
A second signal terminal connected to a second host-side signal terminal to which a second signal from the host device is supplied;
A second diode element provided between the second signal terminal and the ground terminal;
Have
When the ground terminal is in the floating state, a low level voltage of the second signal is supplied to the ground terminal via the second diode element. In addition to performing read or write access control to the nonvolatile storage unit of the storage device,
When detecting a floating state of at least one of the power supply terminal of the storage device connected to the host-side power supply terminal of the host device and the ground terminal of the storage device connected to the host-side ground terminal of the host device,
Switching between supply / non-supply of the detection target voltage for detecting the floating state among the power supply voltage supplied to the host-side power supply terminal and the ground voltage supplied to the host-side ground terminal;
An error detection method comprising: determining whether the detection circuit is normal or abnormal based on a signal from the storage device when the detection target voltage is set to non-supply. A switching circuit;
A determination unit;
Including
The storage device to which the power supply voltage and ground voltage from the host device are supplied is
A non-volatile storage unit;
An access control unit that performs read or write access control on the nonvolatile storage unit;
A detection circuit for detecting a floating state of at least one of a power supply terminal connected to the host-side power supply terminal and a ground terminal connected to the host-side ground terminal;
Have
The switching circuit is
A switching circuit for switching supply / non-supply of a detection target voltage from which the floating state is detected among the power supply voltage supplied to the host-side power supply terminal and the ground voltage supplied to the host-side ground terminal;
The determination unit
A host device that determines whether the detection circuit is normal or abnormal based on a signal from the storage device when the detection target voltage is set to non-supply.

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