JP2011081660A - Storage device, substrate, liquid container, system, and control method for storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage device, a substrate, a liquid container, a system, and a control method and the like for a non-volatile storage part for suppressing destruction of data stored in a non-volatile storage part. <P>SOLUTION: A storage device 20 includes: a non-volatile storage part 60; a control part 30; and a capacitor 70. The control part 30 includes: a detection circuit 32; and an access control part. The detection part 32 detects the power source abnormality state of a power supply voltage VDD. An access control part 36 performs access control of reading or writing from or to the non-volatile storage part 60, and when the power source abnormality state is detected by the detection circuit 32, stops the access control of reading or writing from or to the non-volatile storage part 60. When the power source abnormality state is detected by the detection circuit 32, the capacitor 70 holds the power supply voltage VDD in order to complete at least one time access control of reading or writing. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a storage device, a substrate, a liquid container, a system, a storage device control method, and the like.

  As a nonvolatile memory (a nonvolatile storage unit in a broad sense), an EEPROM, an FERAM, or the like is known. These memories transmit / receive data to / from the host device and read / write the data. For example, an ink cartridge (liquid container) is attached to an ink jet printer (host device). Some ink cartridges are provided with a storage device having a nonvolatile memory (for example, Patent Document 1). The nonvolatile memory stores various information such as ID, manufacturing information, and ink remaining amount, and the storage device transmits and receives such information to and from the printer.

JP 2004-299405 A

  However, when an abnormality occurs in the power supply of the storage device, data stored in the non-volatile memory may be destroyed because the data is not normally read / written. For example, a storage device of an ink cartridge and a printer are generally connected by contact of a terminal, and power is supplied from the printer to the storage device via the terminal. At this time, if a power supply abnormality such as a power supply terminal being in a floating state (non-contact state) occurs during access to the nonvolatile memory, data stored in the nonvolatile memory may be destroyed. For example, when the non-volatile memory is an FERAM or the like that requires a rewrite operation at the time of reading, the information may be lost because the rewrite is not normally performed when reading ID or manufacturing information. is there.

  According to some aspects of the present invention, it is possible to provide a storage device, a substrate, a liquid container, a system, a method for controlling the nonvolatile storage unit, and the like that can prevent destruction of data stored in the nonvolatile storage unit.

  One embodiment of the present invention includes a nonvolatile storage unit, a control unit that controls the nonvolatile storage unit, and a capacitor, and the control unit is in a power supply abnormal state of a power supply voltage supplied from a host device And a read or write access control for the nonvolatile storage unit, and when a power supply abnormal state is detected by the detection circuit, a read or write access control for the nonvolatile storage unit And an access control unit for stopping the access from the host device in order to complete at least one read or write access control when the power supply abnormal state is detected by the detection circuit. The present invention relates to a storage device that holds a supplied power supply voltage.

  According to one embodiment of the present invention, when a power supply abnormal state is detected by the detection circuit, access control to the nonvolatile storage unit is stopped. The power supply voltage supplied from the host device is held by the capacitor in order to complete at least one read or write access control. As a result, it is possible to suppress the destruction of data stored in the nonvolatile memory.

  In one embodiment of the present invention, when the power supply voltage supplied from the host device is equal to or lower than a threshold voltage, the detection circuit detects a power supply voltage drop as a power supply abnormal state, and the capacitor has the at least In a period in which one read or write access control is performed, the power supply voltage supplied from the host device is set to a capacitance value that does not drop below the threshold voltage and does not fall below the lower limit operating voltage of the nonvolatile storage unit. May be.

  In this way, the power supply voltage can be held at a voltage that does not become lower than the lower limit operation voltage of the nonvolatile storage unit in a period in which at least one read or write access control is performed. This makes it possible to perform at least one read or write access control after detecting a power supply voltage drop.

  In one embodiment of the present invention, the non-volatile storage unit is a ferroelectric memory, and the read access control for the ferroelectric memory is performed during the period in which the at least one read or write access control is performed. It may be a period until the rewrite operation is completed.

  In this way, at least one read or write access control is completed up to the rewrite operation of the ferroelectric memory, and the read access control can be completed.

  In one embodiment of the present invention, the nonvolatile memory portion may be a ferroelectric memory, and the capacitor may be a capacitor in which an insulator is formed by a ferroelectric layer of the ferroelectric memory. Good.

  In this way, a capacitor can be realized by forming an insulator with the ferroelectric layer of the ferroelectric memory.

  In one embodiment of the present invention, the control unit includes a mask processing unit that performs mask processing of a system clock supplied to the access control unit, and the mask processing unit detects a power supply abnormal state by the detection circuit. In such a case, the system clock may be masked.

  In this way, by masking the system clock supplied to the access control unit, access control to the nonvolatile storage unit can be stopped when a power supply abnormal state is detected by the detection circuit.

  In the aspect of the invention, the access control unit may stop the read or write access control in the access cycle when a power supply abnormal state is detected by the detection circuit after the start of the access cycle. The detection circuit detects a power supply voltage drop as a power supply abnormal state when the power supply voltage supplied from the host device is equal to or lower than a threshold voltage, and the capacitor reads or In a period during which the write access control is performed, the power supply voltage supplied from the host device may be set to a capacitance value that does not drop below the threshold voltage and does not fall below the operation lower limit voltage of the nonvolatile storage unit.

  In this way, the power supply voltage can be held at a voltage that does not fall below the operation lower limit voltage of the nonvolatile storage unit during the period of access control in the access cycle. Thereby, when a power supply voltage drop is detected after the start of the access cycle, the access control in the access cycle can be completed.

  In one embodiment of the present invention, the access cycle is started by a change in the logic level of an enable signal for enabling read or write access control, and the read operation or write operation performs read or write access control. The access control unit is configured to make the access control unit perform read or write access control when a power supply abnormal state is detected by the detection circuit after the start of the access cycle. May be activated to complete read or write access control in the access cycle.

  In this way, the access control in the access cycle can be started by activating the clock for performing the access control. Even when a power supply abnormal state is detected by the detection circuit, the started access control can be completed without stopping.

  Another embodiment of the present invention relates to a substrate including any of the memory devices described above.

  Another aspect of the invention relates to a liquid container including any of the storage devices described above.

  Another aspect of the present invention relates to a system including any of the storage devices described above and a host device.

  According to another aspect of the present invention, a nonvolatile storage unit is controlled, a power supply abnormal state of a power supply voltage supplied from a host device is detected, and read or write access control is performed on the nonvolatile storage unit. When the power supply abnormal state is detected, the read or write access control to the nonvolatile storage unit is stopped, and when the power supply abnormal state is detected, at least one read or write access control is performed. In order to complete the process, the present invention relates to a control method of a storage device that holds a power supply voltage supplied from the host device.

1 is a first configuration example of a storage device according to an embodiment. 2 shows a second configuration example of a storage device according to the present embodiment. Signal waveform example of read control for nonvolatile memory. Signal waveform example of write control for nonvolatile memory. Signal waveform example of access control to nonvolatile memory when a power supply abnormality is detected. FIG. 6A shows a configuration example of a ferroelectric memory. FIG. 6B is an explanatory diagram of a write operation with respect to the ferroelectric memory cell. FIG. 6C is an explanatory diagram of the read operation for the ferroelectric memory cell. Detailed signal waveform example of read operation for ferroelectric memory. 3 shows a detailed configuration example of a signal generation circuit. Explanatory drawing about the capacitance value of a capacitor. A detailed configuration example of a ferroelectric memory including a capacitor. 2 shows a detailed configuration example of a detection circuit and a detailed configuration example of a mask processing circuit. Operation example of power failure detection and mask processing. Operation example of power failure detection and mask processing. Operation example of power failure detection and mask processing. Operation example of power failure detection and mask processing. Operation example of power failure detection and mask processing. 2 is a configuration example of a power supply monitoring circuit. 3 is a detailed configuration example of an ink cartridge. 19A and 19B show detailed configuration examples of the circuit board. Detailed configuration example of the system. The signal waveform example in the case of reading data from a memory | storage device. The flowchart example of a read process of a printer. 6 is a flowchart example of read processing of a storage device. An example of a signal waveform when data is written to a storage device. The flowchart example of the write process of a printer. 6 is a flowchart example of a write process of a storage device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration Example FIG. 1 shows a first configuration example of the storage device of this embodiment. 1 includes a control unit 30 (memory control unit, control circuit), a nonvolatile memory 60 (nonvolatile storage unit), a capacitor 70, a power supply terminal TV (first power supply terminal, high-voltage side power supply). Terminal), ground terminal TG (second power supply terminal, low-voltage side power supply terminal, ground terminal), clock terminal TK (first terminal), data terminal TD (second terminal), and reset terminal TR. Note that the storage device of the present embodiment is not limited to the configuration in FIG. 1, and some of the components (eg, clock terminal, data terminal, mask processing unit) are omitted, or other components are added. Various modifications such as this are possible.

  The storage device 20 is for suppressing data destruction of the nonvolatile memory 60 due to power supply abnormality by masking the system clock when a power supply abnormality is detected. Hereinafter, a case where the nonvolatile storage unit is the nonvolatile memory 60 will be described as an example. However, in the present embodiment, the non-volatile storage unit may be other, for example, a magnetic drive such as a hard disk drive or an optical drive such as a DVD. In the following, a case where a power supply voltage, a ground voltage, and various signals are supplied by contact of terminals will be described as an example. However, in the present embodiment, the power supply voltage, the ground voltage, and various signals may be supplied by non-contact transmission (non-contact transmission) using electromagnetic induction between coils.

  The power supply terminal TV, the ground terminal TG, the clock terminal TK, the data terminal TD, and the reset terminal TR are respectively a host-side power supply terminal TVH, a host-side ground terminal TGH, a host-side clock terminal TKH, a host-side data terminal TDH, It is electrically connected to the host side reset terminal TRH. For example, each terminal of the host device 10 and the storage device 20 is composed of a metal terminal, and the terminals are electrically connected by physically contacting them. When the terminal of the host device 10 and the terminal of the storage device 20 are connected, the power supply terminal TV is supplied with the power supply voltage VDD (first power supply voltage, high voltage power supply voltage) from the host side power supply terminal TVH. Is done. The ground terminal TG is supplied with the ground voltage VSS (second power supply voltage, low voltage power supply voltage) from the host side ground terminal TGH. A system clock SCK (first signal) from the host side clock terminal TKH is supplied to the clock terminal TK, and a data signal (second signal) from the host side data terminal TDH is supplied to the data terminal TD. The The reset signal XRST from the host side reset terminal TRH is supplied to the reset terminal TR.

  The control unit 30 controls the nonvolatile memory 60 (nonvolatile storage unit in a broad sense), performs data transmission / reception (data communication) with the host device 10 (host), and detects a power supply abnormality. Specifically, the control unit 30 includes a detection circuit 32 (detection unit), a mask processing unit 34 (mask processing circuit), an access control unit 36 (access control circuit), and a transmission / reception unit 38 (communication unit, transmission / reception circuit). .

  The detection circuit 32 detects an abnormality in the power supplied to the storage device 20 and outputs a detection signal (information on the detection result) to the mask processing unit 34. Specifically, the detection circuit 32 detects a voltage drop of the power supply voltage VDD, a floating state (open state, non-contact state) of the power supply terminal TV or the ground terminal TG, and the like. For example, the detection circuit 32 detects a voltage drop of the voltage supplied from the power supply terminal TV or a voltage rise of the voltage supplied from the ground terminal TG as a voltage drop of the power supply voltage VDD.

  The mask processing unit 34 performs mask processing of the system clock SCK based on the detection signal from the detection circuit 32. Here, the system clock SCK is a clock used for controlling the storage device 20. For example, SCK is a clock for generating a clock for read / write (reading or writing) access control of the nonvolatile memory and for transmitting and receiving data between the host device 10 and the storage device 20. The system clock SCK may be supplied from the terminal TK as shown in FIG. 1 or may be generated inside the storage device 20.

  When a power supply abnormality is detected by the detection circuit 32, the mask processing unit 34 masks the system clock SCK from the clock terminal TK. That is, the system clock SCK is not supplied to the components of the control unit 30 such as the access control unit 36 and the transmission / reception unit 38. For example, the SCK is not supplied by fixing the system clock after mask processing to a low level (first logic level) or a high level (second logic level). In this case, the operation of the storage device 20 is stopped. That is, no read / write operation with respect to the nonvolatile memory 60 or data transmission / reception with the host device 10 is performed. On the other hand, if no power supply abnormality is detected by the detection circuit 32, the mask processing unit 34 does not mask the system clock SCK and supplies SCK to the components of the control unit 30. In this case, the storage device 20 performs a normal operation.

  The access control unit 36 performs access control (memory access control) for the nonvolatile memory 60 based on the system clock after the mask processing from the mask processing unit 34. That is, in synchronization with the system clock, a read operation (read operation) of data stored in each address of the nonvolatile memory 60 and a write operation (write operation) of data with respect to each address of the nonvolatile memory 60 are performed. Specifically, the access control unit 36 generates a write enable signal, a read address signal, a write address signal, a write data signal, and the like, and performs access control. The access control unit 36 may perform sequential access to the nonvolatile memory 60 or may perform random access.

  The transmission / reception unit 38 (reception unit or transmission unit) performs data transmission / reception between the host device 10 and the storage device 20 based on the system clock after the mask processing from the mask processing unit 34. Then, the transmission / reception unit 38 outputs the received data to the access control unit 36, and the access control unit 36 writes the data in the nonvolatile memory 60. The transmission / reception unit 38 transmits the data read from the nonvolatile memory 60 by the access control unit 36 to the host device 10. More specifically, the transmission / reception unit 38 receives the data signal SDA from the host device 10 via the data terminal TD. The received data signal SDA includes, for example, a command such as a read command and a write command, an address signal, and a data signal. The transmission / reception unit 38 transmits the data read from the nonvolatile memory 60 by the access control unit 36 to the host device 10 via the data terminal TD.

  The nonvolatile memory 60 is composed of, for example, an EEPROM such as FERAM (ferroelectric memory) or flash memory. The nonvolatile memory 60 may include a memory array, a column selection circuit, and a row selection circuit. The nonvolatile memory 60 stores the ID and manufacturing information written at the time of manufacturing, and information written from the host device 10. For example, in the case of an ink cartridge, the nonvolatile memory 60 stores manufacturing date information, ink color information, and the like as manufacturing information, and stores ink remaining information as information written from the host device 10.

  The capacitor 70 is provided between the power supply terminal TV and the ground terminal TG, and holds the power supply voltage VDD supplied from the power supply terminal TV. That is, the voltage drop of the power supply voltage VDD supplied from the host device 10 is suppressed (suppressed). Specifically, as described above, in order to suppress the destruction of data stored in the nonvolatile memory 60, access control to the nonvolatile memory 60 is stopped when a power supply voltage drop (power supply abnormality) is detected. However, if a power supply voltage drop is detected during a write operation or a read operation, if the write operation or read operation is stopped halfway, data may be destroyed. Therefore, the access control unit 36 completes (continues) the write operation or read operation without stopping. At this time, the capacitor 70 secures a time for completing the write operation and the read operation by reducing the voltage drop per unit time of the power supply voltage VDD shared from the host device 10.

  The insulating layer of the capacitor 70 is preferably composed of a ferroelectric layer of a ferroelectric memory. Specifically, FIG. 2 shows a second configuration example of the storage device. The storage device 20 includes a control unit 30, a ferroelectric memory 60, and terminals TV, TG, TK, TR, and TD. The ferroelectric memory 60 includes a capacitor 70. VDD is supplied to one electrode of the capacitor 70 and VSS is supplied to the other electrode. The insulating layer (dielectric) between these electrodes is composed of a ferroelectric material used in a memory cell of a ferroelectric memory.

2. Access Control As described above, in this embodiment, when a power supply abnormality is detected during a write operation or a read operation, the write operation or read operation is completed (continued) without being stopped. First, the access control of this embodiment will be described with reference to FIGS. Then, with reference to FIGS. 6A to 8, the completion of the write operation and the read operation will be specifically described by taking as an example the case where the nonvolatile memory 60 is a ferroelectric memory.

  FIG. 3 shows a signal waveform example of read control for the nonvolatile memory. As shown in F1 of FIG. 3, the address signal AD [0: n] is set to the address AD1 [0: n], and the write enable signal WE is set to the high level as shown in F2. When the rising edge (or falling edge) of the memory access clock CK is input as indicated by F3, the data RD1 [0: m] of the address AD1 [0: n] is indicated as indicated by F4. ] Is read as read data RD [0: m]. Here, as shown in FIG. 3, the clock CK is a clock generated by dividing the system clock SCK (system clock after masking), for example.

  FIG. 4 shows a signal waveform example of write control for the nonvolatile memory. As indicated by G1 in FIG. 4, the address signal AD [0: n] is changed to the address AD1 [0: n], and as shown by G2, the write enable signal WE is set to the low level (active). As indicated by G3, the write data WD1 [0: m] is supplied as the data signal WD [0: m]. Then, as indicated by G4, when the rising edge of the clock CK is input, the write data WD1 [0: m] is written to the address AD1 [0: n].

  FIG. 5 shows an example of an access control signal waveform when a power supply abnormality is detected in the access cycle. As shown in FIG. 5, it is assumed that a power supply abnormal state is detected at timing Td in the access cycle Ta (access period). Then, the edge of the clock CK for performing the write operation or the read operation is output as indicated by H1 (CK is activated), and the system clock SCK is masked as indicated by H2. When the system clock SCK is masked, the clock CK, the address signal AD [0: n], and the write enable signal WE do not change. In this embodiment, when the edge of the clock CK for performing the write operation or the read operation is output, the write operation or the read operation in the access cycle Ta is completed without being stopped even if the system clock SCK is masked.

  Here, the access cycle Ta is a period starting from the timing when the write enable signal WE and the address signal AD [0: n] are supplied to the nonvolatile memory 60, for example. Alternatively, when SCK is masked by the falling edge (or rising edge) of system clock SCK, it starts from the falling edge of system clock SCK immediately before the output of clock CK for performing the write operation or read operation. It is a period to do. The access cycle Ta is, for example, a period that ends when the write operation or read operation for the address AD1 [0: n] to be accessed in Ta is completed. Alternatively, it is a period that ends when the next access cycle starts.

  In this embodiment, even when a power supply abnormal state is detected in the access cycle Ta, the system clock SCK is masked before the edge of the clock CK for performing the write operation or the read operation is output. In some cases, access control may be stopped. That is, the operation may be stopped without performing a write operation or a read operation in the access cycle Ta.

3. Ferroelectric Memory Next, the completion of the write operation and the read operation will be specifically described with reference to FIGS. 6A to 8, taking as an example the case where the nonvolatile memory 60 is a ferroelectric memory. However, in this embodiment, the nonvolatile memory 60 may be another nonvolatile memory such as an EEPROM.

  FIG. 6A shows a configuration example of a ferroelectric memory. This ferroelectric memory includes a ferroelectric capacitor CS, an N-type transfer transistor TR (first conductivity type transistor in a broad sense), a sense amplifier SA, first and second transistors SW1, SW2, and a latch LT. In FIG. 6A, a case where the memory cell is a 1T1C (1 Transistor 1 Capacitor) type will be described as an example. However, in this embodiment, a 2T2C (2 Transistor 2 Capacitor) type, an FET type, or the like is used. May be.

  A node NC is connected to one end of the ferroelectric capacitor CS, and a plate line PL is connected to the other end. A word line WL is connected to the gate electrode of the transistor TR, a bit line BL1 is connected to the source electrode (drain electrode), and a node NC is connected to the drain electrode (source electrode). A memory cell is formed by the ferroelectric capacitor CS and the transistor TR, and a plurality of memory cells are arranged along the bit line BL1 and the word line WL.

  The sense amplifier SA amplifies the charge (voltage) read to the bit line BL1, and outputs the amplified voltage to the bit line BL2. For example, a power supply voltage VCC corresponding to logic “1” or 0 V corresponding to logic “0” is output as the amplified voltage. The transistors SW1 and SW2 are composed of, for example, N-type transistors, and are turned on / off by a signal YSEL. The signal YSEL becomes active when reading from the memory cell. The latch LT holds (latches) the read logic level (voltage level), and outputs the held logic level as the output signal LTQ.

  A write operation for the ferroelectric memory cell will be described with reference to FIG. As shown in FIG. 6B, when logic “1” is written in the memory cell, a selection voltage is applied to the word line WL, and a power supply voltage VCC (for example, power supply voltage VDD; broadly defined) is applied to the bit line BL1. , The first power supply voltage) is applied, and 0 V (for example, the ground voltage VSS. In a broad sense, the second power supply voltage) is applied to the plate line PL. Thereby, the remanent polarization of the ferroelectric capacitor CS becomes “negative”. Thus, a state in which the remanent polarization is “negative” can be defined as a state in which, for example, logic “1” is stored.

  On the other hand, when writing logic “0” in the memory cell, a selection voltage is applied to the word line WL, 0 V is applied to the bit line BL1, and VCC (for example, 5 V) is applied to the plate line PL. Thereby, the remanent polarization of the ferroelectric capacitor CS becomes “positive”. Thus, a state in which the remanent polarization is “positive” can be defined as a state in which, for example, logic “0” is stored.

  A read operation for the ferroelectric memory cell will be described with reference to FIG. As shown in FIG. 6C, in the first period T1, a selection voltage is applied to the word line WL, and charge is transferred from the ferroelectric capacitor CS to the bit line BL1. In the subsequent second period T2, the voltage of the bit line BL1 is amplified by the sense amplifier SA. In the third period T3, a rewrite operation (rewrite operation) is performed in order to retain the read data (logic “0” or “1”) and recover the data destroyed by the read.

  In this embodiment, the read operation may be performed in the above-described order. For example, the read operation is performed in another order, for example, the sense amplifier amplification and the rewrite operation are performed in the same period and held in the next period. It may be done.

  FIG. 7 shows a detailed signal waveform example of the read operation for the ferroelectric memory. When the rising edge of the clock CK is input as indicated by I1 in FIG. 7, the power supply voltage VCC is applied to the word line WL as indicated by I2. Then, the power supply voltage VCC is applied to the plate line PL as indicated by I3, and the charge of the ferroelectric capacitor CS is read to the bit line BL1 as indicated by I4. As indicated by I5, the sense amplifier SA is turned on, and as indicated by I6, the voltage amplified (high level or low level) by the sense amplifier SA is output to the bit line BL2. As indicated by I7, since YSEL is at a high level (active), BL1 and BL2 have the same voltage.

  As shown at I8, the read logic level is latched at the rising edge (active edge) of the output data latch signal LAT. As indicated by I9, 0V is applied to the plate line PL, and the voltage of the bit line BL1 (BL2) is rewritten to the ferroelectric capacitor CS. Then, as indicated by I10, the output enable signal OE is set to high level (active), and the latched logic level is output as read data.

  As indicated by I11, when a power supply abnormal state is detected in the access cycle Ta, the clock CK does not fall. Therefore, in this embodiment, in order to complete the access control, the above-described access control is performed at the rising edge of the clock CK.

  FIG. 8 shows a detailed configuration example of a signal generation circuit that can generate a control signal by the rising edge of the clock CK. This signal generation circuit includes delay buffers DB1 to DB20 (DB1 to DBi in a broad sense, i is a natural number), inverters IB1 and IB2, AND circuits AB1 and AB2 (logical product circuits), and a set / reset latch SLR. For example, the signal generation circuit can be included in the access control unit 36 and the nonvolatile memory 60 shown in FIG. In FIG. 8, the control signal of the word line WL is described, but other control signals can be generated in the same manner.

  The delay buffers DB1 to DB20 receive the clock CK and sequentially delay the clock CK. Inverter IB1 inverts the output logic level of DB4. The output signal of DB2 and the output signal of the inverter IB1 are input to the AND circuit AB1. Inverter IB2 inverts the output logic level of DB17. The output signal of DB15 and the output signal of the inverter IB2 are input to the AND circuit AB2. The output signal of the AND circuit AB1 is input to the set terminal of the latch SLR, and the output signal of the AND circuit AB2 is input to the reset terminal.

  When the rising edge of the clock CK is input, AB1 outputs a high pulse (differential pulse of the rising edge of CK) due to the delay of DB3 and DB4. The latch SLR receives the high pulse and sets the logic level of the word line WL to the high level. And after the elapse of the period due to the delay of DB5 to DB15, the AND circuit AB2 outputs a high pulse. The latch SLR receives the high pulse and sets the word line WL to the low level. In this way, the control signal can be generated by the rising edge of the clock CK.

4). Capacitor As described above with reference to FIG. 7 and the like, in the present embodiment, the read operation is completed by the active edge of the access control clock CK. At this time, in order to prevent the stored data from being destroyed even when the power supply voltage is lowered, at least the rewrite operation needs to be completed as the read operation. As shown in FIG. 7, the rewrite operation is completed, for example, at a timing when the sense amplifier SA is turned off.

  The capacitance value of the capacitor for completing the read operation (or write operation) will be described with reference to FIG. Assume that the power supply voltage VDD becomes equal to or lower than the threshold voltage LowVdd after the start of the access cycle Ta as indicated by J1 in FIG. Then, an output signal of a power supply monitoring circuit 120 described later with reference to FIG. 11 or the like becomes active (for example, low level). A period from the voltage drop detection to the completion of the read operation or the write operation is defined as a period Tb. The period Tb is, for example, a period having the same length as that of the access cycle Ta at the maximum. As indicated by J3, the capacitor 70 is set to a capacitance value that does not cause the power supply voltage VDD to be lower than the operation lower limit voltage VT of the nonvolatile memory 60 in the period Tb. This operation lower limit voltage VT is, for example, the lower limit of the power supply voltage of the nonvolatile memory in design specifications and product specifications. Alternatively, it is the lower limit of the power supply voltage that can be read / written in the actual IC.

  For example, the current consumption when the storage device 20 performs access control is Idd, and the capacitance value of the capacitor 70 is C. Then, the voltage drop per unit time of the power supply voltage VDD is expressed as ΔV / Δt = Idd / C. Therefore, by setting the capacitance value C of the capacitor 70 so as to satisfy LowVdd− (Idd / C) × Tb> VT, it is possible to set the capacitance value C at which the power supply voltage VDD does not become the voltage VT or less in the period Tb.

  In the above description, the read operation is described as an example. However, in the case of the write operation, for example, the write operation is ensured by securing the time from the voltage application to the word line and the bit line to the end of writing to the ferroelectric capacitor. To complete.

As described above with reference to FIG. 2 and the like, such a capacitor 70 can be incorporated in a ferroelectric memory. FIG. 10 shows a detailed configuration example of a ferroelectric memory including a capacitor. This ferroelectric memory includes a base substrate 400 (die, eg, Si), an insulating layer 410 (insulating film, eg, SiO ₂ ), a transfer transistor 500, a ferroelectric capacitor 510, and a capacitor 520.

The transfer transistor 500 includes a source electrode 420, a drain electrode 430, an insulating layer 440, and a gate electrode 450. The transfer transistor 500 and a ferroelectric capacitor 510 described later constitute a memory cell. The insulating layer 440 is made of, for example, SiO ₂ (silicon dioxide). The gate portion 450 is made of, for example, polycrystal Si. The source part 420 and the drain part 430 are formed, for example, by ion implantation into the base substrate 400.

  The ferroelectric capacitor 510 includes a barrier layer 461, a lower electrode 471, a ferroelectric layer 481, and an upper electrode 491. The capacitor 520 includes a barrier layer 462, a lower electrode 472 (first electrode), a ferroelectric layer 482 (insulating layer), and an upper electrode 492 (second electrode). The barrier layers 461 and 462 are made of, for example, TiN. The lower electrodes 471 and 472 and the upper electrodes 491 and 492 are formed of a metal layer such as aluminum. The ferroelectric layer 481 is formed of a ferroelectric material such as PZT. One of the upper electrode 492 and the lower electrode 472 of the capacitor 520 is supplied with the power supply voltage VDD, and the other is supplied with the ground voltage VSS. In this way, the insulating layer of the capacitor can be formed from the ferroelectric layer of the ferroelectric memory.

  As described above, in a storage device having a nonvolatile memory, data stored in the nonvolatile memory may be destroyed when a situation in which data reading / writing is not normally performed due to a power supply abnormality occurs. There is a problem.

  In this regard, according to the present embodiment, when the power supply abnormal state is detected by the detection circuit 32, the access control to the nonvolatile memory 60 is stopped. The power supply voltage VDD supplied from the host device 10 is held by the capacitor 70 in order to complete at least one read or write access control.

  Thereby, it can suppress that the data memorize | stored in the non-volatile memory are destroyed. That is, the power supply voltage VDD supplied from the host device 10 is held by the capacitor 70, so that data destruction due to incomplete read / write access control that has already been started can be suppressed.

  Specifically, in this embodiment, when the power supply voltage VDD becomes equal to or lower than the threshold voltage LowVdd, a power supply voltage drop is detected as a power supply abnormal state. The capacitor 70 is set to a capacitance value at which the power supply voltage VDD does not decrease from the threshold voltage LowVdd and does not fall below the operation lower limit voltage VT of the nonvolatile memory 60 during the period of at least one read / write access control. The

  In this way, the power supply voltage VDD can be held at a voltage that does not fall below the operation lower limit voltage VT of the nonvolatile memory 60 in a period in which at least one read or write access control is performed. As a result, at least one read or write access control can be performed after the power supply voltage drop is detected.

  More specifically, in the present embodiment, when power supply voltage drop is detected after the start of the access cycle Ta, the access control in the access cycle Ta is completed without stopping. Capacitor 70 is set to a capacitance value such that power supply voltage VDD does not become lower than operation lower limit voltage VT of nonvolatile memory 60 during a period of access control in access cycle Ta.

  In this way, the power supply voltage VDD can be held at a voltage that does not fall below the operation lower limit voltage VT of the nonvolatile memory 60 during the period of access control in the access cycle Ta. Thereby, when a power supply voltage drop is detected after the start of the access cycle Ta, the access control in the access cycle Ta can be completed.

  As described above with reference to FIG. 1 and the like, in the present embodiment, the mask processing unit 34 masks the system clock supplied to the access control unit 36 when a power supply abnormal state is detected by the detection circuit 32.

  In this way, by masking the system clock SCK supplied to the access control unit 36, when the detection circuit 32 detects a power supply abnormal state, the read / write access control to the nonvolatile memory 60 is stopped. it can.

  Further, as described above with reference to FIG. 7 and the like, in this embodiment, when a power supply abnormal state is detected by the detection circuit 32 after the start of the access cycle Ta, the clock CK for performing read / write access control is activated. To do. Then, the read / write access control in the access cycle Ta is completed.

  In this way, the access control in the access cycle Ta can be started by activating the clock CK for performing access control. Even when a power supply abnormal state is detected by the detection circuit 32, the started access control can be completed without stopping.

  More specifically, an access control control signal is generated based on a signal obtained by delaying the active edge of the clock CK. That is, a plurality of delay clocks are generated by sequentially delaying the clock CK, a differential pulse of the active edge of each delay clock is generated, and an edge of each control signal is generated by the differential pulse.

  In this way, the read / write access control in the access cycle Ta can be completed by activating the clock CK.

  For example, in the present embodiment, the nonvolatile memory 60 may be a ferroelectric memory. The period during which at least one read or write access control is performed may be a period until the rewrite operation in the read access control for the ferroelectric memory is completed.

  In this way, since the rewrite operation can be completed, data destruction can be suppressed and read access control to the ferroelectric memory can be completed.

  In the present embodiment, the capacitor 70 may be a capacitor in which an insulator is formed of a ferroelectric layer of a ferroelectric memory.

  In this way, the capacitor 70 can be realized by forming the insulator with the ferroelectric layer of the ferroelectric memory. This facilitates the formation of a large-capacity capacitor from the ferroelectric layer. In addition, the number of components of the storage device 20 can be reduced.

5). FIG. 11 shows a configuration example of the detection circuit 32 that detects a power supply abnormal state and a configuration example of the mask processing unit 34 that masks the system clock SCK. A detection circuit 32 shown in FIG. 11 includes a power-on reset circuit 110, a power supply monitoring circuit 120 (power supply voltage drop detection circuit), a floating detection circuit 130, and an AND circuit AN1 (logical product circuit). 11 includes a holding circuit 100 (holding unit) and an AND circuit AN2 (logical product circuit). The detection circuit and the mask processing circuit of the present embodiment are not limited to this configuration, and some of the components are omitted (for example, a power-on reset circuit or a power supply monitoring circuit) or other components are added. It is possible to implement various modifications such as.

  The power-on reset circuit 110 performs a power-on reset based on the power supply voltage VDD. Specifically, the storage device 20 is reset until the power is turned on, and the reset of the storage device 20 is released when the power is turned on. The power-on reset circuit 110 sets the output signal POROUT to a high level (in a broad sense, when the difference between the power supply voltage VDD and the ground voltage VSS is equal to or higher than a threshold voltage (predetermined voltage) when the power of the host device 10 is turned on. 1st logic level).

  The power supply monitoring circuit 120 detects a voltage drop of the power supply voltage VDD. Specifically, the power supply monitoring circuit 120 outputs a high-level output signal LVD when the difference between the power supply voltage VDD and the ground voltage VSS is greater than or equal to the threshold voltage. On the other hand, when the difference between the power supply voltage VDD and the ground voltage VSS is equal to or lower than the threshold voltage, an output signal LVD of a low level (second logic level in a broad sense) is output.

  The floating detection circuit 130 detects the floating state of the power supply terminal TV and the ground terminal TG. For example, as will be described later with reference to FIG. 17 and the like, the floating detection circuit 130 detects the floating state by comparing the power supply voltage VDD or the ground voltage VSS with the voltage of the reference signal. When the floating state is not detected, the high level output signal FLTO is output. When the floating state is detected, the low level output signal FLTO is output.

  The AND circuit AN1 calculates the logical product of the output signal POROUT from the power-on reset circuit 110, the output signal LVD from the power supply monitoring circuit 120, and the output signal FLTO from the floating detection circuit 130. That is, when at least one of POROUT, LVD, and FLTO is at a low level (active), a low level (active) output signal QDT is output.

  The holding unit 100 (mask signal generation circuit in a broad sense) outputs a mask signal QMS for masking the system clock SCK based on the detection signal QDT from the detection circuit 32. Specifically, the mask signal QMS is deactivated until the floating state is detected, and the mask signal QMS is activated when the floating state is detected. Then, once the mask signal QMS is activated, the QMS is held active. More specifically, holding unit 100 holds detection signal QDT. That is, when the detection signal QDT changes to the low level, the low level is maintained thereafter. The holding unit 100 includes a selector SEL (selection circuit) and a flip-flop circuit FF.

  The selector SEL selects either the detection signal QDT or the mask signal QMS based on the mask signal QMS, and outputs the selected signal as the output signal QSL. Specifically, when the mask signal QMS is at a high level, the detection signal QDT is selected and output. When the mask signal QMS is at a low level, the mask signal QMS is selected and output.

  The flip-flop circuit FF latches (holds) the logic level of the output signal QSL from the selector SEL at the falling edge (or rising edge) of the system clock SCK, and outputs the latched logic level mask signal QMS. When the reset signal XRST (or set signal) is activated, the latched logic level is reset (or set). Specifically, when the reset signal XRST is at a low level, the mask signal QMS is reset (cleared) and a high level mask signal QMS is output. On the other hand, when the reset signal XRST is at the low level, the reset is released and the latched logic level mask signal QMS is output.

  Since the high level mask signal QMS is output immediately after the reset is released, the detection signal QDT is selected by the selector SEL. When the detection signal QDT becomes low level, the output signal QSL of the selector SEL becomes low level, and the low level is latched by the flip-flop circuit FF. Then, when the low-level mask signal QMS is selected by the selector SEL, the mask signal QMS is held at the low level. This holding state is maintained until reset by the reset signal XRST.

  The AND circuit AN2 (mask processing circuit in a broad sense) performs mask processing of the system clock SCK based on the mask signal QMS. Specifically, the AND circuit AN2 calculates a logical product of the mask signal QMS and the system clock SCK. That is, when the mask signal QMS is at a low level, the system clock MSCK after masking is set to a low level, and the system clock SCK is not supplied to the subsequent circuit. On the other hand, when the mask signal QMS is at a high level, the system clock SCK is output as the system clock MSCK after the mask processing, and the system clock SCK is supplied to the subsequent circuit.

6). Power Supply Abnormality Detection and Mask Processing An example of operation of power supply abnormality detection and mask processing will be described with reference to FIGS. FIG. 12 shows an operation example during normal operation, that is, when there is no power supply abnormality such as floating of the power supply terminal.

  As shown at A1 in FIG. 12, when the power supply voltage VDD exceeds the threshold voltage PORH (first threshold voltage), the signal POROUT becomes high level and the power-on reset is released as shown at A2. As shown in A3, when VDD exceeds the threshold voltage LowVDD, as shown in A4, the signal LVD becomes high level, and the low voltage detection becomes a non-detection state. As shown at A5, a high level is output to the signal FLTO, and the floating detection is not detected. Therefore, as shown at A6, a high level is output to the mask signal QMS, and the system clock SCK is supplied to the control unit.

  Then, as indicated by A7, the reset signal XRST is set to the high level to release the reset, and the data signal SDA and the system clock SCK are input. As shown in A8, when the power is turned off and VDD becomes equal to or lower than the threshold voltage LowVDD, the signal LVD becomes low level as shown in A9. As shown at A10, when VDD becomes lower than or equal to the threshold voltage PORL (second threshold voltage), the signal POROUT becomes low level as shown at A11.

  FIG. 13 shows an operation example when the power supply terminal TV or the ground terminal TG is in a floating state before the system clock SCK is input.

  As shown in B1 of FIG. 13, when the power supply terminal TV is in a floating state, the signal FLTO becomes a low level as shown in B2. As shown in B3, the system clock SCK is input, and as shown in B4, the mask signal QMS becomes low level at the first falling edge of SCK. Therefore, as shown in B5, SCK is output until the first falling edge of SCK in the system clock MSCK after mask processing, and thereafter, the low level is output. As shown in B6, when the reset is released, as shown in B7, the holding state of the mask signal QMS is released, and the QMS becomes high level. Other operations are the same as the operation example described in FIG.

  As described above, during the normal operation shown in FIG. 12, the system clock SCK is supplied to perform normal access control and the like. In contrast, when the floating state shown in FIG. 13 is detected, the mask signal QMS is held at a low level (active). As a result, the system clock SCK is masked, and access control and the like are stopped.

  FIG. 14 shows an operation example when the power supply voltage VDD decreases during normal operation. As indicated by C1 in FIG. 14, when the power supply voltage VDD becomes equal to or lower than the threshold voltage LowVDD, the signal LVD becomes low level as indicated by C2. As indicated by C3, after the signal LVD becomes low level, the mask signal QMS becomes low level at the first falling edge of the system clock SCK. Then, as indicated by C4, the system clock SCK is masked, and a low level is output to the system clock MSCK after the masking process. Other operations are the same as the operation example described in FIG.

  FIG. 15 shows an operation example when the power supply voltage VDD decreases during normal operation and the power supply voltage VDD is restored again. As shown in D1 of FIG. 15, when the power supply voltage VDD becomes equal to or lower than the threshold voltage LowVDD, the signal LVD becomes low level as shown in D2, and the mask signal QMS becomes low level as shown in D3. As indicated by D4, when the power supply voltage VDD becomes equal to or higher than the threshold voltage LowVDD again, the signal LVD becomes high level as indicated by D5. At this time, as indicated by D6, the mask signal QMS is held at a low level, and as indicated by D7, the system clock SCK is not supplied. As shown in D8, the holding state of the mask signal QMS is reset by reset release. Other operations are similar to the operation example described in FIG.

  FIG. 16 shows an operation example when the power supply voltage VDD is equal to or lower than the threshold voltage LowVDD before the operation starts. Since the power supply voltage VDD is equal to or lower than the threshold voltage LowVDD as indicated by E1 in FIG. 16, a low level is output as the signal LVD as indicated by E2. Then, as indicated by E3, the mask signal QMS is set to the low level at the falling edge of the first system clock SCK, and the system clock SCK is masked. Other operations are the same as the operation example described in FIG.

  In FIG. 13 described above, the case where the power supply terminal TV is in a floating state has been described as an example. However, in the present embodiment, the same operation is performed when the ground terminal TG is in a floating state or when the power supply voltage VDD is lowered. Further, in the above-described FIGS. 14 to 16, the case where the power supply voltage VDD is reduced is described as an example. However, in this embodiment, the same operation is performed when the power supply terminal TV or the ground terminal TG is in a floating state.

7). Power supply monitoring circuit (low voltage detection circuit)
FIG. 17 shows a detailed configuration example of the power supply monitoring circuit (low voltage detection circuit). This power supply monitoring circuit includes a comparator CP (op-amp) and first and second resistance elements R1 and R2. Note that the power monitoring circuit of the present embodiment is not limited to this configuration, and various modifications may be made such as omitting some of the components or adding other components.

  The resistor element R1 is provided between a power supply line to which the power supply voltage VDD is supplied and the node NI. The resistance element R2 is provided between the node NI and a ground line to which the ground voltage VSS is supplied. A voltage VI obtained by resistance-dividing the voltage between VDD and VSS by R1 and R2 is output to the node NI. The node NI is connected to the positive input terminal (first input terminal in a broad sense) of the comparator CP, and the voltage VI is input. The reference voltage Vref is input to the negative input terminal (second input terminal in a broad sense). For example, the reference voltage Vref is generated by a not-shown band gap circuit or the like. The comparator CP outputs a high level to the output signal LVD when VI> Vref, and outputs a low level to the output signal LVD when VI <Vref.

8). Liquid Container Next, a detailed configuration example of the liquid container provided with the storage device of the present embodiment described above will be described with reference to FIG. In the following, an example in which the host device is an ink jet printer, the liquid container is an ink cartridge, and the substrate is a circuit board provided in the ink cartridge will be described. However, in the present embodiment, the host device, the liquid container, and the substrate may be other devices, containers, and substrates. For example, the host device may be a memory card reader / writer, and the substrate may be a circuit board provided on the memory card.

  An ink chamber (not shown) for containing ink is formed in the ink cartridge 200 (liquid container in a broad sense) shown in FIG. The ink cartridge 200 is provided with an ink supply port 240 that communicates with the ink chamber. The ink supply port 240 is for supplying ink to the print head unit when the ink cartridge 200 is installed in the printer.

  The ink cartridge 200 includes a sensor 210 and a circuit board 220 (substrate in a broad sense). The sensor 210 is for detecting the remaining amount of ink in the ink chamber. The sensor 210 is composed of, for example, a piezoelectric element and is fixed inside the ink cartridge 200. The circuit board 220 is provided with the storage device 20 of the present embodiment, and stores data and transmits / receives data to / from the host device 10. The circuit board 220 is realized by a printed circuit board, for example, and is provided on the surface of the ink cartridge 200. The circuit board 220 is provided with terminals such as a power supply terminal TV. Then, when the ink cartridge 200 is mounted on the printer, the terminals and the terminals on the printer side come into contact (electrically connected), whereby power and data are exchanged.

9. Substrate FIGS. 19A and 19B show a detailed configuration example of a circuit board provided with the memory device of this embodiment. As shown in FIG. 19A, a terminal group having a plurality of terminals is provided on the surface of the circuit board 220 (surface connected to the printer). This terminal group includes a ground terminal TG, a power supply terminal TV, a first sensor driving terminal TSN, a reset terminal TR, a clock terminal TK, a data terminal TD, and a second sensor driving terminal TSP. Each terminal is realized by, for example, a metal terminal formed in a rectangular shape (substantially rectangular shape). Each terminal is connected to the storage device 20 or the sensor 210 via a wiring pattern layer or a through hole (not shown) provided on the circuit board 220.

  As shown in FIG. 19B, the storage device 20 of this embodiment is provided on the back surface of the circuit board 220 (the surface on the back side of the surface connected to the printer). The storage device 20 can be realized by, for example, a semiconductor storage device having a ferroelectric memory. The storage device 20 stores various data related to the ink or the ink cartridge 200, for example, data such as ink consumption and ink color. The ink consumption data is data indicating the total amount of ink consumed for the printing of the ink stored in the ink cartridge 200. The ink consumption data may be information indicating the amount of ink in the ink cartridge 200 or information indicating the ratio of the consumed ink amount.

10. System FIG. 20 shows a detailed configuration example of a system in which the storage device of this embodiment is used. The system shown in FIG. 20 (information processing system, printing system) includes a printer 10 and an ink cartridge 200. The printer 10 includes a main control unit 300 and a sub control unit 310. The ink cartridge 200 includes the storage device 20 and the sensor 210 of the present embodiment. Hereinafter, a case where one ink cartridge is mounted on the printer will be described as an example. However, in the present embodiment, a plurality of ink cartridges may be mounted on the printer.

  The sub control unit 310 supplies the power supply voltage VDD and the ground voltage VSS to the storage device 20 via the power supply terminal TVH and the ground terminal TGH, respectively. The sub-control unit 310 performs data reading / writing with respect to the storage device 20 and sensor processing using the sensor 210. Specifically, the sub control unit 310 includes a communication processing unit 312 and a sensor processing unit 314.

  The communication processing unit 312 performs communication processing between the storage device 20 and the main control unit 300. Specifically, the reset signal XRST, the system clock SCK, and the data signal SDA are supplied to the storage device 20 via the reset terminal THR, the clock terminal THK, and the data terminal THD, respectively. Then, as will be described later with reference to FIG. 11 and the like, serial communication processing with the storage device 20 is performed using these signals. However, in the present embodiment, the communication processing unit 312 and the storage device 20 may perform parallel communication processing. In addition, the communication processing unit 312 performs communication processing with the main control unit 300 by exchanging commands and data signals via the bus BS. For example, the communication processing unit 312 determines connection or disconnection between the ink cartridge 200 and the printer 10 and a communication error with the storage device 20, and transmits these determination results to the main control unit 300.

  The sensor processing unit 314 performs a remaining ink level determination process by the sensor 210. The sensor processing unit 314 applies the sensor driving signal DS from the main control unit 300 to the electrode of the sensor 210 via the sensor driving terminal THSN or THSP. The sensor processing unit 314 determines whether the remaining amount of ink is greater than or less than the threshold based on a signal obtained by applying the sensor drive signal DS to the sensor 210. The determination result is transmitted to the main control unit 302 via the communication processing unit 312.

  The main control unit 300 controls the printer 10. For example, the memory access is controlled, the power supply voltage VDH and the ground voltage VSH are supplied to the sub-control unit 310, and the remaining ink level is determined (calculation processing). More specifically, the main control unit 300 includes a control circuit 302 and a drive signal generation circuit 304.

  The control circuit 302 transmits commands and data to the communication processing unit 312 via the bus BS, and controls communication processing between the communication processing unit 312 and the storage device 20. Specifically, when the connection of the ink cartridge 200 is detected by the communication processing unit 312, data such as the remaining amount of ink stored in the storage device 20 is read, and the ink remaining amount newly calculated based on the data is read. Are written in the storage device 20. In addition, the control circuit 302 controls the drive signal generation circuit 304 and supplies the sensor drive signal DS to the sensor 210. Then, the control circuit 302 determines the remaining amount of ink based on the determination result of the remaining amount of ink from the sensor processing unit 314 and the estimated ink consumption amount due to printing. When it is determined that the ink has run out, the ink running information may be displayed on a display unit (not shown).

  The storage device 20 includes a memory control circuit 30 (control unit) and a ferroelectric memory cell array 60 (ferroelectric memory). The memory control circuit 30 includes a detection circuit 32, a mask control circuit 34, an ID comparison unit 40, a command interpretation unit 42, an address counter 44, a read / write control unit 46, a data transmission / reception unit 38 (transmission / reception unit), a counter control unit 48, A duplicate data generation unit 50, an inverted data generation unit 52, and a data determination unit 54 (determination unit) are included. Note that the same components (for example, the detection circuit) as those described above with reference to FIG.

  The ID comparison unit 40 compares the ID data (identification data) received from the sub-control unit 310 with the ID number assigned to the storage device 20 (for example, a number corresponding to the color of the ink). It is determined whether or not it is an access target.

  The command interpretation unit 42 interprets SOF (communication start data), command data, and EOF (communication end data) received from the sub-control unit 310, and determines the type of access such as access start, read and write, and access end. To do. The address counter 44 counts the system clock SCK and outputs a count value for designating an address (for example, a word line) of the ferroelectric memory cell array 60. The read / write control unit 46 performs read / write control with respect to the ferroelectric memory cell array 60 based on the access type interpreted by the command interpretation unit 42 and the count value of the address counter 44. The counter control unit 48 (sequencer) counts the system clock SCK and controls memory access based on the count value and command interpretation by the command interpretation unit 42.

  The duplicate data generating unit 50 copies the original data read from the ferroelectric memory cell array 60 and generates mirror data (replicated data). The inverted data generation unit 52 inverts each bit value of the original data read from the ferroelectric memory cell array 60 (for example, inverts 0 to 1 and 1 to 0) to generate inverted data. The data determination unit 54 determines the data consistency by performing a parity check of the original data and the mirror data and an exclusive OR operation of the original data and the inverted data.

  The ferroelectric memory cell array 60 includes a plurality of ferroelectric memory cells arranged along word lines and bit lines. The ferroelectric memory cell array 60 can include a row address decoder, a column address decoder, a sense amplifier, etc. (not shown).

11. Communication processing (read control)
As described above, the storage device of this embodiment stops access control to the ferroelectric memory when detecting a power supply abnormal state such as a power supply voltage drop. At this time, since the printer cannot directly recognize that the power supply abnormal state has been detected, it needs to be recognized through communication processing with the storage device.

  Hereinafter, communication processing between the printer 10 and the storage device 20 will be described in detail with reference to FIGS. FIG. 21 schematically shows an example of a signal waveform when data is read from the storage device 20. In FIG. 21, the direction of data transmission / reception is indicated by arrows. That is, an arrow from H to C indicates that the sub-control unit 310 is the transmission side and the storage device 20 is the reception side, and an arrow from C to H indicates that the storage device 20 is the transmission side and the sub-control unit 310 is the transmission side. Indicates the receiving side.

  As shown in A1 of FIG. 21, when the communication process is started, the reset signal is changed from the low level to the high level. As shown in A2, the system clock SCK is supplied to the storage device 20. As indicated by A3, first, SOF (Start Of Frame) data is transmitted to the storage device 20 as the data signal SDA. As indicated by A4, ID data and read command data are transmitted to the storage device 20 as operation codes. As the ID data, original ID data ID and inverted ID data / ID obtained by inverting each bit value of the original ID data (hereinafter, the inverted data is indicated by a slash symbol /) are transmitted to the storage device 20. Original command data CM and inverted command data / CM are transmitted as command data.

  As indicated by A5, read data (read data) from the storage device 20 is transmitted to the sub-control unit 310. As read data, upper 8 bits UD1 of 16-bit original data, its inverted data / UD1, lower 8 bits LD1 of original data, and its inverted data / LD1 are transmitted. Also, mirror data Ud1 of UD1, its inverted mirror data / Ud1, mirror data Ld1 of LD1, and its inverted mirror data / Ld1 are transmitted. UD1, LD1, Ud1, and Ld1 are data read from the storage device 20. On the other hand, the inverted data / UD1, / LD1, / Ud1, and / Ld1 are data generated by the inverted data generation unit 52. As indicated by A6, reading and transmission of the above-described read data (unit read data) are repeated. As shown in A8, when the transmission of the read data is completed, the reset signal is set to the low level.

  As described above, it is possible to suppress erroneous operation of the storage device 20 by multiplexing the data with the original data and the inverted data. For example, it is possible to prevent destruction of data in the nonvolatile memory by receiving an erroneous command due to a communication failure and performing erroneous writing or reading on the nonvolatile memory.

  Here, as described with reference to FIG. 1 and the like, when a power supply abnormal state such as a power supply voltage drop is detected, the system clock SCK is masked, and read / write control and data transmission / reception are not performed. At this time, for example, a low level is output as read data transmitted to the printer 10. Thereby, the printer 10 can detect the power supply abnormal state as an error in the communication process.

  FIG. 22 shows a flowchart example of printer read processing. As shown in FIG. 22, when the reading process is started, the printer 10 transmits SOF data (S2), transmits ID data (S4), transmits a read command (S6), and receives unit read data. (S8). When the unit read data is received, the data determination process for the unit read data is performed (S10). If the result of data determination is an error (N), error processing is performed (S12), and the communication processing is terminated. If the result of the data determination is normal (Y), it is confirmed whether all the read data has been received (S14). If all the read data has been received (Y), the communication process is terminated, and if it has not been received (N), the unit read data is received (S8).

  In the data determination process (S10), for example, exclusive OR of original data and inverted data, exclusive OR of mirror data and inverted mirror data, and exclusive OR of original data and inverted mirror data are calculated. . When reading or data transmission / reception is performed normally, each bit of these exclusive ORs is 1. In the data determination process, a communication error or a memory cell error is determined based on the calculation result. In error processing (S12), for example, in the case of a communication error, a message indicating that the ink cartridge 200 is not correctly attached to the printer 10 is displayed on the display unit of the printer 10.

  FIG. 23 shows a flowchart example of read processing of the storage device. As shown in FIG. 23, when the communication process is started, the storage device 20 receives SOF data (S102), receives ID data (S104), and determines whether the received ID data is normal (S106). ) If the ID data is abnormal (N), the communication process is terminated, and if the ID data is normal (Y), whether the ID data matches or not is determined (S108). If the ID data and the ID number of the storage device 20 do not match (N), the communication process is terminated, and if the ID data matches, (Y) command data is received (S110). Then, it is determined whether the received command data is normal (S112). If the command data is abnormal (N), the communication process is terminated, and if it is normal (Y), the command type is determined (S114). If the command is a read command, a read process is performed (S120), and the communication process is terminated. In the read process, reading and transmission of original data and the like, and generation and transmission of inverted data are performed.

  If the command is a write command, the storage device 20 performs a write process, which will be described later with reference to FIG. 26 and the like (S116). If the command is a write lock command, write lock processing is performed (S118). In the write lock process, a process of setting a part (or all) of the rewritable area of the ferroelectric memory 60 as a non-writable area is performed. Specifically, address data is received following the write lock command. Then, the area designated by the received address data is set as the write lock area. For example, the write lock area is set for each row of the ferroelectric memory 60 by setting a write flag in the control register.

12 Communication processing (write control)
FIG. 24 schematically illustrates an example of a signal waveform when data is written to the storage device 20. 24, SOF data, ID data ID, inverted ID data / ID, write command data CM, and inverted write command data / CM are transmitted to the storage device 20. Then, as shown in B2, the upper 8 bits UD1 of the 16-bit original data, its inverted data / UD1, the lower 8 bits LD1 of the original data, and its inverted data / LD1 are transmitted as write data. Further, the mirror data Ud1 of UD1, its inverted mirror data / Ud1, the mirror data Ld1 of LD1, and its inverted mirror data / Ld1 are transmitted to the storage device 20.

  As shown in B3, the storage device 20 determines whether or not the transmitted data is normal, and an OK / NG flag is transmitted to the printer 10 based on the determination result. For example, when it is determined that the data is normal, a high-level OK flag is transmitted, and when it is determined that the data is abnormal, a low-level NG flag is transmitted. Then, as shown in B4, the transmission of the write data (unit write data) and the transmission of the OK / NG flag are repeated. As shown in B5, when the transmission of the write data is completed, EOF (End Of Frame) data is transmitted to the storage device 20.

  Here, when a power supply abnormal state such as a power supply voltage drop is detected, the storage device 20 outputs, for example, a low level as the data signal SDA (stops transmission of determination result information). As a result, the printer 10 receives the low level (NG) as the OK / NG flag, and can determine that it is a communication error. In this way, the printer 10 can detect a power supply abnormality state as an error in communication processing.

  FIG. 25 shows a flowchart example of printer write processing. As shown in FIG. 25, when the writing process is started, the printer 10 transmits SOF data (S202), transmits ID data (S204), and transmits write command data (S206). Then, processing for transmitting unit write data is performed (S208), an OK / NG flag is received (S210), and it is determined whether the received OK / NG flag is an OK flag or an NG flag (S212). If the OK / NG flag is an NG flag (N), an error process is performed (S214) and the communication process is terminated. If the OK / NG flag is an OK flag (Y), it is determined whether all the write data has been transmitted (S216). When all the write data is transmitted (Y), the EOF data is transmitted (S218), and the communication process is terminated. If all the write data has not been transmitted (N), a process of transmitting unit write data is performed (S208).

  FIG. 26 shows a flowchart example of the write processing of the storage device. As described above with reference to FIG. 23 and the like, the storage device 20 performs a write process when it receives the write command data. As shown in FIG. 26, in the write process, a process of receiving unit write data is performed (S302), and it is determined whether or not the received write data is normal (S304). If the write data is abnormal (N), an NG flag is transmitted (S306), and the communication process is terminated. If the write data is normal (Y), an OK flag is transmitted (S308), and the write data is written in the target area of the nonvolatile memory (S310). It is determined whether or not EOF data has been received (S312). If it has been received (Y), the communication process is terminated, and if it has not been received (N), a process for receiving unit write data is performed (S302). ).

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, at least once, terms (nonvolatile memory, open state, etc.) described together with different terms (nonvolatile storage, floating state, substrate, liquid container, host device, etc.) in a broader sense or the same meaning (Circuit board, ink cartridge, printer, etc.) may be replaced with the different terms anywhere in the specification or drawings. Further, the configurations and operations of the control unit, the nonvolatile storage unit, the storage device, the substrate, the liquid container, the host device, and the like are not limited to those described in this embodiment, and various modifications can be made.

10 host device, 20 storage device, 30 control unit, 32 detection circuit,
34 mask processing unit, 36 access control unit, 38 transmission / reception unit, 40 ID comparison unit,
42 command interpreter, 44 address counter, 46 read / write controller,
48 counter control unit, 50 duplicate data generation unit, 52 inverted data generation unit,
54 data determination unit, 60 nonvolatile storage unit, 100 holding unit,
110 power-on reset circuit, 120 power supply monitoring circuit,
130 floating detection circuit, 200 liquid container, 210 sensor,
220 substrate, 240 ink supply port, 300 main control unit, 310 sub-control unit,
TV power supply terminal, TVH power supply terminal on the host device side, TG ground terminal,
TGH Host device side ground terminal, TR reset terminal,
TRH Host device side reset terminal, VDD power supply voltage, VSS ground voltage,
SCK system clock, Ta access cycle, LowVdd threshold voltage,
VT operation lower limit voltage

Claims (11)

A non-volatile storage unit;
A control unit for controlling the nonvolatile storage unit;
Capacitors,
Including
The controller is
A detection circuit for detecting a power supply abnormal state of the power supply voltage supplied from the host device;
An access control unit that performs read or write access control on the non-volatile storage unit and stops read or write access control on the non-volatile storage unit when a power supply abnormal state is detected by the detection circuit; ,
Have
The capacitor is
A storage device that holds a power supply voltage supplied from the host device in order to complete at least one read or write access control when a power supply abnormal state is detected by the detection circuit. In claim 1,
The detection circuit includes:
When the power supply voltage supplied from the host device is equal to or lower than the threshold voltage, a power supply voltage drop is detected as a power supply abnormal state,
The capacitance value of the capacitor is
In the period of performing at least one read or write access control, the power supply voltage supplied from the host device has a capacitance value that does not drop below the threshold voltage and does not fall below the operation lower limit voltage of the nonvolatile storage unit. A storage device that is set. In claim 2,
The nonvolatile storage unit is a ferroelectric memory,
The storage device characterized in that the period for performing at least one read or write access control is a period until the rewrite operation in the read access control for the ferroelectric memory is completed. In claim 1 or 2,
The nonvolatile storage unit is a ferroelectric memory,
The capacitor is
A storage device comprising a capacitor in which an insulator is formed by a ferroelectric layer of the ferroelectric memory. In any one of Claims 1 thru | or 4,
The controller is
A mask processing unit for performing mask processing of a system clock supplied to the access control unit;
The mask processing unit
The storage device, wherein the system clock is masked when a power supply abnormal state is detected by the detection circuit. In claim 1,
The access control unit
When a power supply abnormal state is detected by the detection circuit after the start of the access cycle, the read or write access control in the access cycle is completed without stopping,
The detection circuit includes:
When the power supply voltage supplied from the host device is equal to or lower than the threshold voltage, a power supply voltage drop is detected as a power supply abnormal state,
The capacitance value of the capacitor is
In a period of performing read or write access control in the access cycle, the power supply voltage supplied from the host device is set to a capacitance value that does not drop below the threshold voltage and does not fall below the operation lower limit voltage of the nonvolatile storage unit. A storage device. In claim 6,
The access cycle is started by a change in the logic level of an enable signal for enabling read or write access control. The read operation or write operation is performed by activating a clock for performing read or write access control. Start,
The access control unit
When a power supply abnormal state is detected by the detection circuit after the start of the access cycle, the clock for performing the read or write access control is activated to complete the read or write access control in the access cycle. A storage device.   A substrate comprising the storage device according to claim 1.   A liquid container comprising the storage device according to claim 1. A storage device according to any one of claims 1 to 7,
The host device;
A system characterized by including. Control the non-volatile storage,
Detects the power supply abnormal state of the power supply voltage supplied from the host device,
Performs read or write access control to the nonvolatile storage unit,
When the power supply abnormal state is detected, the read or write access control to the nonvolatile storage unit is stopped,
A method for controlling a storage device, comprising: holding a power supply voltage supplied from the host device in order to complete at least one read or write access control when the power supply abnormal state is detected.

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