JP2003100088A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which a sufficient write-in state can be obtained when a power source is raised next even if a state is an insufficient write-in state when the power source falls and reliability of data stored for each memory cell of a nonvolatile memory is improved. SOLUTION: Write-in operation immediately before cut off of a power source of a nonvolatile memory is stored in a data storage circuit DM1 and an address storage circuit AM1, when the power source is applied next, rewrite-in is performed for write-in immediately before cut off using the same data for the same address of a memory array MA1. Thus, a complete write-in state is obtained for each memory cell in the memory array MA1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a ferroelectric memory, a non-volatile memory such as an EEPROM or a flash memory.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit composed of a nonvolatile memory such as a ferroelectric memory, an EEPROM or a flash memory has been widely used as a semiconductor integrated circuit in many electronic devices. Since it has the characteristics of non-volatile, low power consumption, and small size and light weight,
It has come to be widely used as an information recording medium for images, sounds, characters and the like in small portable devices and the like.

In such a semiconductor integrated circuit, a memory cell corresponding to a plurality of addresses for storing data written from the outside is formed in a nonvolatile memory inside the semiconductor integrated circuit. As shown, power supply voltage VDD
A capacitor is provided between the line and the ground (GND) line, and by adjusting this capacitance, the power supply for supplying power to the circuit is turned off (OFF) while writing data to the internal nonvolatile memory. When the state is reached, the power supply voltage VDD is configured to gradually decrease with a predetermined slope from the time when the voltage is cut off.

In the above-mentioned falling characteristic, there is an operation lower limit voltage point on the way, and there is a final write voltage point at a point where a predetermined write operation time has elapsed from that point. The area from the operation lower limit voltage to the final write voltage becomes the storage data unstable area, and the data stored in this area may be destroyed in some cases.

It should be noted that as the capacitance of the capacitor provided between the VDD line and the GND line is increased, the slope of the falling characteristic becomes gentler and the unstable region is reduced, but a region for forming the capacitor is required and the die is required. The size increases.

As described above, Japanese Patent Laid-Open No. 2000-41972 discloses a method for protecting the contents of the memory so as not to be destroyed even when the power is turned off with the characteristics shown in FIG. 5 during the access to the nonvolatile memory. Is shown in.

Further, Japanese Patent Laid-Open No. 10-334671 also discloses a method for preventing the data stored in the memory from being destroyed even when the power supply is cut off due to the characteristic shown in FIG. There is.

[0008]

However, in the conventional semiconductor integrated circuit as described above, Japanese Patent Laid-Open No. 2000-4 has been proposed.
In the one described in Japanese Patent No. 1972, the data is temporarily stored in the RAM when the power is cut off.
To this end, RA is used even when the system power is cut off.
It is necessary for M to continue the functional operation, and if there is no separate power source such as a backup battery for the functional operation,
The data temporarily stored in the RAM is not retained, and in order for the RAM to continue the functional operation, a separate power source means such as a backup battery is required, which increases the number of system components and complicates the configuration. Had the problem.

Further, in the one disclosed in Japanese Patent Laid-Open No. 10-334671, since a ferroelectric memory is provided for each memory cell to prevent data destruction, the memory configuration becomes very large, and therefore the die There was a problem that the size became very large.

Further, since the nonvolatile memory is characterized in that data can be held without a backup power source, it is best to eliminate restrictions on how to apply the power source voltage. Is provided, and a circuit for determining and setting a voltage at which the memory starts operating, a voltage for stopping the memory operation, and the like is provided, thereby limiting operations such as writing outside the specified voltage range. Since these set voltages change due to variations in process conditions in the manufacturing process of semiconductor integrated circuits, the power supply voltage is normally maintained from the time when the signal is output to stop the memory operation until the writing is completed. It is difficult to maintain the range within the specified range for proper write operation, so the final write becomes insufficient write, and it becomes difficult to ensure the reliability of data retention. Was.

The present invention solves the above-mentioned conventional problems, and is insufficient for the reliability guaranteed for data retention when the power is turned off, for example, "data retention period of 10 years". Even in the written state, the semiconductor device can be brought into a sufficient written state at the next power-on, and the reliability of the data stored in each memory cell of the nonvolatile memory can be greatly improved. An integrated circuit is provided.

[0012]

In order to solve the above problems, a semiconductor integrated circuit of the present invention has a non-volatile memory for storing externally written data in a memory cell corresponding to a plurality of addresses. In a semiconductor integrated circuit, in response to the write operation, an address storage unit that stores an address of the nonvolatile memory that is a write target, and a write target to the write target address corresponding to the write operation And a data storage means for storing the data stored in the address storage means at the time of a write operation immediately before the power source is turned off to the nonvolatile memory when the power source is turned on. The stored address of the nonvolatile memory is stored in the data storage means at the time of the write operation immediately before the power is turned off. And characterized by being configured to include a control means for controlling to write.

As described above, when the power is turned from the off state to the on state and rises, the data is stored in the address storage means and the data storage means provided separately from the nonvolatile memory by the access just before the power is turned off and falls. It is possible to rewrite the data stored in the data storage means to the address stored in the address storage means in the nonvolatile memory by using the address and the data.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit according to claim 1 of the present invention has a memory cell corresponding to a plurality of addresses.
In a semiconductor integrated circuit having a non-volatile memory for storing data written from the outside, address storage means for storing an address of the non-volatile memory to be written corresponding to the writing operation, In response to the write operation, the data storage means for storing the data to be written to the write target address and the power supply to the nonvolatile memory when the power supply is turned from the off state to the on state. To write the data stored in the data storage unit at the time of the write operation immediately before the power supply is turned off to the address of the nonvolatile memory stored in the address storage unit at the time of the write operation immediately before the power supply is turned off. And a control means for controlling.

According to this structure, when the power is turned on from the off state and rises, the address storage means and the data storage means provided separately from the nonvolatile memory are accessed by the access just before the power is turned off and the power is turned on. Using the address and data stored in the memory, the data stored in the data storage means is rewritten to the address stored in the address storage means in the nonvolatile memory.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit according to the first aspect, further comprising power supply monitoring means for monitoring the state of the power supply voltage, and the control means for controlling the power supply voltage from the power supply monitoring means. Based on monitoring information about
It is configured to automatically execute write control to the nonvolatile memory when the power is turned on from the off state.

According to this structure, when a non-volatile memory that supplies power through radio waves, such as an RFID tag or a contactless smart card, is used as the non-volatile memory, the power supply voltage changes momentarily depending on the communication state. Then, even when the power supply voltage drops once and then rises again, the state of such power supply voltage is constantly monitored, and the change in the power supply voltage is automatically tracked based on the monitoring information. When the power is turned on, the address and the data stored in the address storage means and the data storage means provided separately from the non-volatile memory by the access just before the power is turned off are used.
The data stored in the data storage means is automatically rewritten to the address stored in the address storage means.

Here, in describing the embodiments of the present invention, an outline of the examination process of the present invention will be described. In EEPROM or flash memory, a data write operation to a non-volatile memory in a semiconductor integrated circuit is performed by applying a potential difference between nodes of the memory cell and injecting hot electrons or FN current into a floating gate so that the memory cell is This is done by changing the threshold voltage of the transistors that compose it. Since the completeness of writing at this time is determined by the voltage difference between the nodes and the application time, when the potential difference at the time of writing is small or the application time is short, the guaranteed reliability,
For example, the “data retention period of 10 years” cannot be satisfied.

Similarly, also in the ferroelectric memory, the completeness of writing is determined by the potential difference between the nodes of the ferroelectric capacitor and the application time. Similarly, when the potential difference between the nodes is small, the guaranteed reliability is ensured. For example, "data retention period 10
It becomes impossible to satisfy "year" etc.

Further, since the nonvolatile memory is characterized by holding data without a backup power source,
It is best to remove restrictions on how to apply the power supply voltage.To this end, a function to monitor the power supply voltage is provided inside the memory to determine the voltage at which the memory starts operating, the voltage at which the memory operation is stopped, etc. A circuit for setting is set to limit operations such as writing outside the specified voltage range. Since these set voltages change due to variations in process conditions in the manufacturing process of the semiconductor integrated circuit,
Since it becomes difficult to secure the voltage within the specified power supply voltage from the time when the signal is output to stop the memory operation until the writing is completed, the final writing becomes insufficient writing and It becomes difficult to secure the reliability of retention.

In the present invention, in response to the write operation immediately before the uncertain power supply voltage is lowered, the data is written so that the rewriting is performed when the power supply voltage exceeding the specified value is applied next. I have to.

A semiconductor integrated circuit according to an embodiment of the present invention will be specifically described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit of the present embodiment. FIG. 2 is a timing chart showing the operation of the semiconductor integrated circuit of the same embodiment.

During the read operation during the normal operation, the control circuit CC1 causes the address storage circuit AM1 to set the address / data storage circuit control signal (1) MS1 to Low.
At the same time as the input of the address / data storage circuit control signal (2) MS2 to the data storage circuit DM1, the operation of the address storage circuit AM1 and the data storage circuit DM1 is stopped and the memory array M
A normal read operation to A1 can be performed to A1 through the address circuit AC1 controlled by the address control signal AS1 and the data circuit DC1 controlled by the data control signal DS1.

During the write operation, the control circuit CC1
As a result, by inputting Low as the address / data storage circuit control signal (1) MS1 to the address storage circuit AM1 and simultaneously inputting High as the address / data storage circuit control signal (2) MS2 to the data storage circuit DM1, the address The memory circuit AM1 and the data memory circuit DM1 are operated to operate from the outside through the memory array MA1 through the address circuit AC1 controlled by the address control signal AS1 and the data circuit DC1 controlled by the data control signal DS1. In addition to enabling normal write operation, the address storage circuit AM of the same address as the memory array MA1 in the write operation
1 and a write operation to the data storage circuit DM1 of the same data as the memory array MA1 are performed at the same time. By these write operations, the address in the address storage circuit AM1 and the data in the data storage circuit DM1 are written. Always memorize while rewriting.

As the address storage circuit AM1 and the data storage circuit DM1, the memory array MA1 is used.
In order to improve the stability of the write operation as compared with the above, a complementary non-volatile memory cell with two transistors is adopted.

During the above normal operation, the power is cut off, and
As shown in (b), when the power supply voltage PW1 is turned off, as in the above write operation, the control circuit CC
1, by inputting Low as the address / data storage circuit control signal (1) MS1 to the address storage circuit AM1 and simultaneously inputting High as the address / data storage circuit control signal (2) MS2 to the data storage circuit DM1 Address storage circuit AM of the same address and the same data as the memory array MA1 in the write operation
1 and the data storage circuit DM1 write the last address and data to the address storage circuit A.
It is stored in M1 and the data storage circuit DM1.

At this time, the power supply voltage PW1 is decreasing, and the final write data to each memory cell of the memory array MA1 may be insufficiently written. The state memory cell is
In some cases, it may not be possible to sufficiently satisfy the reliability, especially the data retention characteristic, and for example, the data retention may decrease to about 1 year with respect to the data retention specification of 10 years (“data retention period 10 years”). To be

Next, when the power is turned on again and the power supply voltage PW1 is turned on as shown in FIG. 2 (a), the control circuit CC1 causes the address storage circuit AM1 to send the address / data storage circuit control signal ( 1) High as MS1
Simultaneously with the input of h, the address / data storage circuit control signal (2) MS2 is set to High in the data storage circuit DM1.
By inputting h, the data stored in the data storage circuit DM1 is transferred to the sense amplifier from the address storage circuit AM1 and the data storage circuit DM1 to the memory array MA1 at the address stored in the address storage circuit AM1. Writing (rewriting in this case) is performed through SA1.

During this period, the above-mentioned normal read / write operation is prohibited. However, if the write operation is to the same address, it is possible to set the specification so that the prohibition can be released.

As described above, in each memory cell in the memory array which has been completed by insufficient writing before the power is turned off,
Sufficient writing can be performed, and the reliability of the data written in the memory cell can be improved.

As described above, in order to perform the writing and erasing operations in the address storage circuit AM1 and the data storage circuit DM1 very quickly as compared with the memory array MA1, it is necessary to perform the writing and erasing operations on the memory area. Although it is provided separately from the array MA1, for this reason, if the power is turned off during the writing and erasing operations, writing and erasing to the memory cells of the memory array MA1 may become insufficient.

Therefore, the nonvolatile memory, especially EEPRO
In M, "1" or "0" data is stored depending on whether the VT of the memory cell transistor is raised or lowered by a certain level or more according to the write operation or the erase operation. , The VT of the transistor of the memory cell is increased to a value equal to or higher than a certain value VTA, and VT is decreased to a value equal to or lower than VTB in the write operation. These operations are performed by applying potentials to the gate, drain / source, and substrate of the memory cell. Further, the time required to make the VT value of the memory cell transistor above or below a certain level is determined by the applied potential.

However, when the potential is increased, the stress on the memory cell transistor increases. For this reason, for example, for the memory array MA1 that needs to guarantee data retention and rewriting of 500,000 times for 10 years, it is necessary to satisfy this guarantee. Therefore, the potential during writing or erasing is higher than a certain level. Can not do it.

On the other hand, in the address storage circuit AM1 and the data storage circuit DM1, the period for holding the data is only required from the power-off to the next power-on, and writing and erasing are performed by the power-supply. Since it only occurs during ON / OFF, it is OK with a small number of times (10 times a day * 10 years = 36500 times). Therefore, the voltage at the time of writing or erasing can be increased, and the rewriting and erasing times can be greatly shortened.

The address storage circuit AM1 and the data storage circuit D which can be rewritten and erased in this extremely short period.
The address and data stored in M1 are rewritten to the memory cell of the memory array MA1 which has been insufficiently written or erased when the power is turned off the next time the power is turned on. To do.

After the above operation is completed, the control circuit CC1 inputs Low as the address / data storage circuit control signal (1) MS1 to the address storage circuit AM1 and at the same time to the address / data storage circuit control signal (1) to the data storage circuit DM1. 2) By inputting Low as MS2, the normal read operation as described above can be performed for the memory array MA1, and address / data storage circuit control signal (1) Low is input to the address storage circuit AM1. At the same time, the address / data storage circuit control signal (2) MS2 is set to H level in the data storage circuit DM1.
By inputting "high", the normal write operation as described above can be performed on the memory array MA1, and the write operation to the address storage circuit AM1 and the data storage circuit DM1 as described above is simultaneously performed.

The above rewriting is always performed when the power is turned on. However, when the data writing when the power is turned off is systematically guaranteed, the rewriting is performed when the power is turned on again. It is also possible to set to skip.

By the above operation, when using the non-volatile memory, it is possible to greatly reduce the specification of turning on / off of the power supply voltage, so that the configuration of the system to be used can be made very simple. (Embodiment 2) Next, as a non-volatile memory in the semiconductor integrated circuit of the present embodiment, a non-volatile memory such as an RFID tag or a contactless smart card that supplies power through radio waves will be described.

FIG. 4 is a timing chart showing the operation of the power supply monitoring circuit with respect to the time change of the power supply voltage in the RFID tag or the contactless smart card according to the present embodiment.

RF is used as the semiconductor integrated circuit of the present embodiment.
In the case of ID tags and smart cards, as shown in FIG. 4, for example, due to changes in the distance between them and a reader / writer (not shown) that transmits and receives data to and supplies power to them. , The power supply voltage PW1 for the nonvolatile memories formed therein changes.
As described above, the internal power supply voltage PW1 changes every moment while the RFID tag or the smart card moves, and the read / write operation of the nonvolatile memory is limited to cope with the voltage fluctuation. The need arises.

Therefore, as described above, the RFID in operation
For tags and smart cards, its power supply voltage PW1
However, if the power supply voltage PW1 rises above the predetermined voltage again after the power supply voltage PW1 rises again due to constant fluctuation due to the positional relationship with the reader / writer, It is very useful to perform the above rewriting operation automatically by always monitoring the power supply voltage PW1.

The above operation in the semiconductor integrated circuit such as the RFID tag or the smart card will be described below with reference to FIG. 3 by taking the operation by the power supply monitoring circuit PM1 shown in FIG. 1 as an example.

First, the basic operation of the power supply monitoring circuit PM1 will be described. FIG. 3 is a timing chart showing the basic operation of the power supply monitoring circuit PM1 in the semiconductor integrated circuit of this embodiment. As shown in FIG. 3, in the semiconductor integrated circuit, when the power is turned on at point C and turned on, the power supply voltage PW1 rises at a predetermined slope, and at the same time, the power supply monitoring circuit PM1 starts monitoring the voltage of the power supply, and the voltage is being increased. At point D, the power supply monitoring circuit PM1 detects the operation upper limit voltage UL1. This operation upper limit voltage UL1 has a variation UB1 due to the process / temperature of the semiconductor integrated circuit, and the upper side thereof is an unstable region US1 in which the writing state to the memory cell in the nonvolatile memory is unstable.

The semiconductor integrated circuit starts the normal operation after the power supply voltage PW1 further rises and reaches the normal operation voltage TD1 at the point E, and continues the normal operation until the point F at which the power is turned off next. .

At this point F, when the power supply voltage PW1 begins to drop at a predetermined slope, the semiconductor integrated circuit causes the G
At this point, the power supply monitoring circuit PM1 detects the operation lower limit voltage LL1. This operation lower limit voltage LL1 has a variation LB1 due to the process / temperature of the semiconductor integrated circuit, and the lower side thereof is an unstable region US2 in which the writing state to the memory cell in the nonvolatile memory is unstable.

Note that DW1 is the operating voltage range from point D to point G, and BW1 is the variation LB1 due to the process / temperature during the voltage increase and the variation LB1 due to the process / temperature during the voltage decrease. It is the operating voltage range.

In such a power supply monitoring circuit PM1,
As shown in FIG. 4, at the point A, when it is detected that the power supply voltage PW1 is out of the range defined as the operable voltage and becomes the operation lower limit voltage, the read / write operation to the nonvolatile memory is performed. STOP signal ST1 indicating the prohibition period of
To the control circuit CC1 and, based on this STOP signal ST1, after the control circuit CC1 completes the write operation to the nonvolatile memory being executed at that time,
Disables read / write operations to non-volatile memory.

Next, the power supply voltage PW1 rises again,
When the power supply monitoring circuit PM1 detects that the power supply voltage PW1 is within the range defined as the operable voltage at the point B, the control circuit CC1 sets the rewriting period as described in the first embodiment. As in the case of the rewriting described above, High is input to the address storage circuit AM1 as the address / data storage circuit control signal (1) MS1 and, at the same time, High is input to the data storage circuit DM1 as the address / data storage circuit control signal (2) MS2. By inputting, the rewriting operation is automatically started. After the end of this write operation, the above-mentioned normal read / write operation is continued according to the control signals AS1, DS1, MS1, MS2 from the control circuit CC1.

[0049]

As described above, according to the present invention, when the power source is turned from the off state to the on state and rises, it is provided separately from the non-volatile memory by the access just before the power source is turned off and falls. Using the address and data stored in the address storage means and the data storage means,
The data stored in the data storage means can be rewritten to the address stored in the address storage means in the nonvolatile memory.

As the non-volatile memory, for example, RF
When using a non-volatile memory that supplies power through radio waves, such as an ID tag or contactless smart card, the power supply voltage may change momentarily depending on the state of communication, and the power supply voltage may temporarily drop and then rise again. Even in such a case, the power supply voltage state is always monitored, and based on the monitoring information, it automatically follows changes in the power supply voltage, and when the power supply starts up, the access just before the power supply is turned off. By using the address and the data stored in the address storage means and the data storage means provided separately from the non-volatile memory, the data stored in the data storage means is automatically transferred to the address stored in the address storage means with respect to the non-volatile memory. Can be rewritten manually.

For the above reasons, when the power source is turned off, even if the writing state is insufficient with respect to the reliability guaranteed for data retention, for example, "data retention period of 10 years", Can rise to a sufficient written state, and the reliability of the data stored in each memory cell of the nonvolatile memory can be greatly improved.

As a result of the above, since it becomes possible to use the memory without worrying about how to apply the power supply voltage, the convenience of the non-volatile memory is improved and the system to be used can turn on / off the power of the non-volatile memory. Since there is no need to deal with this, the circuit configuration can be simplified to a simple state.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the semiconductor integrated circuit of the same embodiment.

FIG. 3 is a timing chart showing a basic operation of the power supply monitoring circuit in the embodiment.

FIG. 4 is a timing chart showing an operation of a power supply monitoring circuit with respect to a temporal change of a power supply voltage in an RFID tag or a contactless smart card as the embodiment.

FIG. 5 is a characteristic diagram showing temporal voltage changes in a conventional semiconductor integrated circuit when power is turned off.

[Explanation of symbols]

AC1 address circuit AM1 address storage circuit AS1 address control signal CC1 control circuit DC1 data circuit DM1 data storage circuit DS1 data control signal MA1 memory array MS1 address / data storage circuit control signal (1) MS2 address / data storage circuit control signal (2) PM1 power supply monitoring circuit PW1 power supply voltage SA1 sense amplifier ST1 STOP signal

Claims (2)

[Claims] 1. A semiconductor integrated circuit having a non-volatile memory for storing data written from the outside in a memory cell corresponding to a plurality of addresses, which corresponds to the write operation and is a write target. Address storage means for storing an address of the non-volatile memory, data storage means for storing data to be written to the write target address in correspondence with the write operation, and power supply from an off state to an on state When the power supply is turned off, the nonvolatile memory is written to the address of the non-volatile memory stored in the address storage means at the time of the write operation immediately before the power supply is turned off immediately before the power supply is turned off. A semiconductor integrated circuit comprising: a control unit that controls to write the data stored in the data storage unit during operation. 2. A power supply monitoring means for monitoring the state of the power supply voltage, wherein the control means is nonvolatile when the power supply is switched from the off state to the on state based on the monitoring information on the power supply voltage from the power supply monitoring means. 2. The semiconductor integrated circuit according to claim 1, wherein the write control for the nonvolatile memory is automatically executed.