JP2012032915A - Control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable on-off control of a controlled object subjected to on-off control by a CPU via an address line without using an I/O port.SOLUTION: A first controlled object 3 is specified by a plurality of address lines B0 to B15 and is subjected to motion control. Second controlled objects 5, 7 are subjected to start-up control by start control signals of on or off. A main control unit 1 specifies the first controlled object 3 by the address lines B0 to B11 and performs motion control, and outputs the start control signals respectively to the second controlled objects 5, 7 by any of the available address lines B12 to B15 not related to the specification of the first controlled object 3 among the address lines B0 to B15 and performs start-up control of the second controlled objects 5, 7 independently.

Description

  The present invention relates to a control apparatus, for example, a printer, a copier, a facsimile machine, or a multifunction apparatus (MFP: Multi Function Peripheral) having these functions and other improvements to a control apparatus suitable for being mounted on various electronic devices.

  An electronic device such as an image forming apparatus optically reads image data from image information on a document, forms a toner image based on the image data, transfers it to a sheet, and heat-fixes the sheet to which the toner image is transferred. In addition to a printing function for printing (printing), it has various processing functions.

  In the image forming apparatus, a central processing unit (CPU) as a main control unit executes and controls these various operation functions based on programs and data stored in a memory.

  Furthermore, in the image forming apparatus, in the process of executing these functions, the CPU also controls activation of control objects such as fans and LEDs (light emitting diodes) that are activated by simple on or off signals. Yes.

  Conventionally, when controlling these fans and LEDs, it is performed using I / O (input / output) ports of a CPU or ASIC (application specific integrated circuit), but when there are many control targets, the number of I / O ports CPUs with a large number of CPUs and other dedicated CPUs for I / O need to be installed. As the number of I / O ports increases, the CPU package size tends to increase and the cost tends to increase. It has been.

  In this specification, “port” is used to mean a signal input or output terminal.

  As a patent document serving as a reference for solving such a problem, there is a gaming machine disclosed in, for example, Japanese Patent Laid-Open No. 11-290529 (Patent Document 1).

  This patent document 1 describes a main control board on which a main control unit and an information communication control unit for controlling the progress of a game are mounted, and a circuit unit and a main control board related to the operation of electrical components provided in a gaming machine. The game control board can be diverted by controlling the electrical components by transmitting information to the circuit board by the main control unit. It is possible to improve the performance and reduce the development cost and the manufacturing cost.

  In addition, a storage system disclosed in Japanese Patent Laid-Open No. 2008-71005 (Patent Document 2) has also been proposed.

  This patent document 2 proposes a configuration for effectively utilizing an empty port generated in connection with a controller or a plurality of storage device units, and is in a switch device different from a controller or a switch device having an empty port. The second free port is physically connected and logically connected through a physical path connecting the first and second free ports, and the free port is effectively used. .

  Furthermore, a control device for an electric device disclosed in Japanese Patent Laid-Open No. 2006-40782 (Patent Document 3) has also been proposed.

  In this patent document 3, in a configuration in which a drive circuit or an input port of a control circuit having different equipment depending on a model is used as an input port for setting a model, whether or not an LED display means is connected by a microcomputer is detected. / Model B is discriminated. Thereafter, program A is executed for model A, program B is executed for model B, and a port for driving the LED display means and model setting are set. It also serves as an input port.

Japanese Patent Laid-Open No. 11-290529 JP 2008-71005 A JP 2006-40782 A

  However, the above-described Patent Document 1 decodes an address signal given from a basic circuit and outputs a signal for selecting one of the I / O port units in order to increase the possibility of diversion of the game control board. Although the circuit is provided and each electrical component is controlled by the address decode circuit based on the information transmitted from the main control unit to the circuit board, the configuration is easily complicated to control a plurality of fans and LEDs. There is room for improvement.

  Further, Patent Document 2 is a configuration that makes effective use of empty ports. However, it is difficult to achieve without substantial empty ports, and, like Patent Document 1, the configuration is likely to be complicated, and there is room for further improvement. There is.

  Further, Patent Document 3 uses both a port for driving the LED display means and an input port for setting the model, but it is difficult to realize without a port dedicated for driving the LED display means or setting the model.

  Therefore, as a result of careful examination of the CPU port configuration and data output from the port, the present inventor has set, for example, 16 bits (pieces) in units of 4 bits, while the memory mounted in the image forming apparatus, for example. Focusing on the fact that there are many configurations in which only 12 bits (pieces) can be used for addressing, and not all of the address lines are used for addressing, the present invention has been completed.

  This is particularly noticeable in the address / data bus mode in which addresses and data are switched over at the same position line (bus).

  The present invention has been made to solve such a problem. Even if there is a control target that is controlled to be turned on and off by the CPU as the main control unit, the control target is turned on and off without using the I / O port in the CPU. An object of the present invention is to provide a control device that can be controlled and can easily suppress an increase in the package size and cost of the CPU.

  In order to solve such a problem, a control device according to claim 1 of the present invention includes a first control target that is controlled by a plurality of address lines and controlled for activation by an on / off activation control signal. The second control object to be operated and the first control object are designated by these address lines to control the operation, and the activation control signal is sent from the address lines that are not related to the designation of the first control object. And a main control unit that outputs to each second control target and controls activation of the second control target.

  In the control device according to claim 2 of the present invention, the main control unit outputs an activation control signal to the second control target over an operation period of the second control target, and the second control target is The operation is controlled over the output period of the activation control signal.

  The control device according to claim 3 of the present invention is configured such that the second control target includes an operation control unit that controls the operation of the second control target for a predetermined period by the activation control signal.

  In the control device according to claim 4 of the present invention, the main control unit outputs an operation stop signal for controlling the operation of the second control target to the second control target through an empty address line, and The second control target has a configuration including an operation control unit that controls the second control target to stop operation by the operation stop signal.

  In such a control device according to the first aspect of the present invention, the main control unit controls the first control object of the address lines with respect to the second control object that is activated by the activation control signal that is turned on or off. Since the activation control signal is output to the second control object by the vacant address line regardless of the designation and the second control object is activated, the control object is turned on / off without using the I / O port in the main control unit. Control is possible, and it becomes easy to suppress an increase in the package size and cost of the main control unit.

  In the control device according to claim 2 of the present invention, the main control unit outputs a start control signal during the operation period of the second control target, and the second control target outputs the start control signal. Since the operation control is performed during the period, the main control unit can arbitrarily control the activation of the operation period of the second control target.

  In the control device according to claim 3 of the present invention, the second control object has an operation control unit that controls the operation for the period by the activation control signal, so the main control unit controls the second control object. Once the activation control signal is output, the operation period activation control of the second control target is possible.

  In the control device according to claim 4 of the present invention, the main control unit outputs an operation stop signal for stopping the operation of the second control target to the second control target through an empty address line, and the second control target. Since the control target has an operation control unit for controlling the operation of the second control target by the operation stop signal, the address lines are used for functions other than the address designation during the activation of the second control target. However, the operation control period of the second control target can be arbitrarily controlled by the main control unit.

It is a schematic block diagram which shows embodiment of the control apparatus which concerns on this invention. It is a figure explaining operation | movement of the control apparatus which concerns on this invention.

  Embodiments of a control device according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic block diagram showing an embodiment of a control device according to the present invention.

  In FIG. 1, the control device of the present invention is configured to include a CPU 1 as a main control unit, a memory 3, a fan 5 and an LED 7 connected to the CPU 1, and constitutes a part of an image forming apparatus, for example. is doing.

  CPU 1 from memory 3 addressed by eg address lines B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15 forming the address bus. Functions that take in programs and various data, perform operations such as computation and control, address various electronic circuits and electronic mechanisms (not shown), control their operation, and execute and control various operation functions of the image forming apparatus And a function of executing start-up control of the fan 3 and LED lighting control in the process of executing these operation functions of the image forming apparatus.

  Although the image forming apparatus has a configuration other than the above, it is not the gist of the present invention, and thus description and illustration are omitted.

  That is, the CPU 1 has, for example, 16-bit address ports A0, A1, A22, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, AA13, A14, A15 to address lines connected thereto. The memory 3 is addressed via B0 to B11, and the above-described program and various data are input / output from the n-bit data ports D0 to Dn via the data bus D, for example, and conventionally known arithmetic and control operations It has a function to execute. Other functions of the CPU 1 will be described later.

  The CPU 1 may be configured to operate in the address / data bus mode in which the address ports A0 to A15 are switched as the data ports D0 to D15 to control the switching operation, and this is included in the present invention.

  Symbols CLK, Vcc, and GND in the CPU 1 in FIG. 1 are an input port for a high-frequency clock signal, an input port for a power supply Vcc, and a ground port as a common potential, and other ports are not shown.

  The memory 3 is a first control target including, for example, a DDR (double data rate) SRAM (synchronous dynamic random-access memory), and is controlled by the CPU 1 from the address ports A0 to A11 via the address lines B0 to B11. When the operation of the memory 3 is controlled by address designation, the above-described program and various data can be read and written via the data bus D.

  Moreover, the memory 3 has a capacity that is addressed by the address lines B0 to B11, and is not connected to the address lines B12 to B15.

  The memory 3 is not limited to the SRAM, and may be, for example, a hard disk HDD or other general storage unit, and may be any storage unit that generates empty address lines B12 to B15 among the address ports A0 to A15 of the CPU 1. good.

  The fan 5 is a second control target that is activated and controlled by an activation control signal that is turned on or off, and is a cooler that is rotated by, for example, a 5 V DC power source (not shown). It is built in and is arranged in a main body case (not shown) of the image forming apparatus.

  The operation control unit 5a of the fan 5 receives the start control signal transmitted by one empty address line B12, for example, among the empty address lines B12 to B15 that are not specified by the memory 3 among the address lines B0 to B15. 5 and a function of continuously controlling the rotation of the fan 5 during the input period of the activation control signal.

  The LED 7 is a second control target that is activated and controlled by an activation control signal that is turned on or off, and is a display that is lit by, for example, a 1.5 V DC power supply (not shown). For example, it is arranged on the operation panel of the main body case of the image forming apparatus.

  Similar to the fan 5, the operation control unit 7a of the LED 7 uses an activation control signal transmitted by one empty address line B13, for example, irrespective of the designation of the memory 3 and the activation of the fan 5 among the address lines B12 to B3. The LED 7 is turned on and activated, and has a function of continuously lighting the LED 7 during the input period of the activation control signal.

  The CPU 1 described above addresses the memory 3 by address lines B0 to B11 according to a predetermined program and controls the operation thereof, and the fan 5 needs to be rotated and the LED 7 needs to be lit according to the operation control. In this case, the activation control signals are individually output to the fan 5 and the LED 7 via the vacant address lines B12 and B13 that are not related to the addressing of the memory 3 among the address lines B0 to B15, and the activation control is performed for these. Have.

  Next, the operation of the control device according to the present invention will be briefly described with reference to FIG. 1 and FIG.

  In FIG. 2, among the address ports A0 to A15 of the CPU 1, A0 is a lower bit, A15 is an upper bit, A0 to A11 are address ports, and A12 to A15 are empty address ports.

  The CPU 1 designates the address of the memory 3 via the address ports A0 to A11 in accordance with a predetermined program, and then controls reading and writing of the program and various data via the data bus D.

  When the fan 5 needs to be rotated or started in accordance with the operation control of the CPU 1, or when the fan 5 needs to be rotated, the address port A12 is set to "1" and the fan 5 is specified to start via the address line B12. When the operation control unit 5a of the fan 5 starts to rotate the fan 5 itself and the address port A12 becomes “0”, the operation control unit 5a controls to stop the rotation.

  On the other hand, when it becomes necessary to turn on the LED 7, if the address port A13 is set to "1" and the LED 7 is addressed via the address line B13, the operation control unit 7a of the LED 7 turns on the LED 7, and the address port A13 The lighting is continuously controlled until it becomes “0”, and when the address port A3 becomes “0”, the operation control unit 7a controls the lighting to stop.

  As described above, the control device according to the present invention includes the memory (first control target) 3 that is designated and controlled by the plurality of address lines B0 to B15, and the fan 5 that is activated and controlled by the on / off activation control signal. And the LED 7 (second control target) and the address lines B0 to B15 to control the operation of the memory 3, and among these address lines B0 to B15, free address lines B12 to B15 that are not related to the specification of the memory 3 And a CPU (main control unit) 1 for controlling the activation by outputting activation control signals to the fan 5 and the LED 7 respectively, and the CPU 1 is operating during the operation period of the fan 5 and the LED 7. The startup control signal is output to the fan 5 and the LED 7, and the fan 5 and the LED 7 are controlled during the output period of the startup control signal. It is configured to be.

  For this reason, the address ports (address terminals) in the CPU 1 can be effectively used by using, for example, the higher-order bit address lines B12 to B15 for controlling the fan 5 and the LED 7, which are not used when the memory 3 is addressed. It becomes possible.

  That is, according to the present invention, it is possible to suppress an increase in the package size and cost of the CPU 1 due to an increase in the number of I / O ports by substituting an address terminal not used in the CPU 1 as an output port. However, if there are a plurality of empty address lines B12 to B15, it is possible to perform on / off control of a second control target such as a plurality of fans 5 and LEDs 7.

  In addition, since each fan 5 or LED 7 has operation control units 5a and 7a that control the operation for the period by the activation control signal, once the activation control signal is separately output from the CPU 1 to the fan 5 or LED 7. During the predetermined period, the fan 5 and the LED 7 can be controlled continuously.

  Further, if the CPU 1 is configured to output an operation stop signal to the fan 5 and the LED 7 by the address lines B12 and B13, and the operation control units 5a and 7a of the fan 5 and the LED 7 are configured to control the operation stop by the operation stop signal, Even if the address lines B12 and B13 of the CPU 1 are used for functions other than the startup control of the fan 5 and LED 7 during the startup of the fan 5 and LED 7, the CPU 1 can arbitrarily control the startup period of the operation period of the fan 5 and LED 7.

  Moreover, the address ports and address lines described above are not limited to those for addressing the memory 3, but may be those for addressing the above-described fan 5 or LED 7 that is the second control target.

  By the way, in the present invention, the first control target is not limited to the memory 3 described above, but can be implemented in an electronic circuit or an electronic mechanism that is addressed and controlled by the address lines B0 to B15.

  In addition, the second control target of the present invention is not limited to the fan 5 and the LED 7 described above, and can be implemented in an electronic circuit or an electronic mechanism that is activated and controlled by an on or off activation control signal. The on / off activation control signal may be either “1 (H)” or “0 (L)”.

  The control device of the present invention is not limited to an image forming apparatus, and the same effect can be obtained even when mounted on various electronic devices.

1 CPU (main control unit)
3 Memory (first control target)
5 Fan (second control target)
5a, 7a Operation control unit 7 LED (second control target)
A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15 Address ports B0, B1, B2, B3, B4, B5, B6, B7, B8 , B9, B10, B11, B12, B13, B14, B15 Address line D Data bus

Claims (4)

A first control target that is designated and controlled by a plurality of address lines;
A second control object that is activated by an on or off activation control signal;
The first control object is designated by the address line to control the operation, and the activation control signal is individually sent to the second control signal by an empty address line not related to the designation of the first control object among the address lines. A main control unit that outputs to the control target and activates the second control target;
A control device comprising:   The main control unit outputs the activation control signal to the second control object over an operation period of the second control object, and the second control object operates over an output period of the activation control signal. The control device according to claim 1 to be controlled.   The control device according to claim 1, wherein the second control target includes an operation control unit configured to control the operation of the second control target for a predetermined period by the activation control signal.   The main control unit outputs an operation stop signal for controlling to stop the operation of the second control target to the second control target by the empty address line, and the second control target is output by the operation stop signal. The control device according to claim 3, further comprising the operation control unit configured to stop operation of the second control target.

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