JP2012032290A - Semiconductor integrated circuit and inspection method of circuit to be inspected - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute inspection in plural times on a circuit to be inspected without requiring a long time in a semiconductor integrated circuit having a BIST circuit and also to enable an individual recognition of inspection result of each time.SOLUTION: An inspection result storage circuit 8 is prepared, which is configured so that the inspection results of a circuit to be inspected, like a memory macro 1, can be stored in plural numbers. The inspection result storage circuit 8 makes signals BIST_GO and BIST_DONE to be the inputs, which are output from a BIST control circuit 7, and stores the inspection result showing by the signal BIST_GO each time the signal BIST_DONE shows the end of inspection when a mode changeover signal BIST_MODE shows an inspection mode. When the mode changeover signal BIST_MODE shows a result readout mode, the inspection result storage circuit 8 outputs the inspection result being stored.

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a function of inspecting a circuit under test such as a memory or a logic circuit using a self-test circuit (BIST (Built-In Self Test) circuit).

  With the recent miniaturization of processes, various failure modes that have not existed in the past have appeared in memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). For this reason, in order to maintain the quality of the memory, a corresponding inspection pattern and inspection time are required.

  In particular, in some failure modes, it takes a long time to detect a failure. Therefore, verification for a long time is required for developing a screening test for the failure mode, and the inspection time is greatly increased. For this reason, how to perform efficient verification and shorten the verification period, and how to reduce the inspection cost by setting reasonable inspection time and inspection conditions have become major issues.

  In this failure mode verification, a large number of memories are operated repeatedly for a long time, and information such as how long or how often each memory fails is obtained, and then quality standards, yields, and inspections are obtained. In view of cost and the like, it is necessary to appropriately set screening test conditions.

  Conventionally, verification and inspection of such failure modes have been performed using a memory tester. However, since the number of measurements is limited, a long verification time and inspection time are required. As a means for reducing the verification time and the inspection time, a method of increasing the number of measurements using a wafer level burn-in apparatus can be considered. However, since the wafer level burn-in apparatus itself cannot generate a complex pattern, in this case, inspection by a self-inspection circuit (BIST circuit) built in the chip is required.

  However, the normal BIST circuit performs an inspection of an inspection object such as a DRAM only once, outputs the pass / fail result, and stops. For this reason, in order to utilize the wafer level burn-in apparatus, it is necessary to separately provide a method for repeatedly inspecting the BIST circuit and performing a plurality of inspections.

  For example, Patent Document 1 discloses an example in which repeated inspection is realized by detecting an inspection end signal of a BIST circuit and automatically generating a BIST restart signal inside the chip as a repeated inspection method using a BIST circuit. Has been.

Japanese Patent No. 3788983

  However, in the technique disclosed in Patent Document 1 described above, once a failure occurs, the information is retained until the inspection is completed a plurality of times, so how many times the inspection has failed or how many times it has failed. There is a problem that individual test results cannot be recognized.

  A method of inputting a BIST activation signal from the wafer level burn-in apparatus a plurality of times and reading out the inspection result each time is also conceivable. However, the wafer level burn-in device cannot determine the inspection results of a large number of wafer level chips at the same time due to hardware restrictions (the number of channels for determining the inspection results is small). It is necessary to judge. For this reason, it takes a considerable time (about several tens of minutes depending on the number of chips) to determine only one inspection result. In addition, if the inspection is repeated thousands and tens of thousands of times, the determination time becomes enormous, resulting in a demerit that the verification period and inspection time are long.

  The problem described above is not limited to the case where the circuit to be inspected is a memory. For example, the same problem occurs even when the logic circuit is a circuit to be inspected.

  In view of the above problems, the present invention allows a semiconductor integrated circuit having a BIST circuit to perform a plurality of inspections on a circuit under test without requiring a long time and to individually recognize each inspection result. The purpose is to.

  One embodiment of the present invention controls the execution of a test of a circuit under test as a semiconductor integrated circuit, and indicates a first signal indicating a test result of the circuit under test and a test end of the circuit under test. A BIST (Built-In Self Test) control circuit that outputs a second signal, the first and second signals, and a mode switching signal indicating an inspection mode or a result reading mode are input, and a plurality of inspection results are input. A test result storage circuit configured to be capable of storing each of the test results, the test result storage circuit, when the mode switching signal indicates a test mode, each time the second signal indicates the end of the test. While the test result indicated by the signal is stored, when the mode switching signal indicates the result read mode, the stored test result is output.

  According to this aspect, the semiconductor integrated circuit is provided with the inspection result storage circuit configured to be capable of storing a plurality of inspection results of the circuit to be inspected. When the mode switching signal indicates the inspection mode, the inspection result storage circuit indicates the inspection result indicated by the first signal output from the BIST control circuit, and the second signal output from the BIST control circuit indicates the end of inspection. Store every time. As a result, the inspection result storage circuit stores a plurality of inspection results in the inspection mode. When the mode switching signal indicates the result reading mode, the inspection result storage circuit outputs the stored inspection result. That is, after completion of a plurality of inspections in the inspection mode, each inspection result is read at a time in the result reading mode. Thereby, the determination time of the inspection result can be greatly reduced, and the individual inspection result can be recognized. Therefore, verification can be performed efficiently and appropriate inspection conditions can be set.

  The inspection result storage circuit is preferably realized by a scan register chain for a scan test or a boundary scan test of a logic circuit.

  According to this configuration, since the test result storage circuit is also used as the scan register chain, it is not necessary to add a test result storage circuit separately, so that the circuit area can be reduced.

  The semiconductor integrated circuit according to the aspect preferably includes a transfer control circuit that generates the mode switching signal.

  Furthermore, the transfer control circuit receives the second signal, and counts the number of times the second signal has reached a logic level indicating the end of the inspection, and the count value of the counter unit is set to a predetermined value. It is preferable to include a latch unit that changes the mode switching signal to a logic level indicating the result reading mode.

  According to this configuration, when the inspection in the inspection mode reaches a predetermined number of times, the storage of the inspection result in the inspection result storage circuit can be stopped by changing the logic level of the mode switching signal.

  Furthermore, it is preferable that the transfer control circuit is configured such that the predetermined value can be set from the outside.

  According to this configuration, the number of inspection results stored in the inspection result storage circuit can be arbitrarily set from the outside.

  Another aspect of the present invention is a semiconductor integrated circuit including a BIST (Built-In Self Test) control circuit and a test result storage circuit configured to be capable of storing a plurality of test results. As a method of performing the inspection, a step of setting the semiconductor integrated circuit to an inspection mode by a mode switching signal, and in the inspection mode, the BIST control circuit inspects the circuit to be inspected, and the inspection result is used for the inspection. The operation of storing the result in the result storage circuit is repeatedly executed a plurality of times, the step of setting the semiconductor integrated circuit in the result read mode by the mode switching signal, and the test result storage circuit in the result read mode, Outputting a plurality of stored test results to the outside of the semiconductor integrated circuit.

  According to this aspect, the semiconductor integrated circuit is provided with the inspection result storage circuit configured to be capable of storing a plurality of inspection results of the circuit to be inspected. When the inspection mode is set by the mode switching signal, the BIST control circuit repeatedly inspects the circuit to be inspected a plurality of times, and the inspection result is stored in the inspection result storage circuit. That is, the inspection result storage circuit stores a plurality of inspection results in the inspection mode. When the result reading mode is set by the mode switching signal, the inspection result storage circuit outputs a plurality of stored inspection results to the outside of the semiconductor integrated circuit. That is, after completion of a plurality of inspections in the inspection mode, each inspection result is read at a time in the result reading mode. Thereby, the determination time of the inspection result can be greatly reduced, and the individual inspection result can be recognized. Therefore, verification can be performed efficiently and appropriate inspection conditions can be set.

  According to the present invention, a test result storage circuit configured to be capable of storing a plurality of test results of a circuit to be tested is provided in the semiconductor integrated circuit, and after completion of a plurality of tests in the test mode, the test results are stored in the result reading mode. A plurality of inspection results are read out at a time from the result storage circuit. Accordingly, since the inspection can be performed using a wafer level burn-in apparatus capable of measuring a large number of devices at the same time, the device verification period can be greatly shortened and appropriate inspection conditions can be set.

1 is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit according to a first embodiment. 3 is a flowchart illustrating an inspection method using the semiconductor integrated circuit according to the first embodiment. FIG. 2 is a circuit diagram illustrating a specific configuration example of an inspection result storage circuit in FIG. 1. 3 is a timing chart illustrating an operation example of the semiconductor integrated circuit according to the first embodiment. FIG. 6 is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit according to a second embodiment. FIG. 6 is a circuit diagram illustrating a specific configuration example of a transfer control circuit in FIG. 5. 6 is a timing chart illustrating an operation example of the semiconductor integrated circuit according to the second embodiment. FIG. 6 is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit according to a third embodiment. It is a circuit diagram which shows the specific structural example of the test result storage circuit in FIG. FIG. 9 is a circuit diagram illustrating a specific configuration example of a transfer control circuit in FIG. 8. 10 is a timing chart illustrating an operation example of the semiconductor integrated circuit according to the third embodiment. FIG. 6 is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit according to a fourth embodiment. FIG. 13 is a circuit diagram illustrating a specific configuration example of a logic circuit unit including a test result storage circuit in FIG. 12. 10 is a timing chart illustrating an operation example of the semiconductor integrated circuit according to the fourth embodiment. FIG. 10 is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit according to a fifth embodiment. FIG. 10 is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit according to a sixth embodiment. It is a figure which shows the structural example of TAP in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit having a BIST circuit according to the first embodiment. A BIST circuit 10 shown in FIG. 1 is a circuit for inspecting a memory macro 1 which is an example of a memory as a circuit to be inspected. In the BIST circuit 10, 3 is a signal generator that generates a control signal to be output to the memory macro 1, 4 is an address generator that generates an address signal to be output to the memory macro 1, and 5 is a data signal to be output to the memory macro 1. A data generator 6 is a comparator that compares a read data signal input from the memory macro 1 with an expected value signal generated by the BIST circuit 10, and 7 controls the operation of the BIST circuit 10 and executes a test of the memory macro 1. A BIST control circuit 8 controls the inspection result storage circuit 8 for storing the inspection result of the memory macro 1. The inspection result storage circuit 8 is configured to be able to store a plurality of inspection results.

  The BIST control circuit 7 outputs signals BIST_GO and BIST_DONE. BIST_GO is a signal (first signal) indicating the inspection result of the memory macro 1, and BIST_DONE is a signal (second signal) indicating the end of the inspection of the memory macro 1. The signals BIST_GO and BIST_DONE are both output to the outside of the BIST circuit 10 and input to the inspection result storage circuit 8. BIST_CLK is a clock signal for the BIST circuit 10, BIST_EN is a signal for starting the BIST circuit 10, SCLK is a clock signal applied to the inspection result storage circuit 8, SI is a data signal input to the inspection result storage circuit 8, and SO is This is a data signal output from the inspection result storage circuit 8.

  BIST_MODE is a mode switching signal for switching the operation mode of the BIST circuit 10. Specifically, the mode switching signal BIST_MODE indicates an inspection mode in which the inspection of the memory macro 1 is repeated a plurality of times, or a result reading mode in which a plurality of inspection results are output to the outside. The mode switching signal BIST_MODE is given to the inspection result storage circuit 8. When the mode switching signal BIST_MODE indicates the inspection mode, the inspection result storage circuit 8 stores the inspection result indicated by the signal BIST_GO every time the signal BIST_DONE indicates the end of inspection, while the mode switching signal BIST_MODE indicates the result reading mode. If so, the stored test results are output. In this embodiment, it is assumed that the mode switching signal BIST_MODE is supplied from the outside of the semiconductor integrated circuit, and the semiconductor integrated circuit includes an external terminal to which the mode switching signal BIST_MODE is supplied.

  FIG. 2 is a flowchart showing an outline of the inspection method using the semiconductor integrated circuit according to the present embodiment. First, the semiconductor integrated circuit is set to the inspection mode by the mode switching signal BIST_MODE (step S1). In the inspection mode, the BIST control circuit 7 performs the operation of inspecting the memory macro 1 after setting the inspection pattern and storing the inspection result in the inspection result storage circuit 8. This operation is repeatedly executed in the inspection mode (steps S2 to S5). Then, the semiconductor integrated circuit is set to the result read mode by the mode switching signal BIST_MODE (step S5). In this result read mode, the test result storage circuit 8 outputs the stored test result to the outside of the semiconductor integrated circuit. (Step S6).

  In the following description, it is assumed that the signal BIST_GO indicates the inspection result of the memory macro 1 by its logic level, and the signal BIST_DONE indicates the end of the inspection of the memory macro 1 by its logic level. Specifically, when the signal BIST_GO is at “H” level, a pass is indicated, and when the signal BIST_GO is at “L” level, a failure is indicated, and when the signal BIST_DONE becomes “H” level, an inspection end is indicated. The mode switching signal BIST_MODE indicates the operation mode according to its logic level. When the signal is “L” level, the inspection mode is indicated. When it is “H” level, the result reading mode is indicated. Note that the relationship between the logic level of a signal and the information that it means is not limited to this.

  FIG. 3 is a circuit diagram showing a specific configuration example of the inspection result storage circuit 8. Note that the circuit configuration shown in FIG. 3 can store three test results, but a configuration that can store other numbers of test results can also be realized as in FIG.

  In FIG. 3, 81a and 81b are first and second selectors, and 82a to 82d are D-FFs (flip-flops). The D-FFs 82a to 82d are serially connected and constitute a so-called four-stage shift register 82. Note that the shift register may be configured using another clock synchronous latch circuit instead of the D-FF.

  Signals BIST_GO and SI are respectively applied to the input terminals A and B of the first selector 81a, and one of the signals BIST_GO and SI is output from the output terminal Y in accordance with the mode switching signal BIST_MODE applied to the S terminal. Selected as. When the mode switching signal BIST_MODE is “L” (inspection mode), the signal BIST_GO is selected and output, while when it is “H” (result reading mode), the signal SI as the third signal is selectively output. Similarly, signals BIST_DONE and SCLK are respectively applied to the input terminals A and B of the second selector 81b, and one of the signals BIST_DONE and SCLK is output from the output terminal Y in accordance with the mode switching signal BIST_MODE applied to the S terminal. Signal RCLK. When the mode switching signal BIST_MODE is “L” (inspection mode), the signal BIST_DONE is selected and output, while when it is “H” (result reading mode), the signal SCLK as the fourth signal is selectively output.

  The output of the first selector 81a, ie, the signal RDAT, is given to the data input of the leading D-FF 82a of the shift register 82, and the output of the second selector 81b, ie, the signal RCLK, is supplied to each D-FF 82a-82d of the shift register 82. To the clock input. The data output QR0 of the D-FF 82a is supplied to the data input of the D-FF 82b, the data output QR1 of the D-FF 82b is supplied to the data input of the D-FF 82c, and the data output QR2 of the D-FF 82c is the data input of the D-FF 82d. Given to. The data output of the D-FF 82d is output from the terminal SO.

  That is, the shift register 82 is configured to sample and sequentially shift the data signal RDAT in synchronization with the rising edge of the clock signal RCLK. In the inspection mode, the signal BIST_GO is sequentially stored in the shift register 82 with the signal BIST_DONE as the clock signal RCLK. In the result read mode, the signals stored in the shift register 82 are sequentially output using the signal SCLK as the clock signal RCLK.

  FIG. 4 is a timing chart showing an operation example of the semiconductor integrated circuit according to the present embodiment. First, in the inspection mode, the BIST circuit 10 is activated at time t0 and the inspection of the memory macro 1 is started. At this time, the signal BIST_DONE is “L” which is an initial value. At time t1, when the first test of the memory macro 1 is completed, the signal BIST_DONE becomes “H” indicating the end of the test. Also, the BIST control circuit 7 compares the data read from the memory macro 1 with the expected value data one by one. When they match, “H” indicating “pass”, and when they do not match, “fail”. L ″ is output as the signal BIST_GO. This signal BIST_GO is stored in the inspection result storage circuit 8. Here, the BIST control circuit 7 has a function of fixing “L” until the next activation of the BIST circuit 10, that is, holding the fail result once “fail” is detected during the inspection. Therefore, if the signal BIST_GO when the signal BIST_DONE becomes “H” is sampled, it is possible to leave information as to whether the inspection at that time was “pass” or “fail”.

  Subsequently, when the BIST circuit 10 is started again at time t2, the signal BIST_DONE becomes “L” again, and at the same time, the signal BIST_GO, that is, the first inspection result is reset and becomes the initial value “H” again. In this way, the BIST circuit 10 is repeatedly activated to perform inspection n times, and the inspection results for n times are stored in the inspection result storage circuit 8.

  At time t3, the mode switching signal BIST_MODE is shifted from “L” to “H”, and the mode shifts to the result reading mode in which the n stored test results are read. Here, by inputting the read clock signal SCLK to the BIST circuit 10 from the outside n times, the inspection results from the first time to the nth time can be sequentially read out serially from the SO terminal.

  As described above, according to the present embodiment, the test results of each time are stored in the test result storage circuit 8 provided in the semiconductor integrated circuit, and the test results can be read at a time after a series of test sequences are completed. For this reason, the determination time of the inspection result can be greatly reduced, and the individual inspection result can be recognized. Therefore, for example, it is possible to greatly reduce the inspection result read time when using a wafer level burn-in apparatus.

(Embodiment 2)
FIG. 5 is a block diagram showing a schematic configuration of a semiconductor integrated circuit having a BIST circuit according to the second embodiment. The configuration of FIG. 5 is substantially the same as the configuration of FIG. 1 except that a transfer control circuit 21 that generates a mode switching signal BIST_MODE is newly added. That is, in the first embodiment, the mode switching signal BIST_MODE is supplied from the outside. In the present embodiment, the transfer control circuit 21 receives the signal BIST_DONE and generates the mode switching signal BIST_MODE. In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof is omitted here.

  FIG. 6 is a circuit diagram showing a specific configuration example of the transfer control circuit 21. In FIG. 6, 91a to 91c are D-FFs, 92 is an AND circuit, 93 is a NOR circuit, and 94a and 94b are inverter circuits. A D-FF 91a, 91b constitutes a 2-bit counter unit 21a, and a D-FF 91c, a NOR circuit 93, and inverters 94a, 94b constitute a latch unit 21b. The counter circuit 21a counts the number of “H” of the signal BIST_DONE, and when the counter value reaches the maximum value (“3” in this case), the latch unit 21b changes the mode switching signal BIST_MODE from “L” to “H”. And hold.

  The signal BIST_DONE is given to the clock input of the D-FF 91a and the input terminal of the inverter circuit 94b, the inverted output of the D-FF 91a is given to the data input of the D-FF 91a and the clock input of the D-FF 91b, and the inverted output of the D-FF 91b. Is given to the data input of the D-FF 91b. The output QC0 of the D-FF 91a and the output QC1 of the D-FF 91b are input to the input terminal of the AND circuit 92, respectively.

  The NOR circuit 93 receives the output signal A0 of the AND circuit 92 and the output QL0 of the D-FF 91c, and outputs a signal N0. Inverter circuit 94a receives signal N0 and outputs signal I0. In the D-FF 91c, the signal I0 is supplied to the data input, the output signal I1 of the inverter circuit 94b is supplied to the clock input, and the signal QL0 is output. This signal QL0 is output as the mode switching signal BIST_MODE.

  FIG. 7 is a timing chart showing an operation example of the semiconductor integrated circuit according to the present embodiment. Here, it is assumed that the inspection result storage circuit 8 has the configuration shown in FIG. 3, and the transfer control circuit 21 has the configuration shown in FIG. It is assumed that the initial value of the output Q of each D-FF is “L” by reset.

  At time t0, the inspection mode is started. The inspection of the memory macro 1 is performed four times, and the signal BIST_DONE is changed to “H” four times (time t4, t8, t12, t16). In the transfer control circuit 21, the counter unit 21a counts the signal BIST_DONE, and the counter outputs QC0 and QC1 are (L, L) at time t0, (H, L) at time t4, and at time t8 ( L, H) and (H, H) are sequentially counted up at time t12. At time t12, the output A0 of the AND circuit 92 that receives the counter outputs QC0 and QC1 changes from “L” to “H”.

  On the other hand, the output QL0 (mode switching signal BIST_MODE) of the D-FF 91c has an initial value “L” at time t0, and the initial value of the output A0 of the AND circuit 92 is the initial value of the counter outputs QC0 and QC1 (L , L), it is “L”. Therefore, the initial value of the output N0 of the NOR circuit 93 is “H”, and the initial value of the output I0 of the inverter 94a is “L”.

  As described above, since the output A0 of the AND circuit 92 is “L” until time t12, the mode switching signal BIST_MODE holds “L”, but at time t12 when the counter value reaches the maximum value “3”. The output A0 of the AND circuit 92 transits from “L” to “H”. At time t13, this “H” is latched by the D-FF 91c at the rising edge of the inverted signal I1 of the signal BIST_DONE, and the mode switching signal BIST_MODE changes to “H”. Then, since “H” is given to the input of the NOR circuit 93, the output N0 of the NOR circuit 93 becomes “L” regardless of the logic level of the output A0 of the AND circuit 92, and the inverted signal I0 is Becomes “H”. Accordingly, since the data input of the D-FF 91c is always “H”, the mode switching signal BIST_MODE, which is the output thereof, also maintains “H”.

  In this way, the transfer control circuit 21 counts the signal signal BIST_DONE “H”, and when the count number reaches the maximum value (here, “3”), the mode switching signal BIST_MODE is set to “H” and the state is changed. Hold. Therefore, after time t16, even if the output A0 of the AND circuit 92 becomes “L” again, the mode switching signal BIST_MODE maintains “H”. That is, the mode can be automatically switched when the number of inspections reaches a preset number by the operation of the transfer control circuit 21.

  Until time t13, since the mode switching signal BIST_MODE is “L”, the test result storage circuit 8 selects the signal BIST_GO as the signal RDAT and the signal BIST_DONE as the signal RCLK.

  In FIG. 7, the signal BIST_GO transits to “L” at time t <b> 2, indicating that “fail” has occurred in the first inspection. Next, it is “H” at times t5 to t8, indicating that the second inspection was “pass”. Next, at time t9 to t12, transition to “L” at time t11 indicates that “fail” has occurred in the third inspection. Similarly, the fourth inspection is “pass”. A signal RDAT indicating such a transition is sequentially taken into the shift register 82 in accordance with the clock signal RCLK.

  Since the input (signal RDAT) of the D-FF 82a is “L” at the rising edge of the signal RCLK at time t4, the output QR0 is “L”. Next, at time t8, since the signal RDAT is “H”, QR0 transits to “H”. Next, at time t12, since the signal RDAT is “L”, the output QR0 transits to “L”. The input of the D-FF 82b is the output QR0 of the D-FF 82a, but it is "L" at times t4 and t8, so the output QR1 remains "L", and QR0 is "H" at time t12. Therefore, the output QR1 changes to “H”. The output QR2 of the D-FF 82c remains “L” at time t4, t8, and t12 because QR1 is “L”. Therefore, the output SO of the D-FF 82d that receives QR2 also remains “L”.

  Therefore, at the time t13 when the inspection is completed three times, the outputs QR0, QR1, QR2, and SO of the D-FFs 82a to 82d of the shift register 82 are set to “L”, “H”, “L”, and “L”, respectively. It has become.

  Next, at time t13, the mode switching signal BIST_MODE becomes “H”, so that the test mode is shifted to the result reading mode. At this time, since the mode switching signal BIST_MODE is “H”, the test result storage circuit 8 selects the signal SI as the signal RDAT and the signal SCLK as the signal RCLK.

  Accordingly, at the rising edge of the signal SCLK at time t20, that is, the signal RCLK, the output QR0 of the D-FF 82a is “L” because the input is “L” of the signal SI, that is, the signal RDAT. Since the signal SI is fixed at “L”, the output QR0 remains “L” even at the rising edge of the signal RCLK at times t22 and t24.

  On the other hand, the output QR1 of the D-FF 82b is “H” as described above until time t20, but takes in “L” of QR0 at time t20 and transitions to “L”. Thereafter, “L” of QR0 is taken in, and QR1 also maintains “L”.

  The output QR2 of the D-FF 82c is “L” as described above until time t20, but takes in “H” of QR1 at time t20 and transitions to “H”. At time t22, “L” of QR1 is fetched, and thereafter, QR2 also maintains “L”.

  The output of the D-FF 82d, that is, SO is “L” as described above until time t20. However, at time t20, “L” of QR2 is taken in and maintained at “L”. At time t22, QR2 “H” is captured, and SO transitions to “H”. At time t24, QR2 “L” is captured, and SO transitions to “L”.

  As described above, the inspection result serial read terminal SO outputs “L” for the first clock of the signal SCLK, “H” for the second clock, and “L” for the third clock. Thus, it can be seen that the first inspection was “Fail”, the second inspection was “Pass”, and the third inspection was “Fail”.

  As described above, in the inspection mode, the signal BIST_GO indicating the inspection result is supplied to the shift register 82 of the inspection result storage circuit 8 as the data input, and the signal BIST_DONE indicating the end of the inspection is supplied as the clock input. Is stored. Thereafter, the level of the mode switching signal BIST_MODE is changed to switch the data input of the shift register 82 to the signal SI and the clock input to the signal SCLK. Thereby, in a result reading mode, a series of test results can be read from the output terminal SO at a time.

(Embodiment 3)
FIG. 8 is a block diagram showing a schematic configuration of a semiconductor integrated circuit having a BIST circuit according to the third embodiment. The configuration of FIG. 8 is almost the same as the configuration of FIG. 5, but the configuration of the transfer control circuit 35 is different. That is, in the second embodiment, the transfer control circuit 21 has a fixed value (“3” in FIG. 6) that is compared with the counter value obtained by counting the number of times that the signal BIST_DONE has become “H”. On the other hand, in the present embodiment, the transfer control circuit 35 is configured such that a predetermined value for switching the logic level of the mode switching signal BIST_MODE can be set from the outside by the signal DATA. The inspection result storage circuit 31 is basically the same as the inspection result storage circuit 8 shown in the first and second embodiments, but the number of inspection results that can be stored is different.

  FIG. 9 is a circuit diagram showing a specific configuration example of the inspection result storage circuit 31. In FIG. 9, 33a and 33b are first and second selectors, and 34a to 34f are D-FFs. The D-FFs 34a to 34f are serially connected and constitute a so-called six-stage shift register 34. Note that the shift register may be configured using another clock synchronous latch circuit instead of the D-FF. Note that the difference from the configuration of FIG. 3 is only the number of stages of the shift register 34, and therefore detailed description thereof is omitted here.

  FIG. 10 is a circuit diagram showing a specific configuration example of the transfer control circuit 35. In FIG. 10, 191a to 191g are D-FFs, 192 is an AND circuit, 193 is a NOR circuit, 194a and 194b are inverter circuits, and 195a to 195c are EXNOR circuits. The D-FFs 191a to 191c constitute a 3-bit counter unit 35a, and the D-FFs 191d to 191f constitute a shift register unit 35b that sets a predetermined value for comparison with the count value of the counter unit 35a. The D-FF 191g, the NOR circuit 193, and the inverters 194a and 194b constitute a latch unit 35c. The counter circuit 35a counts the number of “H” of the signal BIST_DONE, and when the counter value reaches a predetermined value set in the shift register 35b, the latch unit 35c changes the mode switching signal BIST_MODE from “L” to “H”. And hold.

  The signal BIST_DONE is given to the clock input of the D-FF 191a and the input terminal of the inverter circuit 194b, the inverted output of the D-FF 191a is given to the data input of the D-FF 191a and the clock input of the D-FF 191b, and the inverted output of the D-FF 191b. Is applied to the data input of the D-FF 191b and the clock input of the D-FF 191c, and the inverted output of the D-FF 191c is applied to the data input of the D-FF 191c. In this way, the D-FFs 191a to 191c constitute a 3-bit counter unit 35a.

  On the other hand, the signal DATA is given to the data input of the D-FF 191d, the output QS0 of the D-FF 191d is given to the data input of the D-FF 191e, and the output QS1 of the D-FF 191e is given to the data input of the D-FF 191f. A signal SCLK is given to each of the clock inputs of the D-FFs 191d to 191f. In this way, the D-FFs 191d to 191f constitute a three-stage shift register unit 35b.

  The EXNOR circuit 195a receives the output QC0 of the D-FF 191a and the output QS0 of the D-FF 191d, and outputs a signal EN0. The EXNOR circuit 195b receives the output QC1 of the D-FF 191b and the output QS1 of the D-FF 191e, and outputs a signal EN1. The EXNOR circuit 195c receives the output QC2 of the D-FF 191c and the output QS2 of the D-FF 191f, and outputs a signal EN2.

  The AND circuit 192 receives the signals EN0 to EN2 output from the EXNOR circuits 195a to 195c, respectively, and outputs a signal A0.

  In the latch unit 35c, the NOR circuit 193 receives the output A0 of the AND circuit 192 and the output QL0 of the D-FF 191g, and outputs a signal N0. The inverter circuit 194a receives the output N0 of the NOR circuit 193 and outputs a signal I0. In the D-FF 191g, the output I0 of the inverter circuit 194a is supplied to the data input, the output I1 of the inverter circuit 194b is supplied to the clock input, and the signal QL0 is output. This signal QL0 is output from the transfer control circuit 35 as the mode switching signal BIST_MODE.

  That is, in the transfer control circuit 35, the counter unit 35a configured by the D-FFs 191a to 191c counts the number “H” of the signal BIST_DONE. On the other hand, the signal DATA is transferred to the shift register unit 35b constituted by the D-FFs 191d to 191f. Then, the outputs QC0 to QC2 of the D-FFs 191a to 191c of the counter unit 35a are compared with the outputs QS0 to QS2 of the D-FFs 191d to 191f of the shift register unit 35b, and when all match, the latch unit 35c switches the mode. The signal BIST_MODE is changed from “L” to “H” and held.

  FIG. 11 is a timing chart showing an operation example of the semiconductor integrated circuit according to the present embodiment. Here, it is assumed that the inspection result storage circuit 31 has the configuration of FIG. 9, and the transfer control circuit 35 has the configuration of FIG. Times t0 to t6 are a transfer count setting mode for setting how many test results are transferred to the test result storage circuit 31, times t6 to t27 are a test mode, and times t27 to t44 are a result read mode.

  In the transfer count setting mode, the shift register unit 35b of the transfer control circuit 35 sequentially shifts the data input as the signal DATA according to the signal SCLK. The number of test results stored can be controlled by the data set in the shift register unit 35b. The signal DATA is “H” at time t0, “L” at time t2, and “H” at time t4. This data is sequentially taken into the shift register unit 35b by the three clocks of the signal SCLK, and at time t5, QS0 to QS2 become “H” “L” “H”. These QS0 to QS2 represent 3-bit binary data, which is “5” in the decimal system. That is, in this example, the number of inspection results to be stored is set to “5”.

  In the inspection mode, the counter unit 35a of the transfer control circuit 35 counts the signal BIST_DONE. The counter outputs QC0 to QC2 start at “L”, “L”, and “L” at the time t6 at the start of inspection, and at time t26 when the signal BIST_DONE is counted five times, “H”, “L”, “H”, Decimal number “5”.

  The EXNOR circuit is a circuit that outputs “H” when two inputs coincide with each other. That is, at time t26, the outputs QC0 to QC2 of the counter unit 35a and the outputs QS0 to QS2 of the shift register unit 35b coincide with each other at “H”, “L”, and “H”, so that the outputs of the EXNOR circuits 195a, 195b, and 195c All become “H”. Then, the output A0 of the AND circuit 192 becomes “H”, and this “H” is held by the latch unit 35c as described in the second embodiment. That is, the mode switching signal BIST_MODE becomes “H” after the time t27 when the signal I1, which is the clock input of the D-FF 191g, rises, and shifts to the inspection reading mode. Here, since the sixth inspection is performed after the mode switching signal BIST_MODE is switched to “H”, the inspection result is not stored.

  Note that the method of holding and reading the inspection result is the same as that described in detail in the second embodiment, and thus the description thereof is omitted here.

  As described above, according to the present embodiment, the transfer control circuit 35 can arbitrarily set the number of times of inspection result storage by the signal DATA given from the outside.

(Embodiment 4)
FIG. 12 is a block diagram showing a schematic configuration of a semiconductor integrated circuit having a BIST circuit according to the fourth embodiment. In contrast to the configuration of FIG. 5, the test result storage circuit 50 is configured outside the BIST circuit 40, and the test result storage circuit 50 is scanned in the logic circuit unit 45 for scan testing of the logic circuits 41 and 42. The difference is realized by the register chain.

  Here, the scan test is one of test facilitating methods and detects a failure of a logic circuit. Specifically, flip-flops in the circuit are serially connected to form a shift register, that is, a scan register chain. Then, data is input from the external terminal to the scan register chain, the logic circuit is operated by the data, the operation result data is again taken into the scan register chain, and is output from the external terminal. The output operation result data and the expected value data are compared to determine the presence or absence of a failure in the logic circuit.

  As shown in FIG. 12, when compared with the inspection result storage circuit 8 of FIG. 5, the inspection result storage circuit 50 is added with a scan enable signal SE, a scan mode signal SCAN, and a capture clock CCLK as inputs. Yes.

  FIG. 13 is a circuit diagram showing a specific configuration example of the logic circuit unit 45. However, in FIG. 13, the detailed circuit configuration of the inspection result storage circuit 50 is shown, but the detailed circuit configuration of the logic circuits 41 and 42 is omitted.

  The inspection result storage circuit 50 in FIG. 13 has the same function as the inspection storage circuit 8 in FIG. 3 with respect to the BIST inspection operation. However, it has the following differences so that it can be operated for a scan test. That is, the select inputs of the first and second selectors 52a and 52b receive the output signal of the OR circuit 51 that receives the scan mode signal SCAN and the mode switching signal BIST_MODE. In addition, selectors 52c to 52f for exchanging data with the logic circuits 41 and 42 are inserted in front of the D-FFs 53a to 53d constituting the four-stage shift register, respectively. Furthermore, the output DCLK of the selector 52g that selectively outputs the signal RCLK or the capture clock signal CCLK is given to the clock input of the D-FF 53d. A signal SE is given to the S inputs of the selectors 52c to 52g.

  The output signal of the logic circuit 42 is given to the A input of the selector 52c, and the output signal RDAT of the selector 52a is given to the B input. The selector 52c outputs the signal RDAT when the signal SE is “H”, and outputs the output signal of the logic circuit 42 when the signal SE is “L”. This output is given to the data input of the D-FF 53a.

  The output signal of the logic circuit 42 is given to the A input of the selector 52d, and the output QR0 of the D-FF 53a is given to the B input. The selector 52d outputs the output QR0 when the signal SE is “H”, and outputs the output signal of the logic circuit 42 when the signal SE is “L”. This output is given to the data input of the D-FF 53b.

  The output signal of the logic circuit 42 is given to the A input of the selector 52e, and the output QR1 of the D-FF 53b is given to the B input. The selector 52e outputs the output QR1 when the signal SE is “H”, and outputs the output signal from the logic circuit 42 when the signal SE is “L”. This output is given to the data input of the D-FF 53c.

  The output A1 of the AND circuit 41a of the logic circuit 41 is given to the A input of the selector 52f, and the output QR2 of the D-FF 53c is given to the B input. The AND circuit 41a receives the output QR0 of the D-FF 53a and the output QR1 of the D-FF 53b as inputs. The selector 52f outputs the output QR2 when the signal SE is “H”, and outputs the output A1 when it is “L”. This output is given to the data input of the D-FF 53d.

  The signal CCLK is given to the A input of the selector 52g, and the signal RCLK is given to the B input. As the output DCLK, the selector 52g outputs a signal RCLK when the signal SE is “H”, and outputs a signal CCLK signal when the signal SE is “L”. This output DCLK is given to the clock input of the D-FF 53d. The output of the D-FF 53d is output as the signal SO.

  FIG. 14 is a timing chart showing an operation example of the semiconductor integrated circuit according to the present embodiment. FIG. 14 shows a state of switching from the scan test to the inspection of the memory macro 1 by the BIST circuit. The time t0 to t20 is the scan test mode, and the signal SCAN for controlling the execution of the scan test is “H” during this period. Time t20 to t33 is an inspection mode, time t33 to t46 is a result reading mode, and the signal SCAN is “L” that invalidates the scan test.

  When the signal SCAN is “H”, that is, in the scan mode, in the test result storage circuit 50, the first selector 52a selectively outputs the signal SI as the signal RDAT, and the second selector 52b selectively outputs the signal SCLK as the signal RCLK. . That is, the signal SI is input to a shift register constituted by the D-FFs 53a to 53d.

  The signal SE is a signal for switching between a scan-in / scan-out operation and a capture operation in the scan mode. When the signal SE is “H”, the inspection result storage circuit 50 is in a scan-in operation mode in which data is serially input from the SI terminal or a scan-out operation mode in which data is serially output from the SO terminal. In this case, a capture operation mode for capturing data from the logic circuits 41 and 42 is set.

  Times t0 to t9 are in a scan-in operation mode, and a data signal “H” “L” “H” “H” serially input from the SI terminal constitutes a shift register by four clocks of the signal SCLK. ~ 53d. At time t9 after the completion of the scan-in operation, the outputs QR0 to QR2 and SO of the D-FFs 53a to 53d are set to “H” “H” “L” “H” in order.

  From time t9 to t13 is the capture operation mode, and since the signal SE is “L”, the output signals of the logic circuits 41 and 42 are input to the data inputs of the D-FFs 53a to 53d. The capture clock signal CCLK selected by the selector 52g is supplied to the clock input of the D-FF 53d. Here, for simplicity of explanation, only the D-FF 53d captures the output signal A1 of the AND circuit 41a of the logic circuit 41, which is the circuit under test of the scan test, in accordance with the capture clock signal CCLK.

  At time t9, since the inputs QR0 and QR1 of the AND circuit 41a are both “H”, the expected value of the output A1 is “H”. This output A1 is taken into the D-FF 53d in accordance with the capture clock signal CCLK at time t11. Here, for example, when there is a failure in which one of the inputs of the AND circuit 41a, which is the circuit under test, is shorted to the GND level, the output A1 becomes "L" regardless of the levels of QR0 and QR1. Therefore, it is possible to detect whether or not the logic circuit 41 has failed by outputting the data captured by the D-FF 53d serially from the SO terminal by the scan-out operation and comparing it with the expected value. Here, when the output data is the same “H” “L” “H” “H” with respect to the input data “H” “L” “H” “H”, there is no failure in the logic circuit 41, For example, when “L”, “L”, “H”, or “H”, the logic circuit 41 has a failure.

  After performing the scan test in this way, after time t20, the signal SCAN is switched to “L”, and the mode is shifted to the inspection mode and the result reading mode. Note that the operations in the inspection mode and the result reading mode are the same as those described in the second embodiment, and thus description thereof is omitted here.

  As described above, according to the present embodiment, the inspection result storage circuit 50 used for the BIST inspection is realized by the scan register chain for the scan test of the logic circuits 41 and 42. That is, since the scan register chain for the scan test of the logic circuit can be used as a storage circuit for the inspection result of the BIST inspection, it is necessary to newly add a storage circuit for storing a plurality of inspection results. Therefore, an increase in chip area can be suppressed, and an increase in chip cost can be suppressed.

(Embodiment 5)
FIG. 15 is a block diagram showing a schematic configuration of a semiconductor integrated circuit having a BIST circuit according to the fifth embodiment. In contrast to the configuration of FIG. 1, the mode switching signal BIST_MODE is generated by a TAP (Test Access Port) 13 for boundary scan. Since other configurations are the same as those of the first embodiment, description thereof is omitted here.

  In FIG. 15, a signal BIST_EN for starting BIST is given from the TAP 13 to the BIST circuit 10. The signals BIST_GO and BIST_DONE output from the BIST control circuit 7 are input to the TAP 13, and the mode switching signal BIST_MODE output from the TAP 13 is applied to the inspection result storage circuit 8 of the BIST circuit 10.

  The TAP is an interface related to a JTAG (Joint Test Action Group) standard that defines a boundary scan architecture for testing a connection between chips, checking a state of a terminal of the chip itself, and testing an internal logic circuit. TAP is standardized by IEEE 1149.1, has five terminals of TDI, TMS, TCK, TRST, and TDO, and is used for input / output and control of test data. TDI (Test Data Input) is a test data input terminal, TDO (Test Data Output) is a test data output terminal, TMS (Test Mode Select) is a JTAG operation selection terminal, TCK (Test Clock) is a test clock terminal, TRST (Test Reset) is a reset terminal for the JTAG function.

  The JTAG device includes the above-described interface, a TAP controller, a data register, and an instruction register. The TAP controller is a circuit for inputting / outputting instructions, test data, test results, etc. to the circuit under test, BIST, etc., and the data register is a register circuit such as a boundary scan register, a bypass register, an internal data register, etc. The instruction register is a circuit that decodes an instruction from the TAP controller and is used to select a test to be executed and a data register to be accessed. The type of instruction to be mounted and the assignment of the instruction code can be freely determined for each device.

  The instruction data serially input from the TDI terminal is decoded by an instruction register, a signal for controlling the BIST is output, and a signal such as a test result from the BIST is received and output serially from the TDO terminal.

  Regarding generation of the mode switching signal BIST_MODE described in the first to fourth embodiments, a new command code for generating BIST_MODE is assigned in the instruction register, and desired command data is input from the TDI terminal, so that control at the TAP 13 is performed. Is possible.

(Embodiment 6)
FIG. 16 is a block diagram showing a schematic configuration of a semiconductor integrated circuit having a BIST circuit according to the sixth embodiment. In the present embodiment, the inspection result storage circuit is realized by a scan register chain for a boundary scan test. However, since there is no functional difference between the boundary scan register and the scan register of the logic circuit, the boundary scan register 66 in FIG. 16 can be configured similarly to the test result storage circuit 50 described in the fourth embodiment. The description is omitted.

  The TAP 65 receives signals TDI, TMS, TCK, TRST, signals BIST_GO, BIST_DONE output from the BIST circuit 60, a mode switching signal BIST_MODE, and an output signal BSO of the boundary scan register 66, and signals TDO, BIST_EN, RDAT, RCLK is output. The BIST circuit 60 receives signals BIST_EN and BIST_CLK output from the TAP 65, and outputs signals BIST_GO, BIST_DONE and a mode switching signal BIST_MODE. Boundary scan register 66 receives signals RDAT and RCLK from TAP 65 and outputs signal BSO.

  FIG. 17 is a diagram illustrating a configuration example of the TAP 65. The TAP 65 receives a signal BIST_GO at the A input and a first selector 67a that receives the signal TDI at the B input, and a second selector 67a that receives the signal BIST_DONE at the A input and receives the internal clock ICLK output from the instruction register 68 at the B input. Selector 67b, instruction register 68, and TAP controller 69. A mode switching signal BIST_MODE is supplied to S inputs of the first and second selectors 67a and 67b.

  The first selector 67a outputs the signal BIST_GO as the signal RDAT when the mode switching signal BIST_MODE is “L”, and outputs the signal TDI as the signal RDAT when the mode switching signal BIST_MODE is “H”. The second selector 67b outputs the signal BIST_DONE as the signal RCLK when the mode switching signal BIST_MODE is “L”, and outputs the internal clock ICLK as the signal RCLK when the mode switching signal BIST_MODE is “H”.

  The boundary scan register 66 receives the signal RDAT and the signal RCLK, and outputs the stored data from the TDO terminal. Therefore, when the mode switching signal BIST_MODE is “L”, the boundary scan register 66 can store a plurality of test results of the memory macro 1 by the signal BIST_GO, that is, the BIST circuit 60. When the mode switching signal BIST_MODE is “H”, the plurality of inspection results can be read from the TDO terminal using the internal clock ICLK generated by the signal TCK.

  As described above, according to the present embodiment, the test storage circuit used for the BIST test is realized by the scan register chain for the boundary scan test. That is, since the scan register chain for the boundary scan can be used as a storage circuit for the inspection result of the BIST inspection, it is not necessary to newly add a storage circuit for storing the inspection results of a plurality of times, and the chip area can be reduced. An increase can be suppressed, and an increase in chip cost can be suppressed.

  In the present embodiment, as the configuration of the TAP 65, the signals BIST_GO and BIST_DONE are switched to the signals TDI and ICLK. However, the configuration is not limited to this, and any configuration that can realize an equivalent function may be used.

  In each of the above-described embodiments, the circuit to be inspected is described as being a memory. However, the present invention is not limited to this. For example, another circuit such as a logic circuit may be the circuit to be inspected. Absent.

  In addition, the logic level and the number of clocks described in each of the above-described embodiments, the configuration of the inspection result storage circuit, such as the number of stages of the shift register, the configuration of the transfer control circuit, such as the number of bits of the counter unit, etc. It is an example and it is not limited to these.

  The present invention is useful in a semiconductor memory device having a BIST circuit, for example, as a technique for shortening a verification period for setting inspection conditions, shortening inspection time, and optimizing inspection conditions.

1 Memory macro (circuit under test)
7 BIST control circuit 8, 31 Inspection result storage circuit 10, 20, 30 BIST circuit 13, 65 TAP
21, 35 Transfer control circuit 21a, 35a Counter unit 21b, 35c Latch unit 33a, 81a First selector 33b, 81b Second selector 34, 82 Shift registers 34a-34f, 82a-82d D-FF (clock synchronous latch) circuit)
41, 42 Logic circuit 50 Inspection result storage circuit 66 Boundary scan register BIST_MODE mode switching signal BIST_GO signal (first signal)
BIST_DONE signal (second signal)

Claims (12)

BIST (Built−) that controls execution of inspection of the circuit under test, and outputs a first signal indicating the inspection result of the circuit under inspection and a second signal indicating completion of the inspection of the circuit under inspection. In Self Test) control circuit,
A test result storage circuit configured to receive the first and second signals and a mode switching signal indicating a test mode or a result read mode, and configured to store a plurality of test results;
When the mode switching signal indicates the inspection mode, the inspection result storage circuit stores the inspection result indicated by the first signal every time the second signal indicates the end of inspection, while the mode switching signal is A semiconductor integrated circuit which outputs a stored inspection result when indicating a result reading mode. The semiconductor integrated circuit according to claim 1,
2. The semiconductor integrated circuit according to claim 1, wherein the inspection result storage circuit includes a shift register in which a plurality of clock synchronous latch circuits are serially connected. The semiconductor integrated circuit according to claim 2.
The inspection result storage circuit includes:
The first signal and the third signal are input, and when the mode switching signal indicates the inspection mode, the first signal is selectively output, while when the result reading mode indicates the third signal, the third signal is selected. A first selector that selectively outputs a signal;
The second signal and the fourth signal are input, and when the mode switching signal indicates the inspection mode, the second signal is selectively output, while when the mode reading signal indicates the result reading mode, the fourth signal is output. A second selector that selectively outputs a signal,
The output of the first selector is supplied to the data input of the clock synchronous latch circuit at the head of the shift register, and the output of the second selector is supplied to the clock input of each clock synchronous latch circuit of the shift register. A semiconductor integrated circuit characterized by being given. The semiconductor integrated circuit according to claim 1,
2. The semiconductor integrated circuit according to claim 1, wherein the inspection result storage circuit is realized by a scan register chain for a scan test or a boundary scan test of a logic circuit. The semiconductor integrated circuit according to any one of claims 1 to 3,
A semiconductor integrated circuit comprising a transfer control circuit for generating the mode switching signal. The semiconductor integrated circuit according to claim 5, wherein
The transfer control circuit includes:
A counter unit that receives the second signal and counts the number of times the second signal has reached a logic level indicating the end of the inspection;
A semiconductor integrated circuit comprising: a latch unit that changes the mode switching signal to a logic level indicating a result read mode when a count value of the counter unit reaches a predetermined value. The semiconductor integrated circuit according to claim 6.
The transfer control circuit includes:
A semiconductor integrated circuit characterized in that the predetermined value can be set from the outside. The semiconductor integrated circuit according to any one of claims 1 to 3,
The semiconductor integrated circuit according to claim 1, wherein the mode switching signal is given from outside the semiconductor integrated circuit. The semiconductor integrated circuit according to any one of claims 1 to 3,
The semiconductor integrated circuit, wherein the mode switching signal is a signal generated by a TAP (Test Access Port). The semiconductor integrated circuit according to claim 1,
A semiconductor integrated circuit, wherein the circuit under test is a memory. The semiconductor integrated circuit according to claim 1,
A semiconductor integrated circuit, wherein the circuit to be inspected is a logic circuit. A method for inspecting a circuit to be inspected by a BIST (Built-In Self Test) control circuit and a semiconductor integrated circuit including an inspection result storage circuit configured to be capable of storing a plurality of inspection results,
Setting the semiconductor integrated circuit to an inspection mode by a mode switching signal;
In the inspection mode, the BIST control circuit inspects the circuit to be inspected and repeatedly performs an operation of storing the inspection result in the inspection result storage circuit a plurality of times;
Setting the semiconductor integrated circuit to a result reading mode by the mode switching signal;
In the result read mode, the test result storage circuit includes a step of outputting a plurality of stored test results to the outside of the semiconductor integrated circuit.

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