JP2012028801A - Chip connector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a process of easily forming a chip-to-chip electric connection by a via penetrating a wafer.SOLUTION: In a method of electrically coupling a first contact 3306 on a first wafer and a second contact 3304 on a second wafer, the first contact contains a rigid material, and the second contact contains a material which is malleable as compared with the rigid material. When they are coupled together, the rigid material enters the malleable material and both the rigid material and malleable material are conductive. The method includes a step for bringing the rigid material into contact with the malleable material, a step for applying a force to any one of the first contact or second contact so that the rigid material enters the malleable material, a step for heating the rigid material and malleable material in order to soften the malleable material, and a step for confining the malleable material in a region specified previously.

Description

  The present invention relates to semiconductors, and more particularly to electrical connections for semiconductor devices.

  It is difficult to make electrical contacts (by creating conductive vias) that extend in all directions through the electronic chip. It is almost impossible to produce electrical contacts while maintaining high accuracy or controlled reproducibility, not to mention mass production, unless one or more of the following applies. That is, a) the via is very shallow, that is, the depth is well below 100 μm, b) the via width is large, or c) the distance between the vias is large, ie, many times the via width. If the vias are close enough to cause signal crosstalk, or if the chip through which the via penetrates is charged, the conductor in the via does not short-circuit and what is the charge at the relevant part of the chip? The problem is exacerbated because it cannot carry different charges. Furthermore, conventional processes can damage the formed integrated circuit (IC) chips (ie, active semiconductor devices), so as long as these processes exist, they are not suitable for use with such chips, leading to increased costs, This reduces the final yield. In addition to the above problems, capacitance and resistance problems can occur when the material through which the via penetrates has a charge or when the frequency of the signal transmitted through the via is very high, e.g. above about 0.3 GHz. It is necessary to work on it.

  Indeed, many problems remain in semiconductor technology, including: That is, the packaging used is large and not scalable; the assembly cost does not drop like a semiconductor; the chip cost is proportional to the area, the highest performance process is the most expensive, but the high performance process Requires only a portion of the chip area; current processes are subject to voltage and other technology constraints; designers are subject to one process and one material design constraints; High power pad drivers are required for chip-to-chip (through-package) connections; one or more new masks can be used to make a whole new chip, even for minor changes or corrections of minor design mistakes Need to be manufactured; if a new chip as a whole requires millions of dollars in mask cost alone; individual chips are difficult to inspect and complicated When the combination of the chip, that the packaging of the previous test is more difficult.

  Thus, there is a great need in the prior art for techniques that can address one or more of the above issues.

  The inventors have developed a process for easily forming chip-to-chip electrical connections by vias penetrating a wafer, preformed (preform) third party chips, or doped semiconductor substrates. Each aspect described herein is useful in this approach and presents improvements in the general field of bonding chips together.

  One aspect includes a method of electrically coupling a first contact on a first wafer to a second contact on a second wafer, where the first contact includes a rigid material and the second contact is malleable as compared to the rigid material. Including a material, and when both are in contact, the rigid material penetrates the malleable material, both the rigid material and the malleable material are electrically conductive, and the method includes combining the rigid material with the malleable material. Contacting, applying a force to either the first contact or the second contact to allow the rigid material to enter the malleable material, heating the rigid and malleable materials to soften the malleable material And constraining the malleable material within a pre-specified region.

  Another aspect includes forming a well on the second wafer that forms a boundary of the malleable material and that performs the constraining step.

  Yet another aspect includes applying a malleable material on the IC pad of the second wafer, the IC pad being in proximity to the IC pad and the dielectric on the second wafer. The malleable material is recessed with respect to at least one of the bodies, a portion of which is placed on the top surface of the IC pad and a portion is placed on the top surface of the cover glass and / or the dielectric. Thereby, the outer surface portion of the malleable material on the IC pad is at a different height than another portion of the malleable material disposed on the cover glass and / or the dielectric.

  Another aspect includes a connection formed between complementary contacts on two chips, the connection including a first electrical contact on a first chip of the two chips and a second of the two chips. The second electrical contact on the chip, the bonding metal that physically and electrically connects the first and second electrical contacts, and the bonding metal forms a boundary around the bonding metal, and the bonding metal swells or creeps laterally from the contact. And a material that prevents the

  The advantages and features described herein are only a few of the many advantages and features available from the exemplary embodiments and are presented only to assist in understanding the present invention. Needless to say, these should not be construed as limiting the invention as defined in the claims, or limiting the equivalents of the claims. For example, some of these advantages may contradict each other and may not apply simultaneously to a single embodiment. Similarly, some advantages may apply to one aspect of the invention but not other aspects. Thus, this summary of features and advantages should not be considered a clue in determining equality. Additional features and advantages of the invention will be apparent from the following description, drawings, and claims.

1 is a schematic side view of a portion of a chip that includes a number of active electronic devices. It is a top view of the upper surface of the specific area | region of FIG. Fig. 2 shows a schematic sectional view of a part of Fig. 1; FIG. 4 is a plan view of the upper surface of the specific region of FIG. 1 immediately after generation of the groove shown in the side view of FIG. 3. FIG. 2 shows a schematic cross-sectional view of the portion of FIG. 1 as a result of subsequent processing. It is a top view of the upper surface of the specific area | region of FIG. 1 immediately after filling of the groove | channel with the electrically insulating material shown by the side view of FIG. 1 shows a partial cross-sectional schematic diagram of FIG. 1 as a result of subsequent processing. It is a top view of the upper surface of the specific area | region 124 of FIG. 1 immediately after producing | generating a via groove | channel. 1 shows a partial cross-sectional schematic diagram of FIG. 1 as a result of subsequent processing. It is a top view of the upper surface of the specific area | region of FIG. 1 immediately after giving a metallization to a via groove | channel. The partial cross-sectional schematic of FIG. 1 is shown as a result of the following optional processing. FIG. 2 is a top plan view of a particular region of FIG. 1 immediately after optional introduction of adhesive into the remaining voids. The partial cross-sectional schematic of FIG. 1 is shown as a result of other optional processing. FIG. 2 is a top plan view of a particular region of FIG. 1 immediately after optionally adding a finish into the remaining void. 1 shows a partial cross-sectional schematic diagram of FIG. 1 as a result of subsequent processing. FIG. 2 shows a partial cross-sectional schematic of FIG. 1 immediately after thinning the substrate and removing the bottom metallization. FIG. 6 shows a partial cross-sectional schematic diagram of FIG. 5 as a result of processing of an alternative variant. It is the top view of the cross section which took out the lower part of the specific area | region of FIG. 1 immediately after producing | generating a via groove | channel. As a result of further processing with the method described in connection with FIG. 9, the partial cross-sectional schematic of FIG. 5 is shown. FIG. 5 is a partial cross-sectional schematic diagram as a result of further option processing by the method described in connection with FIG. FIG. 5 is a partial cross-sectional schematic diagram as a result of further option processing using the method described in connection with FIG. FIG. 5 shows a partial cross-sectional schematic of FIG. 5 as a result of thinning the substrate and exposing the bottom metallization in the manner described in connection with FIG. 15 in the alternative variation of FIG. FIG. 5 shows a partial cross-sectional schematic of FIG. 5 as a result of thinning the substrate and removing the bottom metallization in the manner described in connection with FIG. 16 for the alternative variation of FIG. A simplified version of a double conductor variant immediately after sidewall metallization is shown. A simplified variation of a double conductor immediately after filling a groove with an electrically insulating material 500 is shown. Shown is a simplified via trench produced by removing an entire island of semiconductor material. A simplified illustration of a via trench produced by removing only the inner islands of semiconductor material is shown. A variation of an exemplary double conductor is shown in a simplified manner. A variation of an exemplary double conductor is shown in a simplified manner. FIG. 6 shows a simplified alternative exemplary double conductor variant. FIG. 6 shows a simplified alternative exemplary double conductor variant. FIG. 30 shows the use of an optional additional thermally generated dielectric or insulator in the approach of FIGS. 28A and 29A. FIG. 28B shows the use of an optional additional thermally generated dielectric or insulator in the approaches of FIGS. 28B and 29B. The deformation | transformation form of one example triple conductor is simplified and shown. FIG. 17 shows a partial cross-sectional schematic diagram of an alternative exemplary chip mounting that is similar to the mounting of FIGS. 9-16 except that voids remaining after metallization are not filled. FIG. 24 shows a partial cross-sectional schematic diagram of an alternative exemplary chip mounting similar to that of FIG. 23 except that the voids remaining after metallization are not filled. Each cross-sectional view of the chip of FIG. 32 immediately after hybridization (mixing) is shown. Each cross-sectional view of the chip of FIG. 33 immediately after hybridization (mixing) is shown. FIG. 35 shows the implementation of FIG. 34 after optional coating with an insulator or insulating protective coating. The illustration of the cross section of an annular groove is shown. The process for preparing wafers for stacking is shown in a simplified and comprehensive manner. FIG. 6 illustrates a portion of an example chip that has been processed to create a through-chip connection and then stacked to form a chip unit using different variations of the process described herein. FIG. 6 illustrates a portion of an example chip that has been processed to create a through-chip connection and then stacked to form a chip unit using different variations of the process described herein. FIG. 6 illustrates a portion of an example chip that has been processed to create a through-chip connection and then stacked to form a chip unit using different variations of the process described herein. Fig. 6 shows a simplified process for performing a back-to-front variant. A simplified process for performing a capacitive connection variation is shown. A simplified process for performing a pre-connect variant is shown. An exemplary tack-fusion parameter is shown in a simplified manner. An exemplary tack-fusion parameter is shown in a simplified manner. FIG. 6 is a simplified illustration of a “minimum” contact. It is the simplified illustration about the extended contact. Fig. 4 shows a portion of a stack of semiconductor chips, each having a through-chip connection as described herein. FIG. 50 illustrates a portion of a simplified stack of the chips shown in FIG. 49 stacked using a post-penetration connection approach. A simplified illustration of voids in a metallization filled with preformed posts. FIG. 52 shows a simplified version of the chip of FIG. 51 after it has been hybridized to an electronic chip. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 4 shows a simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Fig. 5 illustrates an alternative simplified exemplary variation of the basic contact formation and hybridization approach. Later, the first part of two further exemplary variant approaches to form what will become a rigid post on the back of the daughter wafer will be simplified and shown side by side. Later, the first part of two further exemplary variant approaches to form what will become a rigid post on the back of the daughter wafer will be simplified and shown side by side. Later, the first part of two further exemplary variant approaches to form what will become a rigid post on the back of the daughter wafer will be simplified and shown side by side. Later, the first part of two further exemplary variant approaches to form what will become a rigid post on the back of the daughter wafer will be simplified and shown side by side. 2 is a cross-sectional photograph of an exemplary inclined via. 2 is a photograph of an exemplary via having a depth of 100 μm and a diameter of 20 μm. It is a cross-sectional photograph of a chip having a via with a sharp tip formed therein. The second part of the two further exemplary variants of FIGS. 88-91 are simplified and shown side by side. The second part of the two further exemplary variants of FIGS. 88-91 are simplified and shown side by side. The second part of the two further exemplary variants of FIGS. 88-91 are simplified and shown side by side. The second part of the two further exemplary variants of FIGS. 88-91 are simplified and shown side by side. The second part of the two further exemplary variants of FIGS. 88-91 are simplified and shown side by side. The second part of the two further exemplary variants of FIGS. 88-91 are simplified and shown side by side. The second part of the two further exemplary variants of FIGS. 88-91 are simplified and shown side by side. The second part of the two further exemplary variants of FIGS. 88-91 are simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A variant process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. FIG. 6 is a photograph of a further variation of the process of preparing a wafer for hybridization to other elements. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. A further alternative process for preparing a wafer for hybridization to other elements is simplified and shown side by side. The daughter wafer contact and the mother wafer contact immediately before the tack stage are shown in a simplified manner. 140 shows a simplified view of the contacts of FIG. 140 after the fusion process is complete. Shows profiled malleable contacts. Some examples of the myriad possible mother contact profiles are shown. Some examples of the myriad possible mother contact profiles are shown. Some examples of the myriad possible mother contact profiles are shown. FIG. 6 is a photograph of a profiled malleable contact of an alternative embodiment. FIG. 145 is a photograph of a profiled rigid contact designed to enter the malleable contact of FIG. 144. Furthermore, a simplified example of profiled contacts is shown. Fig. 4 illustrates a variant process for implementing the well attachment concept. Fig. 4 illustrates a variant process for implementing the well attachment concept. Fig. 4 illustrates a variant process for implementing the well attachment concept. Fig. 4 illustrates a variant process for implementing the well attachment concept. Fig. 4 illustrates a variant process for implementing the well attachment concept. Fig. 4 illustrates a variant process for implementing the well attachment concept. The types of deformation of the reverse well are shown in a simplified manner. The types of deformation of the reverse well are shown in a simplified manner. The types of deformation of the reverse well are shown in a simplified manner. The types of deformation of the reverse well are shown in a simplified manner. It is a photograph of a longitudinal section of a via extending to a diameter of 15 μm and a depth of 135 μm. It is a photograph of a longitudinal section of a via extending to a diameter of 25 μm and a depth of 155 μm. 158 is a photograph of a via similar to that of FIGS. 157A and 157B but not filled to the bottom. Fig. 4 shows a further variation of the class II rigid well attachment technique. Fig. 4 shows a further variation of the class II rigid well attachment technique. Fig. 4 shows a further variation of the class II rigid well attachment technique. Fig. 4 shows a further variation of the class II rigid well attachment technique. Fig. 4 shows a further variation of the class II rigid well attachment technique. Fig. 4 shows a further variation of the class II rigid well attachment technique. Fig. 4 shows a further variation of the class II rigid well attachment technique. Fig. 4 shows a further variation of the class II rigid well attachment technique. Fig. 4 shows a further variation of the class II rigid well attachment technique. Figure 7 shows a further variation of the well attachment technique in which the tips are applied to each other by separate spaced contacts. Figure 7 shows a further variation of the well attachment technique in which the tips are applied to each other by separate spaced contacts. Figure 7 shows a further variation of the well attachment technique in which the tips are applied to each other by separate spaced contacts. FIG. 6 shows a plan view of an alternative remote contact variation. FIG. 6 shows a plan view of an alternative remote contact variation. Figure 3 shows a cross-sectional view of an exemplary coaxial contact. 2 illustrates an exemplary usage of a coaxial contact. 2 illustrates an exemplary usage of a coaxial contact. 2 illustrates an exemplary usage of a coaxial contact. A simple example of a hermetic seal using contacts as described herein is shown. A simple example of a hermetic seal using contacts as described herein is shown. A simple example of a hermetic seal using contacts as described herein is shown. A simple example of a hermetic seal using contacts as described herein is shown. FIG. 6 is a chart summarizing different approaches for forming other variations using the principle of rigid / malleable contacts. Figure 6 is a chart summarizing different approaches for forming via variants. Figure 6 is a chart summarizing different approaches for forming via variants. Figure 6 is a chart summarizing different approaches for forming via variants. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving deposition of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving plating of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving plating of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving plating of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving plating of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving plating of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving plating of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving plating of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving plating of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving plating of metal on a daughter wafer. Figure 2 shows in more detail the process flow for a specific case involving plating of metal on a daughter wafer. The deformation | transformation form of the electroless plating of a mother wafer is simplified and shown. The deformation | transformation form of the electroless plating of a mother wafer is simplified and shown. The deformation | transformation form of the electroless plating of a mother wafer is simplified and shown. The deformation | transformation form of the thin dielectric material of a mother wafer is simplified and shown. The deformation | transformation form of the thin dielectric material of a mother wafer is simplified and shown. The deformation | transformation form of the thin dielectric material of a mother wafer is simplified and shown. The deformation | transformation form of the thin dielectric material of a mother wafer is simplified and shown. The deformation | transformation form of the thin dielectric material of a mother wafer is simplified and shown. A simplified variation of the thick dielectric of the mother wafer is shown. A simplified variation of the thick dielectric of the mother wafer is shown. A simplified variation of the thick dielectric of the mother wafer is shown. A simplified variation of the thick dielectric of the mother wafer is shown. A simplified variation of the thick dielectric of the mother wafer is shown. One example and some representative dimensions are shown for a mother wafer contact with 14 μm wide contact pads spaced at a 50 μm pitch prior to barrier deposition. 209 shows the contacts of FIG. 209 after barrier and cap deposition. Representative dimensions for a mother wafer contact having 8 μm wide contact pads spaced at a 25 μm pitch are shown. One example and some representative dimensions for a daughter wafer contact with 14 μm wide contact pads spaced by a 50 μm pitch produced by deposition are shown. One example and some representative dimensions are shown for a daughter wafer contact having 8 μm wide contact pads spaced by a 25 μm pitch produced by deposition. One example and some representative dimensions are shown for a plated mother wafer contact having 14 μm wide contact pads spaced at 50 μm pitch before a self-alignment seed etch is performed. FIG. 214 shows the contacts of FIG. 214 after a self-alignment seed etch has been performed. A method of using inner vias as part of heat pipe knitting is shown. An exemplary insulation and cross-linking variant is shown in a simplified manner. Another exemplary insulation and cross-linking variation is simplified and shown side by side. An exemplary representative conventional microprocessor chip and its respective components are shown in a simplified manner. FIG. 2 shows a simplified method in which an alternative microprocessor can be constructed from the elements of the microprocessor of FIG. 219 to reduce the projected area and substantially reduce the distance between elements. FIG. 2 shows a simplified method in which an alternative microprocessor can be constructed from the elements of the microprocessor of FIG. 219 to reduce the projected area and substantially reduce the distance between elements. FIG. 2 shows a simplified method in which an alternative microprocessor can be constructed from the elements of the microprocessor of FIG. 219 to reduce the projected area and substantially reduce the distance between elements. FIG. 2 shows a simplified method in which an alternative microprocessor can be constructed from the elements of the microprocessor of FIG. 219 to reduce the projected area and substantially reduce the distance between elements. 229 shows a direct comparison of the projected area of the chip of FIG. 219 with that of the chip of FIG. The modification of the package according to function is shown. FIG. 222 shows details of a variation of the package of FIG. Simplifies a variant of processing without routing and gives an overview. Simplifies a variant of processing without routing and gives an overview. Simplifies a variant of processing without routing and gives an overview. Simplifies a variant of processing without routing and gives an overview. Simplifies a variant of processing without routing and gives an overview. Simplifies a variant of processing without routing and gives an overview. Simplifies a variant of processing without routing and gives an overview. Simplifies a variant of processing without routing and gives an overview. A simplified variant without alternative routing is shown. A simplified variant without alternative routing is shown. A simplified variant without alternative routing is shown. A simplified variant without alternative routing is shown. Connections using light rather than wiring between two chips are shown in a simplified manner. Using a variation of the heated pipe configuration, a simplified illustration of how light can pass from the laser loaded chip to the photodetector loaded chip even though two other chips are interposed between them is shown. A simplified illustration of the tack-fusion process approach. The functional layer of the daughter contact is shown in a simplified manner. The functional layer of the mother contact is shown in a simplified manner. An exemplary material configuration of a functional layer of a daughter contact is shown in a simplified manner. An example material composition of a functional layer of a mother contact is simplified and shown. It is a photograph of the combined mother and daughter contact. It is a photograph of the combined mother and daughter contact. It is a photograph of the combined mother and daughter contact. A single pin tooling is shown simplified for each chip. A single pin tooling is shown simplified for each chip. Simplified tooling for multiple pins per chip. Simplified tooling for multiple pins per chip. An alternative tooling technique is shown in a simplified manner. An alternative tooling technique is shown in a simplified manner. Another alternative tooling approach is shown in a simplified manner. Another alternative tooling approach is shown in a simplified manner. Another alternative tooling approach is shown in a simplified manner. Another alternative tooling approach is shown in a simplified manner. Another alternative tooling approach is shown in a simplified manner.

  First, it goes without saying that the term “wafer” as used herein refers only to the entire wafer from which a particular description can be cut, eg, an 8 inch or 12 inch wafer, “chip to wafer” or “ The terms “chip”, “die”, and “wafer” are all interchangeable, unless it is clearly and not limited to “die-to-wafer”, “wafer-to-wafer”, or “wafer-scale” processing. Are intended to be included in that scope. If the use of the term makes sense when viewed from a technical point of view, when replaced by the term “chip” or “die”, these terms are still intended. Further, reference herein substantially to "wafer or chip" or "wafer or die" should be considered inadvertent duplication unless the above conditions are met.

  In general, certain implementations of the aspects described herein allow deep vias, high repeatability, controlled capacitance and resistance, and electrical isolation between the via and the wafer or substrate through which the via passes. In a simple and controllable manner, it becomes possible to form connections between two or more wafers, including fully formed electronic devices, active optical devices or electro-optical devices.

  Implementation of this process is narrow (ie, up to about 15 μm wide) and aspect ratios on the order of 5: 1 to 10: 1 are more typical, but on the order of 3: 1 and 30: 1. It is possible to form conductive vias with a depth-to-width ratio that is deep enough to penetrate the chip (ie, to a depth greater than about 50 μm). Furthermore, the present inventors have the advantage that this is possible under the condition that the chip portion through which the via penetrates becomes electrically active. In particular, the inventors are able to provide electrical access through the doped semiconductor portion of the wafer using a path that insulates the doped semiconductor from the conductor traveling through the path by its sidewalls. I made it. In addition, our process is advantageous for narrow passages (ie, about 15 μm wide or even less), while insulating materials and conductors to maintain constant and acceptable capacitance and resistance. Enables strict thickness control.

  Furthermore, our technique is suitable for use in forming a contact having a pad having a diameter of 0.1 μm to 15 μm if it is circular. The upper limit is unrestricted, and according to our approach, only dimensions below that (15 μm) that allow integration, which is generally not possible with other approaches, are restricted, and the lower limit is the currently available photo Depends on lithography technology. In other words, advances in photolithography technology that allow narrower definition can further reduce current limitations.

  In addition, unlike solder contacts that are hundreds or thousands of μm long, or even thousands of μm long, unlike wire bonding contacts that often require a large pad driver to drive the chip-to-chip impedance. According to our approach, we can use very short contacts (10 μm or less) that can greatly reduce the effects of parasitic electricity between chips. Our representative contacts have a contact spacing no more than three times the width of the malleable material (defined below) before being integrated by complementary contacts (eg, the initial contact is 8 μm high) In this case, the contact interval is up to about 25 μm).

  According to the technique of the present inventors, it is possible to stack chips with a separation distance of about 20 μm or less. The inventors have demonstrated that it can be carried out at intervals of less than about 1 μm, but in practice, intervals of 10 μm or less are typical values. Generally, the minimum value is determined by the topology (unevenness) of the closest surfaces of the two wafers to be bonded when the distance between the pads is in contact at the point of the maximum height indicating the maximum distance.

  According to the technique of the present inventors, it is possible to form contacts at a pitch of 50 μm or less. The inventors have demonstrated that the pitch can be narrowed down to 7 μm, but as a typical value, a pitch of about 25 μm or less is used and is repeated, but the limit depends on the currently available photolithography technology . The pitch is narrowed by technological advances.

  Some variation features include one or more of the following: potential of millions of contacts per square centimeter; electrical, mechanical, and thermal adhesion occur simultaneously; Apply with low force but produce high strength connections (on the order of 1,000 kg / cm 2); connections are made with economic scale merit; fits non-planar wafers; most processes can be performed on wafer scale ( For example, a 10 μm GaAs substrate with 8, 10 or 12 inch wafers); the process can be based on chip-to-chip, chip-to-wafer, or wafer-to-wafer; the process is electrically grounded; Performed on a preform (ie, a chip fitted with a device) so that it can be used with a chip supplied by The chip combination can be inspected and then permanently connected and reworked as needed; different technologies can be mixed and combined (ie GaAs to InP, InP to Si, GaAs Capable of producing chip-size packages for semiconductor processes that are economically advantageous; core to low speed functionality Can be removed from the process, expensive processes and still operate the entire circuit set as a single chip, individual chip designs enjoy the benefits of the various voltages, technologies and materials available Can be optimized for that particular design; independent of the technology required for other aspects of the design; off-chip communication (off chip communication) is enhanced; helps to advance modularization of chip-level designs that allow core designs to be leveraged in multiple products without absorbing duplicate development design costs; and required The speed can be matched to the technical form so that it is not necessary to form a low speed circuit with expensive and high speed technology.

  Overall, our process can be used with a doped substrate, but does not short circuit the substrate and therefore can carry a charge opposite to that of the substrate it penetrates. Improve the ability to create chip-to-chip connections using “through-wafer” electrical contacts. Furthermore, this “through-wafer” approach can be used with semiconductor materials, insulators such as ceramics, and wafers of other conductive or non-conductive materials. Furthermore, using current equipment for etching semiconductor materials, ie, materials having an aspect ratio of 30 to 1, the process can be applied to narrow cross-sectional vias (ie, 15 μm wide, or possibly less), and 50 μm. It is sufficiently effective for vias that extend from the super to a depth of 500 μm or more. Furthermore, the process allows, for example, vias generated using the process to transmit high speed electrical signals (ie, electrical signals having a frequency greater than 0.3 GHz) or optical signals depending on the implementation. Thus, tight control of capacitance and resistance is possible.

  In some embodiments, the conductivity also allows for intensive vias that each carry different signals or different charges. Further, in some embodiments, a centralized via is possible that allows the inner vias to be used as part of the cooling system, and a portion of the knitting is used to be part of the heat pipe knitting. In other implementations, the advantage is that the chips are stacked and compatible with stacking techniques that are electrically connected to other chips based on chip-to-chip, chip-to-wafer or wafer-to-wafer, and the use of that technique Provides the advantage of being possible.

  Substantially all stacking processes and variations described herein or derived directly therefrom have the advantage that the new stack piece need only be aligned with the underlying piece. This is in stark contrast to the prior art that attempts to stack, where all pieces must be aligned with one another in a stack and then conductive material inserted to form a transverse stack connection. Such an approach needs to be stacked so that all pieces, as a whole, not just the piece immediately below, are correctly aligned with all other pieces. Furthermore, our technique works equally well with single-axis, coaxial and triaxial connections, but on the other hand, even though they can be provisionally connected, the overall alignment technique does not work. .

  Various techniques have been simplified for illustration, eg, preformed (ie, already integrated circuits or components, and / or optical devices such as lasers, detectors, modulators, and contacts for these devices) An example including a wafer of a semiconductor material such as silicon (Si), silicon germanium (SiGe), and gallium arsenide (GaAs) in which a pad is accommodated will be described.

  The first embodiment of the present approach involves two wafers that need to etch only the wafer for an exemplary semiconductor material (ie, a doped semiconductor with or without some or all of the substrates involved). Includes an etching process. This exemplary process begins with a device mounted wafer of semiconductor material. In the case of a semiconductor wafer, one or more precisely-width trench regions are etched into the wafer to a desired depth so that the trench extends into the wafer substrate and creates a boundary for some semiconductor material. . It should be noted that the surrounding shape can be any closed shape, and the outer and inner walls of the groove need not be the same shape. The capacitance and resistance of the final via connection can be controlled by selecting the inner and outer shape of the groove and the separation distance. The depth of the groove is typically 50 μm or more, and in some cases 500 μm or more, but the groove cannot be spread over the entire wafer substrate so that the defined semiconductor piece cannot be removed. The groove is then filled with an electrically insulating material. Next, at least a portion of the defined semiconductor piece is etched away, leaving a narrower cross-sectional hole than that defined by the outer groove wall, thereby etching the semiconductor piece. Ensure that the vias that are created are defined by either the insulating material, or the central semiconductor piece for part of the depth, or the surrounding ring of material from the substrate for the other. . The hole is metallized to create an electrical connection between the top surface of the wafer and the bottom of the hole. The wafer (i.e., substrate) is then thinned back and the bottom surface of the hole becomes a substrate side contact or part thereof (referred to interchangeably herein by the broad term "contact"). Expose the activation. Typically, at least the full depth of the portion of the surface defining the hole is metallized, but in some embodiments the metallization is deep enough to be exposed when the substrate is thin enough. It just extends. In this method, if the process used to perform the metallization cannot be used for metallization down to the full depth, as long as sufficient metallization extends to stop the thinning step, A contact can be formed. For example, in one exemplary embodiment, the via extends halfway through the substrate for a total length of about 600 μm, but metallization can only be reliably performed to an overall depth of about 300 μm (ie, 300 μm shallower than the via itself). The process is not adversely affected as long as the substrate can be thinned and at least metallization can be reached so that the wafer or chip is not unacceptably weakened.

  Through the above techniques, variations described herein, and permutations thereof, connection points can be provided near on-chip devices. Connection points located close to the on-chip device facilitate chip-to-chip connections in the vertical direction (ie, due to the stack of chips), reduce the distance between connection points, and provide chip-to-chip connection wires. The need to use bonding is reduced or eliminated. Furthermore, this approach facilitates the creation of subcomponent-specific designs that can be mixed and combined as desired during manufacturing. In other words, the third dimension is readily available for chipset materials, dimensions and manufacturing. In addition, this approach allows for the mixing of different speeds or material technology types, as well as the mixing and combining of components and subcomponents, thereby reducing development and manufacturing costs. Furthermore, chip-to-chip connections can create connections that use light rather than electrical connections between chips.

  The above is further facilitated by the optional use of a chip-to-chip connection technique that reduces the stress on the bonded chips and reduces the risk of chip damage.

  Certain aspects of the above description will be described in further detail by way of example and with particular reference to the drawings, which are generally simplified and not scaled for purposes of clarity of illustration and description. In some cases, the scale is intentionally significantly exaggerated or distorted at the expense of accuracy to ensure expression and understanding.

  Further, the techniques described herein are not related to specific devices on a chip or specific devices in which the aspects described herein are used together. Thus, a reference to any particular type of device, such as the laser of the first embodiment, is independent of the aspects described herein, except in the case of devices that need to make electrical contacts. Unrelated. In other words, the approach described herein is essentially the same for all devices and circuit elements that can make contacts.

  FIG. 1 is a schematic side view of a portion 100 of a chip 102 that includes a number of solid state electronic devices, such as resistors, capacitors, transistors, diodes, lasers, photodetectors, or some combination thereof. The portion 100 shown in FIG. 1 includes, for illustrative purposes only, a laser 104 having a “top” mirror 106, an active area 108 below the top mirror 106, and a “bottom” mirror 110 disposed on the substrate 112. , Whereby the device 104 has a height 114 of a few μm above the upper outer surface 116 that is the non-device portion of the chip 102 near the device 104.

  As shown, laser 104 is a conventional vertical cavity surface emitting laser (VCSEL). For illustrative purposes only, it is assumed that the top mirror 106 is electrically connected to some element on the substrate 118 opposite the side 120 on which the laser 104 is mounted, and is doped in the specific region 124 close to the device 104. It is necessary to penetrate the formed semiconductor material 122.

  First, of course, when describing an extent laser or photodetector as a device, the terms “top” and “bottom” are, according to convention, “bottom” is the portion closest to the substrate, Is emitted toward the substrate 112 or emitted away from the substrate (or in the case of a photodetector, regardless of the direction of receiving light).

  FIG. 2 is a plan view of the top surface 116 of the particular region 124 of FIG. 1 before the process is initiated.

  The basic process of forming through-chip contacts will be described with reference to these aspects shown in FIGS.

  FIG. 3 shows a schematic cross-sectional view of a portion 100 of FIG. 1 as a result of processing as follows.

  Initially, preferably using an anisotropic etch process (to produce relatively straight trench sidewalls 304), the trench 302 is routed into and through the semiconductor material 122 in the middle of the substrate 112. Etching is performed until the groove 302 enters the depth. The total depth of the groove 302 can be expanded to 100 μm or more, and in some cases, 500 to 600 μm or more. However, the groove 302 should be stopped before fully penetrating the substrate 112, otherwise the ability to practice the present invention will often be lost. The groove 302 has a closed shape that generates an annular cross section in a plane parallel to the substrate surface. Using this annular groove 302, the “island” 306 of the semiconductor material 122 remains and is held in place by at least the intact portion 308 of the substrate 112. It should be noted at this point that the “annular” referred to for the groove 302 is shown as circular, but this is merely for ease of illustration. As used herein, the term “annular” or “ring” is not to be limited to any particular or regular shape, or it should be understood that the outer periphery need not have the same shape as the inner periphery. As long as the groove has a closed shape so that an isolated “island” can be created therein, the groove should be considered as an annular groove or “ring” as used herein. In other words, the term refers to closed polygons (regular or irregular) or closed perimeter shapes, including other closed perimeter shapes that are independent of, for example, whether the shape is smooth or uneven. It is intended to include any combination. In addition, the term is intended to cover a range of fixed and varying widths for a particular case as needed or desired.

  4 is a plan view of the upper surface 116 of the specific region 124 of FIG. 1 immediately after the formation of the groove 302 shown in the side view of FIG. In this figure, the annular feature of the groove 302 is clearly shown. Since the groove 302 has a closed inner periphery 312 and outer periphery 314 and a width 310, the groove 302 surrounds and creates an island 306 within the semiconductor material 122.

  FIG. 5 shows a schematic cross-sectional view of portion 100 of FIG. 1 as a result of subsequent processing as follows.

  At least the trench 302 may be coated with a dielectric or other electrically insulating material 500, optionally covering a portion of the top surface 116 to a desired thickness. As an option, if there is an interest in heat transfer, a material having good heat conduction while being electrically insulated can be used as the electrically insulating material 500.

  The advantages achieved by the above approach can be seen by contrast in the context of the prior art. First, it is generally difficult to apply a dielectric material uniformly, especially when a uniform thickness is required. Second, this problem becomes more difficult when the dielectric needs to be applied to a non-planar surface, and must be applied to a vertical wall as in the case of vias described herein. Further increases the difficulty. Therefore, as long as other approaches attempt to create holes and accurately apply the walls of these holes with a dielectric and then make them conductive, these other approaches have uniformity. Lack of some important ability to control. The lack of uniformity exposed by these approaches dramatically affects capacitance and impedance, and hence performance, especially if the signal frequency involved is very high, for example above about 0.3 GHz. In contrast, the approach described herein allows precise control of capacitance and resistance because the dimensions of the groove 302 can be precisely controlled to the accuracy of the groove 302 itself. The walls around the trench 302 constrain the insulating material 500 and thus define the thickness and uniformity of the coating (and hence the final capacitance and impedance). Therefore, all that is required is to reliably fill the groove 302, which requires a very low accuracy and low cost process. Thus, unlike the prior art, accuracy when applying the dielectric is not required.

  6 shows the specific region of FIG. 1 immediately after filling the groove 302 and (optionally) partially covering the upper outer surface 116 with an electrically insulating material 500, as shown in the side view of FIG. 12 is a plan view of the upper surface 116 of 124. FIG.

  FIG. 7 shows a schematic cross-sectional view of portion 100 of FIG. 1 as a result of subsequent processing shown below.

  As the electrically insulating material 500 solidifies (by curing, curing, or other processing), the via grooves 702 are necessary for the semiconductor material islands 306 in the ring 704 of the insulating material 500 to achieve a particular desired implementation. Up to a sufficient depth 502, which is exemplary only, to a depth similar to the depth of the groove 302 (ie, to a depth that also extends into the substrate 112 a certain distance but preferably does not penetrate it). , Generated by removing. In practice, the depth 502 of the via groove 702 is sufficient to reach the distance into the substrate 112 that is essentially the same as the groove 302, if necessary during processing, as described below. It may be deeper or shallower than the depth of the groove 302 as long as it extends to the same depth. Further, the innermost wall of the ring 704 that defines the island 306 is generated by a removal process to determine the shape and profile (outer curved shape) of the via groove 702 that is a dielectric. Thus, since strict control of removal is not required in the width or depth direction, it is typically unaffected by the etching process, and the island 306 can be removed from the semiconductor material using a low precision etching process. Of course, the removal can be further increased, or alternatively can of course be achieved by using one or more other suitable processes such as laser ablation, laser drilling or some combination thereof. It is.

  Continuing the process of this embodiment, once the via groove 702 is generated, the sidewall 706 of the via groove 702 and the bottom portion 708 of the via groove 702 have the sidewall 706 of the insulating material 500 and the bottom portion 708 is the substrate 112. Therefore, it is non-conductive.

  8 is a plan view of the upper surface 116 of the specific region 124 of FIG. 1 immediately after forming a via groove in the ring 704 of the electrically insulating material 500 shown in the side view of FIG.

  FIG. 9 shows a schematic cross-sectional view of portion 100 of FIG. 1 as a result of the following subsequent processing.

  Via groove 702 may be at least a longitudinal portion of via groove sidewall surface 706 (ie, along its depth), eg, sputter, vapor deposition, plating, or other physical or chemical deposition techniques for filming with metal. Or, if necessary, using some combination of these to make it conductive by “metalizing” it. In other words, metallization involves the use of conductive solids, conductive epoxies or reflowable materials (eg, conductive liquids at appropriate temperatures such as solder). Using this metallization process, at least from the bottom of the via bottom 708 to the top surface 116, often a continuous conductive connection all the way to the target device if the target device is part of the chip that created the via Is typically generated. For purposes of illustration, FIG. 9 shows the electrical wiring 902 generated by the process extending from a contact 904 on the top mirror 106 of the laser 104 to the bottom 708 of the via groove 702. As illustrated, the entire surface of the sidewall 706 and bottom 708 of the via groove 702 is completely coated with metal.

  As described above, the width and length of the insulating ring can be precisely controlled, as can the thickness of the conductor formed by metallization, so that a certain capacitance to the metallized surface can be achieved. Further, since the insulating material 500 electrically insulates and penetrates the contact 904 from the semiconductor material 122, a semiconductor material that, if not insulated, may electrically short the contact to another device or conductor. The influence of defects can be suppressed.

  FIG. 10 is a plan view of the top surface 116 of the particular region 124 of FIG. 1 immediately after metallization of the via groove 702 and generation of electrical wiring 902 to the device contact 904, as shown in the side view of FIG. .

  FIGS. 11-14 illustrate additional optional processing that may be useful in some implementations or desired. The technique shown in FIG. 11 or 12 is independent of the technique shown in FIG. 13 or FIG. As a result, depending on the particular implementation, either the approach shown in FIGS. 11 and 12 or the approach shown in FIGS. 13 and 14 can be used separately or can be used together in any order. it can.

  Several advantages are gained by one or both of these optional approaches. First, filling the void with material adds mechanical strength and increases structural rigidity, thus reducing potential stress. Second, the use of solder, epoxy, or other adhesives is useful when the chip is ultimately connected to another element, particularly when the connection involves hybridizing the chip to another chip. Third, inserting a material into the void reduces the risk of unwanted material entering the void. Finally, the filler reduces or eliminates the possibility of damage to the metallized portion inside the via groove, particularly if the metallization is not the entire sidewall. Further, by changing the thickness of the insulator and metal, the coefficient of thermal expansion (“CTE”) of the wafer can be balanced to match that of the wafer. For example, oxide (CTE 1 ppm) can be used with copper (CTE 17 ppm) to match the CTE of silicon (2.5 ppm).

  Since both of these aspects are optional, both can be applied while using the present invention. However, for further understanding, both processes will be described in conjunction with FIGS.

  FIG. 11 shows a schematic cross-sectional view of portion 100 of FIG. 1 as a result of the following optional processing.

  Once metallization is complete, the remaining void 1100 may optionally be partially or wholly made of some material, eg, adhesive 1102 in this case, unless the remaining void 1100 is left empty, as described below. Can be filled with. Depending on the specific implementation using this variant, the adhesive 1102 may be conductive or non-conductive, ie, solder deposited by, for example, electroless or electrolytic plating techniques, or by vapor deposition or sputtering. A metal or alloy, or a non-conductive adhesive such as, for example, a suitable type of adhesive or an oxide such as epoxy or silicon dioxide.

  FIG. 12 is a plan view of the top surface 116 of the particular region 124 of FIG. 1 immediately after optional introduction of adhesive 1102 into the remaining void 1100 of the via groove 702 shown in the side view of FIG.

  FIG. 13 shows a schematic cross-sectional view of portion 100 of FIG. 1 as a result of the following optional processing.

  Alternatively or in addition, if the metallization is not completely filled with voids, when the metallization is finished, if there are remaining voids 1100, optionally partially or completely, for example, filled with a simple finish 1302 be able to. Depending on the particular implementation using this variation, the finish 1302 may be an insulator, such as an insulating material 500 originally used to fill the groove 302, a conductive epoxy, a conductive solid, or reflowable. A conductive material such as a new material or an insulating protective coating can be used. Further, when the finishing agent 1302 is used, the finishing agent 1302 may be introduced only in the void 1100 and need not be limited. As shown in FIG. 13, if it is an electrically insulating material and an adhesive 1102 is used, the finish 1302 can later be inserted on the top surface of any such adhesive 1102; To cover and protect some portion of the outer surface of the wafer and / or the portion 1304 of the wiring 902 that extends to the contact 904, it can extend outside the void 1100, or planarize the wafer without voids To do. For example, the finish 1302 can be a planarizable oxide so that the entire surface can be used to adhere to another element, such as a wafer or individual chips, thereby planarizing the wafer. To do.

  FIG. 14 illustrates a finish in an amount sufficient to provide coverage and protection for at least a portion 1304 of the wiring 902 within the remaining void 1100 on the top surface of the adhesive 1102, as shown in the side view of FIG. FIG. 2 is a plan view of an insulator top surface 116 of a specific region 124 of FIG. 1 immediately after an agent 1302 is optionally added.

  15 returns to basic processing and shows a schematic cross-sectional view of portion 100 of FIG. 1 as a result of subsequent processing as follows.

  When the metallization aspects shown in FIGS. 9 and 10 are completed (whether or not one or both of the optional aspects shown in FIGS. 11-14 are used), the back side of substrate 112 (ie, device non- The mounting surface 118 is thinned using, for example, a chemical process such as etching, a mechanical process such as polishing, a chemical mechanical process (CMP), or some combination thereof until at least the bottom metallization 1502 is exposed. Of the substrate 112 that is electrically connected from the doped semiconductor material 122 (in this case, the bottom mirror 110 of the laser 104) to the electrically isolated device contact 904 without performing any special backside processing. An electrical contact 1504 on the back surface 118 is created.

  Alternatively, the bottom metallization 1502 can be removed, or a thinning step can be performed until the volume of void 1100 is exposed (with or without filling). FIG. 16 shows a schematic cross-sectional view of the portion of FIG. 15 immediately after thinning the substrate and removing the bottom metallization. Advantageously, void 1100 has been filled with adhesive 1102 using at least the approach of FIGS. Accordingly, as shown in FIG. 16, thinning the back surface 118 of the substrate 112 until the bottom metallization 1502 of FIG. 15 is removed, a “small” of metal contacts 1602 that can still serve as part of the back surface electrical contacts. The adhesive 1102 is exposed while leaving the “ring”. Thus, when the adhesive 1102 is conductive, eg, solder, both the small ring 1602 and the adhesive 1102 act as contacts, while the small ring 1602 acts as a contact even when the adhesive 1102 is not conductive. While providing a conductive path from the back surface 118 to the device contact 904, it can still be used to couple the chip to other elements.

  The organization of FIG. 15 or FIG. 16 may alternatively be a metallization or metal for use as a contact when used only with the post-penetration approach, or with the tack-fusion approach, as described herein. The contacts can be thinned so that they protrude beyond the bottom of the wafer.

  Needless to say, the basic process described above, and more complex alternative processes built upon it according to that basic process, can be used to create vias and then devices on the wafer (eg, transistors, diodes, lasers, photodetectors). Etc.) is further provided over the prior art in that it does not need to be made. Furthermore, the process does not require that vias be placed only around the chip in areas that would be placed with conventional wire bonding pads. Rather, this simple process can be performed more locally and can be performed at a sufficiently low temperature to place vias at locations other than the periphery of the chip so that vias can be formed after forming or incorporating a circuit in a semiconductor. . This makes it possible to use this process together with chips produced by other processes without being involved in the design process of these chips, and to connect using wire bonding pads as will be described in more detail later. It is possible to create connection paths between devices on different chips that are much shorter. In addition, as will be described in detail below, the process is very useful for creating a stack of chips, or a mix or combination of chip “units” because the process can easily create a path through the wafer. It is.

  One problem that may arise in connection with filling the groove with an electrically insulating material is that the pin of the electrically insulating material is particularly problematic when the width of the groove is narrow and relatively deep, eg, when the depth is 100 μm or more. That is the possibility of holes, bubbles or other defects. If these defects remain, there can be an undesirable conductive path between the doped semiconductor material of the device and the conductors therein that the trench penetrates.

  The advantage is that if this is a potential problem or concern, the alternative variations shown in FIGS. 17-23 can account for the problem or concern.

  FIG. 17 shows a schematic cross-sectional view of portion 100 of FIG. 5 as a result of processing according to the following alternative variation.

  Although similar to FIG. 7, unlike FIG. 7, a via trench 1700 is created and the entire island 306 of semiconductor material 122 within the ring 704 of insulating material 500 is not removed. Rather, the via groove 1700 has a smaller diameter than that of FIG. 7 so that the peripheral volume 1702 of the ring of semiconductor material 122 remains. The surrounding volume 1702 of the semiconductor material 122 is electrically isolated from the semiconductor material 122 of the device 104 because it is bounded by the insulating material 500 and the substrate 112. In addition, because the entire semiconductor material 122 is formed completely and homogeneously, any defects in the insulating material 500 inside the trench 302 are isolated from the metallization in the via 1700 by the surrounding volume 1702 of the semiconductor material 122. . This method is the same as that described in connection with FIG. 7 except for the above description. Thus, the via groove 1700 is similarly fabricated to a depth 1704 that extends into the substrate 112, eg, by a further etching process or via another suitable process, such as laser drilling (but preferably Do not penetrate). Once the via groove 1700 is created, the sidewall 1706 of the groove 1700 and the bottom 1708 of the via groove 1700 are all non-conductive as described above, but the sidewall 1706 is insulated from the annular insulating material 704. The resulting semiconductor material 1702 is obtained.

  FIG. 18 shows the bottom of the particular region 124 of FIG. 1 immediately after creating a via groove 1700 within the annulus of semiconductor material 1702 delimited by the electrically insulating material 704, as shown in the side view of FIG. It is a top view of an AA cross section.

  FIG. 19 shows a schematic cross-sectional view of portion 100 of FIG. 5 as a result of further metallization of the alternative variation of FIG. 17 in the manner described in connection with FIG.

  FIG. 20 shows a schematic cross-sectional view of portion 100 of FIG. 5 as a result of further processing of this alternative variation of FIG. 17 in the manner described in connection with FIG.

  FIG. 21 shows a schematic cross-sectional view of portion 100 of FIG. 5 as a result of further processing of this alternative variation of FIG. 17 in the manner described in connection with FIG.

  FIG. 22 shows a schematic cross-sectional view of portion 100 of FIG. 5 as a result of thinning the substrate and exposing bottom metallization 1502 in the manner described in connection with FIG. 15 for the alternative variation of FIG.

  FIG. 23 illustrates the portion of FIG. 5 as a result of thinning the substrate to remove the bottom metallization 1502 and exposing the adhesive 1102 in the manner described in connection with FIG. 16 for the alternative variation of FIG. 100 shows a schematic cross-sectional view.

  Based on the above description, further alternative variations having double insulation (ie, coaxial or coax) conductors can be generated. Double conductors are advantageous because they can increase contact density and reduce crosstalk. Furthermore, due to the variant of the double conductor, it goes without saying that the outer conductor is electrically separated from the inner conductor, so that both can be operated at different voltages, and one conductor has electromagnetic interference ( EMI) acts as a shield to protect against signal noise, or signals can propagate separately through the structure so that low noise data can be transmitted. Furthermore, as with the single conductor approach, only the annular groove is the only lithographically defined precise etch that is performed. As will be seen in the following description, the removal of the central material is controlled by the boundary metal and is therefore unaffected by process variations inherent in photolithography-defined steps or etching. Therefore, this method is also highly reproducible and robust to the process.

  Two exemplary coaxial variants are shown in FIGS. 24-29B as follows. These variants are suitable when the outermost conductor can be brought into direct contact with the semiconductor material without adverse effects. Thereafter, an exemplary alternative coaxial variant is continued in FIGS. 30A and 30B. The alternative dual conductor variant of FIGS. 30A and 30B is similar and improved to the alternative variant shown in FIGS. 17-23, and similarly to illustrate the same problems or concerns. Is suitable.

  Initially, the basic double conductor generation process follows the approach described in connection with FIGS. Since this variation is built upon what has been previously described, only the additional or different aspects associated with this variation will be described for simplicity. Others can be understood from the preceding description. Accordingly, processing according to this alternative variant of double conductor is as follows. Initially, as shown in FIG. 24, at least the sidewall 304 of FIG. 3 is metallized 2402, as described above. It should be noted that the bottom surface 2400 of the groove 302 may or may not be metallized, as will be apparent from the following, this does not affect the final result. FIG. 24 shows a schematic cross-sectional view of the portion 100 of FIG. 3 immediately after metallization according to this variant.

  Following metallization, at least the trench 302 is filled with an electrically insulating material 500. The result of this step is shown in FIG.

  As shown again in FIG. 26, the entire island 2406 of the semiconductor material 122 defined by the inner periphery of the ring 2602 of the metallization 2402 is removed to create a via groove 2600.

  As an alternative, as shown in FIG. 27, an approach similar to that of FIG. 17 can be used at this point (ie, instead of removing the entire island 306 of the semiconductor material 122 inside the ring 704 of the insulating material 500). Only the inner portion 2702 is removed, leaving an annular volume 2704 around the semiconductor material 122).

  On the other hand, after this, the present technique is basically the same as described above. Via grooves 2600, 2702 are made to a depth extending into substrate 112, for example, by further etching processes or via another suitable process, such as laser drilling or ablation (but preferably not penetrating). ).

  The via grooves 2600, 2702 are then filled with a conductor 2802, and the substrate is thinned as described above. In the case of the double conductor variant of the first embodiment (FIG. 28A), as shown in FIG. 28B, the bottom metallization is removed and the inner conductor 2802 is thinned until it is exposed on the side of the substrate 112. Is done. In the case of the double conductor variant of the second embodiment (FIG. 29A), it is thinned until the bottom of the metallization is exposed with the inner conductor, as shown in FIG. 29B. It should be noted that in the variant of FIG. 28B, one conductor is made by the outer ring of metallization 2804, and both the inner ring and inner conductor 2802 of metallization 2806 are in contact and short together, so the other A conductor is made, whereas in the variation of FIG. 29B, one conductor is made of metallized 2402 and the other conductor is made of inner conductor 2802.

  In the double conductor variant as shown in FIG. 28B, it is thus highly likely that both the depth of the ring 704 and the depth of the via groove 2700 both exceed the point where the substrate is ultimately thinned. desirable. In other words, if the total thickness of the wafer is 500 μm and the wafer substrate is thinned down to 200 μm, the depth of the via groove 2700 must be at least 300 μm plus the appropriate thickness of the metallization. Therefore, it is considered that the original depth of the ring 704 needs to exceed the depth of the via groove 2700. The reason for this requirement is that electrical insulation between the two conductors is necessary. The above explanation also explains that in some implementations, the coating defects at the bottom of the trench 302 are removed anyway during the thinning process and thus have little or no effect.

  Based on the above description, it goes without saying that, similar to that of FIG. 28B or FIG. 29B, an alternative coaxial variant can be created simply by making the sidewalls of the groove non-conductive and then metallizing. This can be done, for example, by applying a thin dielectric coating to the sidewalls, eg, by dielectric sputtering, plasma deposition, or by generating the initial annular groove in advance (ie, prior to electronic device fabrication) Or by using steam oxidation techniques. This technique involves exposing the sidewall to a reactive gas and oxidizing it in the case of a silicon wafer (conceptually equivalent to iron rusting) to form a thin film of silicon dioxide on the sidewall surface. As a general overview, silicon oxidation can be performed in a steam environment based on the Deal-Grove model. This technique allows oxidation to be performed in a highly controlled and accurate and reproducible manner. Similar processes can be used to produce silicon oxynitride or silicon nitride coatings. According to this variant, the resulting oxidation is only thermally grown and not deposited, so it is uniformly formed, thereby inherent problems with applying a liquid, viscous, paste or other form of dielectric. It is an advantage not to invite. In addition, this approach produces a very uniform and highly controllable dielectric material coating over the entire surface of a 12 inch silicon wafer to a depth of 1 mm or more with extremely high accuracy tolerances. Furthermore, the process has the effect of smoothing the side walls, so that the metallization becomes more uniform.

  Needless to say, this further alternative variation may not be suitable for some applications due to the dielectric constant of silicon dioxide, silicon oxynitride or silicon nitride, or is not relevant to the understanding of the subject matter described herein. It may not be possible to implement due to other factors. Also, the present technique is the same as that described above in connection with any of the variations described above in connection with FIGS.

  FIGS. 30A and 30B, respectively, show an embodiment shown as an optional addition to the approach of FIGS. 28 and 29, with the addition of a thermally generated dielectric or insulator 3002 embodiment for completeness. . Similarly, it goes without saying that in some variations of FIG. 30B, that is, in some variations that only remove a partial inner island to leave a small ring of semiconductor material in the via trench, it is thermally generated. Dielectric techniques can be used to form a dielectric coating on the remaining small annulus. However, prior to device generation, this aspect may be performed following means to ensure that the process does not damage any devices already formed in or on the chip, or As long as any device in or on the chip is either affected by the process, this aspect is performed on the chip.

  Alternatively, the partial removal can be the reverse partial removal, i.e., the inner island is removed inward from the via groove, leaving a smaller island inside the via groove. This variation will make this narrow island useful as a post where contacts can be built and connected to metallization or conductors. Similarly, partial removal can be partial removal by depth perspective, leaving wells or depressions that can be used as the female part of a male / female connector, or if conductive It can serve as an electrical contact.

  As is clear from the above description, as shown in FIG. 31, the three conductors (ie, triaxial or triax) variants are thinned to the range shown in FIG. 28A using the technique obtained in FIG. 28B. The advantage is that it can also be constructed simply by doing (ie until the groove bottom metallization material is completely removed). The three conductor variants allow the outer metallization to act as a shield between the inner metallization and / or conductor and the semiconductor material mounting the nearby device, Advantageously, the metallization between the inner conductors can act as a shield between them or as a third conductor. Thus, the same three conductor variants provide several alternative advantages in themselves. Needless to say, any one item (ie coating (thermally generated or applied), void filling) in terms of the relationship between a single conductor, two conductors and three conductor variants. All options that describe usage for post-penetration contacts (described below) are generally interchangeable and applicable to all.

  As briefly mentioned above, it is not always necessary to try to fill anything anyway with the remaining voids that exist after removing the central island of material. Furthermore, some implementations described herein have certain advantages over not performing.

  FIG. 32 shows a schematic cross-sectional view of a chip mounting portion 100 disposed on top of the electronic chip 3200 (similar to the mounting of FIGS. 9-16 except that no void 3210 remaining after metallization is filled). The chip 102 is hybridized to the electronic chip 3200 so that the contact pads 3202 on the electronic chip 3200 to be electrically connected to the top contact 904 of the laser 104 are directly under the void 3210. When a solder bump or other softenable, deformable conductive material 3204 is on the contact pad 3202, using it to insert this portion of the two chips 102, 3200 under capillary action or pressure They are physically and electrically coupled to each other by any of the deformations.

  FIG. 33 is a schematic cross-sectional view of an alternative chip mounting portion disposed on top of electronic chip 3300 similar to that of FIG. 23 except that void 3310 remaining after metallization is not filled as in FIG. The chip 102 is hybridized to the electronic chip 3200 so that the contact pads 3302 on the electronic chip 3300 to be electrically connected to the top contact 904 of the laser 104 are directly under the void 3310. Solder bumps 2404 are on the contact pads 3302 and are used to physically and electrically couple this portion of the two chips 3302, 3300 to each other.

  Since the voids 3210, 3310 are not filled in the implementation of FIG. 32 or FIG. 33, capillary action can be used to pull the solder 3204 into the voids 3210, 3310, or pressure can be used to deform the deformable material 3204. Can be placed in the void, which helps a) ensure good electrical connection and b) align the chips with each other.

  34 and 35 show cross-sectional views of FIGS. 32 and 33, respectively, immediately after the chips are hybridized to each other. As can be seen, the solder contacts 3202 are each centered on the contacts 3202 and 3302 of the respective electronic chips 3200 and 3300 to be hybridized, so that the solder 3202 has a respective void 3210, It has just been sucked into 3310.

  As shown in FIG. 36, for the implementation of FIG. 34 (the same is true for the implementation of FIG. 35, but not shown), an insulator coating or an insulating protective coating 2800 may optionally be performed. it can.

  As briefly described above, regardless of the variation used, the annular groove (and around the semiconductor material if that variation is used) can be any closed shape. However, as an extension of the above, it goes without saying that the via groove need not be the same shape as the annular groove or the width of the annular groove need not be uniform, but in most implementations both are the same shape. Yes, for ease of implementation and for capacitance, resistance, or both. FIGS. 37a) to 37f) show a few examples of the cross section of the annular groove to show the main points. In FIG. 37a), the annular groove 3702 is shown as being triangular. As a result, the width 3704 of the groove 3702 is wider than the side 3708 at the triangular vertex 3706. In FIG. 37b), the annular groove 3710 is shown as a rectangle. As a result, in the corner 3712, the width of the groove 3710 is wider than the side 3714, and the long side 3716 is farther away than the short side 3718. In FIG. 37c), the annular groove 3720 is shown as being defined by two different ellipses. As a result, the width of the ellipse of the annular groove 3720 varies depending on the position. In FIG. 37d), the annular groove 3722 is shown as a square. As a result, in the corner, the width of the groove 3722 is wider than the side, but the side is separated by a uniform distance, in FIG. 37e), the annular groove 3724 is rectangular and the outer periphery 3726 is rectangular but the inner periphery 3728. In, it shows as a circle. In FIG. 37f), the annular groove 3730 is circular at the outer periphery 3732 but shown as a rectangle at the inner periphery 3734. In FIG. 37g), the annular groove 3736 has a concave-convex shape (kidney shape), the outer periphery 3738 and the inner periphery 3740 are in a scaled relationship with each other, and the groove width is constant. In FIG. 37h), the annular groove 3742 has an outer periphery 3744 and a hexagonal inner periphery 3746 similar in shape to FIG. 37g).

  The above expansion applies equally to variants having a ring of semiconductor material in addition to the ring of insulator, i.e. the shape of each peripheral surface is the same as the other, depending on the requirements or demands of the particular application. Or one or more shapes can be changed from one or more other shapes.

  In addition to the inherently obtainable advantages, from the above use to the final creation of a connection between two chips, the above approach can be used in the area of a stack of chips, dies or wafers, in particular chips, dies or It provides significant advantages when the wafer is preprocessed. For example, it is a case where the device is formed from a completely functional aspect, including some functional devices such as transistors, capacitors, diodes, switches, resistors, capacitors, and the like.

  Generating vias using an annular via process provides a method of stacking wafers in a manner that allows electrical conductivity and requires little or no post-processing after fusing the wafers. . This is very advantageous in terms of cost and yield, especially at the wafer level where two wafers are hybridized to each other or where a large number of individual chips are mounted on the wafer. When two wafers are placed on each other, one important thing to understand is that two hybridized wafer pieces (ie, after placing two wafers on each other) are converted into a single wafer piece ( That is, it has a much higher value than a single wafer immediately before hybridization. Similarly, when three wafer pieces are stacked together, the value is even higher. Any post-processing that must be done to a series of stacked dies after integration adds significant risk, as damage can scrap very high value-added pieces.

  In this way, the process provides a much better approach since all via processing and thinning steps are performed before stacking the device. As a result, there is no additional wafer processing and only one layer is stacked on top of another (wafer) for via formation bonding (ie, hybridization) where post-processing of on-chip devices is done prior to hybridization. Fully stack ready pieces are generated. Chips are stacked in the above manner, but the value of the combination will only increase, so it is typical to give another layer, i.e. only one step to give the next die ( Unless needed to be thinned but not executed before hybridization). This minimizes the risk of reduced yield of expensive components due to post-processing associated with prior art stacks that stack chips and then generate electrical contacts.

  Thus, compared to the prior art, creating vias and then stacking allows you to:

  1) Reduce or eliminate post-processing of stacked pieces (high yield can be obtained with little effort).

  Increased alignment tolerances (just align each chip to the chip directly below (as opposed to prior art stacks where all pieces need to be aligned to the bottom piece in common) Is)).

  FIG. 38 illustrates the process for preparing a wafer for stacking in a simplified and overall overview. FIG. 38A) shows in simplified form a portion of the initially fully formed wafer, in particular the device 3802 and its underlying substrate 3804. The whole process is as follows. First, material 3806 is deposited on the device side of the wafer (FIG. 38B)). The material 3806 and the underlying contact location are then etched to create a groove 3830 (FIG. 38C)). The wall 3810 of the groove 3808 is insulated 3812 to prevent the doped semiconductor material from being potential shorted with the generated contact (FIG. 38D)).

  Alternatively, material 3806 can be “automatically” generated during the deposition of insulating layer 3812. For example, we formed (oxidized) TEOS on the wafer by removing the initial deposition of material 3806, etching the trench 3808, and then depositing TEOS. Due to the circumstances of depositing this material, a 2.5 μm material was formed on the upper surface of the wafer and a 1.25 μm was formed on the groove wall. This provides an alternative approach in which a thick upper layer is obtained while covering the groove walls. In other words, according to this alternative method, the step of forming material 3806 as a separate step can be eliminated or used in conjunction with the remaining steps depending on the topology of the wafer.

  Metal 3814 is then introduced into the trench to provide a seed layer for plating the conductor (FIG. 38E)). The remaining via volume is then filled with metal 3816, which becomes a conductor (FIG. 38F)). The excess metal (and optionally some material 3806 and / or insulating layer 3812) is then removed, for example by a chemical or mechanical process or some combination thereof (FIG. 38G)). The wafer is then etched to create openings 3820, 3822 that provide access to the original, existing contact locations 3824, 3826 (FIG. 38H)). Next, a film is formed with metals 3828 and 3830, and existing contact locations 3824 and 3826 are interconnected with contacts 3832 and 3834 formed by a new process (FIG. 38I). Next, the backside 3836 of the wafer is thinned to expose the other ends of the contacts 3832, 3834 that have been processed and optionally the insulator 3812 at the bottom of the groove 3808 is removed (FIG. 38J). The wafer back side 3836 is then etched to produce raised posts 3838, 3840 that are removed if the insulator 3812 at the bottom of the groove 3808 was not removed in the previous step (FIG. 38K)). . Alternatively, in some implementations, the insulator 3812 may be partially removed if conductivity is not required, for example, simply to align or use to create a non-electrical post-type connection. It may or may not be removed at all. Finally, if the exposed filler material that becomes the post is of a type that oxidizes or otherwise reacts to adversely affect the connections that will be formed later, an optional barrier layer 3842 may be provided with raised posts 3838, 3840. It can be formed on top to prevent oxidation or other such adverse reactions.

  The steps of FIGS. 38J), 38K), and 38L) are performed after film forming a malleable material (for use described below) on top of the metal 3828, 3830, as yet another alternative variation. be able to. This variation reduces the number of steps to be performed after thinning the wafer.

  At this point, an entire through-chip connection has been created that facilitates chip, die or wafer-based stacking and thus forms one or more multi-wafer units.

  FIGS. 39-41 are schematics of portions of an exemplary chip that have been processed to create a through-chip connection using different variations of the process described above, and then stacked together to form a chip unit. Indicates. In particular, FIG. 39 shows a corresponding portion 3900 of a series of stacked chips that are interconnected using a variation of the basic approach. FIG. 40 shows a corresponding portion 4000 of a series of stacked double conductor variants of the chip. FIG. 41 shows a corresponding portion 4100 of a series of stacked triple conductor variants of the chip. Not to mention from the above description, by utilizing one of the processes described herein, there is no need to organize by a coplanar method, or even by a complete overlapping method. Stacks and units can be formed from wafer components that can still extend longitudinally.

  Note that optional contact pads 3902, 4002, 4102, 4104 are added as standoffs to each of the three stacks of FIGS. 39-41 to ensure proper spacing between wafers and good electrical contact. To.

  Depending on the particular application using the above, the contacts can be formed in several ways. For example, the via can be a microbump, for example, in a prior art C-4 solder mold process, so that two points to be electrically connected can be placed in the contact, and the solder is in a liquid phase. Then, the two pieces are cured to physically and electrically bond. In other variations, a pair of contacts can be used, with one pair of contacts being a rigid body and the other contact being relatively malleable, using the process described herein. Join them together. In yet other variations, both mating contacts can have malleable material thereon and are coupled together using a suitable process or other process as described herein. Alternatively, a prior art post-socket type approach can be used. In this approach, two mating contacts are made in complementary shapes and the post is slightly larger than the socket or the socket is slightly smaller than the post and the two When they are joined, an interference fit is generated between them.

  In certain cases, it is desirable to ensure handling strength using a thicker wafer (FIG. 42A). In situations where the wafer is particularly thick and the desired via diameter is less than about 1/20 to 1/30 of the desired thickness of the wafer, an alternative process may be used for some variations to produce a thicker wafer. Can be adapted. The process of forming such “back-to-front” vias is shown in simplified form in FIGS. 42B) -42E). First, vias are etched into the backside of the device-mounted wafer (FIG. 42B)). The via is then made conductive using one of the processes described herein (ie, single conductor, coaxial, triaxial, etc.) or by some other process such as inserting a preformed post. (FIG. 42C)). This approach can create a backside with either malleable material or rigid post material. The corresponding via on the conductor is then etched from the top (ie, front or device side) down to the end of the bottom of the back side conductor (FIG. 42D)). Next, optionally protect the front side device and, if desired, contact or reroute to the device, for example using the techniques described herein (not shown), for the back side. Make the via conductive in essentially the same way as it did (FIG. 42E)). In some variations, the bottom material of the backside conductor has the advantage that it serves as an etch stop and / or seed layer for plating the conductor from the front side. This can reduce the number of processing steps compared to the technique used to form the conductor on the back side. Further, in other variations, if it is desired that there be no physical connection between the conductors from the back via and the front via, an appropriate amount of wafer can be left between them. In that situation, the connection is made by capacitive coupling.

  This approach can be performed with a conventional via process that performs a single via and deposits insulator and metal in one hole, or by an annular via approach to produce a highly controlled impedance via. It works in our process described above.

  In addition, a back-to-front approach can be used, where one side has an incompletely filled via so that the unfilled portion of that via can serve as a “slot” to receive a “post”. Can (ie, press fit or interference fit), thereby providing alignment and / or physical and electrical connections. This type of press-fit or interference fit is illustrated in FIG. 42F).

  In another alternative variation, the via-generated back-to-front method described above can be used to create a connection that only pierces the chip halfway to allow for interchip data transmission using capacitive coupling. Capacitive coupling works the closer the contacts are, and the connection density is limited by crosstalk, so the variation of the approach described here is ideal for producing chips that use this type of communication. Is. These approaches allow the distance between the contacts to be minimized and, moreover, the use of coaxial, triaxial posts to provide a shield can immediately minimize crosstalk due to close proximity connections. Furthermore, capacitive contacts have the advantage that no actual electrical contacts between parts are required. 43A) -43D), the vias are etched from the back of the chip in a manner that is sufficiently close to the contacts on the top surface of the chip (FIG. 43B)), physically separated from the contacts, When filled, close enough to provide good capacitive coupling of the signal applied between the filling and the contacts. The via is then filled with a metal stud, single conductor, coaxial or triaxial conductor to allow good capacitive coupling (FIG. 43C)). In this way, the overall thickness of the wafer can be maintained so that the handling strength of the wafer is sufficient and the connections are at an appropriate distance. This approach further provides the advantage that stacking can be done by stacking the back side of one wafer to the front side of another wafer. In this way, multi-stacking of chips can be performed as shown in FIG. 43D). This is in sharp contrast to the approach where the chip needs to be face-to-face rather than front-to-back. The reason is that in such an approach, the third chip is placed on the back of one of the other two chips, and then across the wafer where sparse contact density is required to avoid the possibility of crosstalk. This is because, since communication must be performed, it is not easy to make a multi-stack of chips (that is, a stack of three or more chips). Needless to say, according to the method described in this specification, signal shielding can be strengthened and crosstalk can be prevented by using coaxial or triaxial vias.

  In addition, for example, if a true back-to-front connection is not created in the sense that the two vias are not connected (ie, if material remains between the via generated from the front side and the back side post), press Capacitive coupling by mating connection can be used. In such a case, the front side vias are generated independently, similar to the back side vias, based on one of the variations described herein.

  Furthermore, capacitive coupling can be performed between one or more contacts on one chip surface (which can be generated by via techniques or other techniques). This is the case, for example, in the stacking approach, where two complementary contacts are close to each other but cannot be physically easily contacted due to the chip height, for example, a chip or metallization that interferes with the two or It may be desirable if there are other topologies, or one or both are covered by an insulator such as TEOS, photoresist or some other oxide.

  From the above description, the versatility of our technique should become more apparent. There is the advantage that further variants can be generated that show the range of wide and versatile possibilities that can be utilized through our approach. One such variant shown in FIG. 44A) is a “pre-connect” variant, which differs from the above and many approaches. This is because the processed wafer is “pre-” (ie, before the annular groove is formed) “beginning” of processing as described herein (ie, before the annular groove is formed). This is because it is referred to as a “base” wafer in the specification. In this variant, any basic connection formation process can be used. This variant process proceeds as follows.

  Initially, the initial wafer is thinned to the extent necessary to ensure that the via penetrates the substrate completely and reliably (FIG. 44A)). This step is optional and may not be performed if the particular etching process used penetrates the entire chip without problems. The initial wafer is then aligned to the base wafer (FIG. 44B)) and bonded using a covalent bond if the adhesive, wafer fusion, or wafer flatness is very good (FIG. 44C)). Next, an annular via is created in the initial wafer overlying the pad on the base wafer and extending to the base wafer so that the via surrounds the target pad of the base wafer (FIG. 44D)). The annular via is then filled with an insulator so that subsequent conductor deposits are insulated (FIG. 44E)). Next, all or a portion of the central post is etched away to the target pad of the base wafer to create voids on the base wafer pad (FIG. 44F)). Finally, the void is metallized (FIG. 44G) and optionally filled completely with an insulator using one of the techniques described herein (FIG. 44H)) or the metallization is centered on the void. If not completely filled, it can be filled with an insulator (FIG. 44I)). As a result, the metal fill makes an electrical connection to the base wafer pad, effectively extending the base wafer pad up through the initial wafer and physically bonding the two chips together. By using this technique, the central post made of semiconductor material protects the base wafer pad so that the insulator does not interact with the base wafer pad. This is because if you try to do the same using conventional techniques, these conventional techniques will leave the base wafer pad exposed and therefore can be contaminated by the applied insulator, so you know what will happen. There is a significant difference from not.

  However, in some cases, since there is no controllability, the press fitting connection method may not be suitable. In these cases, an optional alternative approach, called the “post-penetration” approach we have improved, can be used. Ideally, post-penetration techniques can be used in conjunction with the “tack-fusion” process, taking advantage of the benefits each provides alone, and the additional benefits provided by using a combination thereof. Would typically be used as such.

  This approach involves the use of a combination of two contacts, a rigid “post” contact and a relatively malleable (as compared to post material) pad contact, and in some cases either or both Has an underlying rigid support structure or standoff. In brief overview, one of the two contacts is a rigid material such as nickel (Ni), copper (Cu) or palladium (Pd) or other suitable rigid alloy as described herein. This contact serves as a “post”. The other of the two contacts is a material that is softer than the post, and when the two contacts are pressed and joined (either externally applied, for example, a force generated by bending the wafer), the post becomes a malleable material. Penetration (“post-penetration” part), heated to a temperature above the pre-defined temperature (tack-tack phase of the fusion process), and cooled below that temperature, both of which did not reach a liquid phase state. Are “tucked” together.

  It should be noted that as used herein, the term “liquid phase” is intended to mean a state in which the described metal or alloy is completely (or substantially completely) liquid. As used herein, when a metal is in a non-liquid or semi-liquid state, the metal is soft enough to adhere as described herein, but the same metal or alloy is a pure liquid or liquid. Not enough liquid to flow to flow in phase. Most variations of our process work with metals or alloys in non-liquid and non-solid states. Expressed on another method, a phase diagram of a metal or alloy, our process variant works between the solid (full solid) temperature and the liquid (perfect liquid) temperature, and most Operates near the equilibrium point between them. This difference can be further understood with reference to coupling the chip to another element, for example, as shown in FIGS. In these figures, if the material 2404 is a liquid phase solder (metal or alloy), the chip “floats” over the molten solder and capillary action sucks the solder into the vias 3210, 3310 so that the vias 3210 and 3310 are automatically centered on the solder balls. In the non-liquid or semi-liquid phase state, as used for most variations of the tack-fusion process described herein, the metal or alloy consists both during the tack phase and during the fusion phase. The condition will not be sufficiently liquid to float the chip or auto-center the vias 3210, 3310, although the metal or alloy will be significantly softened (ie, some of the material will be in a liquid state). That is the state. Thus, some force application (either externally applied or force generated by the weight of the chip without applying external force) is required to place the metal or alloy into the vias 3210, 3310.

  Subsequent heating to a temperature above another temperature above the “tack” temperature (tack-fusion stage of the fusion process) causes the materials from each to interdiffuse (ie, enter and exit the liquid phase (ie, melt). As opposed to solder).

  The integration process of tack-fusion can be separated into two main components: an “attachment” or “tack” stage and a “fusion” stage. The tack phase provides a fairly uniform electrical connection between a pair of contacts. When the formation of the post-penetration connection is combined with a tack process, any surface oxide on any contact can be wiped out more easily. This non-oxide blocking contact approach allows a simpler fusion process without applying significant pressure. In the absence of a combination of post, penetration, and tack stages, the fusion process will cause the oxides that form on the surface of the rigid and malleable materials, either in the hot section of the tack process, or early in the fusion process, Substantially more pressure is required to wipe the contacts. By removing the “fragments” of the oxide early in the tack process, the fusion stage can be generated at a substantially lower pressure, and in some cases, no pressure beyond the weight of the chip itself may be applied. .

  At this point, further terminology conventions are introduced. Needless to say, as described herein, the terms “daughter” and “mother” are used for simplicity and generally indicate whether the particular contact on the wafer under consideration is a rigid or malleable contact. Implied, the term “mother” is associated with a rigid contact, and the term “daughter” is associated with a malleable contact. It is important to note that the terms “mother” and “daughter” apply in principle, although they are shown fairly consistent one-to-one herein. The individual contacts on each wafer can be either rigid or malleable contacts as long as the corresponding contacts on the other wafer to be bonded are in the opposite form. Thus, a given wafer surface can have only (exclusively) only one or the other type of contact, or in some variations, a single wafer side can have a mix of both types. . However, mixing forms on a single surface can be problematic for some applications, and for those applications that use mixing forms, mixing forms on a single surface can complicate processing. However, when performing certain processing steps without intermixing different forms within one area (within a narrow area), a wide area that can easily protect areas containing other forms is only one type of contact. Excludes cases where it is confined to discrete areas to include.

  During the deposition or tack phase of the process, the “mother” wafer is loaded with a number of “daughter” chips. The mother wafer is maintained at a single temperature (ie, the mother wafer is maintained as an isothermal substrate during this deposition process). The isothermal temperature of the mother wafer can be as low as room temperature, but a temperature increase above room temperature will advance the phase of the process. However, the isothermal temperature is kept below the melting point of the malleable material on the daughter chip as well as the temperature of tack or fusion. Thus, the tack process is such that when two chips are brought into contact to make a post-penetration connection, each small daughter chip so that its interface only reaches or slightly exceeds the appropriate “tack” temperature. Can be performed by heating to a temperature higher than that of the mother wafer. In general, for the main materials described herein, the tack temperature could be about 190 ° C. to about 320 ° C., with a typical nominal tack temperature of about 270 ° C. In this way, the other chips on the mother wafer are not heated beyond the elevated temperatures experienced by their contacts, altering the performance of the contacts, leaving some contacts at a higher temperature than others. In situations where it can be experienced for a long period of time, uniform performance may not be achieved.

  The process of tacking or attaching, for example, holding the mother wafer at an isothermal temperature below the malleable temperature, bringing the daughter chip to the mother chip heated below the malleable temperature, bringing the two chips into contact, and the daughter This can be done by rapidly raising the temperature of the chip to the appropriate tack temperature. Thus, when the daughter chip is applied to the mother wafer, the mechanical device that aligns the parts (and then heats the daughter chip) will cause any contact between the parts to be less than 2 g / contact pair, for example, less than 1 g / contact pair. After applying enough pressure to allow, the daughter tip is released.

  After release, the cap / adhesive layer on the daughter chip (or the malleable layer if the malleable material also performs the function of the cap / adhesive layer) is more flexible due to the lowered temperature determined by the current mother chip. Decreases. For example, in the baseline material described herein, the mother chip / wafer substrate can be held at about 230 ° C. to 250 ° C., and the daughter chip is brought to the mother chip at a nominal temperature of about 270 ° C. and after contact, Raise rapidly to about 310-330 ° C. The order of contact for rapid temperature rise (ie, whether the temperature rise is before or after contact with the mother wafer) can be changed. It should be noted that we can minimize oxide formation on the surface of the malleable material by first contacting the tip and then increasing the temperature, and thus a more reproducible contact. Discovered that it would be possible. Advantageously, the use of malleable materials can reduce the amount of pressure per contact pair. We used applied pressures in the range of about 0.001 g to about 10 g / one contact pair, but lower ranges are possible, and the minimum is the effect of gravity on the mass of the chip itself (ie , Weight).

  Furthermore, as described above, if the pressure sufficient to crush any surface oxide is sufficiently applied to the tack process, the temperature of the daughter wafer can be lowered to about room temperature. In this way, any tack process can be started after the daughter chip is mounted on the entire mother wafer. Even with this approach, due to the speed at which the process takes place, there is no time to heat the mother wafer to any substantial temperature. Accordingly, when the second daughter chip is attached to the mother wafer, the cap / mounting layer of the first chip affects the alignment to a meaningful or substantial extent even within 100 μm of the horizontal or vertical direction of the first chip. Does not soften.

  The tack-fusion process typically has the advantage that both are non-liquid phase processes. This means that the process is performed so that the malleable material softens significantly in both the tack or fusion process but does not become a complete liquid phase. This is because if the malleable material goes into a liquid phase, the resulting liquid flows, creating a significant risk of shorting adjacent contacts. By keeping the material in a non-liquid phase, the contact density can be further increased. However, depending on the variant, a semi-liquid phase state is also acceptable (i.e. only a part of the malleable material, but only a part much less than the whole, is easily in the liquid phase). However, these variations generally use some other type of restraining mechanism to limit the liquid phase malleable material to a limited area and avoid the possibility of shorting adjacent contacts, for example, A common property is that non-metallic materials that cannot be easily interdiffused by the spreading material, and that the liquid-phase spreading material is prevented from being adversely affected by reliably surrounding or covering the periphery of the pad forming the malleable material Have

  In some variations, in cooperation with the “tack” phase of the tack-fusion process, an adhesive layer (eg, Sn) that melts at low temperatures to help reduce tack time and increase throughput, with malleable material ( For example, it is desirable to cap (Au / Sn alloy). Further, in some variations, bonding occurs when the chip is left at that temperature for an extended period of time (ie, the time required to load a large amount on the entire wafer) in an uncontrolled environment. It may be desirable to maintain the mother wafer at an isothermal temperature as high as possible below the fusion temperature so that degradation does not occur. We are typically too high for process shortening, but use 230 ° C. Lower temperatures have the effect of modifying the temperature and pressure profile of the penetration phase of deposition. In order to further shorten the process, it is desirable to perform the tack phase sequence (ie, place and heat) as quickly as possible. A further aspect to note is that, depending on the variant, the longer the tack phase is spent, the less influence the fusion phase has on yield. For example, in an extreme case, we continued the tack phase on FC150 (for silicon to silicon) for about 1 minute, but did not obtain the necessary fusion phase. This is summarized in FIG.

  In another extreme example, for mass loading, alignment typically takes about 1 second, and the tack phase takes 2-4 seconds before the fusion phase. Thus, in these variations, the environment for transporting from the tack machine to the fusion stage is important to obtaining good contacts.

  Between these two extreme examples is a continuum of process options that are a trade-off between 1) throughput, 2) complexity, and 3) critical issues of the fusion process. In a very fast 2-4 second change tack process, the tip will only be held lightly, which may require a reducing environment during the fusion phase, or a more sufficient amount of application during the fusion. Pressure may be required. At the other end of the continuum, a one minute tack process is performed at higher pressures and temperatures, and the tack itself can perform pre- "fusion" of the chips relatively well. In this case, the subsequent “fusion” process need only be a contact anneal (or pressure if the planarity of the chip placement during “tack” is sufficient) in conjunction with a method that ensures consistency across the wafer. No specific environment is required. This continuum is shown in FIG.

  An important advantage of the tack stage is that the electrical connection is not final and can not be facilitated, so that after the tack process is finished, the chip inspection can be performed before the fusion process begins. In the point. This allows for inspection and identification of defective dies both before and after this first stage of hybridization (ie, individual chips that have been executed prior to hybridization to another chip are To determine if it has been adversely affected by the process, or in combination with the applied chip). Further, when the daughter chip that has been diced is mounted on the mother wafer before dicing, the inspection can be performed before the mother wafer is cut, that is, diced.

  A further important advantage of using the tack stage is that the chip combination is not very strong, so if a subsequent test determines that one of the bonded chips has not been performed, the bonded chip can be easily disassembled. Can do. Separating the two chips from each other can be performed using heat or pressure or a combination of both. If an individually diced daughter chip is mounted on a mother wafer that has not yet been cut or diced, another daughter chip known to be good if the daughter chip was a problem. Can be applied to the mother wafer. When a specific mother wafer chip is defective, it can be notified that the daughter chip is not attached any more, and can be easily identified immediately after the wafer dice cutting, and the overall yield is remarkably increased. Increase. Furthermore, if the mother chip does not function, the removed daughter chip can be stored for later application to the mother chip, which may further improve the yield and reduce the cost. For example, assume that the malleable contact of the daughter wafer is gold-tin or gold-silver-tin alloy and the malleable cap is tin. Tin can adhere at low temperatures, and if it is thin enough, it will not spread like a thick solder ball. If the daughter chip is found to be defective in the inspection, individual chips on the mother wafer can be heated and peeled off to give another daughter chip. When all the daughter chips are attached and the combination inspection is good, the whole mother wafer is fused together.

  In this way, the tack-fusion technique allows the integration of only those dies that are known to be good. Furthermore, this approach significantly reduces the risk associated with a stack of multiple dies because a single bad chip does not need to scrap the entire stack. For expensive chips or stacked units, this is an inherently / very valuable advantage.

  Furthermore, the tack-fusion stage has the added advantage of being a low pressure process. The force used in both the tack-fusion stage is typically less than 2 g / contact pair for contacts below 50 μm pitch. In the fusion phase, we verified the use of force from 0.8 g / contact pair to 0.001 g / contact pair. The inventors used 300 g for the 400 contact tip and also used 300 g for the 10,000 contact tip, which is in the range of 0.75 g to 0.03 g / contact pair. When the number of contacts is large, for example, 900,000, the present inventors used 3 kg to be 0.003 g / contact pair. Ideally, the technique should use the least possible force to increase speed, and under proper circumstances, the force imposed by the gravity applied to the chip itself (ie, the weight of the chip) ) Do not use any force exceeding.

  Conventional processes for applying dies to each other require adhesion strengths of several grams to tens of grams per contact pair. This generates tremendous stress on each of the semiconductor chips and often leads to damage or cracking. Thus, the described technique dramatically reduces or avoids imposing the stress levels found in conventional techniques.

  Furthermore, conventional approaches are not compatible with the small size dimensions available to the inventors. A typical soldering process is a liquid phase process that is not compatible with such small sizes and pitches and is not compatible with several g / contact pair pressure. In other words, at a typical value of 5 g / contact pair, a chip having 10,000 contacts of 1 cm × 1 cm requires 50 kg for adhesion. In contrast, the pressure during the fusion portion of the process is typically below the pressure used in the deposition process. For example, using the fusion process described herein, a 10,000 contact tip that requires 300 g of pressure during the tack phase requires only 9 g during the fusion phase of the process.

  Furthermore, since little or no pressure is used, multi-reflow / multi-high stacks become practical. To create a multi-chip high stack, the amount of pressure applied to the chip is high during chip fusion, especially when some chips on the mother wafer receive a taller daughter chip stack than others It should be low to prevent chipping, yield loss, the possibility that the lower chip in the stack is not connected, and the like. If the pressure applied to the mother wafer and the daughter chips during the fusion process is fairly high and some mother chips have a much larger stack than others, to maintain the correct pressure applied to each chip A complex touring set will be required. In contrast, our approach, which requires only light or zero external pressure, can avoid this, making multi-high chips much more practical and tolerating stack differences over twice as high. it can.

  A further advantage of the approach variations described herein is high strength after the fusion process is complete. The strength of the contacts after the fusion process is typically over several hundred kg / cm @ 2, with 1000 kg / cm @ 2 being typical. Needless to say, as a result, once the fusion process is complete, the possibility of rework is dramatically reduced.

  Exemplary exemplary malleable materials not intended to be limiting include gold-tin (Au / Sn) and silver-tin (Ag / Sn) and others specified herein. It should be noted at this point that the term “post” is simply used to mean stiffness. It is never intended to limit or enforce size, shape or geometry. Thus, as described below and in the “Specific Variations” section, a “post” can be wider than it is tall, or any sufficient to achieve the intended purpose described herein. The cross-sectional profile can be as follows. Further, “posts” can be generated as part of the process described herein, for example, by thinning the wafer backside without thinning the metallization or metal contacts, or generated separately. It can then be attached to or inserted into the wafer.

  When a stack is involved, a given electrical connection through the wafer has a rigid contact at one end and a malleable contact at the other end. In such cases, for the sake of simplicity herein, once the wafer is designated as “mother” or “daughter”, the term correctly refers to the “daughter” wafer with respect to subsequent stack layers. Even if the “mother” wafer should be pointed out, the contact point of interest here is a rigid contact for forming a post-penetration connection and is used as is. For further clarity, the subsequent “daughter” wafer connected to the other end will be referred to as “daughter wafer 2”.

  47 and 48 show an embodiment of the present technique. 47A) and 48A) show complementary contacts 4702, 4704, 4802, 4804 on two respective chips 4706, 4708, 4806, 4808. For simplicity, neither electrical connections 4710, 4810, nor other elements, if any, are shown beyond the immediate vicinity of contacts 4702, 4704, 4802, 4804.

  As shown in FIGS. 47A) and 48A), one of the contacts 4704, 4804 is a rigid contact, and the other contact 4702, 4802 is a malleable contact. 47B) and 48B) show the respective contacts 4702, 4704, 4802, 4804 at the time of contact with each other. By applying pressure before or during the tack phase, rigid contacts 4704, 4804 enter malleable contacts 4702, 4802. FIGS. 47C) and 48C) show the contacts after the fusion stage where the two materials have interdiffused and formed a high strength bond between them.

  Further, it is worth noting that the “width” of a malleable contact can be “minimum” in the sense that it is generally the same width or narrower than the contact to be connected (prior to coupling), or An “extended” contact can be made in the sense that the width is sufficiently expanded beyond the minimum width. In the above embodiment, FIG. 47 is an embodiment including a “minimum” contact, and FIG. 48 is an embodiment including an extended contact.

  In general, it is advantageous to make the malleable contact size slightly wider than the rigid contact, i.e. use an extended contact. By doing so, the malleable contact wraps around the rigid contact, in which case the rigid contact only has to enter somewhere within the area of the malleable contact, so the alignment accuracy between the two integrated chips is low. Also good. As a result, it is possible to adapt to a larger alignment shift. This is understood by way of illustration considering circular cross-section malleable contacts having a diameter of 12 μm and circular rigid contacts having a diameter of 10 μm to 6 μm. For rigid contacts with a diameter of 10 μm, if there is a 3 μm shift, the edge of the rigid material will exceed the limit of malleable material. For a 6 μm diameter rigid contact, a 3 μm offset will still fit within a malleable contact material of 12 μm diameter. Typically, the end of the rigid contact is less than 40 μm at the widest point, and may be less than 25 μm, less than 15 μm, or less than 10 μm at the widest point. Furthermore, in this approach, the malleable contact should be at least as wide as the rigid contact, preferably 20% or more wide. Further, the height of the post may be greater or less than its width, but typically the width is wider than the height.

  With the basic description above in mind, by utilizing a suitable rigid material as one of the metallized or conductive materials, for example, so that it can be used as a rigid contact, and other components or stacks Forming the second additional malleable material on another part of the metallized or conductive material so that it can serve as a malleable contact for application to the variant described above. Can be extended.

  FIG. 49 shows a portion of a stack of semiconductor chips, similar to that of FIG. 41, each having a through-chip connection generated based on one of the implementations described above. For simplicity, through-chip connections are not shown as being connected to any device on each chip through which the connection passes. This is because the presence or absence of such a connection is not always necessary for understanding the post-penetration technique.

  As shown in FIG. 49, optional contacts 4902, 4904 are added to the top and bottom of metallization 2412 and conductor 2802 to help connect each chip to the top and bottom chips. As mentioned above, metallized or metal contacts can be used directly. Depending on the particular implementation, when adding optional contacts 4902, 4904, the contacts 4902, 4904 may be any prior art type, simple conventional contact pad, non-shaped as described herein. It can be a post-penetration contact or a post-penetration contact as described herein.

  Therefore, it goes without saying that the stack can be executed more easily by using the post-penetration method of FIG. FIG. 50 shows a portion of a simplified stack of the chips shown in FIG. 49 that are stacked using a post-penetration approach.

  Furthermore, variations of the specific implementation described above can be generated to aid in the use of the post-penetration contact approach. For example, in a similar implementation, except for the one shown in FIG. 15 (ie, if the metallization at the bottom of the groove has not been completely removed) and the absence of adhesive 1102 and finish 1302: The metallized 1502 can be used as one of rigid or malleable contacts where the second material inserted into the void is the opposite (ie, rigid if the metallization is “malleable”, metallized is “rigid” In this case, it serves as a contact point for malleability. In such an implementation, as shown in FIG. 51, voids within the metallization can be filled, for example, with a preform post 5102 inserted at an appropriate point in the process. Alternatively, the metallized 1502 and the second material can be the same material when the malleable material is filmed at the end that contacts another “rigid” material to form a bond.

  FIG. 52 is for illustrative purposes only, after hybridizing to another electronic chip 5200 having drive and control electronics 5202 to control the laser 5104 shown on the chip of FIG. A simplified chip is shown. The electronic chip also includes a rigid post 5204 when compared to the metallized material 1504 used for the chip of FIG. Thus, as a result of joining the two chips under appropriate conditions, a post-penetration connection 5206 is formed, thereby electrically connecting the laser 5104 to the drive and control electronics 5202 on the electronic chip 5200.

  53-71 show a simplified exemplary variation of the basic contact formation and hybridization approach. For simplicity, the approach is shown for a pair of conventional chips that have been preprocessed (ie, include both devices and associated contacts and wiring) but have not yet been diced into individual chips. As shown, each figure chip labeled "a)" has one IC pad for later hybridization with the mother chip labeled "b)" in each figure. A daughter chip having contacts rerouted from one location to another. Note that the processing is shown as being done in parallel, but this is only to aid understanding. In practice, one of the processes can precede the other process, or the processes can be performed with some overlap in time, or can be performed simultaneously.

  First, start with a daughter wafer figure 53a) and a mother wafer figure 53b). Each wafer is a fully formed chip in that each has a number of devices (not shown) thereon. As shown, the contacts 5302, 5304 on the daughter wafer are 25 μm to 50 μm in pitch, but use the same technique for contacts with much narrower pitches, such as 2 μm to 7 μm, using the latest technology. Can do. For illustration and understanding purposes only, the contacts 5306, 5308 on the mother wafer have a wider pitch than the contacts 5302, 5304 on the daughter wafer. Contacts 5302, 5304, 5306, 5308 are conventional aluminum IC pads accessed through chip cover glasses 5310, 5312.

  Next, thick dielectric layers 5402 and 5404 are deposited on the chip (FIGS. 54a) and 54b)). Then, the region above the contact for access is opened by patterning by photolithography (FIGS. 55a and 55b)).

  The dielectric is then etched through to provide access to the IC contact pads (FIGS. 56a, 56b)). Thereafter, the photolithography is peeled off (FIGS. 57a and 57b)).

  Alternatively, the thick dielectric layers 5402, 5404 can be thick photoresist layers (FIGS. 54a) and 54b)). In that case, the thick dielectric layers 5402 and 5404 are removed by removing the photoresist (FIGS. 57a and 57b)).

  A seed layer is then deposited on the wafer to facilitate subsequent plating processes (FIGS. 58a) and 58b)).

  Next, a dielectric layer is applied (FIG. 59a), FIG. 59b)), and photolithography patterning is used to define and control where plating is performed (FIG. 60a, FIG. 60b)).

  Thereafter, the wafer is plated until the desired amount of metal is obtained (FIGS. 61a) and 61b)).

  The dielectric is then removed, leaving a “stand-off” or raised contact (FIGS. 62a) and 62b)).

  As an aside, in general, both mother and daughter wafers can have standoffs. On the daughter wafer, the purpose of the rigid structure is to provide a standoff to fit the entire contact to the non-planar of the two chips, so that the reliability of the contact can be increased. May be. On the mother wafer, the purpose of the rigid structure is both as a standoff and as a post that can penetrate into the malleable material on the daughter wafer. In addition, a standoff can be used to allow for height differences between the top IC cover glass and the IC pad, so that some contacts are placed on the top surface of the glass and other contacts on the pad. Placed in.

  Returning to the process flow, further etching is performed to remove the unwanted seed layer (FIGS. 63a) and 63b)). As shown in FIG. 63a), leaving the seed layer material on the daughter wafer between one of the contacts and the new standoff / contact completes the rerouting of the original contact. Optionally, additional or alternative routing layers can be placed before or after the process is completed. Furthermore, it is desirable to plate the routing layer thicker than others in certain areas and then etch to remove the seed layer.

  Next, a barrier layer is formed on the contacts on the daughter (FIG. 64a)). Although nickel in this case, it functions as a barrier against metal diffusing into the IC pads 5302, 5304, 5306, 5308, or as a barrier against damage to individual chips due to the penetration of metal under the chip cover glass 5310, 5312. To do. Optionally, a cap layer 6402, 6404, in this case gold, is deposited on the top surface of the barrier and is preferred during the bonding process, especially when this approach is used in a tack-fusion bonding process involving post-penetration contacts. Prevents diffusion as well. The cap is also formed on the mother wafer (FIG. 64). At this point, the rigid contact on the mother wafer is complete.

  Again, dielectric 6502 is applied to the daughter wafer (FIG. 65a)) and patterning by photolithography opens regions 6602, 6604 above standoff contacts 6606, 6608 (FIG. 66a)).

  Then malleable contacts 6702, 6704 are made on the standoff (FIG. 67a)), removing the dielectric, leaving a fully formed malleable contact (FIG. 68b)).

  The daughter wafer is then inverted, aligned with the mother wafer photolithography pattern, and the area above the contact to be accessed is opened (FIG. 69).

  The two tips are then joined under pressure so that the rigid contacts enter the malleable contacts (FIG. 70).

  Eventually, the two chips enter the fusion stage and the two chips remain permanently attached to each other (FIG. 71). Note that as a result of this process, the distance between the chips measured between the top surface of the rigid post and the top surface of the contact on the other wafer is less than 10 μm, nominally less than 5 μm. is there. On the other hand, if the wafer is completely flat, this is also the distance between the two wafers. If it is not flat, the unevenness of the wafer will increase or decrease this distance.

  FIGS. 72-87 show simplified alternative process variants for contact generation on the daughter (FIG. 72a)) and mother wafer (FIG. 72b)) and subsequent hybridization of the two chips. As with the previous embodiment, we start with two wafers. As shown in FIGS. 72a) and 72b), the cover glass opening on the contact pad of the IC can be as small as about 4 μm, and in some cases, 1 μm or less, but is about 8 μm to 14 μm. Using one or more processes described herein, these small sized openings can be easily handled in the same way as larger sized openings.

  Further, as shown, the pad spacing on the daughter wafer (FIG. 72a) is typically 25 μm to 50 μm pitch. Again, however, the technique described herein can be easily used with contacts with a nominal 7 μm pitch, and even with contacts with a pitch of 2 μm or less.

  This variation proceeds as follows. First, a thick dielectric is applied to the wafer (FIG. 73). Photolithographic patterning is then performed to define the area above the contacts accessed therethrough (FIG. 74). Next, the dielectric on the contacts is etched away (FIG. 75a)), the photolithography is stripped from the mother wafer (FIG. 76b)), and a path change is formed (FIG. 77).

  The exposed areas above the contacts and the path change on the daughter wafer are metallized with a barrier layer (FIG. 78a)) and a seed layer is applied to the mother wafer (FIG. 78b)). Optionally, a barrier can be formed on the mother wafer to protect the IC pad (not shown).

  Next, the photolithography is peeled off from the daughter wafer (FIG. 79a). New photolithography patterning is performed to define the area where the contacts are made (FIG. 80).

  The malleable contact is covered with a suitable material, in this case a discontinuous layer of tin (Sn), and then with a layer of gold (Au) (FIG. 81a)), gold-tin (Au / Sn) By depositing an alloy, it is produced on the daughter wafer and a rigid contact is formed on the mother wafer. The exposed seed layer is plated with copper (FIG. 81b)).

  Next, the photolithography is peeled off from both the daughter and the mother wafer (FIG. 82).

  Next, the unnecessary remaining exposed seed layer is removed from the mother wafer (FIG. 83).

  Finally, a cap (optionally preceded by a barrier) is formed on the mother wafer contact to prevent oxidation (oxidation cap) (FIG. 84b)).

  The wafer is then aligned (FIG. 85), bonded, tucked (FIG. 86), and fused at some later time (FIG. 87), as described previously.

  Having described some variations in a rough overview, here we present additional variations that further include details of the various steps in the process. However, it should be understood that these details are equally applicable to the preceding variations and other variations described herein.

  FIGS. 88-91 and 95-102 show two further exemplary variations for forming what will later become rigid posts on the back of a daughter wafer in a simplified side-by-side configuration. . The “daughter” is called the “daughter” because the aluminum IC pad is a malleable contact and is bonded to a rigid post on another “mother” wafer, so even if the back contact is a “mother-type” contact Like.

  Further, although several variations are shown in parallel, the processes described herein need not be performed in parallel, but may be performed on the same wafer or at different times on different wafers. Variations can be implemented.

  This example begins with wafers 8800, 8802 shown in FIGS. 88a) and 88b), respectively, and includes preparation for contact path changes. That is, the vias are not aligned with the pads on the surface of the wafer (FIG. 88a) -99a)), and the second example has no contact rerouting, so Align with the pad (FIG. 88b) to FIG. 99b)). Furthermore, the relative difference between the widths of the two vias generated allows vias with different widths to be used on a single wafer or chip, and the via width can be varied with the pad width on the chip. , Is intended to indicate (ie, can be the same width as the pad, wider or narrower than the pad). Again, it should be noted that the figures are not to scale and are not necessarily in a proportional relationship.

  First, thick dielectric layers 8902, 8904 are formed on wafers 8800, 8802, in this case silicon wafers having aluminum IC pad contacts 8804, 8806 (FIGS. 89a, 89b)). The thick dielectric layer serves to protect the chip and later serves as a stop area for the process when the top surface is thinned after electroplating. It should be noted that in a later step, the via is either a) not filled with electroplating, or b) thinned (ie, thinned by etching or photolithography lift-off) during the via metal filling process. This step can be optional if it is filled in such a way as to allow removal of excess material deposited on the wafer surface. Suitable for thick dielectric deposition materials include, but are not limited to: TEOS, oxides, nitrides, spin-on glass, polyimide, BCB, other polymers or epoxies, thick photoresist layers, etc. (photoresist If a polyimide or thick photoresist is used, depending on the variant, another photoresist deposition step of the next step is not necessary).

  Next, a photolitho layer is applied and patterned to protect the wafer from being etched away (FIG. 90). This step defines a place for the via to be generated.

  Etching on the wafer is then performed through the dielectric, into the semiconductor and the substrate (FIG. 91), and in the case of a path change, a via 9102 is created in the wafer where the path change contact is located (FIG. 91a). In the conventional case (FIG. 91b)), the via 9104 enters the wafer through the dielectric, aluminum IC pad contact 8806. It should be noted here that, as will be apparent from the following figures, the desired depth is such that exposure of “posts” formed in the process of thinning the wafer backside is possible. A typical value for this depth is about 75 μm. Having this via depth is not important, but under the assumption that it can be in the thousands or millions of contacts / cm2, such depth has good yields in subsequent processes. At the same time, it is possible to handle the entire daughter wafer in a wafer scale manner without the need for a carrier wafer. Alternatively, the via can penetrate the wafer. In these through-wafer variations, the steps described below, thinning the back surface and etching to expose the metal in the via, can be eliminated. Furthermore, although the via shown in this example has only a single conductor, the same approach can be applied to coaxial, triaxial conductors by incorporating these generation steps directly into the process.

  At this point, it is worth highlighting the specific attributes and benefits that result from the use of the process illustrated in the specific implementation. Attributes and advantages arising from this approach include the fact that via etching and generation occurs before hybridization (chip-to-chip, chip-to-wafer, or wafer-to-wafer). In other words, it can be easily performed before bonding the chip, die or wafer to another element. Furthermore, the present technique allows the vias to be etched from the device (ie, active) side of a previously fabricated and usable electronic chip. This approach can be used virtually anywhere on the chip where there are no directly sacrificial circuits in the etch path. Thus, vias formed using this technique can be aligned with the pad or not aligned as desired. Furthermore, by creating vias on the pads and / or in some cases by creating vias much smaller than the pads, ICs for circuits, especially in areas of the chip with little or no circuitry. The loss of the “region” above can be minimized.

  With respect to via formation, in some cases it is desirable to have a sloped via to ensure that subsequent material deposition sufficiently covers the sides. In that case, the slope can be a typical nominal slope of about 88 degrees from the vertical axis of the via longitudinal axis (ie, the via width becomes slightly narrower as the depth increases). A cross-sectional photograph of an example of an inclined via is shown in FIG.

  Typically, vias having a width of 5 μm or more and a depth of 75 μm or more are used. The via of FIG. 92 has a diameter of 20 μm and a depth of about 150 μm. FIG. 93 is a photograph of an exemplary via (filled) having a depth of 100 μm and a diameter of 20 μm. When the depth can be made shallower (for example, to a depth of only 5 μm), a width as small as 0.1 μm is sufficient. However, using vias with a width of less than 0.1 μm may reduce the integrity of the final bond formed. Similarly, using shallow depths less than 5 μm requires the wafer to be so thin that the underlying circuitry (if any) may be damaged. At present, typical ranges are 75-150 μm deep and 5-25 μm wide so as to obtain sufficient production yield with reasonable commercial equipment. It goes without saying that depths and widths outside this range are possible for specific applications. For example, vias can be as deep as 300 μm and, in some cases, can penetrate the wafer, but currently commercially available equipment is aimed at the large-scale sales production envisioned here. It does not have sufficient consistency so far to allow acceptable yields at such significant depths, including the number and density of vias. However, advances in such equipment will eventually narrow or remove this limitation, with little or no modification of the techniques described herein, such depth, number and It is expected that this method of density must be realized.

  Optionally, the bottom of the via can be formed with a pointed point. This ensures a strong rigid post, good penetration of the rigid material into the malleable material, and ultimately a strong contact (maximizing the surface contact between the rigid contact and the malleable material) This is the method used by the inventors. To do this, we have tapered the base of the post as wide as the underlying contact (maximizing adhesion strength to the contact of the post), while the top is much thinner than the contact. We used a technique to make a rigid post in a pyramid shape (or a pyramid on top of a cylinder) that can achieve alignment to the size factor. This variant has the advantage of providing a pointed post formation and thus, when used for post-penetration connection, allows penetration similar to that of a rigid post with a pyramidal profile formed later. Have FIG. 94 is a cross-sectional photograph of a chip having a via with a sharp tip formed therein.

  Next, the photoresist is stripped (FIG. 95) and a dielectric or insulating layer is applied to the exposed via surface (not shown) so that the metal in the via is electrically shorted to somewhere in the circuit in the semiconductor. prevent. The thickness of this layer is typically about 2000 mm to 1 μm. However, the layer can be thickened if the particular application involves a balance of thermal expansion coefficients, or via capacitance reduction (in critical or critical situations). Exemplary insulating materials that can be used include (oxidized) TEOS, other oxides, nitrides, polymers, CVD diamond, and the like.

  Next, a metal barrier layer is deposited on the dielectric (FIG. 96). The barrier layer acts to prevent metal migration (migration) to the insulator and the semiconductor. All barrier materials described herein are suitable for this step, but in the present example, the barrier shown is titanium tungsten (TiW).

  Next, if the metal is to be plated in a specific variation, a plating seed layer is applied (FIG. 97). The seed layer is used as a base for via electroplating. Copper seed layers are preferred because they are good conductors and thermal conductors, and are now popular in industry and easy to work together in standard semiconductor and package lines. However, any material described herein in conjunction with a rigid material and / or a seed layer for the rigid material can be used. If the via is to be filled by a method other than electroplating, this seed may or may not only cover the via itself, rather than a wider portion of the wafer. For example, if the via is filled by CVD or vapor deposition, a seed layer is not necessary).

  Barrier and seed layers are typically deposited by sputtering or physical vapor deposition (“PVD”), but in some implementations electroless plating has significant advantages over sputtering or PVD, so Electroless plating can also be used. The via is then filled with metal or other conductor (usually completely) to form an electrical conduit through the wafer (FIG. 98). The fill material is typically copper for plating techniques. However, other materials can be used, including any other material described herein as a suitable rigid or malleable material. It should be noted that if only simple electrical contacts are required and good heat conduction or low electrical resistance values are not required, the via need not be completely filled with a conductor. In these cases, the remainder of the via can optionally be filled with another material such as oxide or epoxy. When the chip is packaged and sealed, if air is taken into the voids in the via, the chip may fail due to expansion and contraction of the air due to the temperature cycle during operation. Typically, it should be filled with some kind of material. When completely filled with metal, the resistance value is the lowest and the best thermal conduction contact is possible. Furthermore, when using larger diameter vias that are completely filled with metal, the metal can support heat transfer through the wafer.

  As shown in FIG. 98, vias are filled by plating the seed layer using an electroplating process. Optionally, if the plating process is complete and the void remains inside the center of the plating material, the void can be filled with a filler material, such as oxide, additional metal, solder, or some other material suitable for the application. Can be filled.

  The stack advantage can be achieved if the via is filled with the same material as the rigid material for the mother wafer or the same material as the malleable material for the daughter wafer. Alternatively, if the mating contacts on the applied chip have a rigid material on it, there is the advantage that the via can be filled with the same material as the malleable material.

  Note that when the via is filled with a conductor, as shown in FIG. 98b) when the via is aligned with the pad, the via essentially contacts the pad.

  When bonding a specific wafer to another wafer, as expected in most implementations, when daughter chips are hybridized to a mother wafer, the daughter wafer can be run in the same way that the mother wafer does. It is important that the construction of the barrier and via filling material follow the same guidelines as the barrier and rigid material for the mother wafer.

  Returning to the process flow, as a result of the plating in the previous step, a large amount of conductor needs to be deposited on the top surface of the wafer and removed. This can be accomplished by lapping, polishing or a chemical mechanical process (“CMP”). This thinning is done in the thick dielectric deposited in the first step. The actual thickness used in the dielectric applied as the first step is selected to give this lapping step margin for error. This step may be omitted if the conductor filling the via is not deposited by electroplating. Then, as shown, a chemical mechanical process (“CMP”) is used to remove excess plating material and the underlying seed layer down to the surface dielectric layer and slightly inward (FIG. 99). .

  The photolithographic etch process is then used again to provide access to the IC pad contacts 8804, 8806 of the wafer from the top surface of the wafer by application of photoresist (FIG. 100) and then exposed dielectric 10002. (FIG. 101) is supported. If the only contact needed is from the pad to the via itself and no contact is needed between that same pad and the mother chip for that particular pad, that particular pad can skip this step (ie, its The pad can be left covered with photoresist). In an alternative variant, the connection to the IC contacts is made simultaneously when the seed layer is deposited (which can be functionally part of the seed layer) or during via plating or filling. As such, photolithography can be performed. In such variations, this photolithography step may not be required.

  Thereafter, the photoresist is stripped and the wafer is cleaned, leaving a fully formed post in the daughter wafer (FIG. 102).

  At this point, it is assumed that the wafer is further prepared to hybridize to another element, such as another chip, die, or wafer (ie, the approach is equal for all permutations of hybridization) : Chip-to-chip, chip-to-die, chip-to-wafer, die-to-die, die-to-chip, die-to-wafer, and wafer-to-wafer). This further processing is simplified and shown in parallel in FIGS. 103-125 and begins with a daughter wafer as shown in FIG. Further, for ease of understanding, the process is illustrated as a process performed on a wafer that serves as a “mother-type” contact element.

  The process proceeds as follows. Initially, a dielectric layer is applied to the mother wafer except on the IC contact pads (FIG. 103b)), but the dielectric layer already exists on the daughter wafer (FIG. 102a) and FIG. 102b)). .

  Next, a barrier layer is deposited on the daughter wafer (FIG. 104a), and in the case of a contact path change, part of it is finally the electrical connection between the original IC contact and the preformed post. The use of a barrier is advantageous because it prevents the malleable material from subsequently interacting with either the IC pad or either rigid metal or standoff metal.

  As shown, a barrier material, such as Ni / Au, Ti / Pd / Au or Ti / Pt / Au, is deposited on the daughter wafer via sputtering, to name a few examples. In addition, this barrier can generally be used as an under bump metal (“UBM”) for rerouting where the seed need not be removed. This layer is formed using either a sputtering and / or vapor deposition process or electroless plating optionally combined with an electroplating process for the top layer.

  Further, as shown, a seed layer is deposited on the mother wafer using, for example, electroless plating or deposition techniques (FIG. 104b)). As shown, the mother wafer has TiW + Cu filmed, which is used as both a UBM and a seed for electroplating rigid contacts on the mother wafer. Using copper on the top surface allows for easier copper electroplating and subsequent rigid post formation. Depending on the implementation, the UBM of the mother wafer can also serve as a seed layer for rigid member electroplating, rerouting, or function as an RF shield between wafers (patterning for this is not deposition at this point) That would occur in the etching step).

  Optionally and alternatively, the barrier layer and the seed layer can have the same components. In such cases, a single material can function as both layers.

  As shown in FIG. 104, the barrier is formed on the entire wafer. This is to allow subsequent electroplating steps to be performed. However, after this electroplating, the seeds and barriers need to be removed from areas where the contacts are not present so that the various contacts do not remain electrically shorted together (other reasons not relevant here: , Unless explicitly requested that the barrier and seed can function as an electrical rerouting material between the points).

  If the subsequent material can be formed by a process other than electroplating, such as sputtering or vapor deposition, the mother wafer step can alternatively be lithographically patterned around the pad, forming the barrier metal, forming the subsequent metal, and then lifting off. Includes process execution. The net result of the metal and barrier, primarily around the pad or where rerouting is desired, will be the same.

  A lithographic process is then performed on the daughter wafer to expose the barrier material overlying the original contact (FIG. 105a)). In addition, as shown, the mother wafer is patterned by undercut to provide an optional patterned contact having, for example, a pyramidal, conical or mushroom shape with a pointed tip (FIG. 105b)). Alternatively, form some other contact shape to increase the available area of the contact or to create a contact that is sufficiently smaller in cross-section than the corresponding malleable contact that will eventually be combined. The mother wafer can be patterned. By doing so, the applied force is distributed throughout the narrower region, so that penetration can be enhanced.

  This step (FIG. 105a), FIG. 105b)) defines the location for subsequent metal placement. If this subsequent metal is deposited by means other than electroplating, this step will be performed prior to the barrier and seed deposition described above. Here, it is assumed that electroplating is used. Note again that lithographic patterning is performed to allow subsequent electroplating and / or seed etching (or subsequent lift-off processes if electroplating was not used) to define a rerouting layer. be able to.

  Next, the daughter wafer is metallized by depositing an appropriate metal on the exposed upper surface of the barrier (FIG. 106). Depending on the particular implementation, one or more of the following can be formed on the daughter wafer. Standoff layer (if desired) to handle wafer non-planar, diffusion layer or malleable layer (to deform and form contacts), cap to assist bonding operations during the bonding (tack) stage Or an oxidation barrier that prevents the adhesion layer (if necessary) and / or the adhesion / diffusion layer from being oxidized.

  Further, on the mother wafer, voids generated by the lithography process are filled by plating (electrical or electroless) the seed layer exposed by the lithography process (FIG. 106). Depending on the particular implementation, a rigid material used to form a post for use in a post-penetration connection can also be added at this stage.

  FIG. 107 details an example of a fully plated pyramidal contact for a mother wafer.

  FIG. 108 shows an enlarged portion of an alternative variation of the mother wafer contact, where the profiled contact is similar to that of FIG. In this optional variant (applicable to profiled contacts and non-profiled contacts), the metal of the semiconductor pad 10802 is slightly etched before the metal for the rigid post is plated (metallization) and at the edge of the pad 10802 The undercut profile 10804 is generated. When the rigid material 10902 is stacked (FIG. 109), a portion of the rigid material 10902 fills the undercut 10804. This additional filling acts as an anchor and helps to hold the rigid contact structure in place while the stress applied during the additional process, or stress in operation by thermal cycling, is exerted. As shown, the rigid material 10902 is nickel (Ni).

  When metallization and / or plating is complete, the photolitho is then stripped to expose the contacts stacked on the daughter and mother wafers (FIG. 110). However, it should be noted that if the barrier for the mother contact is electroplating, the step can optionally be performed following metallization and before stripping the photoresist.

  A photolithography process is then used to protect the stacked contacts or posts, but unwanted barrier and seed material can be removed from the daughter and mother wafer, respectively (FIG. 111). Note that this step can also be used to define and / or reroute contacts. Furthermore, these steps may be slightly different since other metal may not have been electroplated yet, as lift-off versus subsequent etching may be used.

  However, etching is used in this example because the seed and barrier material were electroplated. Therefore, unnecessary seed and barrier material are etched away (FIG. 112). Furthermore, in an alternative and optional variant, most of the wafer surface remains covered, since only a small amount of barrier and seed are etched away, i.e. only necessary to prevent unwanted short circuiting of the contacts. Thus, particularly when the remaining barrier / shield is attached to a ground plane, it can be used as an EMI shield to prevent noise or unwanted signal coupling between stack chips.

  Next, the photolithography is removed (FIG. 113).

  At this point, the daughter wafer includes a functional rigid post for use in forming a post-penetration mating connection with another wafer.

  However, as will be apparent from the description herein, in this case, the processing of the mother wafer continues especially through electroless plating of malleable material on the contact (compared to the material on the daughter wafer post) ( FIG. 114b). It should be noted that although this step is described as an electroless plating step, an electroplating step can be used in a variation of the present technique. In such a variation, this part of the process consists of stripping the photolitho used in the metallization step as part of or an alternative to the metallization step, and applying protective photolitho as described herein. As an electroplating operation during However, in any case, barrier deposition is important because the barrier prevents intermixing of malleable and rigid materials and includes malleable material between the rigid material and the IC pad on the daughter wafer.

  At this point, the mother wafer has a functional malleable post for use in forming a post-penetration mating connection with another wafer.

  However, in this embodiment, the third chip should be stacked on the upper surface of the daughter wafer, and thus the formation of the post in the wafer was planned in advance. Therefore, additional processing of the daughter wafer is necessary, and the process proceeds as follows.

  First, the front side of the daughter wafer (ie, the side on which the device and contacts are mounted) is protected by application of a suitable removable protective material to protect against contamination during the subsequent thinning process (see FIG. 115a)). This covering can consist of only a simple photoresist or dielectric, or a glass plate applied to the daughter wafer by means such as photoresist, wax, polymer, epoxy, other adhesives, etc., or another Can be composed of a rigid member such as a semiconductor wafer ("carrier" wafer). In some variations, a very thick layer is used (eg, at least about 50% of the thickness after which the daughter wafer is thinned). In other variations, a rigid carrier wafer can be used. In either case, the very thick layer provides extra strength to the daughter wafer and can be handled without cracking when thinned.

  Next, typical via depths reach up to about 75 μm, so typically the backside of the daughter wafer is thinned until the thickness of the daughter wafer is about 75 μm, and via fill material (eg, Expose previously formed post). If the vias extend deeper, it is necessary to reduce the thinning. Depending on the particular application, the thinning process is specifically performed until the post extends over the back wafer surface. Depending on the application, the post is flush with the back (FIG. 116a)). However, if the bottom of the via is pointed, the thinning process should preferably not be drilled down enough to remove a significant amount of the bottom tip, but if it has a pointed via, When is finished, a pyramid, conical or mushroom shaped structure is desirable.

  In this case, since another post-penetration connection is desired, an etch is performed on the back surface so that the post extends above the surface (FIG. 117a). This etching step serves two purposes. First, some of the substrate surrounding the via is removed so that the via extends beyond the surface (thus, the via can function exactly as a rigid post on the mother wafer). Second, the surface of the contact is cleaned so that the metal adhesion is good in subsequent processes.

  Of course, in daughter wafers with non-through connections, the thinning and etching steps are generally unnecessary, although subject to other height considerations that make them desirable.

  In variations where very thick layers or carriers are used on the front side, the thinning process can potentially far exceed the typical 75 μm final thickness. In fact, in these variations, the thinning process results in a thickness reduced to about 10 μm. Further, if the carrier wafer is not removed after the tack-fusion process, the wafer can be thinned to about 5 μm.

  Note: In an alternative implementation, the thinning step can be performed after the mother-daughter hybridization. In such a variant, the sequence of processing consists of electroless plating of the mother contacts, tack, fusion, daughter thinning, etching the back side of the daughter to extend the contacts above the back side, barrier to the back side contacts And applying a cap, protecting the front side, and removing the protection are unnecessary and omitted.

  A barrier and cap or cover layer is then deposited on the post (FIG. 118). This barrier layer and cover is important to protect the via material. The barrier layer (and barrier cover) performs the exact same function as the barrier material and barrier cover deposited on top of the rigid posts of the “true” mother wafer. Thereby, the malleable material can be fixed between the barrier material on this new post and the barrier layer on the subsequent second daughter wafer (ie, “daughter wafer 2”). As shown, the barrier and cap are deposited using an electroless plating process. In this embodiment, 1 μm Ni and 0.3 μm Au are used. The advantage of using electroless plating is that it does not require any photolithographic steps on the backside of the wafer, simplifying the performance of the process and adapting to the use of thin wafers. This advantage is even more valuable for wafers that have been thinned to more extreme limits and saves costs in the original dielectric etch, via etch, and via fill steps of the via generation process. Again, the specific materials used include any of the barrier materials referenced herein.

  Furthermore, this barrier need not be deposited by electroless plating. Alternatively, depending on the variant, electroplating can be used, when the seed layer is deposited on the backside, it is plated as described above and then etched. In other variations, these barrier layers can be formed using patterning and evaporation or sputtering or other types of deposition processes. Although more steps are required on thin wafers, these alternative approaches are either by seed layer etching in the electroplated process flow or by a lift-off process in the deposited metal process flow. It is also possible to define a routing layer, a shield or ground plane on the back side of the wafer. Next, the protective layer is removed from the front surface of the daughter wafer (FIG. 119).

  Alternatively, if the material formed as either a protective layer or an adhesive that applies the carrier wafer to the daughter wafer can withstand the temperature of the tack-fusion process, this step is complete for the fusion process You can extend it until later. This allows the daughter wafer to be made significantly thinner while still allowing individual dies in the tack process to be handled without breaking or damaging the chip. In this embodiment, the daughter chip typically has an upwardly facing circuit surface (ie, away from the mother chip) and the malleable material is on the mother chip. It goes without saying that the mother / daughter promise is nothing more than a principle, and vice versa, or in the case of specific well attachments or other variations, malleable materials are It may be in itself or added later.

  In another alternative variation, for example, the via is not formed to stack the top third chip, but the via is formed to hybridize the chip and the upward circuit that is not downward, For example, if the optical device is on a daughter wafer and the top carrier wafer has a built-in microlens or other passive element, or the daughter and mother wafer are RF devices and the two electronic circuits are adjacent to each other If this is not the case, this step could be omitted entirely, leaving the protective layer permanently. Again, this typically requires a mother chip having malleable material thereon.

  At this point, it is assumed that the contacts described above on the mother and daughter wafers can be combined together to bond the respective chips. The joining process proceeds as follows.

  First, the daughter wafer is turned over and the mating contacts on the mother and daughter wafers are each aligned with each other (FIG. 120). An alignment step is used to align the mother and daughter wafers. This alignment should be a ± tolerance on the pad size. For extra large malleable contacts, the alignment tolerance can be somewhat larger. In general, the alignment is performed to ensure that the entire top of the rigid contact hits the malleable contact at some point. For illustration purposes only, if the malleable contact is 15 μm wide square on the surface and the top of the rigid contact is 5 μm wide square on the surface, the edge of the rigid contact will be The edge of the malleable contact should be 5 μm and the alignment accuracy will be ± 5 μm.

  The contacts are then joined under pressure to form a post-penetration connection (FIG. 121).

  One of the main advantages of this stacking approach is that the rigid material enters the malleable material. This creates a strong coupling between the two wafers because the surface area between the two contacts is larger than the size of the individual contacts themselves. In addition, this bond is further strengthened because the type of defect required to pull the two parts apart requires both post-level delamination and post-longitudinal shear defects. Note that since the latter is a form of defect that is much less likely to occur, the overall defect risk is much less than either one alone.

  In practice, the amount of protrusion is also important. Typically at least 1/2 μm is desirable. Depending on the implementation, even fewer protrusions will work, but at lower protrusion levels the strength will be significantly reduced. In practice, the inventors have determined that for a malleable material with a total height of 8 μm, the rigid material typically extends 2-3 μm into the malleable material, and for a 10 μm malleable material, the rigid material is Typically, it extends 5 μm into the malleable material. In the general rule of thumb (Rule of thumb), penetration is 10% or more of the thickness of the malleable contact, but the penetration is suppressed to less than 90% of the malleable contact.

  Another major advantage is that the penetration of the post can tolerate a significant non-planarity of the daughter and mother tip relative to the contact pitch. For example, at a 20 μm pitch and 12 μm wide contact, the height of the malleable material is quite high, for example, it can be as high as the height matches the pitch. Similarly, the flatness deviation from contact to contact may have the same range as the malleable contact thickness. For example, if the post is 5 μm high and the malleable material is 8 μm high, the difference in flatness from contact to contact may be as large as 8 μm. In this case, some of the posts will penetrate to the entire malleable material and some will have less penetration.

  Returning to the process flow, the tack phase of the tack-fusion process can be performed following or simultaneously with penetration of the rigid contacts into the malleable contacts. As shown in FIG. 121, two things occur simultaneously. During the tack phase of the process, an electrical connection is made between the two wafers. The advantage is that no intermediate epoxy or material is needed to hold the chips together, or they can act as a barrier between electrical connections.

  Optionally, before the tack phase, an underfill is inserted between the two chips, for example, there is no possibility of rework as part of the process, and the underfill material depends on the temperature used in the tack-fusion process. If not adversely affected, the void between the two can be filled.

  At this point, the mother and daughter wafers can be combined and inspected (replace if one is defective).

  If it is determined that a permanent connection between the two is desired, the fusion phase of the tack-fusion process is performed (FIG. 122) to form a combined pair (eg, hybridization unit) 12202, 12204. During the fusion process, the mother diffusion / cap, daughter oxidation cap, and daughter malleable material all diffuse together to form the final component of the entire contact.

  If no prior underfill was inserted between the chips prior to the fusion process, it can be optional, or if no temperature is involved, underfill insertion continues into the fusion process. The advantage of using an underfill is that air can be trapped between the two chips, and the possibility of damage to the chip or connection due to subsequent temperature cycling (because the tack-fusion process creates a hermetic seal), The fill is to lower.

  When mounted on a mother wafer in a tack process (ie, in a die-to-wafer process, the alignment-tack process is repeated in order to place each of the mother wafers well without attaching to a known defective mother die site. In the process, if two wafers are tacked together and an optional inspection is performed, the location of the defective chip is marked for later removal), the entire mother wafer is passed through the fusion process, and all of the daughter chips are Grant permanently. This can be done at a much higher temperature than the tack phase. Furthermore, since the process is performed simultaneously on a wafer-by-wafer basis, the processing time is the same for each chip, and the process produces a fairly uniform connection across each individual chip.

  The temperature of the fusion stage is typically, for example, 320 ° C. to 400 ° C., depending on the particular material involved.

  Separating the tack process from the fusion process has the advantage that the speed of the equipment performing the tack does not decrease because there is no need to heat or cool each individual part. By doing this in a controlled manner at the wafer level, all contacts will have very similar final components.

  During the tack phase, the fusion phase, or both, an inert or reducing environment can be used to help minimize or remove oxides on the surface of the material, reducing the required temperature or pressure at each step To help. Typically, these are gases such as nitrogen, argon, other inert gases, or reducing gases such as forming gas or formic acid, or other environments with hydrogen or some other reducing gas.

  As mentioned above, this process is incomplete because the third chip is to be coupled to this newly formed unit. Similar to the mother and daughter chip combination, the unit can be connected to another chip. Accordingly, as shown in FIG. 123, the second daughter wafer is brought to the appropriate contacts on the units 12202, 12204 to align the contacts.

  Due to the previous processing steps, it is advantageous that the exposed surface of the upper via of the first daughter chip has the same components as the upper part of the original rigid contact. Thus, for subsequent “daughter” wafers, hybridization is done in the same way as was done for the first two wafers (ie, alignment, penetration, tack (optional inspection) and fusion. The material is fixed between each barrier layer and a post on the via that penetrates into the malleable material). Thus, an important advantage of the process is that via and base hybridization is the same material system and the same process flow that facilitates repetitive stacking over traditional stacked, one chip pairs that may be found. It is set up to work.

  As a result, the mother wafer can be loaded with one set of chips, then another set (daughter wafer 2), then another set, etc., tuck, fusion, tuck, fusion technique, or in some cases The process is executed in the same manner for each layer as necessary using any of the methods of tack, tack, tack, and fusion.

  Thus, on the second daughter wafer, a second tack step is performed, coupled to the unit, and once completed, this newly formed larger unit can optionally be further inspected to provide a second daughter chip. If it is defective, it is removed and replaced (FIG. 124).

  Finally, if a permanent connection between the second daughter and the unit is desired, the fusion phase of the tack-fusion process is performed again (FIG. 125), and the new, larger hybridization units 12502, 12504 are Form.

  After this step, the process can be repeated many times to integrate more chips on, for example, “daughter wafer 2” or other chips (not shown) on the wafer. it can. Since electrical connections are made between each tack process, it is necessary to align each chip only to the chip immediately below it, so that all of the chips can be stacked first and then through connection attempts can be initiated. A further advantage arises in that there is no alignment error accumulation as in the stacking technique.

  In addition, an inspection of each of the combined units that have grown to the required extent can be performed after each graded layer (rework can be performed if desired). Again, if the dies are stacked in multiple layers, this would be a significant advantage and dramatic cost, as the prior art would need to complete the entire unit and then perform an electrical test. Provide savings and yield improvements. Thus, only after generating expensive units, conventional parts can be inspected, and if defective-rework is not possible, the only option is to scrap the high-cost whole unit. Let's go. Furthermore, the risk of damaging the unit being fabricated by the prior art or the risk of wasting parts increases dramatically, for example if the defect was on the first layer chip.

  In contrast, using one of the techniques described herein, multi-stack configurations can be generated with much less risk. Again, depending on the particular case, the method can be executed as many times as necessary as a sequence of alignment, tack, fusion, alignment, tack, fusion as described above. In situations where the tack process has a sufficiently high strength, for example, with ≧ 500 contacts, the process can alternatively be performed as many times as necessary for alignment, tack, alignment, tack, and all chips vertically You should only be able to perform the fusion after it has been stacked (and tested as benign when using the option). This second approach can be used more effectively when different numbers of chips are stacked in different arrangements.

  At this point, the process of joining the subsequent second daughter wafer (and subsequent wafers) to the unit without adversely affecting the previously formed interconnect connections by using post-penetration connections and tack-fusion processes. It is useful to note that can be performed. In fact, according to the surprising discovery of the present inventors, by using tack, fusion, tack, fusion technique (with or without thinning intervention), the continuous fusion step is actually Reduce the connection resistance. This is noteworthy because the general idea tends to indicate that subsequent fusions tend to weaken and degrade previously formed connections (this is described below. The "well" connection was particularly true).

  126-139 show in a simplified form a further variation starting with the rerouted daughter wafer of FIG. 103 and the corresponding mother wafer to avoid redundancy. However, in this embodiment, the daughter wafer is processed as shown in a simplified form in FIGS. 77 to 104, but in order to facilitate the stacking of the second daughter wafer on the top as in the previous embodiment. Includes post generation.

  With the wafer of FIG. 104, the process begins by photolithography defining areas for rerouting on the wafer daughter wafer (FIG. 126). Next, a barrier layer is formed to reroute contacts on the daughter wafer, and a seed layer is applied to the mother wafer (FIG. 127). The photolithography is then stripped (FIG. 128) and new photolithographic patterning is used to protect all but the area above the original contact (FIG. 129). Next, the contacts are metallized (FIG. 130), a gold-tin (Au / Sn) alloy covered with a discontinuous layer of Sn and a gold cap is applied to the daughter wafer, and copper is plated on the mother wafer contacts. The photolithography is again peeled off (FIG. 131), and the unnecessary seed layer is removed by etching (FIG. 132). Finally, a Ni / Au cap is formed on the mother wafer contact by electroless plating (FIG. 133).

  The wafers are then aligned with each other (FIG. 134). The contacts can then be joined to form a post-penetration connection, and tack, optional inspection, and possibly a fusion process can be performed to produce a combined hybrid unit (as described herein). Since it is described and illustrated elsewhere, it is not shown here to avoid redundancy).

  Since this embodiment is also related to the addition of the second daughter wafer on the upper surface of this daughter wafer, the present process proceeds as follows. First, the backside of the daughter wafer of the unit to be combined is thinned to expose the backside contacts previously formed (FIG. 135). The substrate is then etched to raise the posts on the substrate surface (FIG. 136).

  This adds another step to the post-hybridization, i.e. thinning process, but if this is sufficient for a particular application, the process can be terminated here. . The advantage of doing so is that there is no further lithographic patterning or material deposition that requires further work and is a major source of yield loss risk. Alternatively, a cap can be added (ie, additional processing is required) if the time difference, material, or other factor that couples to another element makes oxidation a problem.

  FIG. 137 is a photograph of an exemplary contact after the steps shown in FIGS. 135 and 136 have been completed. In FIG. 137, the post 13702, the barrier 13704, and the substrate 13706 are clearly visible.

  Assuming that oxidation can be a problem, a cap is filmed on the raised portion of the post (FIG. 138) to complete the back contact formation process.

  As with the first daughter wafer, the next daughter wafer can be placed on this back contact at a position where a post-penetration connection between the two can be formed, along with the tack process or subsequent to the tack process. (FIG. 139).

  In general, there are a myriad of materials suitable for use as a barrier. Such materials include, but are not limited to, Ni, Cr, Ti / Pt, Ti / Pd / Pt, Ti / Pt / Au, Ti / Pd, Ti / Pd / Au, Ti / Pd / Pt / Au, TiW, Ta, TaN, Ti, TaW, and W are included.

  Suitable materials for the seed layer include, but are not limited to, Ni, Cu, Al, Au, W, Pd, and Pt.

  Suitable materials for substitution include, but are not limited to, Ta / Cu, TaN / Cu, Ni / Au, Ni / Cu, Ti / Pd / Au, Ti / Pd / Cu, chromium, and planar. Possible conductive epoxies (eg, by vapor deposition or spraying), or combinations thereof are included.

  However, it should be noted that not all barriers on a chip or chip pair need be made of the same material.

  In general, when using a barrier, the material should have the following properties:

  i) Compatible with specific pad materials (typical pads are aluminum, copper, and gold);

  ii) if a small IC pad (<15 μm) and a large pad (> 50 μm) coexist on a wafer, choose to be able to place on the wafer with good yield for both; and

  iii) When using the under bump metal also as a rigid material or acting as a stand-off, satisfy the above and have a height of several μm (> 3 μm).

  Furthermore, it is desirable that the barrier material be compatible with the deposit on the top surface of both the chip IC pad and the top cover glass / protective layer.

  The use of a barrier can provide one or more of the following advantages:

  i) For hybridization, the use of barriers allows for high yields and increases contact reliability;

  ii) If deposited together on the pad on the chip and the top surface of the top cover glass / protective layer, the barrier layer can later be used as:

  1) Signal routing material,

  2) An electrical shield between the chips to prevent crosstalk between the two chips, and / or

  3) Seed layer for any subsequent steps that can be performed by electroplating (eg formation of rigid posts and film formation of malleable material);

  iii) increase the shelf life of the daughter material because the barrier acts as a cap to prevent or retard oxidation;

  iv) the barrier can be pre-patterned to act as a reroute or shield;

  The above alternative materials can provide certain advantages in some implementations for the following reasons:

  i) The barrier ability of Ta and TaN is considered to be superior to that of TiW.

  ii) The nickel-based process can simplify the process because the UBM and the subsequent rigid material are identical.

  iii) Alternative methods that do not leave exposed copper have a long shelf life and can be highly compatible with specific production processes;

  iv) If no subsequent electroplating step is required (eg, to deposit a rigid or standoff member on the daughter wafer), pattern any of these materials only over the pad and reroute or shield area This eliminates the need to perform subsequent seeding and etching steps that define these regions.

  In relation to the use of the barrier layer, what is important in many variants is to ensure: That is, 1) the appropriate metal premised on the interaction must interact properly, 2) these same metals should interact so that the final composition after the interaction is correct, and 3) others used in the stack The metal (ie, rigid and isolated) interacts so as not to contaminate the metal, and 4) the barrier is soldered to the process tack (eg, at the appropriate temperature) Pb / Sn, or some lead-free solder that works from about 240 ° C. to about 270 ° C.) and the temperature for the fusion of the process, which can typically be between about 300 ° C. and about 350 ° C. Tolerate multiple high temperature cycles up to and above both temperatures. The barrier maintains the integrity of the applied material by preventing intermixing of the metals to be separated for better bond integrity.

  This is shown by way of example with reference to FIG. 140 showing a daughter wafer contact 14002 and a mother wafer contact 14004 just prior to the tack phase. As shown, the barrier layer 14006 at the daughter wafer contact is Ti / Pd / Au and the barrier layer 14008 at the mother wafer contact is Ni. The “rigid” material 14010 on the mother wafer is copper and the malleable material 14012 on the daughter wafer is Au / Sn. Furthermore, the caps 14014 and 14016 on each side are made of gold to prevent oxidation of the respective materials on both sides, and the two metals that are in contact with each other are made of the same material, so that the initial tack process is performed. It serves the two purposes of being easy to do. It should be noted that in most variations, the cap 14014, 14016 layer completely surrounds the other materials, but is only shown on the top for ease of explanation. FIG. 141 shows the same contacts in a simplified manner after the fusion process is complete. When the final bond of the metal is achieved, the two gold cap layers mix with the Au / Sn layer to form the Au / Sn alloy 14102, while nickel and Ti / Pd / Au are Au / Sn acts as a barrier to prevent mixing with each of the copper and pads on the top surface of Ti / Pd / Au. Thus, the fused Au / Sn 14102 is “trapped” between these two barrier layers 14006 and 14008 so that the composition of Au / Sn remains constant and homogeneous even when exposed to a number of subsequent high temperature steps. keep.

  In contrast, for example, if there was no nickel barrier layer 14008, the Au / Sn 14102 would result in a very thick copper layer 14010 (in the actual implementation of this example would exceed 60% of the Au / Sn thickness). Will be in direct contact with the wax. As a result, when temperature is applied, Sn diffuses into the copper and the properties of the resulting alloy begin to change dramatically. For example, the melting point of copper is 1084 ° C. When Sn first diffuses into the copper, the top of the rigid post becomes a much lower melting point Sn rich mixture (eg, a 97% Sn 3% Cu mixture has a melting point of about 230 ° C.). As Sn further diffuses into the copper, it will have a lower melting point than Au / Sn and the copper post will not be a rigid member in the tack-fusion process. Equally important is that copper 14010 exudes Sn from Au / Sn 14102 and raises the temperature at which Au / Sn becomes malleable. Accordingly, the rigid member having gradually increased flexibility tends to enter the malleable member having a gradually increased hardness. This affects the contact strength, uniformity, and ultimately, the density of contact spacing that can be used. In addition, the effects accumulate over time. Depending on the length of time during the fusion process, the composition and performance of the contacts will vary significantly. This is also true when the contacts undergo multiple fusion cycles, for example when the chips are stacked vertically in multiple stages. The chips at the bottom of the stack are very different from the chips that are later merged into the stack, and the behavior is not constant. Since the barrier metal is used to confine most of the Au / Sn, the same composition and the same characteristics can be maintained through multiple fusion processes. It should be noted that some interdiffusion may occur between Au / Sn and Ni, for example, even with a barrier, but the rate of this diffusion is much slower than that of Cu, so it is quite large. Up to a number of stack chips, for example up to 100, can be ignored. Thus, whatever material is used in a particular implementation, the barrier should typically avoid or minimize adverse interdiffusion as a constituent of the final bonded alloy.

  In a typical post-penetration approach, the two contacts that engage are shown to be mostly planar, but this is not a requirement for all applications and is not necessarily a desirable configuration. It is desirable to minimize low quality connections because the quality of the point-to-point electrical contact (or lack thereof) directly affects the resistance value of the connection, and low quality connections reduce yield. The risk of the high resistance connection produced can be easily reduced (without increasing the “projected area” of any contact) by the post-penetration technique, which has the advantage of improving yield. The approach includes improving penetration and increasing contact surface area by generating a pattern or profile on malleable contacts or penetrating contacts.

  If the malleable contact is made relatively larger than the rigid contact, the malleable contact can be profiled almost automatically if the malleable contact is directly above the IC contact pad. By patterning the malleable contact metal in a wider area than the IC pad opening on which the malleable contact is built, natural depressions are formed between the cover glass on the IC pad and the IC pad itself. Due to the relative height difference, it is formed near the center of the contact. FIG. 142 shows such a profiled malleable contact 14202. As shown, malleable contact 14202 is formed wider than IC contact pad 14204. As a result, the cover glass 14206 that is higher than the contact pad 14204 naturally causes the indentation 14208 of the malleable contact 14202. This natural indentation 14208 can better accommodate rigid contact 14210 due to its natural shape, and can even be aligned to aid alignment when the rigid contact 14210 is significantly close to the size of the indentation. The sex contacts 14202 are adapted.

  By profiling a rigid contact, the initial contact area is reduced, effectively increasing the applied force per contact unit area that improves penetration, while reducing the surface area gained by the profile wall in the depth direction. The increase ensures a sufficient area for electrical and mechanical contacts.

  For purposes of explanation, some non-limiting illustrative examples of the myriad of possible mother contact profiles are shown for circular, hexagonal, cross and square contact pads (FIGS. 143-1A) -143. -1H) and FIG. 143-3W), the inverted head of the pyramid base with the cube on top (FIG. 143-2K), FIG. 143-2L)), only the inverted head of the pyramid base (FIG. 143-2M) 143-2N)), or in-well posts (FIGS. 143-2O), 143-2P)) with respect to complex shaped contact pads in FIGS. 143-1I) to 143-2P) Illustrative shapes are shown in the figures and in the A-A section, and only in side views in FIGS. 143-3Q) to 143-3V). Needless to say, for use in the two or three conductor variants described above, or in any other simple or complex combination of shape and volumetric geometry, ring, or pyramid or any cubic A similar approach can be used for contact pads made with a “step” stack of original shapes.

  In another alternative, contact base “wings”, such as those shown in FIGS. 143-3V), can be used, increasing the surface area simply by providing additional lateral areas for the contacts.

  In addition, it may be desirable to use asymmetric or extending contacts (ie, varying widths in different directions to absorb strain in a particular direction, as shown in FIGS. 143-3X). Alternatively or additionally, a group of such asymmetric or elongate contacts may be arranged in a number of directions as shown in FIG. 143-3Y) so as to be symmetric around a point of zero stress Can be used with each other to allow any change in direction. Thus, in some aspects, the configuration of FIGS. 143-3Y) is a more sophisticated variation of the contacts of FIGS. 143-3T).

  Further, the contact profile provides an area for the malleable material to “grab”, which adds strength to the contact (FIGS. 143-1J), 143-2L), 143-2N), and 143-2Q. ), FIG. 143-2R), FIG. 143-2S), and FIG. 143-3U). Similarly, the post can be patterned to have a wide facing surface area or total surface area to ensure that an incomplete contact is a sufficient area contact. Furthermore, as shown in FIGS. 143-3T), a given contact can itself be made with multiple contacts, with the individual parts being electrically independent. Alternatively, some or all can be electrically connected to each other. This variant has a larger surface area to increase the shear strength, and if one or more of the sub-contacts is not aligned, the overall connection can still be made and has enough contact area to carry the required current To provide both redundant effects and so on.

  Furthermore, it should be noted that the particular shape of the contact pad, or the shape or configuration of the profile used, is not critical in nature. An important aspect is to increase the available contact surface area while providing an appropriate shape that couples to comply with engineering requirements for a specific application rather than for the specific contact or profile shape used. Using a profile. The engineering requirement is that the specific current used is the desired purpose compared to the ability to handle the total current requirement for the contact with the minimum allowable amount of contact and the potential for bad connections that would occur if no profile was used. Is to increase the surface area, probably by an amount sufficient to achieve this. Further, although discussed in connection with rigid / mother contacts, malleable / daughter contacts that are similarly profiled can be used. However, in that case, the contact configuration typically includes a rigid well configuration on the mother wafer.

  FIG. 144 is a photograph of an alternative embodiment profiled malleable contact having a pyramidal shape with rounded corners and a slightly dished or recessed top.

  FIG. 145 is a photograph of a profiled rigid contact designed to penetrate the malleable contact of FIG.

  The above will be briefly described with reference to FIGS. 146A) and 146B) showing parts of a pair of chips 14600 and 14602 similar to FIG. However, unlike the chip of FIG. 47, one chip 14602 has a profiled rigid contact 14604 as opposed to the unprofiled rigid contact of FIG. The other chip 14600 has malleable contacts 14606 similar to the malleable contacts shown in FIG. As shown in FIG. 146B), when the two contacts 14604, 14606 are joined, a post-penetration fit is formed. However, unlike the contact of FIG. 47, here each individual minipost of profiled contact 14604 penetrates to malleable contact 14606, thereby coupling to malleable contact 14606 using the same amount of pressure. Provides a surface-to-face contact area for a diffuse connection of a larger width than that available for non-profiled contacts of the same “projected area”. Furthermore, some implementations of profiled contacts offer the advantage of minimizing the risk associated with incomplete connections. This independent embodiment is also shown in FIG. 146B), but despite the fact that the connection between the two contacts 14604, 14606 is less than ideal (ie, there is a gap 14608 near the valley 14610 of the rigid contact 14604). The additional contact area provided by profile side 14610 on rigid contact 14604 means that the connection is acceptable.

  Expressed differently for purposes of illustration, assume that if rigid contact 14604 was not profiled, its contact area would have equaled the minimum contact area that could meet the total current requirement of the contact. . In that case, if any part of the contacts does not produce a good connection, the connection may be unacceptable, resulting in a defect that does not allow prejudice during use or complete unavailability. In contrast, in this example, the rigid contact of FIG. 146 is profiled. As shown in FIGS. 146A) and 146B), assuming that the profile increases the contact surface area by at least twice (the profile that can be easily achieved), even if only half of the total surface area produces a good connection, The connection can still meet the minimum total current requirement. Thus, as shown in an enlarged view in FIG. 146B), although there are areas where no contacts are made, these areas are much less than 1/4 of the required contact area required for a good connection. The use of is still acceptable.

  Alternatively, profiled contacts can be generated by using multiple small rigid contacts in conjunction with one or more larger malleable contacts to create a single overall connection. For example, each individual contact pair can have electrical connections made from three sets of contact pairs made from multiple rigid contacts and a single (or multiple) malleable contact.

  Further variations on the profiling concept, depending on the particular implementation, create "wells" that are designed to assist or improve alignment, constrain malleable materials, or help create good connections including. As illustrated and described in connection with the following figures, these well-attached variants further provide advantages and benefits to particular implementations.

  FIGS. 147-152 illustrate a variation of the process for implementing the well attachment concept for a mother and daughter wafer contact pair (FIG. 147). In this variant, the cover glass opening of the daughter wafer is used as a template, for example in polyimide, SU8, other epoxies, glass, and / or dielectric (FIG. 148a) in a permanent well. Produced. A similar technique is used on the mother wafer. However, the well does not surround the entire area where the cover glass forms a boundary (FIG. 148b)). The malleable material and (optional) malleable cover material are then inserted into the well of the daughter wafer, taking care not to fill the well to its full depth (FIG. 149a)). Similarly, a rigid material is deposited from the pad surface of the mother wafer (FIG. 149b)). The well on the mother wafer is then removed (FIG. 150), but the well on the daughter wafer is kept in that position.

  As a result, the daughter wafer wells constrain bonding materials (eg, covers and malleable materials) during the penetration process as well as during the tack phase (FIG. 151) and the fusion phase (FIG. 152) of the bonding process. It can also define a depth limit because the well has such a height that it will do something else after it hits another wafer or some surface on it (FIG. 152).

  Through this approach, the advantage is that this well allows the cover or cap material and / or the malleable material itself to normally expand so that it reaches the true melting point, or at least to a temperature at which it becomes sufficiently flexible. It makes it possible to be made of a material that is in the liquid phase. This is useful in situations where the contacts are placed close to each other and the flexure that typically occurs during melting causes the material to swell laterally to reduce surface area. For contacts where the spacing between well-free contact edges is less than about 3 times the height of the malleable material, a pre-integrated plan to use it is desirable (for example, if the height of the malleable material is 8 μm This approach should be considered when the spacing between contact edges is about 25 μm or less).

  Furthermore, if they are too close to their melting temperature, some materials may “wet” the wafer surface rather than spread, and they may creep along the surface. In the case of malleable contacts, if no measures are taken, the creep action may cause an electrical short between adjacent contacts. By confining these materials in the well, any wet creep will be counteracted by surface tension, confining the material in the well. That is, the adjacent contacts are prevented from being short-circuited.

  Wells can cause significant problems in some implementations, for example when performing post-bonding processes that can melt the combined contacts. For example, after the contact is made at the appropriate temperature for the rigid- malleable contact to be made, the combined chip needs to be soldered into the package, but the required temperature at the soldering step is Even if it is above the melting temperature of the contact at the time the step was present at the completion of the fusion phase, the molten material is encapsulated in the well so that it remains intact during this process and reattaches upon cooling. It should be.

  In addition, this well technique is well suited for making a large number of densely packed connections because the well is patterned using semiconductor lithography techniques that are not conventional mask printing or solder techniques. In an alternative variation, the “reverse” of the well process described above can be used. In these variations, the process is performed such that the well is not filled with malleable metal. These variations correspond to one of the four classes described in FIGS. 153 to 156, respectively.

  Class I (FIG. 153): In this class of well connections, the daughter wafer contains malleable material and the mother wafer has a rigid well (shown as etched in the semiconductor wafer). The well is covered with a diffusion layer metal, for example, Au. To bond the two wafers, the malleable material on the daughter wafer is inserted and deformed inside the well. Temperature and pressure are added during the tack phase to form a tack connection to the malleable material and the diffusion layer. During the fusion phase, the malleable material of the daughter wafer and the diffusion layer of the mother wafer interdiffuse to form a metal bond. Depending on the particular implementation, the malleable material may be slightly larger than the well, or at least contain more volumetric material, to strengthen the fit of the two wafers during the tack phase. Can be free of voids after the fusion phase is complete. It should be noted that this class is contrary to mother / daughter practice.

  Class II (FIG. 154): This class is similar to Class I, but forms wells or malleable “posts” in a shape to automatically or more easily align between them. It should be noted that this class is also against mother / daughter practices.

  Class III (FIG. 155): In this class, the post is a “rigid” material and the well is coated with a malleable material to a certain thickness. This is similar to the basic profiled malleable contact technique described above. However, the malleable material has a more conspicuously recessed profile than a recess that is only naturally obtained from the height difference between the cover glass and the IC pad. Again, it is desirable to select post and well dimensions so that there are no voids after accumulation (ie, completion of the tack-fusion process).

  Class IV (FIG. 156): In this class, the well is coated with a diffusion layer (similar to class I and II), the post is made of a rigid material, but the outside is also coated with a layer of malleable material. The This creates the same situation as class I and II. However, when the material cost of the rigid material is lower than the cost of the malleable material, for example, when the rigid material is almost copper and most of the malleable material is gold, the cost of the daughter wafer can be reduced.

  Using the techniques described above, the well can be formed, for example, using a dielectric or can be recessed (ie, fabricated into a semiconductor by etching). Further, the well can be a byproduct of the via formation process. For example, it can be part of a via that is not completely filled. FIGS. 157A and 157B are photographs of longitudinal sections of a pair of 15 μm diameter vias extending to a depth of 135 μm and 25 μm diameter vias extending to a depth of 155 μm, respectively. FIG. 158 is a photograph of a similar via that is not all filled up to the bottom formed. As a result, natural wells are formed by thinning the backside of the wafer until the bottom of the via is exposed. As is, this well can be used as a Class I well. Alternatively, class II wells can be obtained by etching the flare or taper at each mouth.

  FIGS. 159-167 illustrate a further variation of the Class II type rigid well attachment technique. This deformation of the rigid hole well begins with one of the fully formed wafer and, in particular, one of its pads 15902 exposed through the cover glass 15904 (FIG. 159). Optionally, first a barrier layer 16002 is deposited on the IC pad 15902 (FIG. 160). Next, a region around the IC pad 15902 including some of the cover glass 15904 is exposed by patterning the photoresist (FIG. 161). The well is automatically formed by a metal deposition process in a recess formed by the cover glass on the IC (FIG. 162). This makes it easier to pattern than some of the other rigid well hole processes. Photoresist stripping removes excess and unwanted metal remaining behind the fully formed rigid well (FIG. 163).

  Like other Class II variants, this variant is contrary to mother / daughter practice. This is because the wafer 16402 that supports the mating side of the wafer of FIG. 163 does not have a rigid “post” in the sense described above, but instead a standoff in which the relevant part is covered by a cap 16406 of malleable material. 16404 (FIG. 164). The rigid hole formation itself allows penetration of the malleable part on the standoff (FIG. 164) with good fit and sufficient surface area. As shown in FIG. 165, the malleable cap gets wet and adheres to the post by heating. As shown in FIG. 166, during the tack phase, malleable cap 16406 goes into a liquid or semi-liquid phase and fills void 16502 in FIG. This is desirable because the gas trapped in the void may expand and contract during the thermal cycle, thereby reducing contact reliability. When the malleable cap fills the void during the tack phase or at the start of the fusion phase, the fusion phase allows the malleable cap to diffuse with the rigid cap and the malleable material to form a fused final connection 16702 ( FIG. 167).

  The profiled contacts of FIGS. 143-2O), 143-2P) or 146 can be used to form further alternative well attachment variations. In this variant, the well is formed by a pattern of rigid material so as to form a wall that prevents the liquid phase material from getting over if something happens. Thus, this approach allows the use of the process regardless of the use or non-use of the stiffness-extensibility principle and allows for very high density connections. This is because, when properly designed, the wells contain any liquid phase material or prevent the lateral bulge of the malleable material from going too far, in any case allowing high yields with high density contacts.

  FIGS. 168-170 show a further variation of the well attachment technique in which the chips are attached to each other by separate spaced contacts. This technique is advantageous for application in at least the following three situations. That is,

  1) Situations where it is not desirable to form a cover material on a malleable material as it may adversely affect the material bonding method;

  2) A situation where the deposition is performed at a very low temperature (or in some cases at room temperature) to increase the speed of the process. For example, if each wafer has a very flat surface, the van der Waals forces can be applied to the chip, or with dangling atomic bonds, like oxides, nitrides or other dielectrics Can create a covalent bond that allows the connection to be made with a simple insulator (this avoids or reduces the waiting time for the part to reach temperature and eliminates the need for a machine with thermal management capabilities) May reduce equipment costs); and

  3) As mentioned above, the liquid phase can flow or creep, thus limiting the potential density of the actual contacts, so that the subsequent fusion process without completely changing the main contacts to the liquid phase. For situations where it is desirable to reflow (change to liquid phase) the adhering material so that the tip is automatically centered for the purpose (this allows the remote mounting contact to indirectly provide that level of accuracy, so that The alignment accuracy required by the high pitch (density) is not necessarily required, and the equipment used for the adhesion can be made inexpensive).

  By way of example only, the remote contacts 16802, 16804 can be made from materials such as indium and are flexible at room temperature so that they can be applied simply by using pressures that push the parts together. Alternatively, any other low-temperature material that can be bonded without the application of high temperatures can be used, and whether it is a special material is generally trivial, as long as it does not adversely affect the whole (ie, it causes a short circuit). That is. For example, low temperature solder (less than 250 ° C.) can be used. Once in its liquid state, the surface tension allows the two chips to be aligned with each other, so the attachment process can be performed with inexpensive elements of equipment with low alignment accuracy, such as a conventional pick and place machine. . In addition, if very flat, remote contacts can be constructed such that the chips are aligned and held together by a simple covalent bond.

  As shown in FIGS. 168-170, this process uses separate contacts to connect the devices during the initial deposition phase (pre-tack phase). FIGS. 171A and 171B show top views of alternative spaced contact variants similar to FIGS. 168-170. These separate contacts can be completely separated from the electrical contacts, for example, around or around the individual chip (FIG. 171A), or can be interspersed between actual electrical contacts ( FIG. 168, FIG. 171B). In addition, the remote contacts as described herein are compatible with all variants of the main contacts and do not need to be narrow pitch, so they can be much larger in height and width than the main electrical contacts. There are advantages. Preferably, the main contact should be high enough so that it does not need to be contacted during the deposition process (FIG. 169). It should be noted that this attachment or adhesion process need not be high strength. It is the subsequent fusion process of the main contacts that can provide strength to the bonded chip. FIG. 170 shows the wafer of FIG. 169 following the fusion process so that the main contacts are permanently combined with each other with a high strength bond.

  In general, as with the tack stage, the fusion stage is performed at a higher temperature and pressure than is required in the attachment or adhesion stage of this variant.

  Again, similar to materials that can change to a liquid or semi-liquid phase during the tack-fusion phase, compression of the adherent contact will cause the contact to expand laterally and / or the material. This heating changes the contact into a liquid phase and spreads outside, and if it spreads to the main contact, an electrical short circuit may occur. Thus, one advantageous option is to apply the principles of forming “well” type electrical contacts described herein to remote contacts. In this way, there is no contamination of the main contacts, no short circuit, they can become liquid or spread laterally during pressure or at temperatures during the tack-fusion process.

  There is the advantage that the remote contacts can be configured so that the actual contacts can be bonded to each other after the two chips have been inspected before or before the bonding at the tack-fusion stage. If you are designing a chip to test whether a particular individual chip combination works, the layout of the remote contacts should be the same as the special pad layout that allows interchip communication. If one or both of the chips does not work (ie, does not work or works but is out of specification), the chip can be removed and a new chip can be applied.

  In addition, the appropriate design allows the design to incorporate whether bonding is done on a wafer-to-wafer, chip-to-wafer or chip-to-chip basis, so this pre-tack pseudo-hybridization testing approach is It will produce great value. Accordingly, the choice of type of bond used for a particular application (ie, wafer-to-wafer, chip-to-wafer or chip-to-chip) may be a factor in inspection capability to some extent. For example, if inspection is possible on a one-wafer basis, all chips on two wafers can be hybridized in parallel on a one-wafer basis, and a non-operational chip that has been cut or diced will have a rework flag Stand up. Alternatively, use this approach when each die comes from one or more foundries and there is no good way to know which given die is a known good die before the hybrid. it can.

  In yet another alternative variation, distant materials are the same material as the main contacts (e.g., stiffness and rigidity) so long as they are taller than the main contacts so that they do not contact during the initial deposition phase. Malleability). The separated contact is then further compressed than the main contact during the fusion process. By using the same material on the remote and main contacts, processing is simplified.

  From the above discussion, derived variants can be derived that build and combine ideas from multi-axis through vias, well attachments, profiled contacts, and remote attachment variants.

  The first group of variations involves complex contact shapes (ie, contact shapes other than the conventional single square or single dot). One such embodiment involves the generation of shielded contacts, the simplest being a two-coax or triax with a square (FIG. 172A)) or circular (FIG. 172B) cross-section. Similar to a through-chip connection and in more complex cases, an irregular open or closed geometry (FIG. 172C)).

  In the case of two or three coaxial contacts, the inner contact is connected to transmit a signal, while the outer closed ring acts as or is connected to the ground plane. When used with a coaxial via (FIG. 173), this ensures that the contacts are shielded throughout the path to another chip. Additionally or alternatively, the use of coaxial contacts independently from the via itself (FIG. 174) ensures that each contact itself is shielded. Thereby, the distance of a chip indirect point can be made closer than the case where a coaxial method is not utilized. In addition, the outer contact rings of each contact are connected to each other and / or to an electrically isolated metal on the wafer to form a ground plane and / or to form a shield between chips (FIG. 175).

  When the outer ring of contacts is used as ground, only the area where the signal is transmitted passes through a very small opening in the shield layer, thus allowing shielding between chips. The same is true for three coaxial connections where the differential signal pair is in the outer ground plane. Therefore, such contacts are particularly well suited for chips that transmit high speed or RF signals.

  A second group of variants is that there is an airtight seal between the two chips (or between the chip and the package or board) and there is a connection pad, for example an I / O pad, or between two external devices. The focus is on using contact techniques to protect other devices (eg, optical devices) that may be present. In this situation, the connection pads and / or optical devices are pre-existing or integrated to be present at the same time, between two elements (eg between two chips or between one chip and a package or board) ). The ring is formed on two elements outside the area to be protected and is configured to be coupled using either malleability / rigidity and well attachment processes, thereby hybridizing the two elements to each other. As a result, an airtight metal seal is formed surrounding everything inside. This hermetic package can withstand virtually any environment because it is not affected by most environmental conditions due to the non-porous nature of the metal.

  The main advantage of some variants of our approach is that it uses malleable and rigid connections, so there are a variety of connections (versus other connection techniques such as liquid phase metal solder). Any geometrically closed shape can be employed. This is in stark contrast to liquid phase materials, which tend to flow out and change shape due to surface tension to the smallest possible surface area (eg, cubes to spheres, corners to round). On the other hand, various techniques are used to allow the liquid phase material to escape along the predefined surface of the chip, for example by capillarity, so as to ensure proper material distribution around the contacts when involving complex shapes. And there is no reliable way to avoid void formation or to prevent some material from flowing out of the defined area and potential contact shorts. Conversely, in a variation of our approach, the simplicity or complexity of the shape is almost irrelevant. Because this approach is the same regardless of shape, the only limitation relates to the ability to define the shape with photolithography and the ability to deposit the appropriate metal.

  FIGS. 176-179 show the two simple embodiments described above. Specifically, FIG. 176 shows a sandwiched device (not shown) that further surrounds and surrounds the device region 17602 to form a hermetic seal around the periphery as described herein. A corresponding chip surface having a region 17602 constituted by a pair of rigid contacts 17604 and malleable contacts 17606 is shown. FIG. 177 shows a side view of the AA cross section of the chip of FIG. 176 after bonding. FIG. 178 shows a more complex knitting where the rigid contacts 17802 and malleable contacts 17804 are more complex in shape, effectively forming three different chambers hermetically sealed around the device regions 17806, 17808, 17810. Is done. FIG. 179 shows a side view of the AA cross-section of the chip of FIG. 178 after bonding.

  At this point, the rigid / malleable contact deformation and via formation deformation can be summarized in chart form using the diagrams of FIGS. 180, 181A, 181B.

  FIG. 180 is a different approach summarized in the chart for forming other variations using the rigid / malleable contact criteria. The chart reads down in a column format, each column containing text represents a step in the process, and each blank (or portion thereof) represents no action required.

  181A, 181B, and 182 are similarly charts summarizing different techniques for forming via variants, including those described herein. These charts also read down in a column format, with each column containing text representing a step in the process, and each blank (or portion thereof) represents no action required. The bottom column in FIG. 181A continues to the top column in FIG. 181B.

  In many of the above embodiments, the technique has been described with reference to metal deposition on a daughter wafer or an alternative to plating a daughter wafer. To better understand, FIGS. 183 through 192 describe the process flow of a particular case involving metal deposition on a daughter wafer in more detail. Thereafter, FIG. 196 to FIG. 205 show a process flow of plating a daughter wafer using the same wafer from the beginning.

  The process begins with each of the daughter and mother wafers of FIG. Photolithographic patterning is performed on a daughter wafer using, for example, a Hoechst AZ4903 or Shipley STR1075 10 μm resist target. A 200 Å Ti, 3000 Ｐ Pd and 400 Ａｕ Au barrier and routing layer is then deposited on the daughter wafer, and a 1000 Ｔｉ TiW barrier layer and a 3000 銅 copper seed layer are deposited on the mother wafer (FIG. 185). ). Next, a thick dielectric (thickness 7 μm) or photoresist is applied to the mother wafer, leaving a 10 μm opening on the pad, assuming a 14 μm wide IC pad (FIG. 186). The daughter wafer was then metallized by depositing a layer of Au / Sn on the daughter contact until the height was about 6-8 μm on the IC cover glass (more usually less), then Finish it with 400 Ａｕ Au (Figure 187). The mother wafer is metallized on the IC cover glass to a height of 4.4-5 μm (FIG. 187). The photoresist is then stripped from both wafers (FIG. 188). Next, photolithography patterning is performed on the mother wafer to produce 15-16 μm wide openings in preparation for barrier deposition (FIG. 189). Alternatively, a self-aligned seed etch that is as wide as necessary to ensure that the undercut does not affect the bump can be performed. Next, a 2 μm Ni barrier with 3000 Å of Au on top is deposited (FIG. 190). Next, the photoresist is removed (FIG. 191). Finally, an unnecessary seed layer is removed by etching (FIG. 192). Since Ni / Au allows etching through Cu / Ti / W, this can be performed as a self-aligned etch using a spray etcher so that photolithography is not required. For example, if self-alignment etching cannot be performed because a spray etcher is not available, an additional patterning step by photolithography (FIGS. 193, 194, 195) is required to protect those areas that are not etched. . However, depending on the etching technique, the potential for significant undercuts, such lithography should ensure that the protective photoresist is wide enough to prevent unwanted undercuts (FIG. 193). For example, the inventors have performed such etching with 50 μm pitch contacts, and in case they are about twice the width of the IC pad, in this case 27 μm for a 14 μm pad. Protected the area. However, if a spray etcher is used to perform self-alignment etching, undercuts of less than about 1 μm are possible, so that much smaller areas can be protected by that technique. Thereafter, die cutting, alignment, tacking, and fusing processes can be performed according to the desire to join the two.

  In contrast, the process flow for the plating case is shown in FIGS. 196-205 as follows. Again, this process begins with the wafer of FIG. Initially, the daughter and mother wafers each have a Ti0.1 / W0.9 barrier, and a 3000 Ｃｕ Cu reroute (daughter wafer) and seed layer (mother wafer) (FIG. 196). Next, as shown in FIG. 197, when photolithography patterning is performed on the daughter wafer to limit the barrier application region and a thick dielectric layer (thickness 7 μm) or photoresist is applied to the mother wafer, 14 μm. Assuming a wide IC pad, an opening of 10 μm remains on the pad as shown in FIG. The daughter wafer then has an added barrier layer (FIG. 198) and when the photoresist is stripped from the daughter, unwanted barrier metal lift-off appears (FIG. 199). Next, photolithography is performed on the daughter wafer using, for example, a Hoechst AZ4903 or Shipley STR1075 10 μm resist target (FIG. 200). Next, the daughter and mother wafer are metallized by plating on the mother wafer to a height of 4.4-5 μm on the IC cover glass and to a height of 6-8 μm on the daughter wafer (similar to FIG. 187) ( (FIG. 201). Furthermore, according to the complexity of plating, for example, a 400 mm Au cap can be applied. Next, the photoresist is removed (FIG. 202). Next, a barrier is added by using patterning by photolithography on the mother wafer (FIG. 203). A barrier is then deposited on the mother wafer (FIG. 204). Again, the photoresist is removed from the mother wafer (FIG. 205). Thereafter, excess seed is removed using self-alignment etching as shown in FIG. Similar to the deposition example above, if a spray etcher is not available, additional photolithographic masking, etching and stripping steps are required to make the protection area large enough to allow for etching undercut.

  At this point, the dicing, alignment, and tack-fusion processes can be performed as desired to join the two together.

  Based on the above description, it is beneficial to note the advantages and disadvantages of each approach, which helps in selecting the process type to use for a particular application.

  The advantages of the deposition technique for the daughter wafer are: no seed layer, no electroplating, one mask process, and automatic Au / Sn composition accuracy. However, this method has the following disadvantages: thickness control from run to run is difficult, metal “wings” appear when deposition direction is off, and Au reuse program is required It is.

  Advantages of plating techniques for daughter wafers: Conventional, currently available plating equipment can be used, so it is inexpensive and does not need to be regenerated and can be supported by major equipment vendors. However, the disadvantage is that the required composition accuracy is +1.5% / − 2.5%, which may require an additional masking step.

  For mother wafers, there are basically three process variants:

  1) Electroless plating (shown in FIG. 206a (chip), FIG. 206b (6-8 μm Ni plating), FIG. 206c (cap of 3000 mm Au));

  2) Copper electroplating process for thin resist (FIG. 207a (first masking), FIG. 207b (4.5 μm copper), FIG. 207c (2 μm Ni covered with 3000 Ａｕ Au cap), FIG. 207d (first 2 masking), shown in FIG. 207e (excess seed removal by etching));

  3) Electroplating process of thick resist with copper (Fig. 208a (first masking), Fig. 208b (copper plating), Fig. 208c (second masking, barrier and cap), Fig. 208d (third masking), Fig. 208e ( Excess seed removal by etching)).

  The advantages and disadvantages associated with each are as follows. The advantages of the electroless approach are: no separate barrier deposition; no seed layer deposition; no seed etch required; and maskless process. However, electroless plating of nickel is difficult in terms of controlling thickness or nodule formation and may affect yield, and may not be suitable for large-scale wafer production. The advantages of the thin dielectric process are: because the thinner Ni is used, the process becomes more controllable; low stress copper is covered on the IC cover glass; the use of copper is the mainstream; Electroplating has better controllability. However, the Ni / Au penetration on the mushroom-shaped side may not be constant and exposed copper may remain; the mushroom shape is not optimal for the tack process, so additional processes (ie seed deposition, seed etching) Etc.) is necessary.

  The advantages of a thick dielectric deposition process are: good contact or “bump” shape, copper over the barrier / cap, good uniformity and shape control, less Ni nodule formation, typically in high volume processing Includes the advantage of achieving high yields. However, with this approach, if self-aligned seed etching is not effective, a special masking step may be required and a spray etcher may be required.

  Continuing with the deposition and plating variations, further details of some mother and daughter contacts will be described to better understand the process.

  FIG. 209 shows an example and some typical dimensions for a mother wafer contact with 14 μm wide contact pads spaced at a 50 μm pitch prior to barrier deposition.

  FIG. 210 shows the contacts of FIG. 209 after barrier and cap deposition.

  FIG. 211 shows typical dimensions for a mother wafer contact having 8 μm wide contact pads spaced at a 25 μm pitch.

  FIG. 212 shows one example and some typical dimensions for a daughter wafer contact having 14 μm wide contact pads spaced by a 50 μm pitch produced by deposition.

  FIG. 213 shows an example and some typical dimensions for a daughter wafer contact produced by deposition and having 8 μm wide contact pads spaced at a 25 μm pitch.

  FIG. 214 shows an example and some typical dimensions for a plated version mother wafer contact with 14 μm wide contact pads spaced at 50 μm pitch before a self-alignment seed etch is performed.

  FIG. 215 shows the contacts of FIG. 214 after performing a self-alignment seed etch.

It should be noted that the range of Au / Sn presented in conjunction with FIGS. 212 to 215 is a representative example of a more typical range. In practice, when proper temperature control is performed (
That is, the higher the Au content, the higher the temperature, and the lower the Au content, the lower the temperature). Use a range of approximately Au _0.7 Sn _{0.3 to} Au _0.9 Sn _0.1 or a wider width. Can do.

  Although a number of through-chip connection variants and applications have been described for various inter-chip connection electrical aspects, alternative additional optional variants have the advantage of implementation including unfilled inner grooves or voids, Alternatively, a variation not particularly related to chip-to-chip signal transfer is presented.

  In particular, if the innermost void is left unfilled, an alternative stacking variant with many advantages can be generated. By sealing the voids from the surrounding components but leaving them in communication with each other, these voids are used to help, for example, cool the stack of chips.

  In this variant, when a series of wafers having such vias are attached to each other, the material around the vias protects the via sidewalls inside the resulting semiconductor wafer and is filled with continuous and adjacent air and liquid. Stack in such a way as to produce a cut tube. The stacked parts are knitted so that the tubes extend through some or all of the stack. One end of the tube passing through the chip stack is covered by a structure having a condensation region, for example, connecting one end of the tube to a tube embedded in a heat sink. When filled with the appropriate fluid (and core if necessary), each of these tubes acts as a heat pipe and can efficiently extract heat from the IC stack. Optionally, the electrically insulated metal can be connected to the heat pipe between the stack chips on the unused chip surface space and extended outward (fin or plate) to increase heat transfer capability. In addition, the fins or plates are formed by barriers or seed layers, potentially giving them many roles, for example by serving as fins at the same time in addition to the shield or ground plane. Can be made.

  This is accomplished, for example, as shown in FIG. 216 by using the inner via as part of the heat pipe knitting. FIG. 216 shows a simplified portion 21600 of a chip stack consisting of several individually stacked identical or different chips 21602-1 to 21602-n + 1. In this embodiment, each inner metallization 2402 is connected one up or down (a process described herein such as a post-penetration connection, or some other such as wafer fusion or covalent bonding). The inner voids are hermetically sealed together, thus creating a tube 21604 in the chip. Appropriate fluid 21606 (as needed) to create heat pipes that help to transfer heat from the individual chips 21602-1 to 21602 -n + 1 through which heat passes, for example, to a heat sink 21610 or other cooling device. The core 21608) is housed in the tube at an appropriate pressure.

  Depending on the particular implementation, one end of the tube can be sealed to doped semiconductor material or substrate 21612 in the chip (ie, the tube does not penetrate) or does not include a portion of the tube itself, but merely as a stopper or plug. It can be sealed to the surface material of another chip that only functions. In addition, multiple tubes can be formed, each having a different working fluid, or different pressures on the working fluid (which can be the same or different), so as to have different evaporation and condensation temperatures. In this way, a wide range of heat pipe operations can be obtained. In addition, these heat pipes can be grouped or distributed around the chip for thermal “hot spots” on the chip.

  In some variations, if any, the core 21608 can be made of, for example, a porous or capillary structure, sintered powder, fluted tube, mesh, carbon nanotube structure, graphite or any other suitable core material. Furthermore, the working fluid may be any heat pipe fluid as long as it does not corrode, degrade or otherwise adversely affect the surfaces in contact with it (ie doped semiconductors, substrates, insulators, conductor metals, etc.). it can. Exemplary working fluids can include water, alcohol, acetone, or optionally mercury. Furthermore, some variations may be solid at 68 ° F. (20 ° C.) in 1 Atm (101.3 kPa) when evaporating or sublimating in a manner suitable to provide the requisite evaporative heat transfer required for heat pipes. Can be used. Finally, it should be noted that prefabricated (i.e., prefabricated) heat pipes can be used as long as the dimensions are suitable for insertion into the inner via.

  This method places heat pipes near the place where heat is generated and distributes the heat pipes throughout the chip, so that whatever cooling method is used, the efficiency is improved. be able to. Furthermore, it goes without saying that the above technique can be used to create a heat pipe in a chip where it is desired or required to have no electrical connection.

  Often it is desirable to electrically insulate the chips from each other to prevent electrical crosstalk. In addition, when stacking devices vertically using one of the via processes described herein (or variations thereof), the two chips are interconnected with a third chip that communicates with both. Although desirable, there may also be applications where the third chip may intervene between three chips or between two chips. Needless to say from the above description, the process for forming the wafer interconnect has been described for one or two contacts, but does not depend on the total number of contacts, and there are chip contact pairs for the rest of the wafer. It does not depend on where it resides (ie on one or more chips). This means that in some cases a single daughter chip can bridge two or more mother wafer chips, or a “daughter wafer 2” chip can bridge two daughter chips, or a mother and a daughter chip. It is. Thus, bridging is a simple application of the additional process of “Daughter Wafer” or “Daughter Wafer 2”, the process is the same, but the full set of connections to which the daughter chip connects are all on the same chip. It does not necessarily have. However, in the specific case of this variant, the heights of the two base tips (i.e. the tips bridged by a single tip) may be different. Therefore, it is necessary to cope with such a difference in height. There is an advantage that this can be achieved by further variations of the via process herein. FIGS. 217A) and 217B) show two embodiments of the method. FIG. 217A) shows the insulation aspect of this variant, and FIG. 217B) shows the bridge connection aspect. In both cases, you get the same shielding benefits. In combination with the previous approach, as can be seen, in step 1, one or more chips with vias are attached to the base chip. In this case, a via (or another contact post connected to the top chip) is made to extend a certain distance over the attached chip. This can be accomplished, for example, by metal plating or by removing the substrate material to expose more metal, depending on which of the via process variants is used. In this approach, the chips are typically hybridized to each other after the vias are created. In the case of the chip of FIG. 217B), in step 2, non-conductive, such as polyamide, BCB, another polymer, a dielectric containing oxygen or nitrogen, or other non-conductive material that can be deposited on the wafer surface. Coat the wafer with a layer of material. In the case shown in FIG. 217A), the layer thickness is determined by the need to insulate the two vertically stacked chips from each other. Since signal strength attenuates with distance, capacitance coupling attenuates with distance, and EMI interference attenuates with distance squared, this thickness is typically thicker than the width of the signal line (eg, > 5 μm), but some variations can be much thicker (eg, 25 μm or more) for better insulation. As shown in FIG. 217B), the two attached chips can be at different heights. The reason for the height difference is independent of the process, but is due to being etched or thinned differently and made on a substrate that was originally of different thickness, or due to lapping or polishing. Depending on the care performed during the process, height differences up to 100 μm or more may be generated. In either case, the coating material is added so that it is at least as high as the top surface of the thickest chip attached to the base chip. If a routing layer is not required (discussed below in conjunction with step 4), this step 2 may be optional in some variations of FIG. 217B). In step 3, the wafer is lapped or polished to expose vias or other tall, plated or metallized connections of various chips. In step 4 (optional), the polished / lapped wafer surface can be patterned and an electrical routing layer (if needed) deposited on the surface to facilitate connection placement. This allows two chips that do not have matching pads to be connected to each other by routing signals to where they need to be connected to each other. Furthermore, in the situation of FIG. 217B), the two chips in the lower layer can be separated further than the paired connection on the upper chip arranged in Step 5 by the path change. In step 5 of FIGS. 217A) and 217B), another chip is attached to the structure by one of the variants of the hybridization method, for example a malleable and rigid hybridization process. The process from step 2 to step 5 is then repeated to add subsequent layers (of course, the tip attached in step 5 has or has a post extending an appropriate distance from the surface upwards. Is assumed to be possible). The chip of step 5 has the advantage that it does not need to have vias unless it must be connected to an additional layer on the top surface of the structure.

  FIGS. 218A) and 218B) show an alternative variation approach to accomplish the task of FIG. 217A) or FIG. 217) B. In this alternative variant approach, rather than thinning the chip in step 3 of the process of FIG. 217A) or 217B), this example typically etches holes in the planarizing material, which is polyimide. To do. Then, using the routing layer of step 4, the electrical signal (if necessary) is routed and connected to the lower chip. Hybridization can then be performed as shown in step 5 of FIG. 218A) or FIG. 218B). This procedure is more complicated than the approach of FIG. 217A) or FIG. 217B) because the electrical contacts are made after hybridization is required. However, as shown in step 6 of FIG. 218B), this process is easier to make subsequent chip connections to many other layers simultaneously than in FIG. 217B). It is more difficult to do the same with the technique of FIG. 217B), and the polishing in step 3 of FIG. 217B) can grind all posts to the same height, so that the upper daughter tip is It becomes difficult to adhere to the lower daughter chip.

  As noted herein, a stack can be formed with any number of multi-element heights. However, depending on the specific case, in some cases, in addition to deciding whether to combine with tack, fusion, tack, fusion method, and tack, tack, tack, global fusion method, stack effects and It is necessary to consider the geometry. For example, in a wafer scale stacking process as described herein using through-via connections, whether the original daughter wafer is pre-thinned and then diced to bond with the mother wafer, or mother wafer (per-chip It must be determined whether it should be thinned after bonding to (on a whole wafer basis). The difference is as follows. Tacking, fusing, thinning, tucking, fusing, thinning techniques eliminates a few steps, and more importantly, very thin wafers when dicing before dicing and competing can reduce yield This is advantageous in that it does not have to be handled. The disadvantage is that it requires a lot of manpower for hybrid parts. That is, the difference between thinning on a more expensive hybridized part versus thinning only the daughter wafer (reducing yield).

  Another drawback appears when there are several daughter stacks on the mother chip, each stack having a different number of chips. Since the thinning steps need to be performed separately for each layer of chips on the mother wafer, the placement and sequence of the thinning steps is important. As a result, without proper planning, some stacks reach a point where additional chips cannot be added. This is because the additional chip is below the height of the adjacent stack, making it difficult or impossible to thin the chip.

  In contrast, the thinning step before bonding has the advantage that it can always be performed, but the drawback is the increased risk associated with having a thin wafer.

  Although a number of various alternative, optional and complementary variants have been described, the exemplary application described above is presented here with reference to FIGS. 219-221 and achieved in a specific application, ie, a microprocessor application. Here are some additional advantages that can be made.

  FIG. 219 shows a conventional microprocessor chip 21900 as a representative example, and components (that is, a conventional arithmetic unit (ALU) laid out in a coplanar type, a register (REG), a buffer and others). Logic (BUFFER & LOGIC), input-output (I / O) device, primary cache memory (L1), secondary cache memory (L2), memory control (MEM CTL), memory read / write control (R / W CTL), random The steps for identifying access memory (RAM), read only memory (ROM), and memory decoding circuit (RAM / ROM DECODE) are simplified. As can be seen, the component elements occupy a significant area and there is a significant distance between a given component and most other components.

  FIG. 220 illustrates how, using the above approach, an alternative microprocessor can be constructed from the same elements with a narrow projected area, fast and slow mixing techniques, and substantial distance reduction between elements. Simplified and shown. Specifically, FIG. 220A shows an alternative to a microprocessor 22000 made of the elements of FIG. 219, having a projected area that is reduced by the use of through-chip connection and element stacking as described herein. Through stacking, the elements are formed in chip units 22002, 22004, 22006 (side views) and are shown in exploded views 22008, 22010, 22012, respectively), thereby increasing the overall projected area covered by the constituent subcomponents. cut back. Further, as shown in the respective side views 22008, 22010, 22012, through-chip connection substantially reduces the distance between all subcomponents of each of the chip units 22002, 22004, 22006. Furthermore, chip-to-chip connections within each chip unit 22002, 22004, 22006 need not be made at the periphery, and can be made virtually anywhere on the subcomponent chip.

  FIG. 221 shows a direct comparison between the projected area of chip 21900 of FIG. 219 and that of chip 22000 of FIG. As is apparent from the figure, the projected area of the latter is considerably smaller than the former, although both have the same size and the same number of elements.

  A further advantage can be obtained if the chip is designed with the possibility of stacking in mind. For example, in the embodiment of FIG. 220, it is only necessary to design the subcomponent chips independently and share a common interface with the other, so that the processing units 22006 and 22012 can be designed in various mixed and matched configurations. Thus, a common family of processing chip units can be created more easily because several different ALUs at different speeds can be designed. Similarly, different sized L2 caches can be designed for use within the processing chip unit 22006 to vary pricing within the family or enhance performance. This idea is a special case of what is described below as intelligent active packaging.

  As can be readily appreciated from the previous discussion, a further byproduct of the processes and aspects described herein is the ability to efficiently generate a different type of “packaging” (FIG. 222). .

  Currently, complex integrated circuit chips are generated and packaged as shown in FIG. 222A). All low-speed functions, high-speed functions, I / O and high-speed functions (ie, core analog and digital functions) are generated on a single chip through front-end processing. Next, back-end processing adds layer metallization to the chip, creating connections between various on-chip devices. Finally, when the chip is completed, it is attached to individual packages such as pin grid arrays, ball grid arrays, conventional IC packages, and the like. The approach has many drawbacks, including all devices must be implemented with the highest speed / maximum cost technology required for any on-chip device since all devices are on the same chip. is there. As a result, high cost areas are wasted by low speed and / or low cost devices that can be easily implemented with slower or cheaper technology.

  However, using the aspects described herein, the benefits of using various types of packaging to help optimize process costs and time, and low yield risk, to name a few There is. For example, by using the aspects described in this specification, the configurations illustrated in FIGS. 222B) to 222F) can be generated.

  FIG. 222B) is achieved using the aspects described herein, which we call a non-routing architecture, because the routing process can be separated from chip formation and both can be performed simultaneously. An organization of one exemplary embodiment that can be shown is shown. In this embodiment, the chip (chip 1) is generated using front-end processing including low speed functions, I / O and core analog and digital functions. A second chip (chip 2) is generated using a back-end process to generate a metallization layer that interconnects devices on chip 1. Then, chip 1 and chip 2 are hybridized to each other, for example, using wafer-to-wafer or coplanar bonding techniques, wafer fusion, etc., using the techniques described herein. This hybridized unit can then be handled as a conventional chip and connected to a conventional package in a conventional manner, or further hybridized to another wafer, chip or element, eg, as described herein. It can be processed.

  Another alternative approach is shown in FIG. 222C), which we call the “chip package” approach because the chip interconnect is part of the package. This method is similar to the method of FIG. 222B) for chip 1. However, in this method, back-end processing is performed on a wafer part that also serves as a package, or back-end processing that generates routing is performed on one wafer, and the package is generated on another wafer. Both are either processed according to the description herein so that they can be hybridized to each other to form the “chip 2” of the present technique. After this, chip 1 and chip 2 of the present technique can be processed and hybridized as described herein. As an option and as an alternative, all or part of the processing required to hybridize “Chip 1” to “Chip 2” and part of the processing required to hybridize the routing part to the package part Can be run as The present approach and the appropriate design plan have the advantage that the design of “chip 2” can be generalized to a number of different chip 1 designs, and further the possibility of saving costs etc. is obtained.

  Yet another alternative approach is shown in FIG. 222D), where the “Chip 2” generation process adds the low speed function to the package “Chip 2” without making it a part of the main “Chip 1” of this approach. Therefore, we call this the “active package” approach. Thereafter, chip 1 and chip 2 can be hybridized or connected to each other by other means suitable for the particular application. This can reduce the use of high cost areas by low speed / low cost devices. Further advantages and savings can be achieved, especially when low speed functions dominate.

  A further alternative approach is shown in FIG. 222E). This method is similar to the method of FIG. 222D). However, I / O is moved from “chip 1” technology to “chip 2” to generate what we call “active package by I / O technique”. As a result, in this approach, “chip 1” only includes the core analog and core digital functions. Again, both chips can be interconnected to each other to be hybridized or operable. Again, significant savings can be achieved with this approach because I / O is usually slow and large in area. Similarly, careful design allows the “chip 2” of the present technique to be generalized to a number of “chip 1” designs, again providing advantages over the conventional approach of FIG. 222A).

  Furthermore, another state-of-the-art method among the methods is shown in FIG. 222F). We call this approach “system on chip” or “system stack”. In this approach, only the core digital functions are in “Chip 1” with the appropriate speed / cost technology. “Chip 2” is similarly generated to have only the core analog functionality of the appropriate speed / cost technology. “Chip 3” is also created and contains only I / O functions implemented with appropriate technology. Finally, “chip 4” which is basically the same as “chip 2” in FIG. 222D) is generated. This approach allows for considerable mixing and combination, and in many cases the design of chip 1, chip 2, chip 3 and chip 4 has the advantage that it can be designed with just the attached chip in mind. is there. Furthermore, it goes without saying that this approach allows each chip to be, for example, one of a family of chips for that function, all sharing a common interface.

  Thus, any of the approaches in FIGS. 222B) -222F) is intelligent and allows designers to distribute their designs so that most, if not all, circuits use the best technology for their function. Enable active package generation. In some cases this may mean the creation of a completely new design, in other cases it may mean that existing chips are used in combination with each other, in either case the variants described herein. One or more of the embodiments are used. It should be understood in this regard that the functions represented in such examples are not intended to imply that these special aspects must be distributed as shown, but are merely illustrative. That is not. Equally possible is that, for example, a chip containing some of the analog functions and some of the digital functions can be created, as opposed to a single chip per functional group that another chip can produce, The key point is the ability to combine part of the overall design with the appropriate technology, and the functional outcome similar to what has been done in the past (for example, FIG. 222A) by our method, or In the conventional method of FIG. 222A), due to an inherent limitation, a result is obtained for what was not possible before or was extremely expensive.

  As a result, low performance circuits can be designed on one chip and high performance chips can be designed for higher performance technologies. In addition, this type of approach is cost effective by moving low speed circuits “off-chip”, saving significant amounts of high speed technology without the need for powerful signal drive circuits to do so. Can be increased. Some examples of the myriad possibilities are shown in FIG. 223, along with a high level representation of the process described herein.

  Here, some further explanations will be given in detail for some of the aspects of the above description. Currently, to produce an electronic chip, a wafer must undergo two sets of processes: front-end processing and back-end processing. In the front-end process, an actual device is created that includes transistors and resistors. In the case of silicon chips, for example, silicon dioxide growth, patterning and dopant implantation or diffusion to obtain desired electrical properties, gate dielectric growth or deposition, and insulating material to insulate adjacent devices. Includes growth or deposition.

  In the back-end process, various devices generated during the front-end process are interconnected to form a desired electrical circuit. This includes, for example, depositing a layer of metal wiring and insulating material that forms the interconnect, and etching it into the desired pattern. Typically, the metal layer is composed of aluminum or copper. The insulating material is usually silicon dioxide, silicate glass, or other low dielectric constant material. The metal layers are interconnected by etching vias in the insulating material and depositing tungsten therein.

  Currently, it takes about 20 days to complete the front-end and back-end processes using a 90 nm process on a 12 inch wafer, both processes being performed in series. As a result, it may take over 40 days from start to finish to produce a single wafer.

  Using the process described herein, that time is on most current submicron design rule based chip production technologies (eg, 0.5 μm, 0.18 μm, 0.13 μm, 90 nm, 65 nm, 45 nm, etc.). On the other hand, it can be shortened to about half. This is because the above-described method can perform front-end and back-end processing simultaneously in parallel and with different unrelated foundries. This is done by performing front-end processing on a single wafer (front-end wafer or “FE wafer”) in a conventional manner, in parallel, and back-end processing on another wafer (back-end wafer or “BE wafer”). ]) By the conventional method, as if the two wafers are the same wafer. In this way, routing can be performed with less expensive foundries compared to transistors or other device supporting parts, each of which can be generated in about 20 days. Then, using a variation of the via process described herein, the connection points can be placed thereon by thinning the wafer and generating the connection points on the back of the FE wafer. . In a similar manner, the processes described herein can be used on BE wafers to generate a set of complementary connection points corresponding to these on the FE wafer. Then, for example: if the malleable and rigid corresponding connections are formed (typically the FE wafer is the daughter wafer of the above process (ie carrying the malleable contacts)) Tack-fusion process; remote deposition technique as described herein; covalent or other wafer surface bonding techniques (the technique alone, with through-via technique and / or locking the two together to maintain alignment The two can be joined together using a simple filled via that helps to); or any combination thereof / alternatives thereof.

  Through this approach, the metal layer has the advantage of not having to limit the thickness or density that would be required by the topology and stress limitations imposed by increasingly sensitive transistors. In addition, by separating the process into two chips, the wiring can be thickened and the layers can be increased, potentially reducing in-chip connectivity and reducing parasitic resistance to speed chip communication. Can do.

  Our approach is independent of the specific manufacturing method or interconnect technology used to generate a specific FE wafer or BE wafer, or the design rules applied to its manufacture, and thus the process described herein is It has the advantage that it can be used to compile different technologies at the nano level. In other words, the technique described in this specification is based on what chip design rule is applied to a specific material (Si wafer, GaAs wafer, SiGe wafer, Ge wafer, InP wafer, InAs wafer, InSb wafer, GaN wafer, GaP wafer). , GaSb wafers, MgO wafers, CdTe wafers, CdS wafers, etc.) regardless of whether the devices or their interconnections are suitable to ensure that they do not overlap or interact with each other in an unfavorable manner Forming submicron or subnanometer features using high resolution masked or non-masked techniques, or defining distances between devices, between interconnects, or between the interconnect's own geometries; Is irrelevant. Thus, due to the advantages described herein, chip manufacturing techniques can be applied to current technologies such as CMOS and silicon to SiGe, silicon on insulator (SOI), carbon nanotube type interconnects, biochips, molecular electronics or higher. Shifts can be made from other approaches designed to have reduced performance and / or power requirements.

  FIGS. 224-231 illustrate the method in a simplified overview. As shown in FIG. 224a), an FE wafer 22402 having a front-end process that forms transistors and other completed devices is protected with photoresist or other removable protective material 22502 that provides support. A front side device (FIG. 225a)). Then, if necessary, the FE wafer is thinned to a thickness of several μm or more based on the height required or desired for the combined FE / BE chip (ie, part or all of the underlying substrate is removed). (FIG. 226a)). Vias are then removed from the back of the FE wafer, for example using a backside process as described herein, or using a frontside via process as described herein that is only performed from the backside. Inward, generate to the appropriate device connection location point (FIG. 227a)). Optionally, further expand slightly on the device side and use, for example, one or more through vias 22702 with malleable contacts on the back side using, for example, a well or reverse well approach or one side press-fit connection, Generate around each die. Such vias can help to “lock” the FE and BE wafer chips to each other laterally, for example when using covalent bonding or wafer surface bonding techniques between wafers. In addition, it is compatible with via-chip interconnection in via forms that are part of a heat-pipe arrangement or a non-electrical communication arrangement (both described in detail below). Can be added. The via is then made conductive (FIG. 228), at which point the FE wafer is ready to be bonded to the BE wafer.

  At the same time, a BE wafer is generated and its metallized layer 22404 is formed (FIG. 224b)). If it is made, no protection / support is necessary as the semiconductor material serves its purpose. However, if it is too thin, it may be necessary to form a removable support layer. The front surface of the BE wafer is then thinned (FIG. 226b)) and further vias are created (FIG. 227b)), as needed or desired, over the entire hole, or just a specific inner metal layer ( Metallization (FIG. 228b)) is performed up to FIGS. 227b)) and 228b)). Further, depending on the particular implementation, it can be connected to the inner layer by physical connection or non-physical (ie, capacitance) coupling. Otherwise, complementary connections are made, eg, post or well, reverse well complementary connections or other connections if a post-penetration / tack-fusion approach is to be used. Similarly, complementary locking vias 22704 (FIG. 227b)) can optionally be added to the BE wafer, or vias that are part of a heat pipe organization or a non-electrical communication organization can be added. In addition, using heat pipe knitting, especially when using malleable / rigid and tack / fusion techniques, due to the strength and tightness of the seals that can be formed, using BE wafer metallization (FIG. 228b)) It is desirable to seal one end of the heat pipe.

  The FE wafer and BE wafer are then aligned with each other (FIG. 229), thereby joining them (FIG. 230) and joining (FIG. 231) to form a complete wafer unit consisting of individual electronic chips.

  233-235 show a further variation of the previous approach. Similar to the approach of FIGS. 224-231, an alternative variant embodiment is another constructed of doped semiconductor devices 23202 (ie, transistors, lasers, photodetectors, capacitors, diodes, etc.) on the substrate 23204. FE wafer (FIG. 232A)), and a BE wafer (FIG. 232B) containing a metallized interconnect device interconnect layer. However, unlike the method of FIGS. 224 to 231, the BE wafer is turned over and aligned and bonded to the upper surface of the FE wafer, which is performed before the substrate is thinned (FIG. 233A). Alternatively, the same approach as in FIG. 232A) can be performed as in FIG. 233B) showing the BE wafer deposited after thinning.

  FIG. 234 shows yet another alternative approach. In this case, the BE wafer is thinned to expose the innermost layer of the original chip of FIG. 232B) and that layer is deposited on the top surface of the FE wafer.

  FIG. 235 shows a further enhanced alternative variation. As a result of the technique of FIG. 231, FIG. 232B), FIG. 233B), or FIG. 234, the metal on the opposite side of the BE wafer is exposed after deposition. As a result, another chip can be attached to the metal, and another type of chip stacking technique can be created.

  It should be noted at this point that a further advantage of these approaches is that if necessary, any further rerouting of connections can be made on the FE wafer or BE wafer (or both if possible). It can be done. As a result, FE and BE wafers can be generated more generally and provide a suitable connection location for a particular application. Further, at this point, the combined FE / BE wafer or FE / BE / (FE wafer or chip) stack can be treated like any other wafer produced entirely using conventional processes, Thus, for purposes of the subject matter described herein, it can be a mother or daughter wafer for other wafers.

  Furthermore, by using chip-to-chip optical connections, chip units can be designed with much faster inter-chip communication than is available with wire connections that have crosstalk problems that cause interference. For example, by installing a semiconductor laser on one chip in the stack and installing a corresponding photodetector on the other chip in the combined stack, optical connection can be made between the two instead of wiring . If both are close enough to each other, even the possibility of optical crosstalk is minimized. This aspect is shown in a simplified manner in FIG. 236 showing a part of a chip unit 23600 having two chips 23602 and 23604. One chip 23602 has a laser 23606 on it, and the other chip 23604 has a photodetector 23608 on it, so that both the chips receive the optical signal emitted by the laser 23606. Is organized. Furthermore, the techniques described herein facilitate optical communication between chips even if one or more chips are interposed. For example, as shown in FIG. 237, even if two other chips 23702 and 23704 are interposed between the two chips, a modified form of the heat pipe configuration is generated, and the photodetector is mounted from the chip 23602 to which the laser is mounted. Light up to the chip 23604 to be mounted can be obtained. To do so, a through-chip approach is used, but the inside of the via is not filled with a conductor, leaving no opening for use as a heat pipe, and a light transmissive medium such as a photoepoxy or other light transmission material At 23706, a void is filled to form an optical waveguide. In that optical waveguide, the metal and / or insulator acts to confine the light so that the via operates like an optical fiber. Furthermore, by adjusting the via dimensions and the configuration of the outer metal or insulator, the optical waveguide can have essentially the same characteristics as a single mode or multimode optical fiber. Further, in variants having a “central island” of silicon, if the central island is oxidized by heat and is not removed, the oxidation will cause the central island to become silicon dioxide, which will replace the “core” of the optical fiber. Thereafter, laser light can be transmitted through the transmission chip 23706 “through” the intervening chip by placing the laser at one end of the waveguide and the photodetector at the other end of the waveguide.

  Detailed contact and material alternatives

  Needless to say, the contact itself has a rather complex aspect due to the nature of the tack-fusion process, as shown again in simplified form in FIG. As a result, it is important to note some alternative materials that can be used for contact components for both daughter wafer 23802 and mother wafer 23804.

  In general, for any application, the daughter wafer contact 23802 of FIG. 238 has the functional layers shown in FIG. Similarly, the mother wafer contact 23804 of FIG. 238 has the functional layer shown in FIG. It is noteworthy that at both contacts 23802, 23804, each functional layer can be made of one or more material layers, or a single material layer can fulfill the role of multiple functional layers. This is best illustrated by some specific daughter wafer contact embodiments as shown in FIG. 241, and some specific mother wafer contact embodiments as shown in FIG. It is clear from these figures that any particular layer is made from a discrete material, alloy or superlattice material.

  Referring back to FIG. 239, for the electroless variant, the daughter contact 23802 can have the following configuration:

  Barrier layer: Ti / W + Pd

  Standoff layer: None

  Diffusion / extensibility layer: gold / tin (80/20) (1-12 μm)

  Cap / Adhesion: Gold (> 500 mm; typical value 1500-10000 mm)

  Oxidation barrier: Cap / adhesion layer also serves this layer. Note: The malleable layer may comprise any combination of standoff, diffusion, cap and barrier layers, but here the malleable layer is a combination of diffusion and cap layers.

  Similarly, for the mother contact (see FIG. 240), the mother contact 23304 can have the following configuration:

  Barrier layer: Not used for Cu / Al pads

  Rigidity: Copper (> 2μm)

  Diffusion barrier layer: Nickel (5000 mm; typical value 0.5-3 μm)

  Cap / Diffusion: Gold (> 500cm; typical value 1500-10000cm)

  With respect to the above, the following alternative materials that can be used in a particular contact layer further add, if not all.

  Barrier (mother or daughter) / Diffusion barrier (mother): This is, for example, Ni, Cr, Ti / Pt, Ti / Pd / Pt, Ti / Pt / Au, Ti / Pd, Ti / Pd / Au, Ti / It can be Pd / Pt / Au, TiW, Ta, TaN, Ti, TaW, W, or none if the IC pad is made from the same material as the standoff layer. Standoff layer (daughter) / rigid layer (mother): Ni (especially when the barrier is Ni), Cu (especially when the pad is Cu), Al, Au, W, Pt, Pd, Co, or Cr. In the case of sputtering rather than plating, any type of metal having a melting point higher than the melting point of the malleable (diffusion) material (typically> 50 ° C.). It can also be made of any barrier material.

  Malleable (diffusion) materials: Metals that melt at low temperatures such as That is, tin, indium, lead, bismuth, aluminum, zinc, magnesium or other metal material having a melting point of less than 1000 ° C. or an alloy in which two or more of these are combined with each other, or one or more of these. An alloy combined with a higher melting material such as gold, silver, copper, titanium, or other similar metals. Examples of combinations include: Au / Sn, Cu / Sn, Cu / Zn, Bi / Ag and the like. Note: An important aspect to this choice is that it is undesirable for the selected material to actually melt during the deposition process, because that would make the process too slow, add cost, and contact This is because it may cause a problem of short-circuiting and thus creeping or flowing out, which restricts density. It is the malleability / rigidity combination that ultimately gives the contact strength. Typically, alloys comprising a composite of one or more of Au, Ag, Bi, Cd, Cu, Fe, In, Pb, Sn, Sb or Zn are suitable choices. The main condition is that the melting point is below the melting point of the rigid post and, if any, the standoff layer. Typically, the melting point of the malleable material should be at least 50 ° C. below the melting point of the rigid material, but we used a difference in melting point of 100 ° C. to 500 ° C. The advantage is that the malleable material can be composed of several materials that provide the appropriate height necessary to overcome contact non-planarity. Indeed, malleable material can be made on the top surface of a rigid material standoff post. For example, in some cases, the malleable material can be composed of Au / Sn with a height of 5 μm. Alternatively, the post may be composed of a stack of rigid material, such as 4 μm nickel, covered with a thin layer of malleable material, for example 1-1.5 μm.

  Malleable cover materials (caps / adhesive layers): These can be materials that wet under temperature, such as low temperature metals (or alloys) such as tin, indium, lead or zinc. It should be noted that this cover material layer is generally much thinner than the malleable material layer. For example, it is usually about 10 to 20 times thinner. For example, if the malleable (and any standoff) material is 5 μm high, the malleable cover material can be 0.5 μm, typically within the range of 0.1-1 μm. (Or about 50 to 5 times thinner than the malleable layer). A good example of such a cover is tin (Sn). Such a cover material has a low melting point and changes to a liquid phase at the tack temperature. However, the layers are very thin and there is not enough liquid to short circuit, so there is no short circuit between adjacent contacts. At the same time, the tack phase becomes a liquid process, which helps in a quick attachment process to the rigid cap. In general, the cover should be selected to be compatible with the malleable material so that the combination obtained after fusing is suitable for strong bonding. In the tin embodiment, such an approach would typically use Au / Sn contacts with Sn caps.

  Malleable cover material (oxidation barrier) / rigid cover material (diffusion cap): when using an adhesive layer for the "tack" process, very thin oxidation in the case of materials such as tin or zinc that are susceptible to oxidation Should be covered with a barrier. Otherwise, the reaction gas or reaction solution is used to remove the oxide during the tack process, or a sufficiently high pressure is used to remove the oxide, such as occurs when using indium as a cap. There must be. The cover can also be an epoxy. Most materials function normally at a thickness 10 times thinner than the cap itself. Again, the malleable cover is a higher temperature that only becomes a low temperature alloy (or just a binder) when the malleable cover material begins to mix in contact with the rigid or malleable material. Can be a material. For example, if the two covers are two parts of a miscible epoxy or the oxidation barrier is gold and the malleable material is gold-tin, the intermixing of tin into the oxide layer during the deposition process The material should have a lower melting point. In general, this layer can be any metal / material that does not readily oxidize (eg, Au, Pt, etc.).

  FIGS. 243A-243C show examples of different layers and actual contacts (mother and daughter) formed using the above-described variations in the tack-fusion process showing how they interact or do not. ).

  FIG. 243A shows a pair of contacts connecting the mother wafer and the daughter wafer immediately after completion of the tack phase of the tack-fusion process. As can be seen, there is a good connection between the two, but it is not permanent, as evidenced by the large area of unconnected material.

  FIG. 243B is a similar connection pair immediately after completion of the fusion phase. Here we show that the permanent connection is obvious and is worth using the barrier. Note that in both FIGS. 237A and 237B, malleable material is mostly trapped between the barriers.

  FIG. 243C is a photograph of a pair of contacts joined in a similar manner, again just after the fusion phase. In this photo, the components are not clear, but the IC pads of the mother and daughter wafers are clear, which provides a feeling of the relative size relationship between them.

  Connection-related tooling

  We have described many different approaches to chip-on-chip, die and wafer-based interconnects, and various details that make it possible to take advantage of many permutations, variations and combinations thereof, but have been devised so far It would also be useful to describe and describe the particular various types of tooling that would be beneficial to use to support the coupling process. It should be noted that none of these tooling techniques are essential to achieve any permutation, deformation or combination, but rather have been developed to facilitate the process, Chip-related operations such as “place”, particularly when it is desirable to perform multiple chips simultaneously, and more advantageous is that they can be used in situations where the heights of these chips vary from one another.

  By way of example only, various tooling variants will be described in connection with their use in the tack-fusion process. This is because an understanding of the approach obviates the need to account for simpler uses, since they are a subset of or insignificant variations.

  As described herein, the attachment process is divided into two parts: in the first part the chips are lightly attached to each other (the “tack” stage) and in the second part the “fusion” stage provides the bond strength. To do. The tack process heats the contacts and leaves them adjacent with light pressure, causing the materials on the two corresponding contacts to interdiffuse with each other.

  In this process, if the force of gravity alone is not sufficient to provide the required pressure, a small amount of pressure is applied to ensure that the tip does not move during the process, so that the mechanical Reduce the possibility of impact or non-uniformity. Either of these results in inadequate adhesion between the contacts and cannot withstand handling of the wafer. In addition, the pressure may cause some localized heating to force the malleable material partially or completely into the liquid phase (or only to become more malleable than ideal without being in the liquid phase) and to push the piece. When counteracting pressure and surface tension or other forces that are not applied, or when excessive flexibility of the malleable material occurs, the pressure ensures that the individual parts and the whole part move excessively laterally. Can help to prevent. Thus, the application of a slight pressure can more reliably expand the degree of freedom of temperature and handling conditions for the fusion process and allow for production tolerances and variations.

  However, one of the problems of applying pressure to these chips is that if the base element, for example a wafer, has a large number of chips attached to it, the individual chips may not be coplanar and the height May be significantly different. Thus, if a flat surface or plate should have simply been placed on the top surface of the chip, the applied pressure should be uneven.

  As will be shown below, the present technique, devised to solve the above, uses pressures that are equal to all chips, using a knitting between a drive source and chips that adapt to or account for different heights. Is to apply.

  One way to accomplish this is to use a series of pins or posts that coincide with individual chips in a one-to-one reference organization. For example, with the understanding that other variations can be devised by combining aspects from each or other tooling techniques as described below, two different ones of this technique. A modification will be described.

  Examples of tooling for implementing the pin or post type approach are shown in FIGS.

  As shown in FIGS. 244 and 245, the approach uses a set of pins or posts 24402 inside a frame 24404. Individual pins or posts are movable at least along their longitudinal axis (in some implementations, slight pivoting can be tolerated if flatness or tilt may be an issue). The post or pin can be restrained and released. Each post or pin has a surface that is configured to contact a single tip.

  Depending on the particular implementation, the face of any particular pin or post can be: a flat surface, a die with the inverted shape of a chip to which pressure is applied, or some other shape suitable for a particular application be able to. Further, the pin or post itself at and near the face (and along part or all of its length) may have a circular cross-section or some other shape, non-circular (ie, oval, square, hexagonal, It has a closed shape such as an octagon. Further, the perimeter and plane of the surface may be larger or smaller than the perimeter or area of the particular chip to be contacted (i.e. it may extend beyond the perimeter of the chip, or completely or partially within it) And, importantly, that surface is configured to apply force to the chip without damaging the chip, in particular without cracking or chipping).

  In use, the posts in the frame (possibly the frame itself) are lowered without lowering each post until it is in proper contact with the respective chip (FIG. 245). Once this is done, the pin is restrained at that position. As a result, an appropriate level of force can be applied to the frame or pin or post, depending on the implementation. When the tool is lowered, only a longitudinal force is applied on the chip, so that the force is evenly transmitted to each chip via pins or posts.

  Thereafter, the bonding process continues as described herein or in some other manner.

  FIGS. 246 and 247 show an alternative pin or post type approach similar to the approach of FIGS. 244 and 245. FIG. However, instead of a single pin or post per chip, a group of small diameter pins or posts that contact individual chips is used. As a result, the approach can account for single chip non-planarity or height variations using individual pins or posts in the group. Furthermore, depending on the particular implementation, if at least some of the pins are configured to cross the perimeter boundary of the chip, by extending them to extend below the top surface of the chip, Can be used to restrain movement. In other respects, the approach is the same as for a pin / post on a chip-by-chip basis (ie, an unconstrained group of pins / posts so that force can be applied through the frame, group or pins). The surface 246060 is brought into contact with each chip and restrained). Furthermore, the individual pins / posts in the group can have a circular or non-circular cross section near their respective faces. Further, as will become apparent below, by selecting a suitable shape for the pins, the pin / post spacing in the group can be created or eliminated to achieve certain advantages.

  Note that individual pins / posts or groups (in the case of multiple pins / posts per chip) must be wide enough so that any pressure they transmit to the chip does not cause the chip to crack. Yes, during the process, the edges and corners of the chips should be placed so that they do not hit.

  In either case, by using a frame that holds the post or pin, once constrained, the post or pin can only move meaningfully in the vertical direction, so its structure follows the topography of the chip attached to the wafer. It is only possible to apply longitudinal pressure to the surface.

  The advantage is that, as noted herein, when using the tack-fusion approach, the force required for the “tack” step is typically no more than about 1 g per contact, Typically less than 0.001 g per contact. As a result, pins or posts can be easily restrained within the frame, for example simply by clamping or other locking techniques, and this particular technique is only a matter of design choice and understands tooling and its usage Is not important.

  As an advantage, depending on the implementation, any of the above tooling can be further enhanced by providing a vacuum to the chip. In the case of per chip pins / posts, this can be accomplished by providing passages 24412, 24414 through openings in the post and post face 24406. Alternatively, the pin / post group approach can accommodate a passage where the pin / post itself draws a vacuum. Alternatively, by selecting the appropriate shape and spacing for the pins / posts, a passage between adjacent pins can be formed (within the tip boundary) or removed (near the tip periphery) through these gap passages. A vacuum can be drawn.

  In any tooling case, such variations can provide a vacuum to the chip, for example, allowing the tooling itself to be used in a pick-and-place operation, or if the vacuum is, for example, during a tack or fusion process. It is possible to further inhibit the movement of the chip in the non-vertical direction (undesired direction).

  Further alternative methods can be applied to the pin or post surfaces 24406, 24606 with materials selected such that they are first bonded to the chip and can be "peeled off" from the chip when the operation is complete. For example, if the liquid liquefies or melts or evaporates near the tack or fusion temperature, but does not damage the chip and remains on the chip or the element to which the chip is attached, A material can be used on the surface that can be removed through some undamaged process or can be ignored as having no harmful effects.

  Although the post / pin solution provides only vertical movement, some implementations of that approach do not actually hold the chips in place, and in some cases evenly across each chip. There can be no guarantee that force will be applied, or that the tip will not tilt, for example during a tack or fusion process. Thus, in some cases, chip movement or non-uniform fusion can occur across individual chips or between chips having varying heights.

  As shown in FIGS. 248 and 249, in such a case, a sponge-like, flexible, conformable or deformable material 24802 knitted between the rigid plate 24804 and the daughter tip 24906. Alternative tooling techniques including can be used. The material shown in FIG. 249 adapts or adjusts itself to various component heights while maintaining pressure on the chip and preventing local pressure that causes scratches, chips or damage to the chip. . This approach uses a sponge-like or deformable material with a thickness appropriate for the particular application (typically 0.01 to 0.125 inches). Examples of such materials include, but are not limited to, for example, Kalrez® 7075, Kapton®, or Teflon® (both commercially available from Dupont). High temperature polymer such as, a high temperature silicone rubber thermal pad commercially available from Bergquist, Inc. of Chanhassen, Minnesota, a ceramic fiber reinforced alumina composite material such as Zircar RS-100 (commercially available from Zircar Reflexibility Composites, Inc., NY10921, Florida). Catalog No. commercially available through McMaster-Carr Supply Company. Ceramic tapes such as 390-2xM, 390-4xM and 390-8xM (where x is 1, 2 or 3 indicating the width), for example, an aluminum oxide based ceramic tape, McMaster-Carr is commercially available as part number 87575K89 Such as a ceramic fiber strip, glass fiber paper sold by McMaster-Carr as part number 9323K21, or any other material.

  Furthermore, depending on the particular material used between the plate and the chip, the material can be reused for multiple cycles of pressure application and bonding, but it can also be a one-time use material.

  Also, as shown in FIG. 249, similar to the pin / post deformation configuration, pressure is applied to lower the plate onto the chip, so that the deformable material fits the chip and surrounds the chip for lateral movement. to bound. The bonding process then proceeds as in pin / post tooling.

  Alternatively, if it is less desired to apply force to the pin / post through the frame for a particular application, there is the advantage that this knitting can be used in conjunction with a pin / post type tooling. In such a knitting, pin-type tooling is applied as described above. However, if all the pins / posts are the same height, the end of the pin / post reflects the same height difference as the tip when contacting the tip. On the other hand, by using a plate-material knitting on the pin / post end opposite the tip, it is possible to adapt to the height difference and to apply the appropriate force easily and uniformly. Furthermore, through this approach, certain materials that may not be as heat resistant as materials that must be in direct contact with the chip may be physically separated from the chip.

  Another alternative approach similar to the plate variation of FIGS. 248 and 249 that keeps the chip in contact with the mating elements is shown in FIGS. 250-254. This approach includes a tooling made of a body 25000 formed by covering a relatively thin but rigid material 25002 with another curable material 25004, which can be a liquid phase or gel (eg, epoxy). And later cured.

  The body 25000 is then placed on an array of chips 24906 (FIG. 251) so that the curable material 25004 is bonded to each other while maintaining the level position. The curable material is then cured so that the entire body is rigid. (Alternatively, the rigid portion of the fusion body may be a flexible conformable material, provided that the subsequent curable material remains sufficiently thick and cured to cure the entire body (ie, the body and the curable material). Material) behave like a rigid body).

  Once cured, the tip can be moved to the element to which it is attached and, if necessary, a load can be applied to the body with a separate removable weight (if required) (see figure). 252). In addition, since the curable material is applied to each chip and allowed to cure, the attached chips can be in any direction (horizontal, vertical, or inclined) (pitch) with the exception of those that are due to the movement of the entire body itself. Neither) nor yaw) can move. As a result, the tip is maintained in a similar orientation when the entire body is maintained in the level position during the deposition process.

  Optionally, underfill 25302 material can flow between the body and the element to which the chip is attached (FIG. 253). This underfill 25302 can be used to fill any gap between the chip and the element to which it is attached. Further, since the area between the chip and the body is enclosed, the underfill 25302 can be flowed in a controllable manner (ie, so that it does not flow into undesirable locations).

  Any suitable process that does not damage the chip once bonded and unloaded, such as when using weights or underfilling, such as chemical processes, wafer lapping or polishing, or chemical machinery The entire body (or most of it) can be removed by a mechanical process (CMP) (FIG. 254). By removing the body, the entire chip assembly is available for depositing a new chip layer, as if it were the underlying element.

  Similarly, this “body” approach can be used in conjunction with pin / post tooling to allow for the application of forces that are not directly applied to the frame, taking into account differences in pin / post height. In that case, the pin / post is brought into contact with the tip, and then the body is brought into contact with one end of the pin / post opposite the tip and cured. Thereafter, force is applied as described above in the desired process. Once the tip is attached, the entire pin / post-frame-body combination can be immediately removed from the tip in the same manner as a normal pin / post approach. The entire body can then be separated from the pin / post-frame tooling by any convenient process of softening or removing the curable material or simply by cutting or tearing the pin at a point outside the curable material.

  In addition, a further advantage of this particular combination approach is the assembly line approach of coupling multiple chips to one or more respective underlying elements, and the pick and place approach as noted above with respect to particular variations. When used as a part of the above, reproducibility is obtained.

  Finally, with respect to all of the above tooling and other variations, permutations or combinations thereof, it should be noted that a gas such as forming gas or formic acid or flux may be fused to the process if required for a particular use. Inside, it can flow between the frame and the chip

  It should be noted that in some cases, the pin / post approach preferably uses some flexible or sponge-like material (ie, itself may apply too much lateral pressure to the chip, causing fusion If the tip is tilted or moved during the process, or may demand extreme tolerances to the fusion process conditions (and not practical for commercial products).

  To recapitulate, the present invention has been described in the context of a particular type of chip including an optical chip (ie, one or more lasers, one or more photodetectors, or combinations thereof). However, using the technique described herein equally well, the “through” of any kind of doped semiconductor chip with transistors or other electronic circuit components in addition to or instead of optical components. A “chip” electrical connection can be created.

  Similarly, although certain materials have been identified as being suitable for use as “post-penetration” contact materials, these materials should not be taken literally as being the only materials that can be used. What is important is the relative hardness between the two so that diffusion occurs between them and a connection is formed, not the specific material used. The specific pair of materials is determined in part by factors such as availability, cost, compatibility with other components used, or other production-related processes unrelated to what is described herein. As such, it is useless to describe some or more of several possible non-limiting material pairs. Similarly, there are several light transmissive materials beyond the photoepoxy. However, the selection criteria for a particular material used in a particular application may be influenced or controlled by other factors unrelated to the subject matter herein. Thus, it goes without saying that any light-transmitting medium that can be inserted into a void and that transmits the laser light required for a particular application is a material that can be used appropriately without any specific description that could be any alternative. Should be considered.

  Thus, it should be understood that this description (including the figures) is merely a representation of some exemplary embodiments. For the convenience of the reader, the above description has focused on representative examples that teach the principles of the invention, among all possible embodiments. This description is not intended to be exhaustive of all possible variations. It should be noted that alternative embodiments may not be presented for specific parts of the invention, or may be used where there are alternative embodiments not described. It should not be considered a waiver of alternative embodiments. It goes without saying to those skilled in the art that many of these unexplained embodiments are incorporated into the same principles of the invention and others are equivalent.

In the double conductor variant as shown in FIG. 28B, the depth of the ring 704 and the depth of the via groove 2702 both thus certainly exceed the point where the substrate is ultimately thinned. desirable. In other words, if the total thickness of the wafer is 500 μm and the wafer substrate is thinned down to 200 μm, the depth of the via groove 2702 must be at least 300 μm plus the appropriate metallization thickness. Therefore, it is considered that the original depth of the ring 704 needs to exceed the depth of the via groove 2702 . The reason for this requirement is that electrical insulation between the two conductors is necessary. The above explanation also explains that in some implementations, the coating defects at the bottom of the trench 302 are removed anyway during the thinning process and thus have little or no effect.

As is clear from the above description, as shown in FIG. 31, the three conductors (ie, triaxial or triax) are thinned to the range shown in FIG. 28B by taking the technique obtained in FIG. 28B. The advantage is that it can also be constructed simply by doing (ie until the groove bottom metallization material is completely removed). The three conductor variants allow the outer metallization to act as a shield between the inner metallization and / or conductor and the semiconductor material mounting the nearby device, Advantageously, the metallization between the inner conductors can act as a shield between them or as a third conductor. Thus, the same three conductor variants provide several alternative advantages in themselves. Needless to say, any one item (ie coating (thermally generated or applied), void filling) in terms of the relationship between a single conductor, two conductors and three conductor variants. All options that describe usage for post-penetration contacts (described below) are generally interchangeable and applicable to all.

FIG. 33 is a schematic cross-sectional view of an alternative chip mounting portion disposed on top of electronic chip 3300 similar to that of FIG. 23 except that void 3310 remaining after metallization is not filled as in FIG. The chip 102 is hybridized to the electronic chip 3200 so that the contact pads 3302 on the electronic chip 3300 to be electrically connected to the top contact 904 of the laser 104 are directly under the void 3310. Solder bumps 3304 are on the contact pads 3302 and are used to physically and electrically couple this portion of the two chips 3302 and 3300 to each other.

Since the voids 3210, 3310 are not filled in the implementation of FIG. 32 or FIG. 33, capillarity can be used to pull the solder 3204 , 3304 into the voids 3210, 3310, or using pressure, the deformable material 3204 , 3304 can be deformed into the void, which helps a) ensure good electrical connection and b) align the chips with each other.

As shown in FIG. 36, for the implementation of FIG. 34 (the same is true for the implementation of FIG. 35, but not shown), an insulator coating or an insulating protective coating 3600 may optionally be performed. it can.

As briefly described above, regardless of the variation used, the annular groove (and around the semiconductor material if that variation is used) can be any closed shape. However, as an extension of the above, it goes without saying that the via groove need not be the same shape as the annular groove or the width of the annular groove need not be uniform, but in most implementations both are the same shape. Yes, for ease of implementation and for capacitance, resistance, or both. FIGS. 37a) to 37h) show a few examples of the cross-section of the annular groove to show the main points. In FIG. 37a), the annular groove 3702 is shown as being triangular. As a result, the width 3704 of the groove 3702 is wider than the side 3708 at the triangular vertex 3706. In FIG. 37b), the annular groove 3710 is shown as a rectangle. As a result, in the corner 3712, the width of the groove 3710 is wider than the side 3714, and the long side 3716 is farther away than the short side 3718. In FIG. 37c), the annular groove 3720 is shown as being defined by two different ellipses. As a result, the width of the ellipse of the annular groove 3720 varies depending on the position. In FIG. 37d), the annular groove 3722 is shown as a square. As a result, in the corner, the width of the groove 3722 is wider than the side, but the side is separated by a uniform distance, in FIG. 37e), the annular groove 3724 is rectangular and the outer periphery 3726 is rectangular but the inner periphery 3728. In, it shows as a circle. In FIG. 37f), the annular groove 3730 is circular at the outer periphery 3732 but shown as a rectangle at the inner periphery 3734. In FIG. 37g), the annular groove 3736 has a concave-convex shape (kidney shape), the outer periphery 3738 and the inner periphery 3740 are in a scaled relationship with each other, and the groove width is constant. In FIG. 37h), the annular groove 3742 has an outer periphery 3744 and a hexagonal inner periphery 3746 similar in shape to FIG. 37g).

FIG. 38 illustrates the process for preparing a wafer for stacking in a simplified and overall overview. FIG. 38A) shows in simplified form a portion of the initially fully formed wafer, in particular the device 3802 and its underlying substrate 3804. The whole process is as follows. First, material 3806 is deposited on the device side of the wafer (FIG. 38B)). The material 3806 and the underlying contact locations are then etched to produce grooves 3808 (FIG. 38C)). The wall 3810 of the groove 3808 is insulated 3812 to prevent the doped semiconductor material from being potential shorted with the generated contact (FIG. 38D)).

In certain cases, it is desirable to use a thicker wafer 4202 (FIG. 42A) to ensure handling strength. In situations where the wafer is particularly thick and the desired via diameter is less than about 1/20 to 1/30 of the desired thickness of the wafer, an alternative process may be used for some variations to produce a thicker wafer. Can be adapted. The process of forming such “back-to-front” vias is shown in simplified form in FIGS. 42B) -42E). First, the via 4204 is etched into the back surface of the device mounting wafer 4202 (FIG. 42B)). The via is then made conductive using one of the processes described herein (ie, single conductor, coaxial, triaxial, etc.) or by some other process such as inserting a preformed post 4206 . (FIG. 42C)). This approach can create a backside with either malleable material or rigid post material. The corresponding via 4208 on top of the conductor 4206 is then etched from the top (ie, front or device side) down to the end of the bottom of the back side conductor 4206 (FIG. 42D)). Next, optionally protect the front side device and, if desired, contact or reroute to the device, for example using the techniques described herein (not shown), for the back side. Make the via conductive in essentially the same way as it did (FIG. 42E)). In some variations, the bottom material of the backside conductor has the advantage that it serves as an etch stop and / or seed layer for plating the conductor from the front side. This can reduce the number of processing steps compared to the technique used to form the conductor on the back side. Further, in other variations, if it is desired that there be no physical connection between the conductors from the back via and the front via, an appropriate amount of wafer can be left between them. In that situation, the connection is made by capacitive coupling.

In addition, a back-to-front approach can be used, in which one side has an incompletely filled via so that a “slot” 4210 (FIG. 42F) receives the “post” of the unfilled portion of that via . )) (Ie, press fit or interference fit), thereby providing alignment and / or physical and electrical connections. This type of press-fit or interference fit is illustrated in FIG. 42F).

In another alternative variation, the via-generated back-to-front method described above can be used to create a connection that only pierces the chip halfway to allow for interchip data transmission using capacitive coupling. Capacitive coupling works the closer the contacts are, and the connection density is limited by crosstalk, so the variation of the approach described here is ideal for producing chips that use this type of communication. Is. These approaches allow the distance between the contacts to be minimized and, moreover, the use of coaxial, triaxial posts to provide a shield can immediately minimize crosstalk due to close proximity connections. Furthermore, capacitive contacts have the advantage that no actual electrical contacts between parts are required. By this method shown in FIG. 43A) ~ Figure 43D) spaced in such a way as to close enough to contact the upper surface of the chip 4302, via 4304 is etched from the rear chip 4302 (FIG. 43B)), the physical contact However, when filled, they are close enough to provide good capacitive coupling of the signal applied between the fill and the contacts. Via 4304 is then filled with metal studs, single conductor, coaxial or triaxial conductor 4306 to allow good capacitive coupling (FIG. 43C)). In this way, the overall thickness of the wafer can be maintained so that the handling strength of the wafer is sufficient and the connections are at an appropriate distance. This approach further provides the advantage that stacking can be done by stacking the back side of one wafer to the front side of another wafer. In this way, multi-stacking of chips can be performed as shown in FIG. 43D). This is in sharp contrast to the approach where the chip needs to be face-to-face rather than front-to-back. The reason is that in such an approach, the third chip is placed on the back of one of the other two chips, and then across the wafer where sparse contact density is required to avoid the possibility of crosstalk. This is because communication must be performed, so that the chips 4308 and 4310 cannot be easily stacked (that is, a stack of three or more chips). Needless to say, according to the method described in this specification, signal shielding can be strengthened and crosstalk can be prevented by using coaxial or triaxial vias.

From the above description, the versatility of our technique should become more apparent. There is the advantage that further variants can be generated that show the range of wide and versatile possibilities that can be utilized through our approach. One such variant shown in FIG. 44A) is a “pre-connect” variant, which differs from the above and many approaches. This is because the processed wafer 4401 is “pre-formed” (ie, before the annular groove is formed) “processed” as described herein (ie, before the annular groove is formed). This is because it is referred to as a “base” wafer in this specification. In this variant, any basic connection formation process can be used. This variant process proceeds as follows.

First, the initial wafer 4401 is thinned to the extent necessary to ensure that the via penetrates the substrate completely and reliably (FIG. 44A)). This step is optional and may not be performed if the particular etching process used penetrates the entire chip without problems. The initial wafer 4401 is then aligned to the base wafer 4402 (FIG. 44B)) and bonded using a covalent bond if the adhesive, wafer fusion, or wafer flatness is very good (FIG. 44C)) . Then, the annular vias 4404, generated initial wafer 4401 so as to come onto the pads of the base wafer 4402, so as to surround the pad vias is subject to the base wafer, extending to the base wafer 4402 (FIG. 44D)) . The annular via 4404 is then filled with insulator 4406 so that subsequent conductor deposition is insulated (FIG. 44E)). Next, all or a portion of the central post is etched away to the target pad of the base wafer 4402 to create a void 4408 on the base wafer pad (FIG. 44F)). Finally, void 4408 is metallized (FIG. 44G), and optionally filled completely with insulator 4410 (FIG. 44H) using one of the techniques described herein (FIG. 44H)), or the metallization is void 4408. Can be filled with an insulator 4412 (FIG. 44I)). As a result, the metal fill makes an electrical connection to the base wafer 4402 pad, effectively extending the base wafer pad up through the initial wafer 4401 and physically bonding the two chips together. By using this technique, the central post made of semiconductor material protects the base wafer pad so that the insulator does not interact with the base wafer pad. This is because if you try to do the same using conventional techniques, these conventional techniques will leave the base wafer pad exposed and therefore can be contaminated by the applied insulator, so you know what will happen. There is a significant difference from not.

It should be noted that as used herein, the term “liquid phase” is intended to mean a state in which the described metal or alloy is completely (or substantially completely) liquid. As used herein, when a metal is in a non-liquid or semi-liquid state, the metal is soft enough to adhere as described herein, but the same metal or alloy is a pure liquid or liquid. Not enough liquid to flow to flow in phase. Most variations of our process work with metals or alloys in non-liquid and non-solid states. Expressed on another method, a phase diagram of a metal or alloy, our process variant works between the solid (full solid) temperature and the liquid (perfect liquid) temperature, and most Operates near the equilibrium point between them. This difference can be further understood with reference to coupling the chip to another element, for example, as shown in FIGS. In these figures, if the material 3304 is a liquid phase solder (metal or alloy), the chip is “floated” over the molten solder and capillary action sucks the solder into the vias 3210, 3310, so 3210 and 3310 are automatically centered on the solder balls. In the non-liquid or semi-liquid phase state, as used for most variations of the tack-fusion process described herein, the metal or alloy consists both during the tack phase and during the fusion phase. The condition will not be sufficiently liquid to float the chip or auto-center the vias 3210, 3310, although the metal or alloy will be significantly softened (ie, some of the material will be in a liquid state). That is the state. Thus, some force application (either externally applied or force generated by the weight of the chip without applying external force) is required to place the metal or alloy into the vias 3210, 3310.

As shown in FIG. 49, optional contacts 4902, 4904 are added to the top and bottom of the metallization 2402 and conductor 2802 to help connect each chip to the top and bottom chips. As mentioned above, metallized or metal contacts can be used directly. Depending on the particular implementation, when adding optional contacts 4902, 4904, the contacts 4902, 4904 may be any prior art type, simple conventional contact pad, non-shaped as described herein. It can be a post-penetration contact or a post-penetration contact as described herein.

Next, a barrier layer is formed on the contacts on the daughter (FIG. 64a)). Although nickel in this case, it functions as a barrier against metal diffusing into the IC pads 5302, 5304, 5306, 5308, or as a barrier against damage to individual chips due to the penetration of metal under the chip cover glass 5310, 5312. To do. Optionally, a cap layer 6402, 6404, in this case gold, is deposited on the top surface of the barrier and is preferred during the bonding process, especially when this approach is used in a tack-fusion bonding process involving post-penetration contacts. Prevents diffusion as well. The cap is also formed on the mother wafer (see Fig.
64b) ). At this point, the rigid contact on the mother wafer is complete.

Then malleable contacts 6702, 6704 are made on the standoff (FIG. 67a)), removing the dielectric, leaving a fully formed malleable contact ( FIG. 68a) ).

FIGS. 147-152 illustrate a variation of the process for implementing the well attachment concept for contact pairs of the mother 14702 and daughter 14704 wafers (FIG. 147). In this variation, the cover glass opening of the daughter wafer is used as a template, such as polyimide, SU8, other epoxies, glass, and / or dielectric (FIG. 148a), in permanent well 14802 . It is produced. A similar method is used on the mother wafer 14702 . However, the well 14804 does not surround the entire region where the cover glass forms a boundary (FIG. 148b)). The malleable material 14902 and (optional) malleable cover material 14904 are then inserted into the well 14802 of the daughter wafer 14704 , taking care not to fill the well 14802 to its full depth (FIG. 149a)). Similarly, a rigid material 14908 is deposited from the pad surface of the mother wafer 14702 (FIG. 149b)). Then removed and the wells 14804 on the mother wafer 14702 (FIG. 150), wells 14802 on the daughter wafer is kept in that position.

As a result, the daughter wafer well 14802 constrains the bonding material (eg, cover 14904 and malleable material 14902 ) during the penetration process as well as during the tack phase (FIG. 151) and fusion phase (FIG. 152) of the bonding process. To do. It can also define a depth limit because the well has such a height that it will do something else after it hits another wafer or some surface on it (FIG. 152).

Class I (FIG. 153): In this class of well connections, daughter wafer 15302 includes malleable material 15303 and mother wafer 15304 has a rigid well 15305 (shown as etched in the semiconductor wafer). The wall surface of the well 15305 is covered only with the diffusion layer metal 15306 , for example, Au. In order to bond the two wafers 15302 and 15304 , the malleable material 15303 on the daughter wafer 15302 is inserted into the well 15305 so as to be deformed and fitted. Temperature and pressure are added during the tack phase to form a tack connection to malleable material 15303 and diffusion layer 15306 . During the fusion phase, the malleable material 15303 of the daughter wafer 15302 and the diffusion layer 15306 of the mother wafer 15304 interdiffuse to form a metal bond. Depending on the particular implementation, the malleable material may be slightly larger than the well, or at least contain more volumetric material, to strengthen the fit of the two wafers during the tack phase. Can be free of voids after the fusion phase is complete. It should be noted that this class is contrary to mother / daughter practice.

Class II (FIG. 154): This class is similar to Class I, but with wells or malleable “posts” 15403 formed into shapes for automatic or easier alignment between them. It should be noted that this class is also against mother / daughter practices.

Class III (FIG. 155): In this class, post 15406 is a “rigid” material and well 15405 is coated with malleable material 15403 to a certain thickness. This is similar to the basic profiled malleable contact technique described above. However, malleable material 15403 has a profile that is more conspicuously recessed than a recess that is only naturally obtained from the height difference between the cover glass and the IC pad. Again, it is desirable to select the dimensions of post 15406 and well 15405 so that there are no voids after accumulation (ie, completion of the tack-fusion process).

Class IV (FIG. 156): In this class, well 15605 is coated with a diffusion layer (similar to classes I and II) post 15603 is made of a rigid material, but is also a layer of malleable material on the outside. Covered. This creates the same situation as class I and II. However, when the material cost of the rigid material is lower than the cost of the malleable material, for example, when the rigid material is almost copper and most of the malleable material is gold, the cost of the daughter wafer can be reduced.

Using the techniques described above, the well can be formed, for example, using a dielectric or can be recessed (ie, fabricated into a semiconductor by etching). Further, the well can be a byproduct of the via formation process. For example, it can be part of a via that is not completely filled. FIGS. 157A and 157B are photographs of longitudinal sections of a pair of 15 μm diameter vias 15702 extending to a depth of 135 μm and 25 μm diameter vias 15704 extending to a depth of 155 μm, respectively. FIG. 158 is a photograph of a similar via 15802 that is not all filled up to the bottom formed. As a result, natural wells are formed by thinning the backside of the wafer until the bottom of the via is exposed. As is, this well can be used as a Class I well. Alternatively, class II wells can be obtained by etching the flare or taper at each mouth.

FIGS. 159-167 illustrate a further variation of the Class II type rigid well attachment technique. This deformation of the rigid hole well begins with one of the fully formed wafer and, in particular, one of its pads 15902 exposed through the cover glass 15904 (FIG. 159). Optionally, first a barrier layer 16002 is deposited on the IC pad 15902 (FIG. 160). Next, photoresist patterning exposes the region 16102 around the IC pad 15902 that also includes some of the cover glass 15904 (FIG. 161). The well is automatically formed by a metal 16202 deposition process in a recess formed by a cover glass on the IC (FIG. 162). This makes it easier to pattern than some of the other rigid well hole processes. Photoresist 16204 stripping removes excess and unwanted metal remaining behind the fully formed rigid well 16302 (FIG. 163).

As shown in FIGS. 168-170, this process uses separate contacts to connect the devices during the initial deposition phase (pre-tack phase). FIGS. 171A and 171B show top views of alternative spaced contact variants similar to FIGS. 168-170. These separate contacts can be completely separated from the electrical contacts, for example, around or around the individual chip (FIG. 171A), or can be interspersed between the actual electrical contacts 16806. (FIGS. 168 and 171B). In addition, the remote contacts as described herein are compatible with all variants of the main contacts and do not need to be narrow pitch, so they can be much larger in height and width than the main electrical contacts. There are advantages. Preferably, the main contact should be high enough so that it does not need to be contacted during the deposition process (FIG. 169). It should be noted that this attachment or adhesion process need not be high strength. It is the subsequent fusion process of the main contacts that can provide strength to the bonded chip. FIG. 170 shows the wafer of FIG. 169 following the fusion process so that the main contacts are permanently combined with each other with a high strength bond.

The first group of variations involves complex contact shapes (ie, contact shapes other than the conventional single square or single dot). One such embodiment involves the generation of shielded contacts, the simplest being the two coax or three coax (square 17202 (FIG. 172A)) or circular 17204 (FIG. 172B)) cross-section (coax) or three coax ( triax) Similar to through-chip connections and in more complex cases, irregular open or closed geometry 17206 (FIG. 172C )).

In the case of two or three coaxial contacts, the inner contact is connected to transmit a signal, while the outer closed ring acts as or is connected to the ground plane. When used with coaxial via 17302 (FIG. 173), this ensures that the contacts are shielded throughout the path to another chip. Additionally or alternatively, the coaxial contacts 17402 can be used independently of the vias themselves (FIG. 174) to ensure that each contact itself is shielded. Thereby, the distance of a chip indirect point can be made closer than the case where a coaxial method is not utilized. In addition, the outer contact rings of each contact are connected to each other and / or connected to an electrically isolated metal on the wafer to form a ground plane and / or a chip-to-chip shield 17502 (FIG. 175). .

FIGS. 224-231 illustrate the method in a simplified overview. As shown in FIG. 224a), an FE wafer 22402 having a front-end process that forms transistors and other completed devices is protected with photoresist or other removable protective material 22502 that provides support. A front side device ( FIG. 225 ). Then, if necessary, the FE wafer is thinned to a thickness of several μm or more based on the height required or desired for the combined FE / BE chip (ie, part or all of the underlying substrate is removed). (FIG. 226a)). Vias are then removed from the back of the FE wafer, for example using a backside process as described herein, or using a frontside via process as described herein that is only performed from the backside. Inward, generate to the appropriate device connection location point (FIG. 227a)). Optionally, further expand slightly on the device side and use, for example, one or more through vias 22702 with malleable contacts on the back side using, for example, a well or reverse well approach or one side press-fit connection, Generate around each die. Such vias can help to “lock” the FE and BE wafer chips to each other laterally, for example when using covalent bonding or wafer surface bonding techniques between wafers. In addition, it is compatible with via-chip interconnection in via forms that are part of a heat-pipe arrangement or a non-electrical communication arrangement (both described in detail below). Can be added. The via is then made conductive (FIG. 228), at which point the FE wafer is ready to be bonded to the BE wafer.

Similarly, for the mother contact (see FIG. 240), the mother contact 23804 can have the following configuration:

FIG. 243B is a similar connection pair immediately after completion of the fusion phase. Here we show that the permanent connection is obvious and is worth using the barrier. Note that in both Figures 243A and 243B , malleable material is mostly trapped between the barriers.

Claims (31)

A method of electrically coupling a first contact on a first wafer to a second contact on a second wafer, wherein the first contact includes a rigid material and the second contact is malleable as compared to the rigid material. When a material is included and both are brought into contact, the rigid material is bonded so as to enter the malleable material, the rigid material and the malleable material are both electrically conductive, and the method includes:
Contacting the rigid material with the malleable material;
Applying a force to one of the first contact and the second contact to cause the rigid material to enter the malleable material;
Heating the rigid material and the malleable material to soften the malleable material;
And constraining the malleable material within a pre-specified region.   The method of claim 1, further comprising: forming a well on the second wafer that forms a boundary of the malleable material and that performs the constraining step.   The method of claim 2, wherein the forming step further comprises the step of applying a boundary defining material only to a particular area of the second wafer.   The method of claim 2, wherein the forming step further comprises creating a recess in a substrate of the second wafer.   The forming step further includes the step of applying the malleable material on an IC pad of the second wafer, the IC pad being disposed in the vicinity of the IC pad and the cover glass of the second wafer and the first wafer. 2 wherein the malleable material is recessed with respect to at least one of the dielectrics on the wafer, a portion of which is placed on the top surface of the IC pad and a portion of the top surface of the cover glass and / or dielectric. So that the outer surface portion of the malleable material on the IC pad has a different height than another portion of the malleable material disposed on the cover glass and / or the dielectric. The method of claim 2, wherein   The method of claim 1, further comprising forming a well on the first wafer by profiling the rigid contact. A connection formed between complementary contacts on two chips:
A first electrical contact on a first of the two chips;
A second electrical contact on a second of the two chips;
A bonding metal that physically and electrically couples the first and second electrical contacts;
A material that forms a boundary around the bonding metal and prevents the bonding metal from bulging or creeping laterally from the contact;
Connection with.   The connection of claim 7, wherein a portion of the second electrical connection includes the material that defines a perimeter boundary of the bonding metal.   The connection of claim 7, wherein a portion of the first electrical connection is surrounded by a portion of the second electrical connection. The connection of claim 7, wherein the material defining the perimeter of the bonding metal comprises one of a dielectric, a photoresist, and an epoxy. The first electrical connection is:
11. The connection of claim 10, further comprising a barrier layer that is physically isolated but electrically connects the first electrical connection to an IC pad on the first chip.   The barrier layer is made of Ni, Cr, TiPt, Ti / Pd / Pt, TiPt / Au, Ti / Pd, Ti / Pd / Au, Ti / Pd / Pt / Au, TiW, Ta, TaN, TaW and W. The connection of claim 11, comprising one of: The second electrical connection is:
11. The connection of claim 10, further comprising a barrier layer that is physically isolated but electrically connects the first electrical connection to an IC pad on the first chip.   The barrier layer is made of Ni, Cr, TiPt, Ti / Pd / Pt, TiPt / Au, Ti / Pd, Ti / Pd / Au, Ti / Pd / Pt / Au, TiW, Ta, TaN, TaW and W. 14. The connection of claim 13, comprising one of:   The material defining the perimeter of the bonding metal includes one of a dielectric, a photoresist, and an epoxy, and has a height that makes physical contact with each of the two chips. 7 connections.   The material defining the perimeter of the bonding metal is high enough to prevent one of the first and second electrical contacts from penetrating to the other of the first or second electrical contacts. 8. The connection of claim 7, wherein A system for connecting a first chip to a second chip comprising:
A post on the first chip comprising a first metallic material;
A recessed wall extending from an outer surface of the second chip to a location in the second chip and defining a well in the second chip;
A conductive diffusion layer material on the surface of the recessed wall in the well;
A conductive malleable material on the post;
The post is dimensioned to be insertable into the well such that the conductive malleable material deforms within the well, and the post is heated to at least a tack temperature relative to the conductive malleable material. Forming a conductive tack connection with the diffusion layer to create a conductive path between one chip and the second chip;   The system of claim 17, wherein the recessed wall has a shape of the outer surface dimensioned to assist in aligning the post with the well during an insertion operation.   The system of claim 18, wherein the recessed wall comprises a portion of a partially filled via.   The system of claim 17, wherein the recessed wall comprises a portion of a partially filled via.   19. The system of claim 18, wherein the post, the diffusion layer material, and the conductive malleable material fill the recessed well.   18. The system of claim 17, wherein the post, the diffusion layer material, and the conductive malleable material fill the recessed well. A pair of chips that are hybridized to each other:
A pair of chips comprising a conductive path electrically connecting the first chip to the second chip, the conductive path including one of a class I, class II, class III and class IV type well connection. An electrical connection between two chips:
An IC pad on a first of the two chips;
An IC pad on a second of the two chips;
A first barrier metal on the IC pad of the first chip;
A second barrier metal on the IC pad of the second chip;
A conductive malleable metal trapped between the first barrier metal and the second barrier metal and different from the two barrier metals;
The first barrier metal, the conductive malleable metal, and the second barrier metal form a conductive path between the IC pad of the first chip and the IC pad of the second chip. Electrical connection.   25. The electrical connection of claim 24, further comprising a rigid metal material disposed between the conductive malleable metal and one of the first and second barrier metals. The conductive malleable metal includes a metal or alloy having a melting point less than 1000 ° C .;
26. The electrical connection of claim 25, wherein the rigid metal material comprises a metal or alloy having a melting point that is at least 50 ° C. higher than the melting point of the conductive malleable metal.   26. The electrical connection of claim 25, wherein the first barrier metal, the second barrier metal, the conductive malleable metal, and the rigid metal material collectively form a post and penetration connection.   26. The electrical connection of claim 25, further comprising a diffusion barrier disposed between the rigid metal and the malleable metal.   25. The electrical connection of claim 24, wherein the first barrier metal covers the IC pad of the first chip.   25. The electrical connection of claim 24, wherein the second barrier metal covers the IC pad of the second chip.   26. The electrical connection of claim 25, wherein the rigid metal and at least one of the first barrier and the second barrier comprise the same metal.