JP2012028798A - Memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory which can essentially reduce errors caused by interference between reading and writing of information by a memory element and comparatively easily achieve high reliability.SOLUTION: The memory comprises a memory element 10 in which a storage layer 5 is disposed under an interlayer 4 and a magnetization fixed layer 3 is disposed on the interlayer 4, and information is stored in the storage layer 5 such that a magnetization direction of the storage layer 5 is changed by a flow of a current in a lamination direction, and current supply means flows a current in a lamination direction in the memory element 10. When information stored in the storage layer 5 is read, a current is flown into the memory element 10 from the storage layer 5 side to the magnetization fixed layer 3 side through the current supply means.

Description

  The present invention includes a storage element that stores a magnetization state of a ferromagnetic layer as information and a magnetization fixed layer whose magnetization direction is fixed, and changes a magnetization direction of the storage layer by passing a current. The present invention relates to a provided memory and is suitable for application to a nonvolatile memory.

With the rapid spread of information communication devices, especially small personal information devices such as mobile terminals, the elements such as memory and logic that make up these devices have higher integration, higher speed, lower power consumption, etc. There is a need for performance.
In particular, high-speed and large-capacity semiconductor non-volatile memory is a complementary technology to magnetic hard disks that are inherently difficult to reduce in size, increase in speed, and reduce power consumption due to the existence of moving parts. It is becoming more and more important to realize new functions such as “instant-on” that starts up the operation system at the same time as the power is turned on.

  As nonvolatile memories, semiconductor flash memories, FeRAMs (ferroelectric nonvolatile memories) and the like have been put into practical use, and active research and development for further enhancement of performance is being performed.

  Recently, as a new nonvolatile memory using a magnetic material, MRAM (Magnetic Random Access Memory) using a tunnel magnetoresistive effect has been remarkably progressed and attracted attention (for example, see Non-Patent Document 1 and Non-Patent Document 2). ).

This MRAM has a structure in which minute magnetic memory elements for recording information are regularly arranged, and wirings such as word lines and bit lines are provided so that each can be accessed.
Each magnetic memory element includes a storage layer that records information as the magnetization direction of the ferromagnetic material.

  As a configuration of the magnetic memory element, a so-called magnetic tunnel junction (Magnetic Tunnel Junction) including the above-described storage layer, a tunnel insulating film (nonmagnetic spacer film), and a magnetization fixed layer whose magnetization direction is fixed. A structure using MTJ) is employed. The magnetization direction of the magnetization fixed layer can be fixed, for example, by providing an antiferromagnetic layer.

  In such a structure, a so-called tunnel magnetoresistance effect is produced in which the resistance value with respect to the tunnel current flowing through the tunnel insulating film changes depending on the angle between the magnetization direction of the storage layer and the magnetization direction of the magnetization fixed layer. Therefore, information can be written (recorded) by utilizing the tunnel magnetoresistance effect. The magnitude of the resistance value takes a maximum value when the magnetization direction of the storage layer and the magnetization direction of the magnetization fixed layer are antiparallel, and takes a minimum value when they are parallel.

In the magnetic memory element configured as described above, writing (recording) of information to the magnetic memory element is performed on the storage layer of the magnetic memory element by a combined current magnetic field generated by flowing current to both the word line and the bit line. This can be done by controlling the direction of magnetization. In general, the difference in magnetization direction (magnetization state) at this time is stored in association with “0” information and “1” information.
On the other hand, when reading recorded information, a memory cell is selected using an element such as a transistor, and the difference in the magnetization direction of the storage layer is determined by using the tunnel magnetoresistive effect of the magnetic memory element. By detecting as, it is possible to detect the recorded information.

When this MRAM is compared with other nonvolatile memories, the greatest feature is that the direction of magnetization of the storage layer made of a ferromagnetic material is reversed to rewrite “0” information and “1” information. The rewriting of almost infinite (> 10 ¹⁵ times) is possible.

  However, in MRAM, in order to rewrite recorded information, it is necessary to generate a relatively large current magnetic field, and a certain amount of current (for example, about several mA) must be passed through the address wiring. Therefore, power consumption increases.

In addition, in the MRAM, a write address line and a read address line are required, and it is structurally difficult to miniaturize the memory cell.
In addition, as the device becomes finer, the address wiring becomes thinner and it becomes difficult to pass a sufficient current. The coercive force increases, so the current magnetic field required increases and the power consumption increases. Will occur.
Therefore, it is difficult to miniaturize the element.

Therefore, attention has been paid to a memory having a configuration using magnetization reversal by spin transfer as a configuration capable of performing magnetization reversal with a smaller current.
Magnetization reversal by spin transfer is to cause magnetization reversal in another magnetic material by injecting spin-polarized electrons that have passed through the magnetic material into another magnetic material (for example, patents). Reference 1).
That is, when spin-polarized electrons that have passed through a magnetic layer (magnetization pinned layer) whose magnetization direction is fixed enter another magnetic layer (magnetization free layer) whose magnetization direction is not fixed, This is a phenomenon of applying torque to the magnetization. And if the electric current beyond a certain threshold value is sent, the direction of magnetization of a magnetic layer (magnetization free layer) can be reversed.

  For example, a giant magnetoresistive effect element (GMR element) or a magnetic tunnel junction element (MTJ element) having a magnetization fixed layer and a magnetization free layer can be used by passing a current in a direction perpendicular to the film surface. The magnetization direction of at least a part of the magnetic layer of the element can be reversed.

Thus, a storage element having a magnetization fixed layer and a magnetization free layer (storage layer) is formed, and by changing the polarity of a current flowing through the storage element, the magnetization direction of the storage layer is reversed, and “0” information and Rewrite with “1” information.
Reading recorded information can utilize the tunnel magnetoresistive effect in the same manner as the MRAM, by providing a tunnel insulating layer between the magnetization fixed layer and the magnetization free layer (storage layer).

Magnetization reversal by spin transfer has an advantage that magnetization reversal can be realized without increasing current even if the element is miniaturized.
The absolute value of the current passed through the memory element for magnetization reversal is 1 mA or less for a memory element with a scale of about 0.1 μm, for example, and decreases in proportion to the volume of the memory element, which is advantageous in terms of scaling.

  In addition, since the recording word line required in the MRAM is not required, there is an advantage that the configuration of the memory cell is simplified.

JP 2003-17782 A

Nikkei Electronics 2001.1.22 (pages 164-171) J. NaHas et al., IEEE / ISSCC 2004 Visulas Supplement, p.22

When a memory is configured using the above-described magnetization reversal by spin transfer, when information is written in the storage layer (rewriting with “0” information and “1” information), the information recorded in the storage layer is changed. When reading, the current passes through the same path.
For this reason, the read current must be set to be sufficiently lower than the write current, and the variation between the two currents can be minimized to prevent erroneous writing during reading.

FIG. 7 shows a schematic cross-sectional view of a general configuration of a memory element that records information using spin transfer.
The storage element 110 is configured by laminating a base layer 101, an antiferromagnetic layer 102, a magnetization fixed layer 103, a nonmagnetic layer 104, a storage layer 105, and a cap layer 106 from the lower layer.
The memory layer 105 is made of a ferromagnetic material having uniaxial magnetic anisotropy, and information can be stored in the memory element 110 depending on the magnetization state of the memory layer 105, that is, the direction of the magnetization M 112 of the memory layer 105.
In addition, a fixed magnetization layer 103 made of a ferromagnetic material and fixed in the direction of the magnetization M111 is provided to the storage layer 105 via the nonmagnetic layer 104. In the configuration of FIG. 7, since the antiferromagnetic layer 102 is provided below the fixed magnetization layer 103, the direction of the magnetization M <b> 111 of the fixed magnetization layer 103 is fixed by the action of the antiferromagnetic layer 102.

  When writing information to the storage element 110, a current is passed in the direction perpendicular to the film surface of the storage layer 105, that is, the stacking direction of the storage element 105, and the direction of the magnetization M112 of the storage layer 105 is changed by spin transfer. Invert.

Here, the magnetization reversal by spin transfer will be briefly described.
Electrons have two types of spin angular momentum. Temporarily, these two types of spin angular momentum are defined as upward and downward, respectively. The number of both is the same inside the non-magnetic material, and the number of both is different inside the ferromagnetic material.

Then, in the memory element 110 shown in FIG. 7, a case is considered in which the directions of the magnetic moments are antiparallel in the magnetization fixed layer 103 and the storage layer 105, and electrons are moved from the magnetization fixed layer 103 to the storage layer 105. .
The electrons that have passed through the magnetization fixed layer 103 are spin-polarized, and there is a difference between the upward and downward numbers of spin angular momentum.
The thickness of the nonmagnetic layer 104 is sufficiently thin, and before the spin polarization is relaxed and becomes a nonpolarized state (the same number of upwards and downwards) in a normal nonmagnetic material, the storage layer which is the other magnetic material When reaching 105, the direction of the magnetic moment of the magnetization fixed layer 103 and the storage layer 105 is in an antiparallel state, and the sign of the spin polarization degree is reversed. The electrons are inverted, that is, the direction of spin angular momentum is changed. At this time, since the total angular momentum of the system must be preserved, a reaction equivalent to the sum of changes in angular momentum due to the electrons whose direction is changed is also given to the magnetic moment of the storage layer 105.

  When the current, that is, the number of electrons passing through the unit time is small, the total number of electrons changing the direction is small, so that the change in angular momentum generated in the magnetic moment of the memory layer 105 is small. Angular momentum change can be given within a unit time. The time change of the angular momentum is a torque. When the torque exceeds a certain threshold value, the magnetic moment M112 of the memory layer 105 starts to reverse and becomes stable when rotated 180 degrees due to its uniaxial anisotropy. That is, inversion from the antiparallel state to the parallel state occurs.

On the other hand, in the magnetization fixed layer 103 and the storage layer 105, when the directions of the magnetic moments are parallel to each other, if a current is passed in the direction of sending electrons from the storage layer 105 to the magnetization fixed layer 103, the magnetization fixed this time. When electrons that have been spin-reversed when reflected by the layer 103 enter the memory layer 105, torque can be applied to reverse the antiparallel state.
However, the amount of current required for reversing from the parallel state to the anti-parallel state is greater than when reversing from the anti-parallel state to the parallel state.

  As described above, information (0 information / 1 information) is recorded in the storage layer 105 in a direction from the magnetization fixed layer 103 to the storage layer 105, or vice versa, by a current equal to or greater than a certain threshold corresponding to each polarity. It is done by flowing.

Further, the information recorded in the storage layer 105 is read out by a resistance change depending on the relative angle of the magnetic moment between the storage layer 105 and the magnetization fixed layer (reference layer) 103, that is, the minimum resistance and antiparallel when they are parallel to each other. In this case, the maximum resistance can be obtained by utilizing the so-called magnetoresistance effect.
Specifically, information can be read by applying an approximately constant voltage to the memory element 110 and detecting the magnitude of the current flowing at that time.

In the following description, the relationship between the resistance state of the memory element 110 and information is defined as “1” information for the low resistance state and “0” information for the high resistance state.
Further, a current for moving electrons from the cap layer 106 to the base layer 101 in FIG. 7, that is, from the upper layer to the lower layer, is defined as a positive current. At this time, when a positive current is passed, electrons move from the cap layer 106 toward the base layer 101, that is, from the storage layer 105 toward the magnetization fixed layer 103. The magnetization M111 and the magnetization M112 of the storage layer 105 are antiparallel, and the storage element 110 is in a high resistance state.
Therefore, a current for writing “1” information (low resistance state) has a negative polarity, and a current for writing 0 information (high resistance state) has a positive polarity.

Next, in a memory element that records information using spin transfer, such as the memory element 110 shown in FIG. 7, the mutual relationship between the operating currents in the write operation and the read operation is schematically shown in FIG. Shown in The horizontal axis in FIG. 8 represents current, and the vertical axis represents the number of elements through which a certain amount of current flows during a predetermined operation.
FIG. 8 shows the distributions and average values of the currents + Iw and −Iw necessary for writing 1 information or 0 information, respectively.
Ir0 and Ir1 are the distribution and average value of the current that flows at the time of reading. Ir0 having a small amount of current corresponds to reading of a high resistance state (0 information), and Ir1 having a large amount of current is a low resistance state (1 information). Corresponds to reading. Ic is a current that flows in a reference cell for reading (a cell that generates a reference current used by the operational amplifier for comparison), and ΔI indicates a difference current during reading corresponding to a resistance change.

In a memory element that records information using spin transfer, conventionally, the polarity of the read current is arbitrary.
In addition, it is arbitrary whether the polarity of writing, that is, for example, negative writing current -Iw is made to correspond to writing of 1 information or writing of 0 information, but this depends on the configuration of the multilayer film of the memory element. It is prescribed.

However, when the “1” information, that is, the resistance value in the low resistance state is low, as shown in FIG. 9, the current Ir1 that flows when the “1” information is read increases, and is close to the current + Iw necessary for writing. Thus, the tails of the distribution of current values having variations may overlap.
At this time, since there is an overlap between the read current Ir1 and the write current + Iw, an error that causes erroneous writing at the time of reading may occur.

  This fact is disadvantageous when it is desired to reduce the write current + Iw for the purpose of reducing power consumption. In addition, in order to reduce the overlap, there is a development difficulty that variation in write current and read current must be suppressed.

  In order to solve the above problems, in the present invention, errors due to interference between reading and writing of information in a memory element can be essentially reduced, and high reliability can be realized relatively easily. A memory that can be used is provided.

The memory of the present invention has a storage layer that retains information according to the magnetization state of a magnetic substance, and a magnetization fixed layer is provided through the intermediate layer for the storage layer , and the storage layer is disposed below the intermediate layer. The magnetization pinned layer is disposed above the intermediate layer, and the direction of magnetization of the memory layer is changed by passing a current in the stacking direction, and information is recorded on the memory layer. Current supply means for supplying a current in the stacking direction to the element, and when reading information recorded in the storage layer, the current is stored from the storage layer side of the storage element to the magnetization fixed layer side through the current supply means. It flows to the element.

According to the configuration of the memory of the present invention described above, the memory element and current supply means (electrodes, wiring, power supply, etc.) for supplying current in the stacking direction to the memory element are provided, and the memory layer is a lower layer of the intermediate layer. The magnetization pinned layer is arranged on the intermediate layer, and when reading information recorded in the memory layer, the current is transferred from the memory layer side of the memory element to the magnetization pinned layer side through the current supply means. Therefore, even when the read current distribution partially overlaps with the write current distribution, when the read current distribution partially overlaps with the write current distribution, the read current is low. Since it is limited only to the resistance state, it is possible to suppress the occurrence of an error in which the resistance state changes due to the read current.
That is, it becomes possible to substantially reduce the occurrence of errors due to interference between reading and writing.

According to the above-described present invention, since the occurrence of errors due to interference between reading and writing can be essentially reduced, the occurrence rate of errors due to interference can be achieved even if there is some variation in the write current for each memory cell. Can be made very small.
Therefore, according to the present invention, it is possible to easily realize a highly reliable memory.

1 is a schematic configuration diagram (a cross-sectional view of one memory cell) of a memory according to an embodiment of the present invention. FIG. 2A is a plan view showing a lower layer than a first wiring layer of the memory cell of FIG. B is a top view of the memory cell of FIG. It is a schematic block diagram (sectional drawing) of the memory element of FIG. It is a schematic block diagram (sectional drawing) of the memory element which comprises the memory of other embodiment of this invention. A to D When a storage element that records information using spin transfer is configured, each of the cases is classified according to the relative relationship between the write current and the read current and the relative relationship between the polarity of the write current and the information to be written. It is a figure which shows a case. It is a figure which shows the incidence rate of the error of the device corresponding to each case of FIG. 5A-FIG. 5D. It is a schematic sectional drawing of the general structure of the memory element which records information using a spin transfer. FIG. 3 is a diagram schematically showing the mutual relationship between operating currents in a write operation and a read operation in a storage element that records information using spin transfer. It is a figure which shows the case where the current distribution of a write current and a read current overlaps.

First, an outline of the present invention will be described prior to description of specific embodiments of the present invention.
In the following description, as described above, the low resistance state is defined as “1” information, the high resistance state is defined as “0” information, and the current for moving electrons from the upper layer to the lower layer of the memory element is also defined. It is defined as a positive current.
In the present invention, the polarity relationship and the magnitude relationship between the current at the time of writing information and the current at the time of reading information are important for the memory element.

In the present invention, the film configuration of the memory element and the circuit configuration of the memory are adjusted so that writing that overlaps the read current distribution in the low resistance state (one information) becomes an operation of writing the low resistance state (one information).
With this configuration, even if each current distribution of the positive write current + Iw and the read current Ir1 in the low resistance state (one information) has an overlap as shown in FIG. Even if one information is overwritten when data is read, an error does not occur, so that a problem of erroneous writing can be avoided.

  When a storage element that records information using spin transfer is configured like the storage element 110 shown in FIG. 7, the relative relationship between the write currents −Iw and + Iw and the read currents Ir0 and Ir1, and the write Depending on the relative relationship between the polarities of the currents -Iw and + Iw and the information to be written (0 information / 1 information), it can be divided into four cases as shown in FIGS. 5A to 5D.

In the case shown in FIG. 5A, the negative write current −Iw is the current Iw1 for performing the write operation of 1 information, the positive write current + Iw is the current Iw0 for performing the write operation of 0 information, and the read currents Ir0, This is a case where Ir1 is a positive current.
In the case shown in FIG. 5B, the negative write current −Iw is the current Iw0 that performs the write operation of 0 information, the positive write current + Iw is the current Iw1 that performs the write operation of 1 information, and the read currents Ir0, This is a case where Ir1 is a positive current.
In the case shown in FIG. 5C, the negative write current −Iw is the current Iw1 for performing the write operation of 1 information, the positive write current + Iw is the current Iw0 for performing the write operation of 0 information, and the read currents Ir0, This is a case where Ir1 is a negative current.
In the case shown in FIG. 5D, the negative write current −Iw is the current Iw0 for performing the write operation of 0 information, the positive write current + Iw is the current Iw1 for performing the write operation of 1 information, and the read currents Ir0, This is a case where Ir1 is a negative current.

  Conventionally, the polarity of the read current is arbitrary, and therefore, any of the four configurations shown in FIGS. 5A to 5D has been adopted.

The problems are interference between writing 1 information and reading 0 information, and interference between writing 0 information and reading 1 information. As is clear from FIGS. 5A to 5D and FIG. The current Ir0 required for reading information is small, and the more serious problem is interference between reading 1 information and writing 0 information.
Therefore, the multilayer structure of the memory element and the read current are set so that the relationship between the operating currents is the relationship shown in FIG. 5B or 5C so that the read current Ir1 for one information and the write current Iw1 for one information are close to each other. If the polarity is defined, the occurrence of errors can be suppressed.

FIG. 6 shows the rate of occurrence of errors occurring in the device corresponding to each case of FIGS. 5A to 5D. The vertical axis in FIG. 6 represents the occurrence rate of erroneous write errors due to the overlap between the write current distribution and the read current, and the horizontal axis represents the variation in the write current. Note that the variation in the read current of the measured device is 1.5% in terms of standard deviation σ / average value.
In FIG. 6, curve A corresponds to a device showing the relationship between operating currents as in FIG. 5B or 5C, and curve B corresponds to a device showing the relationship between operating currents as in FIG. 5A or 5D.

From FIG. 6, it can be seen that in the case of the curve A having the relationship of FIG. 5B or FIG. 5C, the error occurrence rate is greatly reduced.
The relationship shown in FIG. 5B or FIG. 5C makes it possible to easily reduce errors without greatly improving the variation in write current.

Subsequently, specific embodiments of the present invention will be described.
FIG. 1 shows a schematic configuration diagram (cross-sectional view) of a memory as an embodiment of the present invention. FIG. 1 shows a cross-sectional view of one memory cell constituting a memory (storage device).
In this memory, a memory cell is constituted by a memory element 10 that can hold information in a magnetized state.
The storage element 10 has a storage layer composed of a ferromagnetic layer whose magnetization direction is reversed by spin transfer.

In addition, a drain region 12, a source region 13, and a gate electrode 14 constituting a selection transistor for selecting each memory cell are formed on a semiconductor substrate 11 such as a silicon substrate.
Among these, the gate electrode 14 is connected to a word line WL (see FIG. 2) in a cross section different from that in FIG. The drain region 12 is connected to a sense line SL including a second wiring layer 16B via a contact layer 15D, a first wiring layer 16A, and a buried metal layer 17. The source region 13 is connected via a contact layer 15S, a first wiring layer 16A, a second wiring layer 16B, a third wiring layer 16C, and a buried metal layer 17 between the wiring layers 16A, 16B and 16C. And connected to the memory element 10.
The storage element 10 is connected to the bit line BL including the fourth wiring layer 18 thereon.
For example, by forming the drain region 12 in common for two selection transistors, the sense line SL can be shared by two memory cells.

Further, FIG. 2A shows a plan view showing a layer below the first wiring layer 16A and FIG. 2B shows a top view of one memory cell of the memory according to the present embodiment.
As shown in FIGS. 2A and 2B, the selection transistor is configured such that the NMOS transistor 19N and the PMOS transistor 19P are electrically connected to each other between the source and the drain via the first wiring layer 16A. It is configured.
As a result, the NMOS transistor 19N and the PMOS transistor 19P constitute a so-called transfer gate.
The transfer gate can be used to perform switching such as passing a current through the memory element 10 or preventing a current from flowing through the memory element 10.
The gate electrode 14 of the PMOS transistor 19P is connected to the word line WL formed by the first wiring layer 16A via the contact layer 15G. The gate electrode 14 of the NMOS transistor 19N is connected to the word line WL via the contact layer 15G. Corresponding to ON / OFF of the current flowing through the memory element 10, a control signal is supplied to one of the word line WL on the PMOS transistor 19P side and the word line WL on the NMOS transistor 19N side, and the same control is applied to the other. A control signal is supplied by passing the signal through an inverter.

  As for the size of the selection transistor, for example, the width Wn of the NMOS transistor 19N is set to 1 μm, and the width Wp of the PMOS transistor 19P is set to 1.5 μm.

  A positive or negative potential difference is applied to the bit line BL and the sense line SL, and a voltage is applied to the word line WL to turn on the transfer gate. Current can flow.

Next, FIG. 3 shows a schematic configuration diagram (cross-sectional view) of the memory element 10 constituting the memory of the present embodiment.
The memory element 10 is formed by laminating layers in the order of the underlayer 1, the antiferromagnetic layer 2, the magnetization fixed layer 3, the nonmagnetic layer 4, the memory layer 5, and the cap layer 6 from the lower layer.

  An antiferromagnetic layer 2 is provided under the magnetization fixed layer 3, and the direction of the magnetization M <b> 1 of the magnetization fixed layer 3 is fixed by the antiferromagnetic layer 2. In FIG. 3, the direction of the magnetization M1 of the magnetization fixed layer 3 is fixed to the right.

  The storage layer 5 holds information according to the magnetization state, that is, the direction of the magnetization M2 of the storage layer 5, and can hold information depending on whether the direction of the magnetization M2 is rightward or leftward.

Further, since the nonmagnetic layer 4 is provided between the storage layer 5 and the magnetization fixed layer 3, the storage layer 5 and the magnetization fixed layer 3 constitute a GMR element or an MTJ element. Thereby, the direction of the magnetization M2 of the memory layer 5 can be detected using the magnetoresistive effect.
That is, when the direction of the magnetization M2 of the storage layer 5 is parallel (rightward) to the direction of the magnetization M1 of the magnetization fixed layer 3 (rightward), the electrical resistance is low, and when the direction is antiparallel (leftward). Since the electrical resistance becomes high, the direction of the magnetization M2 of the storage layer 5 can be detected using the magnetoresistance effect.

The material of the magnetization fixed layer 3 and the storage layer 5 is not particularly limited, but an alloy material composed of one or more of iron, nickel, and cobalt can be used. Furthermore, transition metal elements such as Nb and Zr, and light elements such as B can also be contained.
As a material of the antiferromagnetic layer 2, an alloy of a metal element such as iron, nickel, platinum, iridium, and rhodium and manganese, an oxide of cobalt, nickel, or the like can be used.

  The nonmagnetic layer 4 is composed of a nonmagnetic conductive layer or an insulating layer such as a tunnel barrier layer. As the nonmagnetic conductive layer, for example, ruthenium, copper, chromium, gold, silver or the like can be used. As the tunnel barrier layer, an insulating material such as aluminum oxide can be used.

In the present embodiment, in particular, the storage layer is formed by flowing electrons to the storage element 10 in the direction 7 from the base layer 1 to the cap layer 6, that is, from the magnetization fixed layer 3 to the storage layer 5. The information recorded in 5 is read out. Then, current supply means such as electrodes, wirings BL and SL, and a power source are configured so that electrons flow in the direction 7 at the time of reading.
At this time, the read current Ir (Ir0, Ir1) is in the direction from the cap layer 6 to the underlying layer 1 as opposed to the direction 7 in which electrons flow.
This read current Ir corresponds to the negative current described above and has the same polarity as the current Iw1 for writing the low resistance state (current flowing from the magnetization fixed layer 3 to the storage layer 5) Iw1. The laminated film configuration of the memory element 10 and the polarity of the read current correspond to the case shown in FIG. 5C.

  Therefore, as shown in FIG. 6, the occurrence of errors due to interference between reading and writing can be reduced.

According to the memory configuration of the above-described embodiment, when reading information recorded in the storage layer 5 of the storage element 10, the electrical resistance of the storage element 10 is changed from the high resistance state to the low resistance state. As described above, the current having the same negative polarity as the current −Iw (Iw1) at the time of writing (recording information) flows to the memory element 10, so that when the memory element 10 is in a low resistance state at the time of reading, the read current Even if the distribution of Ir1 partially overlaps with the distribution of the write current -Iw, writing with the read current Ir is limited to only the low resistance state.
As a result, it is possible to suppress the occurrence of an error in which the resistance state changes due to the read current, and it is possible to substantially reduce the occurrence of an error due to the interference between reading and writing.

Therefore, since errors due to interference between reading and writing can be essentially reduced, even if there is some variation in write current for each memory cell, the rate of occurrence of errors due to interference can be made very small. become.
Therefore, it is possible to easily realize a highly reliable memory.

  Next, as another embodiment of the present invention, FIG. 4 shows a schematic configuration diagram (cross-sectional view) of a memory element constituting a memory.

In the present embodiment, as shown in FIG. 4, the layers are laminated in the order of the base layer 1, the storage layer 5, the nonmagnetic layer 4, the magnetization fixed layer 3, the reverberant magnetic layer 2, and the cap layer 6 from the lower layer. Thus, the storage element 20 is configured. That is, the stacking order of the magnetization fixed layer 3 and the storage layer 5 is opposite to that of the storage element 10 in FIG.
Since other configurations are the same as those of the memory element 10 of the previous embodiment, the same reference numerals are given and redundant description is omitted.
In addition, the configuration of other parts of the memory can be configured in the same manner as the memory of the previous embodiment shown in FIGS.

Further, in the present embodiment, in particular, by flowing electrons in the direction 8 from the cap layer 6 to the underlayer 1, that is, in the direction from the magnetization fixed layer 3 to the storage layer 5, with respect to the storage element 20, Information recorded in the storage layer 5 is read. Then, current supply means such as electrodes, wirings BL and SL, and a power source are configured so that electrons flow in the direction 8 at the time of reading.
At this time, the read current Ir (Ir0, Ir1) is in the direction from the base layer 1 to the cap layer 6 as opposed to the direction 8 in which electrons flow.
This read current Ir corresponds to the positive current described above, and has the same polarity as the current for writing the low resistance state (current flowing electrons from the magnetization fixed layer 3 to the storage layer 5). The laminated film configuration of the memory element 20 and the polarity of the read current correspond to the case shown in FIG. 5B.

According to the memory configuration of the above-described embodiment, when reading information recorded in the storage layer 5 of the storage element 20, the electrical resistance of the storage element 20 is changed from the high resistance state to the low resistance state. Thus, when a current having the same positive polarity as the current + Iw (Iw1) at the time of writing (recording information) flows through the memory element 20, the read current Ir1 when the memory element 20 is in a low resistance state at the time of reading Is partially limited to the write current + Iw, the writing with the read current Ir is limited to the low resistance state.
As a result, it is possible to suppress the occurrence of an error in which the resistance state changes due to the read current, and it is possible to substantially reduce the occurrence of an error due to the interference between reading and writing.

Therefore, since errors due to interference between reading and writing can be essentially reduced, even if there is some variation in write current for each memory cell, the rate of occurrence of errors due to interference can be made very small. become.
Therefore, it is possible to easily realize a highly reliable memory.

The layer configuration of the memory element in each of the above-described embodiments can be changed within a range that plays an essential role.
For example, a ferromagnetic material having a sufficiently large coercive force alone may be used as the magnetization fixed layer independently of the lamination with the antiferromagnetic layer.
Further, the magnetic layer constituting the storage layer and the magnetization fixed layer is not limited to a single magnetic layer, and two or more magnetic layers having different compositions may be directly laminated or two or more layers may be formed. It is also possible to have a laminated ferrimagnetic structure in which magnetic layers are laminated via nonmagnetic layers.

  The present invention is not limited to the case where the absolute values of the positive and negative bipolar write currents + Iw and -Iw are equal as shown in FIGS. 5B and 5C, but the absolute values of the positive and negative bipolar write currents are different. It is also applicable to.

  The operation principle of the present invention described above is not limited to a memory using spin transfer, and information (0 information / 1 information) is recorded by a bipolar current, and a resistance change is detected by a current in an arbitrary direction. It is considered that the present invention can be generally applied to a memory for reading information.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1 Underlayer, 2 Antiferromagnetic layer, 3 Magnetization fixed layer, 4 Nonmagnetic layer, 5 Memory layer, 6 Cap layer, 10 and 20 Memory element, 12 Drain region, 13 Source region, 14 Gate electrode, 19N NMOS transistor, 19P PMOS transistor, WL word line, BL bit line, SL sense line

Claims (1)

It has a storage layer that holds information according to the magnetization state of the magnetic material,
A magnetization fixed layer is provided via an intermediate layer for the storage layer,
The storage layer is disposed below the intermediate layer;
The magnetization fixed layer is disposed on an upper layer of the intermediate layer,
A storage element in which the direction of magnetization of the storage layer is changed by passing a current in the stacking direction, and information is recorded on the storage layer;
Current supply means for supplying current in the stacking direction to the storage element;
A memory in which, when reading information recorded in the storage layer, a current flows from the storage layer side of the storage element to the magnetization fixed layer side through the current supply means to the storage element.

Images