JP2012027751A - Data transfer device, image forming device, data transfer control method, data transfer control program and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently and properly control accesses on the basis of priority with respect to a high-speed serial bus.SOLUTION: In an image processing device 1, high-priority video output control units 22a, 22b, 22c and 22d issue memory access request signals VOUT_REQa, VOUT_REQb, VOUT_REQc, VOUT_REQd intensively, for each image data line, to a PCIe end controller 28 as an interface and an arbiter 25 that arbitrates access requests to a PCIe route controller 21, on a high-speed serial bus, such as PCIes 8 and 9, where the request commands and responses thereto are separated from each other.

Description

  The present invention relates to a data transfer apparatus, an image forming apparatus, a data transfer control method, a data transfer control program, and a recording medium, and more particularly, data transfer that efficiently and appropriately performs access control based on priority to a high-speed serial bus. The present invention relates to an apparatus, an image forming apparatus, a data transfer control method, a data transfer control program, and a recording medium.

  In image processing apparatuses such as copying apparatuses, composite apparatuses, scanner apparatuses, and facsimile apparatuses, it is important to transfer data (image data, etc.) at high speed and appropriately. For example, image data read by a scanner unit, external data Various image processing for input image data such as image data read from a storage unit (for example, hard disk, CD-ROM (Compact Disc Read Only Memory), DVD (Digital Video Disk), SD (Secure Digital) card, etc.) And temporarily store it in a temporary storage memory such as RAM (Random Access Memory) or hard disk, and the image data stored in the temporary storage memory is necessary again image processing (scanner γ correction, filter processing, background removal, color correction) Printer gamma correction, halftone processing, etc.) and sent to the printer unit for recording output or via a network Or transferred to chromatography data or the like, performs various output processing such as subjecting the facsimile transmission.

  In recent years, image processing apparatuses such as composite devices and printers have been requested to realize high-speed data transfer in data transfer between an image processing chip such as an ASIC (Application Specific Integrated Circuit) and a memory. And PCI (Peripheral Component Interconnect) Express (hereinafter referred to as PCIe), which is a split transaction bus that performs high-speed transfer that can issue the next request without waiting for the response. Yes. In PCIe, the request command and the response to the request command are separated as described above, and the request command can be issued one after another without waiting for the response to the request command. However, a request source (for example, a DMAC (Direct Memory Access Controller: DMA controller) for input / output of video output data) that needs to guarantee the worst value of the transfer rate can be improved. If the transfer amount cannot be maintained at a predetermined amount or more, the guaranteed value cannot be increased with respect to a request source that generates an abnormal image.

  That is, in PCIe, as described above, request commands can be issued one after another without waiting for a response to the request command (hereinafter referred to as first throw), but in order to effectively use this characteristic, Having a buffer (queue) for holding request commands, the issued request commands are temporarily stored in this queue, so that a high request command issue rate can be achieved.

  According to the PCIe standard, a virtual channel function for transmitting packet data of a plurality of traffics by using a serial bus (high-speed serial bus) in a time division manner in units of virtual channels, and packet data for each virtual channel It has an arbitration function that arbitrates the priority to issue the packet, and it is possible to adjust the transfer rate when you want to simultaneously transfer multiple traffic packet data with different data transfer priorities using the serial bus. ing. More specifically, the algorithm in the arbitration of the virtual channel of the PCIe standard follows a round robin method in which packet data is issued at an equal frequency for each virtual channel VC, and a table that can be arbitrarily specified for each virtual channel. There are weighted round robin (Weighted Round Robin) method that issues packet data at a weighted frequency and strict method that issues packet data in a fixed priority order for each virtual channel VC. It is possible to adjust the priority of packets to be processed on a transaction basis.

  However, a high request command issue rate does not mean that a high guaranteed value can be secured for a request source that needs to guarantee the worst transfer rate. That is, in general, PCIe has only a small-capacity buffer memory for receiving a response result to a request command that has been thrown first, and performs a first throw within the capacity range of the buffer memory. ing. Therefore, when the maximum value of the first throw is reached, a situation occurs in which it is impossible to issue a request even if it is desired to continue issuing requests. In this state, a request that needs to guarantee the worst transfer rate is required. Arbitration will be performed in the absence of a source. As a result, even if the request source that needs to guarantee the worst value of the transfer rate is set to the high priority of the arbiter, requests from the request sources of lower priority are successively granted, the requests are issued, When a request source that needs to guarantee the worst transfer rate receives a response to a previously issued request and issues a request continuously, the request of the lower priority request source that has been granted in advance is not received. Multiple allowed and stored in the queue. Therefore, a request from a request source that needs to guarantee the worst transfer rate is executed after these lower priority requests are executed, and the guaranteed transfer rate is set low. There was a need to do. Even if the number of first throws can be increased, the path is monopolized by the high priority request source, and the execution of the request from the low priority request source is waited for a long time. As a result, the number of first throws could not be increased.

  Conventionally, even when a transaction layer transmission buffer is present, a technique has been proposed for arbitrating priorities while maintaining consistency in priority between arbiter settings and actual traffic ( Patent Document 1). Specifically, in this prior art, in a data transfer circuit that arbitrates a plurality of data according to an arbitration table by an arbiter and outputs the data to a serial bus, statistical information of traffic is obtained based on the amount of packet data transmitted through the serial communication path. The priority arbitration is performed by updating the weight information of the arbitration table based on the generated traffic statistical information.

  However, in the prior art described in the above publication, since the arbitration priority arbitration is performed using the statistical information of the actual packet data, the accuracy is unknown and it is necessary to guarantee the worst transfer rate. In order to make it possible to set a high guaranteed value for a certain request source, there is a need for improvement.

  Accordingly, the present invention provides a data transfer apparatus, an image forming apparatus, and a data transfer control method capable of setting a high guaranteed value for an access request means that needs to guarantee the worst value of the transfer rate of a high-speed serial bus. An object of the present invention is to provide a data transfer control program and a recording medium.

  In order to achieve the above object, the present invention makes a transfer access request for image data to a high-speed serial bus and adjusts an access request from a plurality of access request means assigned priority levels by an arbiter. In addition, a high priority is given to the required access requesting means that needs to guarantee the worst value of the transfer rate among the access requesting means, and from the required access requesting means intensively in units of data lines. It is characterized by issuing an access request.

  Further, the present invention counts the time during which access requests from specific access request means having a lower priority than the required access request means are continuously disallowed, and waits for a predetermined waiting time. The access may be preferentially permitted to the specific access request means when time comes.

  Furthermore, the present invention sets a cycle in which the arbiter preferentially grants access permission to a specific access request unit having a lower priority than the guaranteed access request unit, and each time the cycle elapses, An access permission may be preferentially given to the specific access request means.

  Further, according to the present invention, the arbiter can handle one access request means as a plurality of access request means, and the access request from the required access request means requires a frequency that is multiple of the multiple. It is good also as giving an access permission.

  Further, according to the present invention, the arbiter treats the required access request means as a plurality of access request means when the ratio of the required transfer rate of the required access request means is 2 or more, and An access permission may be given to the access request from the requesting means at a frequency that is multiple of the frequency.

  According to the present invention, the guaranteed value can be set higher for the access request means that needs to guarantee the worst value of the transfer rate of the high-speed serial bus.

1 is a block diagram of a main part of an image processing apparatus to which an embodiment of the present invention is applied. The block block diagram of controller ASIC. The timing diagram of each signal in an arbiter.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  1 to 3 are diagrams showing an embodiment of a data transfer apparatus, an image forming apparatus, a data transfer control method, a data transfer control program, and a recording medium according to the present invention, and FIG. 1 shows a data transfer apparatus according to the present invention. 1 is a block configuration diagram of an image processing apparatus 1 to which an embodiment of an image forming apparatus, a data transfer control method, a data transfer control program, and a recording medium are applied.

  In FIG. 1, an image processing apparatus 1 includes a scanner 2, a plotter 3, an engine ASIC 4, a controller ASIC (CTL ASIC) 5, a CPU (Central Processing Unit) 6, a memory 7, and the like. Inputs commands necessary to perform various operations of the apparatus 1 and exchanges data with an operation display unit that displays various types of information from the image processing apparatus 1 and a partner terminal connected via a network or the like. A network unit and the like are provided, such as a copying apparatus and a composite apparatus. The operation display unit includes various keys necessary for operating the image processing apparatus 1, and includes lamps such as a display (for example, a liquid crystal display) and an LED (Light Emitting Diode). Various operations necessary for the copying process using the processing apparatus 1 are performed, and the command content input from the operation keys and various information notified from the image processing apparatus 1 to the operator are displayed on the display.

  The engine ASIC 4, the controller ASIC, the controller ASIC, and the CPU 6 are split transaction buses (high-speed serial buses) that perform a high-speed transfer that can issue the next request without waiting for a response. Some PCIe 8 and 9 are used, and the CPU 6 and the memory 7 are connected by an SSTL (Stab Series Terminated Logic) 10.

  As the scanner 2, for example, an image scanner using a CCD (Charge Coupled Device), a CMOS (Complementary Metal Oxide Semiconductor), or a CIS (Contact Image Sensor) is used. Are read at a predetermined resolution. The scanner 2 is usually provided with a document sensor (not shown). When the document is read, the document sensor detects the size of the set document and the set direction (vertical direction or horizontal direction) of the document. To the controller ASIC5. The detection of the document size and the set direction is not limited to using the document sensor, and may be detected by, for example, pre-scanning the document with the scanner 2.

  The plotter 3 uses, for example, a thermal recording device or an electrophotographic recording device using a thermal element, and records and outputs an image of a document read by the scanner 2 on a recording sheet.

  The engine ASIC 4 cooperates with the controller ASIC 5 to perform data transfer from the engine ASIC 4 to the controller ASIC 5 and data from the controller ASIC 5 to the engine ASIC 4, and to control the document reading operation of the scanner 2 and the image forming operation by the plotter 3. .

  The controller ASIC 5 performs overall control of the image processing apparatus 1 together with the CPU 6, and particularly performs data transfer control described later.

  The memory 7 stores the basic program of the image processing device 7, the data transfer control program of the present invention, system data, image data, and the like, and is read and written by the CPU 6.

  The CPU 6 controls each part of the image processing apparatus 1 based on the program in the memory 7 to execute basic processing as the image processing apparatus 1 and at the worst value of the transfer rate based on the data transfer control program of the present invention. Properly handle data transfer requests from request sources that need to guarantee

  That is, the image processing apparatus 1 includes a ROM, an EEPROM (Electrically Erasable and Programmable Read Only Memory), an EPROM, a flash memory, a flexible disk, a CD-ROM (Compact Disc Read Only Memory), a CD-RW (Compact Disc Rewritable), a DVD. A data transfer control program for executing the data transfer control method of the present invention recorded on a computer-readable recording medium such as a (Digital Versatile Disk), an SD (Secure Digital) card, or an MO (Magneto-Optical Disc) is read. Thus, it is constructed as an image processing apparatus 1 that executes a data transfer method for processing data transfer described later efficiently and at high speed. This data transfer control program is a computer-executable program written in a legacy programming language such as assembler, C, C ++, C #, Java (registered trademark) or an object-oriented programming language, and is stored in the recording medium. And can be distributed.

  The controller ASIC 5 has a block configuration as shown in FIG. The controller ASIC 5 includes a PCIe route controller (root) 21, video output control units 22 a, 22 b, 22 c, and 22 d corresponding to color image data, a line buffer (Line Buff) 23, a video input controller (VIcnt) 24, The ASIC controller includes an arbiter 25, compression units 26a, 26b, 26c, and 26d for each color, image processing units 27a, 27b, 27c, and 27d for each color, a PCIe end point controller (End) 28, an ASIC controller 29, and the like. 29 includes a control register 31 and a timer 32.

  The PCIe route controller 21 is connected to the PCIe 8 between the engine ASIC 4 and the video output control units 22 a, 22 b, 22 c, 22 d and the line buffer 23, and controls the PCIe 8 between the engine ASIC 4. Then, the plotter data from the video output control units 22a, 22b, 22c, and 22d is output to the engine ASIC 4 via the PCIe 8 and the scanner data from the engine ASIC 4 is output to the line buffer 23.

  The PCIe end controller 28 is connected to the PCIe 9 and the arbiter 25 on the CPU 6 side, and controls the PCIe 9 to perform data transfer between the arbiter 25 and the CPU 6.

  The video output control units (guaranteed access request means) 22a, 22b, 22c, 22d are respectively video output controllers 221a, 221b, 221c, 221d, stamp DMACs (STMP DMAC) 222a, 222b, 222c, 222d, video output DMAC 223a. 223b, 223c, 223d, decompressors 224a, 224b, 224c, 224d, code DMACs 225a, 225b, 225c, 225d, image DMACs 226a, 226b, 226c, 226d and line buffers (Line Buff) 227a, 227b, 227c, 227d ing.

  The video output controllers 221a, 221b, 221c, and 221d control the entire video output control units 22a, 22b, 22c, and 22d, and execute processing for transferring plotter data to the engine ASIC 4 side.

  The stamp DMACs 222a, 222b, 222c, and 222d prepare data (stamp data) to be added as stamp printing to the plotter data printed out by the plotter 3.

  The video output DMACs 223a, 223b, 223c, and 223d prepare plotter data to be printed out, and the decompressors 224a, 224b, 224c, and 224d code the data placed on the memory 7 as compressed data, code DMACs 225a, 225b, and 225c. 225d is used to perform decompression processing. The decompressed data can be used in place of data prepared in the video output DMACs 223a, 223b, 223c, and 223d, and can be written on the memory 7 using the image DMACs 226a, 226b, 226c, and 226d. .

  The line buffers 227a, 227b, 227c, and 227d are line buffers for reading and storing data required by the video output controllers 221a, 221b, 221c, and 221d from the memory 7 in advance in units of lines.

  The compression units (access request means) 26a, 26b, 26c, 26d include compressors (ENC) 261a, 261b, 261c, 261d, general purpose DMAC (GDMAC) 262a, 262b, 262c, 262d, and general purpose DMAC (GDMAC) 263a, 263b, 263c, and 263d are installed for each color. The general-purpose DMACs 262a, 262b, 262c, and 262d read the raw data via the arbiter 25 and pass them to the compressors 261a, 261b, 261c, and 261d, and the compressors 261a, 261b, 261c, and 261d store the data using a predetermined compression method. It compresses and passes to general purpose DMAC263a, 263b, 263c, 263d. The general-purpose DMACs 263a, 263b, 263c, and 263d pass the compressed data to the CPU 9 side via the arbiter 25, the PCIe end controller 28, and the PCIe 9.

  The image processing units (access request means) 27a, 27b, 27c, 27d are image processing circuits 271a, 271b, 271c, 271d, general purpose DMACs (GDMAC) 272a, 272b, 272c, 272d and general purpose DMACs (GDMAC) 273a, 273b, 273c, 273d, and four colors are installed. The general-purpose DMACs 272a, 272b, 272c, and 272d read data from the memory via the arbiter 25 and pass the data to the image processing circuits 271a, 271b, 271c, and 271d. The image processing circuits 271a, 271b, 271c, and 271d read from the memory 7. The extracted data is subjected to image processing and passed to general-purpose DMACs 273a, 273b, 273c, and 273d. The general-purpose DMACs 273a, 273b, 273c, and 273d write the image processing results to the memory 7 via the arbiter 25, the PCIe end controller 28, the PCIe 9, and the CPU 6. The image processing units 27a, 27b, 27c, and 27d are mounted for four colors, and image processing can be performed simultaneously for the four colors.

  The line buffer 23 is a line buffer for scanner data, and accumulates scanner data for a plurality of lines. The video input controller 24 controls the line buffer 23 for scanner data.

  The arbiter 25 arbitrates memory access requests from each unit via the PCIe 9 and basically arbitrates each memory access request in a round robin manner.

  An ASIC controller (access control means, cycle setting means) 29 controls the entire controller ASIC 5, and includes a control register 31, a timer 32, and the like. The control register (waiting time setting means) 31 is accessed from the CPU 6, and the control content of the controller ASIC 5 by the ASIC controller 29 changes according to the set value, and in particular, the waiting time until permission is granted for the access request is set. The The timer (time measuring means) 32 controls the arbitration of the arbiter 25 so that the request from a specific request source is preferentially granted to the request source when the request is not granted for a certain period of time. The time is measured for the predetermined time (waiting time).

  Next, the operation of this embodiment will be described. The image processing apparatus 1 according to the present embodiment detects an abnormal image if the transfer amount per unit time cannot be maintained at a predetermined value or more in data transfer via the PCIe 8 and the PCIe 9, particularly in data transfer to the memory 7 via the PCIe 9. For a request source (such as a DMAC for input / output of video output data) that needs to guarantee the worst value of the transfer rate, the guaranteed value can be set high. That is, the video output control units 22a, 22b, 22c, and 22d are used as the required guarantee access means so that the guaranteed value can be set high.

  The data flow of the image processing apparatus 1 according to the present embodiment is shown in FIG. 1. The scanner data path is indicated by Sd, the plotter data path is indicated by Od, and the printer data path is indicated by Pd. ing.

  The scan data path Sd is such that the image data of the document read by the scanner 2 is subjected to image processing by the engine ASIC 4, passed to the controller ASIC 5, and stored in the memory 7 under the control of the CPU 6 by the controller ASIC 5. The data path is issued to the memory 7 and stored in the memory 7.

  The plotter data path Od is a data path in which image data stored in the memory 7 is sent to the plotter 3 for printing. That is, this is a data path for reading out image data from the memory 7 under the control of the CPU 6 and passing the image data to the plotter 3 via the engine ASIC 4 in response to a request from the controller ASIC 5.

  In the printer data path Pd, creation of printer data is performed in parallel with the copying operation. In the printer data path Pd, a printer output request content is input to the controller ASIC 5 as various printer language data from a personal computer (not shown) via a network or the like. The printer language data is stored in the memory 7 by issuing a request to the CPU 6 so as to be stored in the memory 7 under the management of the CPU 6. Thereafter, the CPU 6 interprets the contents of the printer language data and creates image data corresponding to the contents on the memory 7. In creating the image data, the image data is created by using the compressor / decompressors 22a to 22d and 26a to 26d of the controller ASIC 5 by a method that reduces the required memory capacity. The data finally created in the memory 7 is the compressed data. Thereafter, the plotter 3 is released from the copying operation, and when the plotter is free, the printer data is output from the memory 7 to the plotter 3. The output data flow in this printer data is the same as the plotter data path Od. Since the printer data is compressed and stored in the memory 7, decompression processing is added by the decompressors 224a, 224b, 224c, and 224d of the controller ASIC 5 in the printer data path Od.

  In the data flow, the arbiter 25 operates in response to signal states from the respective units as shown in FIG. Note that the arbiter 25 is configured so that the video output control units 22a, 22b, 22c, and 22d have a higher priority than the image processing units 27a, 27b, 27c, and 27d and the compression units 26a, 26b, 26c, and 26d (video output control units 22a, 22d, 22b, 22c, 22d> image processing units 27a, 27b, 27c, 27d, compression units 26a, 26b, 26c, 26d) are set, and the memory access requests from these are arbitrated by the round robin method.

  In FIG. 3, VOUT_DMACa_EN is an enable signal for the video output control unit 22a, and is enabled in a high state. IMPa_EN is an enable signal for the image processing unit 27a, and is in an enable state in a high state.

  VOUT_DMACb_EN and IMPb_EN are enable signals for the video output control unit 22b and the image processing unit 27b, respectively.

  VOUT_REQa is a memory access request signal from the video output control unit 22a to the arbiter 25, and is in a request state at High. VOUT_ACKa is a permission signal from the arbiter 25 with respect to the memory access request signal VOUT_REQa, and “High” indicates permission.

  IMP_REQa is a memory access request signal from the image processing unit 27a to the arbiter 25 and is in a request state at High. IMP_ACKa is a permission signal from the arbiter 25 with respect to the memory access request signal IMP_REQa, and “High” indicates permission.

  In FIG. 3, the memory access request signal VOUT_REQa becomes High at timing t1, and the memory access request is issued from the video output control unit 22a to the arbiter 25.

  As shown at timing t2, the arbiter 25 gives permission to the memory access request signal VOUT_REQa by setting the permission signal VOUT_ACKa to High.

  On the other hand, at timing t3, the image processing unit 27a requests memory access by setting the memory access request signal IMP_REQa to High, but as shown at timing t4, the permission signal IMP_ACKa remains low, and the arbiter 25 Do not give permission. This is because a video-related request becomes an abnormal image if a certain transfer rate cannot be secured, and therefore a high priority is given, and the memory access request signal VOUT_REQa from the video output control unit 22a is continuous. This is because a memory access request from the image processing unit 27a having a lower priority than the video output control unit 22a is not permitted.

  At timing t5 in FIG. 3, in conjunction with the enable signal VOUT_DMACb_EN for the video output control unit 22b becoming High, the video output control unit 22b sets the enable signal VOUT_REQb for the video output control unit 22b to High, and a memory access request Issue. On the other hand, the arbiter 25 sets the permission signal VOUT_ACKb to High as at the timing t6, so that the memory access request from the video output control unit 22b is also arbitrated in round robin and given permission.

  Further, the reason why the memory access request signal VOUT_REQa from the video output control unit 22a is Low at timing t7 in FIG. 3 is that data for a predetermined line is read from the memory 7 and accumulated in the line buffer 227a. This is because the issue of the memory access request signal VOUT_REQa is stopped.

  In the above description, when the other video output control units 22b, 22c, and 22d read out data for a predetermined line from the memory 7 and accumulate in the line buffers 227b, 227c, and 227d, the issuance of the memory access request is stopped. Then, the memory access request signals VOUT_REQb, VOUT_REQc, and VOUT_REQd are set to low.

  Since the arbiter 25 transfers the plotter data to the PCIe 8 on the engine side in parallel with the data transfer process, the arbiter 25 starts memory access to the next line. That is, the memory access request signal VOUT_REQa from the video output control unit 22a becomes High again at the timing t8 in FIG.

  At timing t9 in FIG. 3, since there are no memory access request signals VOUT_REQa, VOUT_REQb, VOUT_REQc, VOUT_REQd from all the video output control units 22a, 22b, 22c, 22d, the video output control units 22a, 22b, 22c, A memory access request is permitted for a memory access request signal IMP_REQa from the image processing unit 27a having a lower priority than 22d.

  As described above, the image processing apparatus 1 according to the present embodiment is connected to the PCIe end controller 28 and the PCIe route controller 21 that are interfaces in a high-speed serial bus in which request commands such as PCIe 8 and 9 and responses to the request commands are separated. For the arbiter 25 that arbitrates the access request, the video output control units 22a, 22b, 22c, and 22d having a high priority are concentrated on a predetermined line unit of the image data and the memory access request signals VOUT_REQa, VOUT_REQb, VOUT_REQc, and VOUT_REQd. Has been issued.

  Therefore, a request gap from a request source having a low priority is permitted with a gap between requests from a request source having high priority (access request means), and a decrease in transfer rate due to waiting for execution of the access request is prevented. it can. As a result, a request source that needs to guarantee the worst value of the transfer rate that results in an abnormal image if the transfer amount per unit time cannot be maintained at a predetermined value or more (eg, DMAC for input / output of video output data, ie, video output) The guaranteed value can be set high for the control units 22a, 22b, 22c, 22d).

  Note that such processing may be performed only for a period during which a request source that needs to guarantee the worst transfer rate is being transferred.

  In this way, it is possible to appropriately transfer the request source that needs to guarantee the worst value of the transfer rate, which makes it difficult to maintain the permission for the target request source at a constant rate, and to transfer the required request source. When is completed, data transfer can be appropriately performed even for a request source having a low priority.

  In addition, there is a possibility that a situation occurs in which a request other than the request source that needs to guarantee the worst value of the transfer rate is not permitted to access the memory for a long time.

  Therefore, the controller ASIC 5 includes a control register 31 and a timer 32 in the internal ASIC controller 29. When the timer 32 measures the non-permission time set in the control register 31, a request source having a low priority, for example, an image The arbiter 25 is preferentially granted memory access requests from the processing units 27a, 27b, 27c, and 27d.

  Therefore, a memory access request from a request source having a low priority can be permitted at a constant rate.

  Further, in this case, the ASIC controller 29 sets a period in which the arbiter 25 gives priority to a request source having a low priority, and after that period, a specific request source having a low priority is set. On the other hand, the arbiter 25 may perform control so as to give permission to a request with priority, and give permission to a request source having a low priority at a constant rate.

  In this way, it is possible to solve the problem that the request is not permitted no matter what time the request source with a low priority passes, and appropriate data transfer can be performed.

  Further, the image processing apparatus 1 of the present embodiment is configured such that the arbiter 25 can handle the same request source as a plurality of target request sources, and the required request sources (video output control units 22a, 22b, 22c). , 22d) may be permitted by the arbiter 25 at a multiple of the frequency. In this case, the register is set in the control register 31 so that it is handled as a plurality of target request sources on condition that the ratio of the request transfer rates of the request sources that need to guarantee the worst value of the transfer rate is 2 or more.

  In this way, the frequency permitted by the arbiter 25 can be adjusted, and the transfer rate for the request source can be set in accordance with the characteristics of the target device. Also, since the ratio of the required transfer rate is 2 or more, transfer is performed in a balanced manner even for objects with different data amounts or required transfer rates for one line, such as scanner data and plotter data. And the guaranteed rate can be kept high.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  The present invention can be used for a data transfer apparatus, an image forming apparatus, a data transfer control method, a data transfer control program, and a recording medium that include an arbiter that controls access according to priority.

DESCRIPTION OF SYMBOLS 1 Image processing apparatus 2 Scanner 3 Plotter 4 Engine ASIC
5 Controller ASIC (CTL ASIC)
6 CPU
7 Memory 8, 9 PCIe
10 SSTL
21 PCIe root controller (root)
22a, 22b, 22c, 22d Video output control unit 221a, 221b, 221c, 221d Video output controller 222a, 222b, 222c, 222d Stamp DMAC (STMP DMAC)
223a, 223b, 223c, 223d Video output DMAC
224a, 224b, 224c, 224d decompressor 225a, 225b, 225c, 225d Code DMAC
226a, 226b, 226c, 226d Image DMAC
227a, 227b, 227c, 227d Line buffer (Line Buff)
23 Line Buff
24 Video input controller (VIcnt)
25 Arbiter 26a, 26b, 26c, 26d Compression unit 261a, 261b, 261c, 261d Compressor (ENC)
262a, 262b, 262c, 262d General purpose DMAC (GDMAC)
263a, 263b, 263c, 263d General-purpose DMAC (GDMAC)
27a, 27b, 27c, 27d Image processing unit 271a, 271b, 271c, 271d Image processing circuit 272a, 272b, 272c, 272d General-purpose DMAC (GDMAC)
273a, 273b, 273c, 273d General-purpose DMAC (GDMAC)
28 PCIe Endpoint Controller (End)
29 ASIC controller 31 Control register 32 Timer

JP 2007-249816 A

Claims (9)

A plurality of access request means for performing transfer access requests for image data to the high-speed serial bus and given priority.
An arbiter for arbitrating an access request from the access request means;
Of the access request means, a high priority is given to the required access request means that needs to guarantee the worst value of the transfer rate, and the access request is concentrated in units of data from the required access request means. Access control means for issuing
A data transfer device comprising: The data transfer device
A waiting time setting means for setting a waiting time until permission is granted for an access request;
Timing means for timing the waiting time;
With
The access control means includes
When the time measuring means measures the time during which access requests from specific access request means having a lower priority than the required access request means are not allowed, and the time reaches the waiting time. A data transfer apparatus that preferentially grants access to the specific access request means. The data transfer device
A period setting means for setting a period in which the arbiter preferentially grants access permission to a specific access request means having a lower priority than the guaranteed access request means;
The access control means includes
3. The data transfer apparatus according to claim 1, wherein an access permission is given to the specific access requesting unit preferentially every time the cycle set by the cycle setting unit elapses.   The arbiter can handle one access request means as a plurality of access request means, and grants an access permission to the access request from the guaranty access request means at a frequency multiple of the multiple. The data transfer device according to claim 1, wherein the data transfer device is a data transfer device.   The arbiter treats the required access request means as a plurality of access request means when the ratio of the requested transfer rate of the required access request means is 2 or more, and requests access from the required access request means. 5. The data transfer apparatus according to claim 4, wherein an access permission is given at a frequency that is a multiple of the frequency. In an image forming apparatus that transfers image data by a data transfer unit and forms an image based on the image data.
An image forming apparatus, wherein the data transfer device according to claim 1 is mounted as the data transfer unit. A plurality of access request processing steps for making a transfer access request for image data to the high-speed serial bus and giving priority.
An arbitration processing step for arbitrating an access request from the access request processing step;
Among the access request processing steps, a high priority is given to the required access request processing step requiring the worst value of the transfer rate, and concentrated from the required access request processing step in units of data lines. An access control processing step for causing the server to issue an access request;
A data transfer method characterized by comprising: On the computer,
A plurality of access request processings for performing transfer access requests for image data to the high-speed serial bus and having priority given thereto;
An arbitration process for arbitrating an access request from the access request process;
Of the access request processing, a high priority is given to the required access request processing that needs to guarantee the worst value of the transfer rate, and the access request is concentrated on the data line basis from the required access request processing. Access control processing to issue
A data transfer program characterized in that   A computer-readable recording medium on which the data transfer program according to claim 8 is recorded.

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