JP2012019641A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which improves malfunction tolerance with an influence of dv/dt phenomena, noises, and others without increasing time delay when controlling an upper arm side switching element in response to input signals.SOLUTION: The semiconductor device solves the above-mentioned problem by continuously transmitting reset signals to an RS flip flop during an off-state period of an upper arm side switching element to prevent wrong turning-on of the upper arm side switching element against dv/dt phenomena, noises, and others during the off-state period of the upper arm side switching element without increasing a time constant of a filter circuit.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for connecting two switching elements in series between main power supply terminals and driving and controlling a high-voltage side switching element.

  FIG. 1 shows a configuration of a conventional semiconductor device for driving a motor.

  In the figure, a DC power supply 1 is a high-voltage power supply voltage Vs of about 141 V to about 600 V, for example, and is used as a high-voltage power supply voltage for driving an inverter of a motor. The DC power supply 2 is, for example, about 15 V, and is used as the drive circuit power supply voltage Vcc.

  S1 and S2 are a pair of switching elements connected in series, and an IGBT, a MOS transistor, a bipolar transistor, or the like is used. D1 and D2 are free-wheeling diodes connected in reverse parallel to the switching elements. The motor 3 is connected to a connection point between the upper arm side switching element and the lower arm side switching element. A half-bridge circuit having a totem pole configuration in which a high voltage side (upper arm side) switching element S1 and a low voltage side (lower arm side) switching element S2 are connected in series is provided between main power supply terminals.

  Usually, in order to drive the motor 3, such a half-bridge circuit is used for three phases. The upper arm and the lower arm are turned on / off in a complementary manner.

  In order to turn on the switching element, it is necessary to drive the gate potential with a voltage larger than the source by the threshold voltage. Since the source of the lower arm side switching element S2 is fixed to the ground potential, the gate can be controlled by the drive circuit power supply voltage Vcc. However, when the upper arm side switching element S1 is turned on, its source potential rises to near the high voltage power supply voltage Vs, so that its gate needs to be driven at a voltage higher than the high voltage power supply voltage Vs.

  FIG. 1 shows a bootstrap drive system, and a bootstrap circuit diode D3 and a bootstrap circuit capacitor C1 are external components for a bootstrap circuit. A bootstrap circuit capacitor C1 provided independently for each phase serves as a floating power supply. As an initial state, it is necessary to turn on the lower arm switching element S2 and to charge the capacitor through a path indicated by a broken line.

  The output of the RS flip-flop 5 is connected to the input of the inverter circuit 4, and the output of the inverter circuit 4 is connected to the gate of the upper arm side switching element S1. The upper arm side switching element S1 is controlled to be turned on / off by the inverter circuit 4 connected to the bootstrap voltage VB having the output voltage VM as a reference potential. The signal that controls the inverter circuit 4 is transmitted by:

  First, a drive signal Vin for controlling on / off of the upper arm is generated by the low voltage side circuit. A pulse signal synchronized with the rising and falling edges of the drive signal Vin is formed by the pulse generation circuit 6 from the drive signal Vin. This pulse is distributed to the upper arm on side and off side, and is input to the gate terminals of the MOS transistors M1 and M2 of the level shift circuit, respectively. A set pulse is input to the level shift circuit MOS transistor M1, and a reset pulse is input to the level shift circuit MOS transistor M2.

  Next, a resistor R2 using the bootstrap voltage VB as a power source is connected to the drain terminal of the level shift circuit MOS transistor M2 responsible for the off-operation of the upper arm. Further, a resistor R1 having a bootstrap voltage VB as a power source is connected to the drain terminal of the level shift circuit MOS transistor M1 responsible for the on-operation of the upper arm. The above is the basic configuration of the level shift circuit.

  FIG. 2 shows a timing chart of the conventional circuit. The level shift circuit MOS transistor M1 is turned on by the set pulse, the set current I1 flows in accordance with the pulse signal, the potential of the drain voltage of the level shift circuit MOS transistor M1 drops, and it is connected to the set side of the RS flip-flop 5 To do. Therefore, the RS flip-flop 5 is set and outputs a Low level.

  Accordingly, the upper arm side switching element S1 is operated by the output of the inverter circuit 4. In addition, when the upper arm side switching element S1 is turned off, the reset pulse is input to the reset side of the RS flip-flop 5 through the other level shift and reset as in the above case. Accordingly, the upper arm side switching element S1 is turned off. The above operation enables high-speed signal transmission.

  Since the upper reference potential input terminal voltage VB in the level shift circuit becomes a high voltage when the upper arm side switching element S1 is turned on, the power consumption becomes a large value when the level shift circuit MOS transistors M1 and M2 are turned on. . In order to avoid this, the pulse widths of the set current I1 and the reset current I2 that are the gate inputs of the level shift circuit MOS transistors M1 and M2 are as small as possible, as shown in the timing chart of FIG. 2, by the edge trigger of the drive signal Vin. The latch circuit is configured to be driven.

  In the bootstrap driving method, the connection point output voltage VM of the upper and lower arm switching elements changes abruptly (dv / dt increase) from the output voltage and the ground potential to the high-voltage power supply voltage Vs. At that time, since parasitic capacitance exists between the drain and source of the MOS transistors M1 and M2 constituting the level shift circuit, current flows due to steep potential fluctuation. With this current, the output of the RS flip-flop 5 is inverted, and the upper arm side switching element S1 is erroneously turned on or off. If the lower arm side switching element S2 is turned on while the upper arm side switching element S1 is erroneously turned on, a through current may flow between the high voltage power source and the ground, and the switching element may be destroyed.

JP 2002-233166 A JP 2003-79131 A JP 2009-89417 A

  In order to prevent malfunction as described above, a filter circuit 7 as shown in FIG. 1 is generally installed between the level shift circuit and the RS flip-flop 5. However, when the time constant of the filter circuit 7 is increased in order to enhance the malfunction tolerance against dv / dt, there is a problem that the controllability is lowered because the delay time increases.

  An object of the present invention is to provide a semiconductor device having a level shift circuit with improved malfunction tolerance due to a dv / dt phenomenon, noise, or the like while suppressing an increase in delay time.

  In order to solve the above-described problem, the level shift circuit of the present invention is configured to always turn on the level shift circuit MOS transistor M2 and continuously send a reset signal to the RS flip-flop while the upper arm side switching element is in the off state. Features.

  According to the present invention, it is possible to prevent the upper arm side switching element from being erroneously turned on due to the dv / dt phenomenon or noise during the off period of the upper arm side switching element without increasing the time constant of the filter circuit.

It is a circuit diagram which shows the structure of the conventional semiconductor device for a motor drive. It is a timing chart figure in the conventional circuit. It is a circuit diagram which shows one Example of the semiconductor device for motor drive of this invention. It is a timing chart figure in the circuit of one example of the present invention.

  Hereinafter, the present invention will be described based on the illustrated embodiments.

  FIG. 3 shows an embodiment of a semiconductor device for driving a motor according to the present invention. The configuration of the present embodiment is substantially the same as the configuration of FIG. 1 described as the conventional example, and here, the description is different from FIG.

  In this embodiment shown in FIG. 3, an inverter circuit 9 is provided in the signal path from the drive signal Vin to the MOS transistor M2 of the level shift circuit, so that the MOS transistor M1 of the level shift circuit is connected to the MOS transistor M1 via the generation circuit 6. The drive signal Vin is sent, and the inverter circuit 9 generates the gate signal of the MOS transistor M2 of the reset side level shift circuit 11 without passing through the pulse generation circuit 6.

  FIG. 4 shows a timing chart of each part in the present embodiment. At the rising timing of the drive signal Vin, the set current I1 flows through the set-side level shift circuit 10 by the operations of the pulse generation circuit 6 and the level shift circuit MOS transistor M1, and the RS flip-flop is passed through the resistor R1 and the filter circuit 7. A set pulse signal is transmitted to 5. By the input of the set pulse, the output QB of the RS flip-flop 5 becomes the low level, and this state is maintained until the reset pulse is input. During this period, the switching element S1 is turned on.

  On the other hand, when the drive signal Vin is at the low level, the reset current I2 flows through the reset-side level shift circuit 11 by the operation of the inverter circuit 9 and the level shift circuit MOS transistor M2, and the RS flip-flop is passed through the resistor R2 and the filter circuit 7. A reset signal is transmitted to group 5. By the input of the reset signal, the output QB of the RS flip-flop 5 becomes Hi level, and the switching element S1 is turned off. While the drive signal Vin is at the low level, the reset current I2 always flows, and the reset signal is continuously input to the RS flip-flop 5.

  In this embodiment, since the reset signal is continuously input to the RS flip-flop 5 while the switching element S1 is off, the RS flip-flop 5 even if an erroneous set signal is transmitted due to dV / dt phenomenon or noise. The QB output QB is not inverted. For this reason, it is not necessary to cut the error signal by the filter circuit 7, and the switching element S1 can be prevented from being erroneously turned on while suppressing the time constant of the filter circuit.

  Further, since the upper arm side switching element S1 and the lower arm side switching element S2 are normally turned on / off in a complementary manner, when the upper arm switching element S1 is off, the lower arm switching element S2 is on, so the output The voltage VM is approximately the ground potential, and the bootstrap voltage VB is approximately 15V. For this reason, the increase in power consumption by always turning on the level shift circuit MOS transistor M2 is slight.

1, 2 DC power supply 3 Motor 4, 8, 9 Inverter circuit 5 RS flip-flop 6 Pulse generation circuit 7 Filter circuit 10 Set side level shift circuit 11 Reset side level shift circuit S1, S2 Switching elements D1, D2 Free-wheeling diode C1 Bootstrap Circuit capacitor D3 Bootstrap circuit diode M1, M2 Level shift circuit MOS transistors R1, R2 Resistance Vs High voltage power supply voltage Vcc Drive circuit power supply voltage Vin Drive signal VB Bootstrap voltage VM Output voltage I1 Set current I2 Reset current

Claims (2)

  A half bridge circuit having a totem pole configuration in which an upper arm side switching element and a lower arm side switching element are connected in series, a control circuit for controlling on / off of the upper arm side switching element, and turning on the upper arm side switching element An input signal having a first state shown and a second state showing that the upper arm side switching element is turned off, a set pulse signal of one shot is generated at the initial stage of the first state, and in the second state, A set / reset signal generator for constantly generating a reset signal, and a level shift unit for level-shifting the set / reset signal to the upper arm side to obtain a level-shifted set / reset signal, the control circuit comprising: Based on the level-shifted set / reset signal, each of the upper arm side switching elements The semiconductor device for outputting a control signal for turning on / off the upper arm switching element.   A semiconductor device for driving a half-bridge circuit having a totem pole configuration in which an upper arm side switching element and a lower arm side switching element are connected in series, the control circuit controlling on / off of the upper arm side switching element; A one-shot set pulse signal is generated at the initial stage of the first state of an input signal having a first state indicating that the arm side switching element is turned on and a second state indicating that the upper arm side switching element is turned off. A set / reset signal generator for constantly generating a reset signal in the second state, and a level shift unit for level-shifting the set / reset signal to the upper arm side to obtain a level-shifted set / reset signal. And the control circuit, based on the level-shifted set / reset signal, respectively, The semiconductor device for outputting a control signal for turning on / off the arm switching element on said arm switching element.

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