JP2012015401A - Method of manufacturing electronic device and electronic device - Google Patents

Method of manufacturing electronic device and electronic device Download PDF

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Publication number
JP2012015401A
JP2012015401A JP2010151975A JP2010151975A JP2012015401A JP 2012015401 A JP2012015401 A JP 2012015401A JP 2010151975 A JP2010151975 A JP 2010151975A JP 2010151975 A JP2010151975 A JP 2010151975A JP 2012015401 A JP2012015401 A JP 2012015401A
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Prior art keywords
substrate
electrode
position recognition
wiring
recognition mark
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Japanese (ja)
Inventor
Hiroshi Ishikawa
寛 石川
Hiroomi Shimizu
洋臣 清水
Ryusuke Suzuki
隆介 鈴木
Kazuhiro Minagawa
和弘 皆川
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Honda Motor Co Ltd
Koa Corp
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Honda Motor Co Ltd
Koa Corp
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Priority to JP2010151975A priority Critical patent/JP2012015401A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

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  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide method of manufacturing electronic device, capable of preventing a foreign material from deteriorating electronic device performance and accurately recognizing a position recognition mark.SOLUTION: The method of manufacturing the electronic device comprises: a wiring forming step of forming a wiring 5 on a surface of a substrate 2; a protective film forming step of forming a protective film 6 except a portion which forms an electrode 3 and a position recognition mark 4 on the surface of the substrate 2; an electrode and mark forming step of forming the electrode 3 on the surface of the substrate 2 and forming the position recognition mark 4 in a position apart from the electrode 3 and the wiring 5; a bonding step of bonding a bonding wire 9 to the electrode 3; and a sealing step of sealing the substrate 2 where the wiring 5, electrode 3, and position recognition mark 4 are formed with a sealing member 10.

Description

本発明は、電子装置の製造方法および電子装置に関する。   The present invention relates to an electronic device manufacturing method and an electronic device.

一般に、ＬＳＩなどの電子装置の製造方法は、電極と配線とを基板に形成する配線形成工程と、電極や配線を形成した基板を保護する保護膜を形成する保護膜形成工程と、ボンディングワイヤーと電極とを接合させるボンディング工程と、基板を封止部材で封止する封止工程とを有することが知られている。   In general, a method for manufacturing an electronic device such as an LSI includes a wiring forming process for forming electrodes and wiring on a substrate, a protective film forming process for forming a protective film for protecting the substrate on which the electrodes and wiring are formed, a bonding wire, It is known to have a bonding step for bonding electrodes and a sealing step for sealing a substrate with a sealing member.

ボンディング工程では、ボンディングワイヤーと基板の表面に形成された電極との接合に関して高い位置合わせ精度が必要となる。そこで、特許文献１では、配線の一部が保護膜から露出され、この露出した部分の形状を位置認識マークとして用いることが提案されている。このような位置認識マークを検出して電極の位置を認識することにより、上記位置合わせが行われる（特許文献１参照）。   In the bonding process, high alignment accuracy is required for the bonding between the bonding wire and the electrode formed on the surface of the substrate. Therefore, Patent Document 1 proposes that a part of the wiring is exposed from the protective film and the shape of the exposed part is used as the position recognition mark. The alignment is performed by detecting such a position recognition mark and recognizing the position of the electrode (see Patent Document 1).

特許第３５４８４６２号公報Japanese Patent No. 3548462

しかし、上記文献の方法では、位置認識マークのために露出した配線部分が剥離して異物となり、この異物によって電子装置が短絡することで、電子装置の性能が低下するおそれがある。また、配線の一部を保護膜から露出させ、この露出した部分を位置認識マークとして用いるため、保護膜との明暗の差が小さくなる場合がある。この場合には、この位置認識マークを正確に認識することができない。   However, in the method described in the above document, the wiring portion exposed for the position recognition mark is peeled off to become a foreign substance, and the electronic apparatus may be short-circuited by the foreign substance, thereby degrading the performance of the electronic apparatus. In addition, since a part of the wiring is exposed from the protective film and this exposed part is used as a position recognition mark, the difference in brightness from the protective film may be reduced. In this case, the position recognition mark cannot be accurately recognized.

そこで、本発明は、異物による電子装置の性能の低下を防止するとともに、位置認識マークの誤認識を防止する電子装置の製造方法および電子装置を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic device manufacturing method and an electronic device that prevent deterioration of the performance of the electronic device due to foreign matter and prevent erroneous recognition of a position recognition mark.

本発明に係る電子装置の製造方法は、配線を基板の表面に形成する配線形成工程と、前記基板の表面上で電極と位置認識マークを形成する部分を除いて保護膜を形成する保護膜形成工程と、前記基板の表面上で前記電極を形成すると共に、前記位置認識マークを前記電極及び配線から離間した位置に形成する電極及びマーク形成工程と、前記電極にボンディングワイヤーを接合させるボンディング工程と、前記配線、電極及び位置認識マークを形成した基板を封止部材で封止する封止工程とを備えることを特徴とする。   The method for manufacturing an electronic device according to the present invention includes: a wiring forming step for forming wiring on a surface of a substrate; and a protective film formation for forming a protective film except a portion for forming an electrode and a position recognition mark on the surface of the substrate. A step of forming the electrode on the surface of the substrate and forming the position recognition mark at a position separated from the electrode and the wiring; and a bonding step of bonding a bonding wire to the electrode; And a sealing step of sealing the substrate on which the wiring, the electrode and the position recognition mark are formed with a sealing member.

又、本発明に係る電子装置は、電極と配線と前記電極の位置を認識するための位置認識マークとが表面に形成された基板と、前記電極と前記位置認識マークを除いた前記基板の表面上に形成された保護膜と、前記電極に接合されたボンディングワイヤーと、前記基板の表面上の前記電極及び配線から離間した位置で前記保護膜から露出して形成された位置認識マークとを備え、前記基板を封止部材で封止したものである。   According to another aspect of the present invention, there is provided an electronic device comprising: a substrate having electrodes, wiring, and a position recognition mark for recognizing the position of the electrode formed on the surface; and the surface of the substrate excluding the electrode and the position recognition mark. A protective film formed thereon, a bonding wire bonded to the electrode, and a position recognition mark formed exposed from the protective film at a position separated from the electrode and wiring on the surface of the substrate. The substrate is sealed with a sealing member.

これらの発明によれば、位置認識マークは、配線の一部ではなく、配線から離間した位置で保護膜から露出した部分に形成されているので、配線の一部が剥離して異物となることがなく、電子装置の性能を低下させない。また、露出した位置認識マークと保護膜との間で明暗の差が小さくなることもなく、位置認識マークを正確に認識することができる。   According to these inventions, since the position recognition mark is formed not on a part of the wiring but on a part exposed from the protective film at a position apart from the wiring, a part of the wiring peels off and becomes a foreign substance. And does not degrade the performance of the electronic device. In addition, the position recognition mark can be accurately recognized without reducing the difference in brightness between the exposed position recognition mark and the protective film.

本実施形態の電子装置の電子回路板であって、基板の表面に電極と位置認識マークと配線とを形成した状態の平面図。It is an electronic circuit board of the electronic device of this embodiment, Comprising: The top view of the state in which the electrode, the position recognition mark, and the wiring were formed in the surface of a board | substrate. 図１のＩＩ−ＩＩ線断面図。II-II sectional view taken on the line of FIG. 本実施形態の電子装置であって、封止部材による封止後の状態の平面図。It is an electronic device of this embodiment, Comprising: The top view of the state after sealing by the sealing member. 図３のＩＶ−ＩＶ線断面図。IV-IV sectional view taken on the line of FIG. 本実施形態の電子装置の製造方法の製造工程を示すフローチャート。6 is a flowchart showing a manufacturing process of the method for manufacturing the electronic device according to the embodiment.

本発明の一実施形態を図面に基づいて説明する。   An embodiment of the present invention will be described with reference to the drawings.

図１、図２では、本実施形態の電子装置を構成する電子回路板１は、基板２と、電極３と、位置認識マーク４と、配線５と、保護膜６と、位置認識部７とを備える。   1 and 2, an electronic circuit board 1 constituting the electronic device of the present embodiment includes a substrate 2, an electrode 3, a position recognition mark 4, a wiring 5, a protective film 6, and a position recognition unit 7. Is provided.

基板２は、矩形の板からなり、例えばセラミック等で構成されている。また、電極３は矩形に形成され、基板２の表面の対角となる位置に２つ設けられている。電極３は金属で構成されている。また、配線５は、基板２の内部及び表面に形成されており、金属で構成されている。   The board | substrate 2 consists of a rectangular board, for example, is comprised by the ceramic etc. The electrodes 3 are formed in a rectangular shape, and two electrodes 3 are provided at diagonal positions on the surface of the substrate 2. The electrode 3 is made of metal. Moreover, the wiring 5 is formed in the inside and surface of the board | substrate 2, and is comprised with the metal.

位置認識マーク４は円形に形成されており、金属で構成されている。位置認識マーク４は基板２の表面の対角となる位置に２つ設けられ、電極３が設けられた角部と反対側の角部に設けられる。位置認識マーク４は、電極３及び配線５から離間して形成されている。なお、位置認識マーク４の形状は、円形以外のものであってもよく、例えば、Ｌ字形や十字形に形成されたものであってもよい。   The position recognition mark 4 is formed in a circular shape and is made of metal. Two position recognition marks 4 are provided at diagonal positions on the surface of the substrate 2, and are provided at a corner opposite to the corner where the electrode 3 is provided. The position recognition mark 4 is formed apart from the electrode 3 and the wiring 5. Note that the position recognition mark 4 may have a shape other than a circle, for example, an L shape or a cross shape.

保護膜６は、例えば透明の合成樹脂被膜であり、基板２の表面とこの基板２上に形成された配線５とを覆うように形成している。また、電極３、位置認識マーク４及び後述する位置認識部７は保護膜６により覆われずに露出している。   The protective film 6 is, for example, a transparent synthetic resin film, and is formed so as to cover the surface of the substrate 2 and the wiring 5 formed on the substrate 2. Further, the electrode 3, the position recognition mark 4, and the position recognition unit 7 described later are exposed without being covered by the protective film 6.

位置認識部７は、位置認識マーク４と、位置認識マーク４の周囲の基板露出部８とで構成されている。なお、位置認識部７における基板露出部８の大きさはゼロであってもよい。このときは、保護膜６は位置認識マーク４に沿って形成される。   The position recognition unit 7 includes a position recognition mark 4 and a substrate exposure part 8 around the position recognition mark 4. Note that the size of the substrate exposed portion 8 in the position recognition unit 7 may be zero. At this time, the protective film 6 is formed along the position recognition mark 4.

図３、図４は、図１、図２に示す電子回路板１の電極３にボンディングワイヤー９が接合されて、封止部材１０により封止がされた状態を示している。   3 and 4 show a state in which the bonding wire 9 is bonded to the electrode 3 of the electronic circuit board 1 shown in FIGS. 1 and 2 and is sealed by the sealing member 10.

ボンディングワイヤー９は金属で構成されており、その一端部９ａが電極３と接合されると共に他端部９ｂがリード１１と接合されている。そのため、電極３とリード１１とは電気的に接続されている。   The bonding wire 9 is made of metal, and has one end 9 a bonded to the electrode 3 and the other end 9 b bonded to the lead 11. Therefore, the electrode 3 and the lead 11 are electrically connected.

基板２と保護膜６と位置認識マーク４とボンディングワイヤー９とは、封止部材１０に密着した状態で封止されており、位置認識マーク４は空気と触れないよう構成されている。封止された電子回路板１は、凹型に形成されたパッケージ１２の凹部に設けられる。封止部材１０には、例えばシリコン系絶縁樹脂やエポキシ樹脂などが用いられる。そして、電子装置１３は、この電子回路板１とボンディングワイヤー９と封止部材１０とリード１１とパッケージ１２とによって構成される。   The substrate 2, the protective film 6, the position recognition mark 4, and the bonding wire 9 are sealed while being in close contact with the sealing member 10, and the position recognition mark 4 is configured not to come into contact with air. The sealed electronic circuit board 1 is provided in a concave portion of a package 12 formed in a concave shape. For the sealing member 10, for example, a silicon-based insulating resin or an epoxy resin is used. The electronic device 13 includes the electronic circuit board 1, the bonding wire 9, the sealing member 10, the lead 11, and the package 12.

図５は、電子装置の製造工程を示すフローチャートである。まず、基板２の表面に薄膜を形成する薄膜形成工程が実行される（ステップＳ１）。ステップＳ１の次には、配線５を光の照射により特定する露光工程が実行される（ステップＳ２）。露光工程では、まず、基板２の表面に形成された薄膜の表面にフォトレジストが塗布される。次に、配線５を描画した図外のフォトマスクを通過した光が図外のフォトレジストを表面に塗布した基板２に照射される。   FIG. 5 is a flowchart showing the manufacturing process of the electronic device. First, a thin film forming process for forming a thin film on the surface of the substrate 2 is executed (step S1). Following step S1, an exposure process for specifying the wiring 5 by light irradiation is performed (step S2). In the exposure step, first, a photoresist is applied to the surface of the thin film formed on the surface of the substrate 2. Next, light that has passed through a photomask (not shown) on which the wiring 5 is drawn is irradiated onto the substrate 2 having a surface of a photoresist (not shown) applied thereto.

光を照射した後に、フォトレジストに現像液を散布することによって、照射されたフォトレジストが現像される。この現像によって、照射されたフォトレジストが溶けて、基板２の表面に形成された薄膜が露わになる。   After irradiating light, the irradiated photoresist is developed by spraying a developing solution on the photoresist. By this development, the irradiated photoresist is melted and the thin film formed on the surface of the substrate 2 is exposed.

その後、配線５を形成するエッチング工程が実行される（ステップＳ３）。このエッチング工程が配線形成工程に相当する。エッチング工程では、露わになった薄膜がエッチングによって除去されることで配線５が形成される。   Thereafter, an etching process for forming the wiring 5 is performed (step S3). This etching process corresponds to a wiring formation process. In the etching process, the exposed thin film is removed by etching, whereby the wiring 5 is formed.

次に、基板２の表面上に保護膜６を形成する保護膜形成工程が実行される（ステップＳ４）。保護膜６は、次の印刷工程で印刷される位置認識マーク４及びその周囲の基板露出部８と、電極３の印刷位置を除いて形成される。保護膜６にはガラスペーストが用いられる。保護膜６は厚膜印刷によって形成されるが、フォトリソグラフィー技術を用いて形成することも可能である。   Next, a protective film forming process for forming the protective film 6 on the surface of the substrate 2 is performed (step S4). The protective film 6 is formed except for the position recognition mark 4 to be printed in the next printing process, the substrate exposed portion 8 around it, and the printing position of the electrode 3. A glass paste is used for the protective film 6. The protective film 6 is formed by thick film printing, but can also be formed by using a photolithography technique.

次に、基板２の表面上に電極３や位置認識マーク４を印刷する印刷工程が実行される（ステップＳ５）。印刷工程では、エッチングによって除去された薄膜の場所であって保護膜６の形成されていない場所に、電極３と位置認識マーク４が印刷される。そのため、位置認識マーク４とその基板露出部８が基板２に露出される。電極３と配線５は連結されているが、位置認識マーク４は電極３、配線５のいずれとも接続されず、離間した所定位置に形成されている。この位置認識マーク４を形成する工程が電極及びマーク形成工程に相当する。また、保護膜６の形成されていない場所に、位置認識マーク４を印刷することで、位置認識マーク４を基板２の表面上に露出させる工程がマーク露出工程に相当する。なお、保護膜６の形成は、厚膜印刷で形成することも可能である。   Next, a printing process for printing the electrodes 3 and the position recognition marks 4 on the surface of the substrate 2 is executed (step S5). In the printing process, the electrode 3 and the position recognition mark 4 are printed at the place where the protective film 6 is not formed but the place where the thin film is removed by etching. Therefore, the position recognition mark 4 and its substrate exposed portion 8 are exposed to the substrate 2. Although the electrode 3 and the wiring 5 are connected, the position recognition mark 4 is not connected to either the electrode 3 or the wiring 5 but is formed at a predetermined position apart. The process of forming the position recognition mark 4 corresponds to an electrode and mark formation process. Further, the step of exposing the position recognition mark 4 on the surface of the substrate 2 by printing the position recognition mark 4 in a place where the protective film 6 is not formed corresponds to the mark exposure step. The protective film 6 can be formed by thick film printing.

次に、電極３にボンディングワイヤー９を接合させるボンディング工程が実行される（ステップＳ６）。ボンディング工程は、上面が開放された方形のパッケージ１２に基板２が挿入された状態で実行される。ボンディング工程では、まず、位置認識マーク４の位置が図外のボンディング装置によって検知される。位置認識マーク４の位置は、位置認識マーク４と位置認識部７とのコントラストで判断される。   Next, a bonding process for bonding the bonding wire 9 to the electrode 3 is performed (step S6). The bonding process is performed in a state where the substrate 2 is inserted into the rectangular package 12 whose upper surface is open. In the bonding process, first, the position of the position recognition mark 4 is detected by a bonding apparatus (not shown). The position of the position recognition mark 4 is determined by the contrast between the position recognition mark 4 and the position recognition unit 7.

その後、電極３とボンディングワイヤー９の一端部９ａとの接合が実行され、その後リード１１とボンディングワイヤー９の他端部９ｂとの接合が実行される。これらの接合により、電極３とリード１１とがボンディングワイヤー９を介して電気的に接続される。   Thereafter, the bonding between the electrode 3 and one end portion 9 a of the bonding wire 9 is performed, and then the bonding between the lead 11 and the other end portion 9 b of the bonding wire 9 is performed. By these joining, the electrode 3 and the lead 11 are electrically connected via the bonding wire 9.

次に、基板２に封止部材１０を密着させて封止する封止工程が実行される（ステップＳ７）。封止工程では、基板２を挿入したパッケージ１２に封止部材１０が流入される。パッケージ１２に流入された封止部材１０は、基板２や位置認識マーク４やボンディングワイヤー９と密着して固化する。この固化により、基板２の封止が完了して、電子装置１３が製造される。   Next, a sealing step for sealing the sealing member 10 to the substrate 2 is performed (step S7). In the sealing process, the sealing member 10 flows into the package 12 in which the substrate 2 is inserted. The sealing member 10 that has flowed into the package 12 is brought into close contact with the substrate 2, the position recognition mark 4, and the bonding wire 9 to be solidified. By this solidification, the sealing of the substrate 2 is completed, and the electronic device 13 is manufactured.

以上のように、本実施形態の電子装置及び電子装置の製造方法では、位置認識マーク４は、配線５の一部ではなく、配線５から離間した位置で保護膜６から露出した部分に形成されているので、配線５の一部が剥離して異物となることがなく、電子装置１３の性能を低下させない。また、露出した位置認識マーク４と保護膜６との間で明暗の差が小さくなることもなく、位置認識マーク４を正確に認識することができる。   As described above, in the electronic device and the method for manufacturing the electronic device according to the present embodiment, the position recognition mark 4 is not formed in a part of the wiring 5 but in a portion exposed from the protective film 6 at a position separated from the wiring 5. Therefore, a part of the wiring 5 is not peeled off and becomes a foreign substance, and the performance of the electronic device 13 is not deteriorated. Further, the position recognition mark 4 can be accurately recognized without reducing the difference in brightness between the exposed position recognition mark 4 and the protective film 6.

２…基板、３…電極、４…位置認識マーク、５…配線、６…保護膜、９…ボンディングワイヤー、１０…封止部材、１３…電子装置。 DESCRIPTION OF SYMBOLS 2 ... Board | substrate, 3 ... Electrode, 4 ... Position recognition mark, 5 ... Wiring, 6 ... Protective film, 9 ... Bonding wire, 10 ... Sealing member, 13 ... Electronic device.

Claims (2)

配線を基板の表面に形成する配線形成工程と、
前記基板の表面上で電極と位置認識マークを形成する部分を除いて保護膜を形成する保護膜形成工程と、
前記基板の表面上で前記電極を形成すると共に、前記位置認識マークを前記電極及び配線から離間した位置に形成する電極及びマーク形成工程と、
前記電極にボンディングワイヤーを接合させるボンディング工程と、
前記配線、電極及び位置認識マークを形成した基板を封止部材で封止する封止工程とを備えることを特徴とする電子装置の製造方法。 A wiring forming process for forming wiring on the surface of the substrate;
A protective film forming step of forming a protective film excluding a portion for forming an electrode and a position recognition mark on the surface of the substrate;
Forming the electrode on the surface of the substrate and forming the position recognition mark at a position separated from the electrode and the wiring; and
A bonding step of bonding a bonding wire to the electrode;
And a sealing step of sealing the substrate on which the wiring, the electrode, and the position recognition mark are formed with a sealing member. 電極と配線と前記電極の位置を認識するための位置認識マークとが表面に形成された基板と、
前記電極と前記位置認識マークを除いた前記基板の表面上に形成された保護膜と、
前記電極に接合されたボンディングワイヤーと、
前記基板の表面上の前記電極及び配線から離間した位置で前記保護膜から露出して形成された位置認識マークとを備え、
前記基板を封止部材で封止した電子装置。 A substrate having electrodes, wiring, and position recognition marks for recognizing the position of the electrodes formed on the surface;
A protective film formed on the surface of the substrate excluding the electrode and the position recognition mark;
A bonding wire bonded to the electrode;
A position recognition mark formed by being exposed from the protective film at a position separated from the electrode and wiring on the surface of the substrate,
An electronic device in which the substrate is sealed with a sealing member.
JP2010151975A 2010-07-02 2010-07-02 Method of manufacturing electronic device and electronic device Pending JP2012015401A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS648733A (en) * 1987-06-30 1989-01-12 Mitsubishi Electric Corp Portable radio communication equipment
JPH03132048A (en) * 1989-10-18 1991-06-05 Matsushita Electron Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS648733A (en) * 1987-06-30 1989-01-12 Mitsubishi Electric Corp Portable radio communication equipment
JPH03132048A (en) * 1989-10-18 1991-06-05 Matsushita Electron Corp Semiconductor device

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