JP2012015198A - Wiring board and manufacturing method of the same - Google Patents

Wiring board and manufacturing method of the same Download PDF

Info

Publication number
JP2012015198A
JP2012015198A JP2010148041A JP2010148041A JP2012015198A JP 2012015198 A JP2012015198 A JP 2012015198A JP 2010148041 A JP2010148041 A JP 2010148041A JP 2010148041 A JP2010148041 A JP 2010148041A JP 2012015198 A JP2012015198 A JP 2012015198A
Authority
JP
Japan
Prior art keywords
solder
semiconductor element
wiring board
element connection
connection pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010148041A
Other languages
Japanese (ja)
Inventor
Keizo Sakurai
敬三 櫻井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera SLC Technologies Corp
Original Assignee
Kyocera SLC Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera SLC Technologies Corp filed Critical Kyocera SLC Technologies Corp
Priority to JP2010148041A priority Critical patent/JP2012015198A/en
Publication of JP2012015198A publication Critical patent/JP2012015198A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board on which semiconductor elements are mounted and a manufacturing method of the same which realize fine pitch in semiconductor connection pads by forming solder bumps on top faces of strip-like semiconductor element connection pads disposed on a top face of an insulation substrate without widening a part of each strip-like semiconductor element connection pad.SOLUTION: A wiring board 10 comprises strip-like semiconductor element pads 4 on a top face of an insulation substrate 1, and solder bumps 4 formed on the semiconductor element connection pads 4 by melting and solidification of solder. On each top face of the semiconductor element connection pads 4, a concavity 4a is formed at a position where a solder bump 5 is to be formed, and a solder bump 5 is formed by solder solidified centering around the concavity 4a.

Description

本発明は、配線基板およびその製造方法に関し、より詳細には例えば半導体集積回路素子等の半導体素子をフリップチップ接続により搭載するのに好適な配線基板およびその製造方法に関する。   The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board suitable for mounting a semiconductor element such as a semiconductor integrated circuit element by flip chip connection and a manufacturing method thereof.

従来から半導体集積回路素子として、多数の電極端子をその一方の主面の外周に沿って配設した、いわゆるペリフェラル型の半導体集積回路素子がある。このようなペリフェラル型の半導体集積回路素子を配線基板に搭載する方法として、フリップチップ接続により接続する方法がある。フリップチップ接続とは、配線基板に設けた配線導体の一部を半導体集積回路素子の電極端子に接続される半導体素子接続パッドとして半導体集積回路素子の電極端子の配置に対応した並びに露出させ、この半導体素子接続パッドと前記半導体集積回路素子の電極端子とを対向させ、これらを例えば半田バンプを介して電気的に接続する方法である。   2. Description of the Related Art Conventionally, as a semiconductor integrated circuit element, there is a so-called peripheral type semiconductor integrated circuit element in which a large number of electrode terminals are arranged along the outer periphery of one main surface. As a method of mounting such a peripheral type semiconductor integrated circuit element on a wiring board, there is a method of connecting by flip chip connection. In flip chip connection, a part of the wiring conductor provided on the wiring board is exposed as a semiconductor element connection pad connected to the electrode terminal of the semiconductor integrated circuit element, corresponding to the arrangement of the electrode terminal of the semiconductor integrated circuit element. In this method, the semiconductor element connection pad and the electrode terminal of the semiconductor integrated circuit element are opposed to each other, and these are electrically connected through, for example, solder bumps.

図９は、ペリフェラル型の半導体集積回路素子Ｓと、この半導体集積回路素子Ｓをフリップチップ接続により搭載する従来の配線基板２０を示す概略断面図である。また図１０は、図９に示す配線基板２０の半田バンプ１５を除く上面図である。   FIG. 9 is a schematic cross-sectional view showing a peripheral type semiconductor integrated circuit element S and a conventional wiring board 20 on which the semiconductor integrated circuit element S is mounted by flip-chip connection. FIG. 10 is a top view of the wiring board 20 shown in FIG. 9 excluding the solder bumps 15.

図９および図１０に示すように、従来の配線基板２０は、絶縁基板１１の上面に多数の帯状の配線導体１２を有している。さらに絶縁基板１１の上面には、帯状の配線導体１２の一部を半導体集積回路素子Ｓの電極端子Ｔの配置に対応して細い短冊状に多数並んで露出させる開口部１３ａを有するソルダーレジスト層１３が被着されている。帯状の配線導体１２においてソルダーレジスト層１３から露出する細い短冊状の部分は、半導体集積回路素子Ｓの電極端子Ｔに電気的に接続される半導体素子接続パッド１４を形成している。さらに、各半導体素子接続パッド１４上には、半田バンプ１５が溶着されている。そして、半導体集積回路素子Ｓの電極端子Ｔと半導体素子接続パッド１４とを対向させ、これらを半田バンプ１５を介して接続することにより半導体集積回路素子Ｓが配線基板２０上にフリップチップ接続される。   As shown in FIGS. 9 and 10, the conventional wiring board 20 has a number of strip-shaped wiring conductors 12 on the upper surface of the insulating substrate 11. Furthermore, on the upper surface of the insulating substrate 11, a solder resist layer having openings 13a that expose a large number of strip-like wiring conductors 12 arranged in a thin strip shape corresponding to the arrangement of the electrode terminals T of the semiconductor integrated circuit element S. 13 is attached. The strip-shaped portion exposed from the solder resist layer 13 in the strip-shaped wiring conductor 12 forms a semiconductor element connection pad 14 that is electrically connected to the electrode terminal T of the semiconductor integrated circuit element S. Further, solder bumps 15 are welded on each semiconductor element connection pad 14. Then, the electrode terminal T of the semiconductor integrated circuit element S and the semiconductor element connection pad 14 are opposed to each other and are connected via the solder bump 15 so that the semiconductor integrated circuit element S is flip-chip connected to the wiring substrate 20. .

ところで、このようなフリップチップ接続に用いられる配線基板２０おいては、半導体集積回路素子Ｓの電極端子Ｔと半導体素子接続パッド１４との半田バンプ１５を介した接続を容易なものとするために、通常、半導体素子接続パッド１４上の所定位置に半田バンプ１５を予め溶着させておく。半導体素子接続パッド１４上に半田バンプ１５を溶着するには、半導体素子接続パッド１４の全面に半田ペーストを塗布した後、その半田ペースト中の半田を加熱溶融させて所定位置に凝集させる方法が採用されている。このとき、半導体素子接続パッド１４における半田バンプ１５が形成される位置の幅を他の部分よりも広く形成しておく。すると、半導体素子接続パッド１４上に塗布した半田ペースト中の半田を加熱溶融させる際に、溶融した半田がその表面張力の影響により半導体素子接続パッド１４の幅の広い部分に集まってきて、半導体素子接続パッド１４の所定の位置に半田バンプ１５を溶着することができる。   By the way, in the wiring board 20 used for such flip-chip connection, in order to facilitate the connection between the electrode terminal T of the semiconductor integrated circuit element S and the semiconductor element connection pad 14 via the solder bump 15. Usually, solder bumps 15 are previously welded to predetermined positions on the semiconductor element connection pads 14. In order to weld the solder bump 15 onto the semiconductor element connection pad 14, a method is adopted in which a solder paste is applied to the entire surface of the semiconductor element connection pad 14, and then the solder in the solder paste is heated and melted to be aggregated at a predetermined position. Has been. At this time, the width of the position where the solder bump 15 is formed in the semiconductor element connection pad 14 is formed wider than the other portions. Then, when the solder in the solder paste applied on the semiconductor element connection pad 14 is heated and melted, the melted solder gathers in a wide portion of the semiconductor element connection pad 14 due to the influence of the surface tension, and the semiconductor element Solder bumps 15 can be welded to predetermined positions of the connection pads 14.

しかしながら、この従来の配線基板によると、半導体素子接続パッド１４における所定の位置に半田バンプ１５を形成するために、半導体素子接続パッド１４の幅を部分的に広げている。その結果、半導体素子接続パッド１４のピッチがその分広くなり、半導体素子接続パッド１４のファインピッチ化が困難であるという問題がある。   However, according to this conventional wiring substrate, in order to form the solder bump 15 at a predetermined position in the semiconductor element connection pad 14, the width of the semiconductor element connection pad 14 is partially expanded. As a result, there is a problem that the pitch of the semiconductor element connection pads 14 is increased accordingly, and it is difficult to make the semiconductor element connection pads 14 finer.

特開２０００−７７４７１号公報JP 2000-77471 A

本発明の課題は、半導体素子を搭載する配線基板において、絶縁基板の上面に配設された複数の短冊状の半導体素子接続パッドの幅を部分的に広げることなく短冊状の半導体素子接続パッドの上面に半田バンプを形成することにより、半導体素子接続パッドのファインピッチ化を実現することが可能な配線基板およびその製造方法を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring board on which a semiconductor element is mounted. It is an object of the present invention to provide a wiring board capable of realizing fine pitch of semiconductor element connection pads by forming solder bumps on the upper surface and a method for manufacturing the same.

本発明の配線基板は、絶縁基板の上面に短冊状の半導体素子接続パッドを有するとともに半導体素子接続パッド上に半田を溶融および凝集させて半田バンプを形成して成る配線基板であって、半導体素子接続パッドは、半田バンプが形成された位置の上面に凹部が形成されているとともに、凹部を中心に凝集させた半田により半田バンプが形成されていることを特徴とするものである。   A wiring board according to the present invention is a wiring board having a strip-shaped semiconductor element connection pad on the upper surface of an insulating substrate and forming solder bumps by melting and aggregating solder on the semiconductor element connection pad. The connection pad is characterized in that a concave portion is formed on the upper surface of the position where the solder bump is formed, and the solder bump is formed by solder aggregated around the concave portion.

また本発明の配線基板の製造方法は、絶縁基板の上面に形成された短冊状の半導体素子接続パッドに半田を付着させるとともに半田を溶融および凝集させて半田バンプを形成する配線基板の製造方法であって、半導体素子接続パッドの半田バンプが形成される位置の上面に凹部を形成しておくとともに、凹部を中心に半田を凝集させることにより半田バンプを形成することを特徴とするものである。   The wiring board manufacturing method of the present invention is a wiring board manufacturing method in which solder is attached to a strip-shaped semiconductor element connection pad formed on the upper surface of an insulating substrate, and solder is melted and aggregated to form solder bumps. A recess is formed on the upper surface of the semiconductor element connection pad where the solder bump is formed, and the solder bump is formed by aggregating the solder around the recess.

本発明の配線基板によれば、半導体素子接続パッドにおける半田バンプが形成される上面に凹部が形成されているとともに、その凹部を中心に凝集させた半田により半田バンプが形成されていることから、半導体素子接続パッドの幅を部分的に広げることなく、半田バンプが所定の位置に形成されている。したがって、半導体素子接続パッドをファインピッチで配置することができる。   According to the wiring board of the present invention, the recess is formed on the upper surface of the semiconductor element connection pad where the solder bump is formed, and the solder bump is formed by the solder aggregated around the recess. Solder bumps are formed at predetermined positions without partially increasing the width of the semiconductor element connection pads. Therefore, the semiconductor element connection pads can be arranged at a fine pitch.

また、本発明の配線基板の製造方法によれば、半導体素子接続パッドにおける半田バンプが形成される上面に凹部を形成するとともに、その凹部を中心に半田を凝集させることにより半田バンプを形成することから、半導体素子接続パッドの幅を部分的に広げることなく、半田バンプを所定の位置に形成できる。したがって、半導体素子接続パッドをファインピッチで配置した配線基板を提供することができる。   Further, according to the method for manufacturing a wiring board of the present invention, the recess is formed on the upper surface of the semiconductor element connection pad where the solder bump is formed, and the solder bump is formed by aggregating the solder around the recess. Thus, the solder bumps can be formed at predetermined positions without partially increasing the width of the semiconductor element connection pads. Therefore, it is possible to provide a wiring board in which semiconductor element connection pads are arranged at a fine pitch.

図１は、本発明の配線基板の実施形態の一例を示す概略断面図である。FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. 図２は、図１に示す配線基板の上面図である。FIG. 2 is a top view of the wiring board shown in FIG. 図３は、本発明の配線基板の製造方法の実施形態の一例を説明するための概略断面図である。FIG. 3 is a schematic cross-sectional view for explaining an example of an embodiment of a method for manufacturing a wiring board according to the present invention. 図４は、本発明の配線基板の製造方法の実施形態の一例を説明するための概略断面図である。FIG. 4 is a schematic cross-sectional view for explaining an example of an embodiment of a method for manufacturing a wiring board according to the present invention. 図５は、本発明の配線基板の製造方法の実施形態の一例を説明するための概略断面図である。FIG. 5 is a schematic cross-sectional view for explaining an example of an embodiment of a method for manufacturing a wiring board according to the present invention. 図６は、本発明の配線基板の製造方法の実施形態の一例を説明するための概略断面図である。FIG. 6 is a schematic cross-sectional view for explaining an example of an embodiment of a method for manufacturing a wiring board according to the present invention. 図７は、本発明の配線基板の製造方法の実施形態の一例を説明するための概略断面図である。FIG. 7 is a schematic cross-sectional view for explaining an example of an embodiment of a method for manufacturing a wiring board according to the present invention. 図８は、本発明の配線基板の実施形態における別の例を示す上面図である。FIG. 8 is a top view showing another example in the embodiment of the wiring board of the present invention. 図９は、従来の配線基板を示す概略断面図である。FIG. 9 is a schematic cross-sectional view showing a conventional wiring board. 図１０は、図９に示す配線基板の上面図である。FIG. 10 is a top view of the wiring board shown in FIG.

以下に本発明にかかる配線基板およびその製造方法について添付の図面を参照して詳細に説明する。   Hereinafter, a wiring board and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

図１は、本発明の配線基板の実施形態の一例を示す概略断面図である。図２は、図１に示す配線基板の半田バンプ５を除いた上面図である。   FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a top view of the wiring board shown in FIG. 1 with the solder bumps 5 removed.

図１および図２に示すように、本例の配線基板１０は、絶縁基板１の上面に多数の帯状の配線導体２を有している。さらに絶縁基板１の上面には、帯状の配線導体２の一部を露出させる開口部３ａを有するソルダーレジスト層３が被着されている。   As shown in FIGS. 1 and 2, the wiring substrate 10 of this example has a number of strip-shaped wiring conductors 2 on the upper surface of the insulating substrate 1. Furthermore, a solder resist layer 3 having an opening 3a for exposing a part of the strip-shaped wiring conductor 2 is deposited on the upper surface of the insulating substrate 1.

絶縁基板１は、例えばエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含む樹脂系の電気絶縁材料から成る。配線導体２は、例えば銅箔や銅めっき層から成る。ソルダーレジスト層３は、エポキシ樹脂等の熱硬化性樹脂を含む樹脂系の電気絶縁材料から成る。   The insulating substrate 1 is made of a resin-based electrical insulating material including a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The wiring conductor 2 is made of, for example, a copper foil or a copper plating layer. The solder resist layer 3 is made of a resin-based electrical insulating material containing a thermosetting resin such as an epoxy resin.

配線導体２においてソルダーレジスト層３の開口部３ａから露出した部位は、半導体集積回路素子Ｓの電極端子Ｔに接続される半導体素子接続パッド４を形成している。この半導体素子接続パッド４は、半導体集積回路素子Ｓの電極端子Ｔの配置に対応して細長い短冊状に多数並んで配設されている。半導体素子接続パッド４は、その厚みが例えば５〜３０μｍ程度、その幅が５〜２５０μｍ程度、その長さが１００〜４００μｍ程度である。   A portion of the wiring conductor 2 exposed from the opening 3a of the solder resist layer 3 forms a semiconductor element connection pad 4 connected to the electrode terminal T of the semiconductor integrated circuit element S. A large number of the semiconductor element connection pads 4 are arranged in an elongated strip shape corresponding to the arrangement of the electrode terminals T of the semiconductor integrated circuit element S. The semiconductor element connection pad 4 has a thickness of, for example, about 5 to 30 μm, a width of about 5 to 250 μm, and a length of about 100 to 400 μm.

さらに、各半導体素子接続パッド４における半導体集積回路素子Ｓの電極端子Ｔに対応する位置には半田バンプ５が溶着されている。半田バンプ５は、半導体集積回路素子Ｓの電極端子Ｔと半導体素子接続パット４とを接続するための接続部材であり、例えば錫を含有する低融点の半田を半導体素子接続パッド４上に溶融させるとともに半導体集積回路素子Ｓの電極端子Ｔに対応する位置に凝集させることにより形成されている。   Further, solder bumps 5 are welded at positions corresponding to the electrode terminals T of the semiconductor integrated circuit element S in each semiconductor element connection pad 4. The solder bump 5 is a connection member for connecting the electrode terminal T of the semiconductor integrated circuit element S and the semiconductor element connection pad 4. For example, a low melting point solder containing tin is melted on the semiconductor element connection pad 4. At the same time, they are formed by aggregating them at positions corresponding to the electrode terminals T of the semiconductor integrated circuit element S.

そして、半導体集積回路素子Ｓの電極端子Ｔと半田バンプ５とを当接させ、半田バンプ５を溶融させた後、冷却固化させることにより半導体集積回路素子Ｓが配線基板１０にフリップチップ接続される。   Then, the electrode terminal T of the semiconductor integrated circuit element S and the solder bump 5 are brought into contact with each other, and the solder bump 5 is melted and then cooled and solidified, whereby the semiconductor integrated circuit element S is flip-chip connected to the wiring substrate 10. .

なお、本例の配線基板１０においては、半田バンプ５が形成された位置の半導体素子接続パッド４の上面に凹部４ａが形成されている。そして、この凹部４ａを中心に凝集させた半田により半田バンプ５が形成されており、そのことが重要である。本例の配線基板１０においては、半導体素子接続パッド４の上面に凹部４ａが形成されており、この凹部４ａを中心に凝集させた半田により半田バンプ５が形成されていることから、半導体素子接続パッド４の幅を部分的に広げることなく、半田バンプ５が所定の位置に形成されている。したがって、半導体素子接続パッド４をファインピッチで配置することができる。   In the wiring board 10 of this example, a recess 4a is formed on the upper surface of the semiconductor element connection pad 4 at the position where the solder bump 5 is formed. The solder bumps 5 are formed of solder aggregated around the recess 4a, which is important. In the wiring substrate 10 of this example, the recess 4a is formed on the upper surface of the semiconductor element connection pad 4, and the solder bumps 5 are formed of solder aggregated around the recess 4a. Solder bumps 5 are formed at predetermined positions without partially expanding the width of the pads 4. Therefore, the semiconductor element connection pads 4 can be arranged at a fine pitch.

なお、凹部４ａの幅Ｗが５μｍ未満である場合、凹部４ａを中心とした半田の凝集が良好に起こらずに所定の位置に十分な大きさの半田バンプ５を形成することができなくなる危険性が大きくなり、２５０μｍを超えると、凹部４ａを中心にして形成される半田バンプ５の高さが低いものとなってしまう危険性が大きくなる。したがって、凹部４ａの幅Ｗは、５〜２５０μｍの範囲であることが好ましい。また、凹部４ａの深さＤが１μｍ未満である場合、凹部４ａを中心とした半田の凝集が良好に起こらずに所定の位置に十分な大きさの半田バンプ５を形成することができなくなる危険性が大きくなる。したがって、凹部４ａの深さＤは、１μｍ以上であることが好ましい。ただし、凹部４ａにおける半導体素子接続パット４の厚みが２μｍ未満となると、半田バンプ５を介した半導体素子接続パッド４と半導体素子Ｓの電極Ｔとの接続信頼性が低くなる。したがって、凹部４ａにおける半導体素子接続パッド４の厚みは、２μｍ以上となるようにすることが好ましい。   If the width W of the recess 4a is less than 5 μm, there is a risk that the solder bumps 5 having a sufficiently large size cannot be formed at a predetermined position without good aggregation of the solder around the recess 4a. If the thickness exceeds 250 μm, the risk that the height of the solder bump 5 formed around the recess 4a will be low. Therefore, the width W of the recess 4a is preferably in the range of 5 to 250 μm. Further, when the depth D of the concave portion 4a is less than 1 μm, there is a risk that the solder bump 5 having a sufficiently large size cannot be formed at a predetermined position without good aggregation of the solder around the concave portion 4a. Increases sex. Therefore, the depth D of the recess 4a is preferably 1 μm or more. However, when the thickness of the semiconductor element connection pad 4 in the recess 4a is less than 2 μm, the connection reliability between the semiconductor element connection pad 4 and the electrode T of the semiconductor element S via the solder bump 5 is lowered. Therefore, the thickness of the semiconductor element connection pad 4 in the recess 4a is preferably 2 μm or more.

次に、上述した配線基板１０を本発明の製造方法に従って製造する場合の実施形態の一例を説明する。   Next, an example of an embodiment in the case where the above-described wiring board 10 is manufactured according to the manufacturing method of the present invention will be described.

まず、図３に示すように、絶縁基板１の上面に帯状の配線導体２を多数並べて形成する。配線導体２は、例えば厚みが５〜３０μｍ程度、幅が５〜２５０μｍ程度、ピッチが２０〜４００μｍ程度である。このような配線導体２は、銅箔や銅めっき層から成り、周知のサブトラクティブ法やセミアディティブ法等のパターン形成法を用いることにより形成される。なお、この配線導体２は半導体素子接続パッド４となる部分を含んでいる。   First, as shown in FIG. 3, a large number of strip-like wiring conductors 2 are formed side by side on the upper surface of the insulating substrate 1. For example, the wiring conductor 2 has a thickness of about 5 to 30 μm, a width of about 5 to 250 μm, and a pitch of about 20 to 400 μm. Such a wiring conductor 2 is made of a copper foil or a copper plating layer, and is formed by using a known pattern forming method such as a subtractive method or a semi-additive method. The wiring conductor 2 includes a portion that becomes the semiconductor element connection pad 4.

次に、図４に示すように、配線導体２の半導体素子接続パッド４となる部分における半田バンプ５が形成される位置の上面に凹部４ａを形成する。凹部４ａは、その幅Ｗが５〜２５０μｍ程度、その深さＤが1〜１５μｍ程度である。このような凹部４ａは、配線導体２における凹部４ａと成る部分をエッチングやブラスト、レーザ加工等により選択的に除去することにより形成される。   Next, as shown in FIG. 4, a recess 4 a is formed on the upper surface of the position where the solder bump 5 is formed in the portion to be the semiconductor element connection pad 4 of the wiring conductor 2. The recess 4a has a width W of about 5 to 250 μm and a depth D of about 1 to 15 μm. Such a recess 4a is formed by selectively removing a portion of the wiring conductor 2 that becomes the recess 4a by etching, blasting, laser processing, or the like.

次に、図５に示すように、絶縁基板１および配線導体２の上に、半導体素子接続パッド４を露出させる開口部３ａを有するソルダーレジスト層３を被着形成する。このようなソルダーレジスト層３は、感光性を有する未硬化の熱硬化性樹脂層を絶縁基板１および配線導体２の全体を覆うように被着するとともに、その感光性を有する未硬化の熱硬化性樹脂層を所定のパターンに露光および現像した後、熱硬化させることにより形成される。   Next, as shown in FIG. 5, a solder resist layer 3 having an opening 3 a for exposing the semiconductor element connection pad 4 is deposited on the insulating substrate 1 and the wiring conductor 2. Such a solder resist layer 3 is coated with an uncured thermosetting resin layer having photosensitivity so as to cover the whole of the insulating substrate 1 and the wiring conductor 2, and uncured thermosetting having the photosensitivity. After the photosensitive resin layer is exposed and developed in a predetermined pattern, it is formed by thermosetting.

次に、図６に示すように、ソルダーレジスト層３の開口部３ａから露出する半導体素子接続パッド４上の全面に半田ペースト５Ｐを印刷塗布する。半田ペースト５Ｐの印刷には周知のスクリーン印刷法を用いればよい。   Next, as shown in FIG. 6, a solder paste 5 </ b> P is printed on the entire surface of the semiconductor element connection pad 4 exposed from the opening 3 a of the solder resist layer 3. A known screen printing method may be used for printing the solder paste 5P.

次に、図７に示すように、半田ペースト５Ｐ中の半田を溶融させるとともにその表面張力により凹部４ａを中心にして凝集させて半田バンプ５を形成する。このとき、半導体素子接続パッド４には、半田バンプ５が形成される位置の上面に凹部４ａが形成されていることから、溶融した半田がその表面張力により凹部４ａを中心にして集まってくるので、半導体素子接続パッド４の所定の位置に半田バンプ５を正確に形成することができる。したがって、本例の配線基板の製造方法によれば、半導体素子接続パッド４の幅を部分的に広げることなく、半導体素子接続パッド４がファインピッチで配置された配線基板１０を提供することができる。   Next, as shown in FIG. 7, the solder in the solder paste 5 </ b> P is melted and aggregated around the concave portion 4 a by the surface tension to form the solder bump 5. At this time, since the recess 4a is formed on the upper surface of the position where the solder bump 5 is formed in the semiconductor element connection pad 4, the melted solder gathers around the recess 4a by its surface tension. The solder bump 5 can be accurately formed at a predetermined position of the semiconductor element connection pad 4. Therefore, according to the method for manufacturing the wiring board of this example, it is possible to provide the wiring board 10 in which the semiconductor element connection pads 4 are arranged at a fine pitch without partially increasing the width of the semiconductor element connection pads 4. .

なお、凹部４ａの幅Ｗが５μｍ未満である場合、凹部４ａを中心とした半田の凝集が良好に起こらずに所定の位置に十分な大きさの半田バンプ５を形成することができなくなる危険性が大きくなり、２５０μｍを超えると、凹部４ａを中心にして形成される半田バンプ５の高さが低いものとなってしまう危険性が大きくなる。したがって、凹部４ａの幅Ｗは、５〜２５０μｍの範囲であることが好ましい。また、凹部４ａの深さＤが１μｍ未満である場合、凹部４ａを中心とした半田の凝集が良好に起こらずに所定の位置に十分な大きさの半田バンプ５を形成することができなくなる危険性が大きくなる。したがって、凹部４ａの深さＤは、１μｍ以上であることが好ましい。ただし、凹部４ａにおける半導体素子接続パット４の厚みが２μｍ未満となると、半田バンプ５を介した半導体素子接続パッド４と半導体素子Ｓの電極Ｔとの接続信頼性が低くなる。したがって、凹部４ａにおける半導体素子接続パッド４の厚みは、２μｍ以上となるようにすることが好ましい。   If the width W of the recess 4a is less than 5 μm, there is a risk that the solder bumps 5 having a sufficiently large size cannot be formed at a predetermined position without good aggregation of the solder around the recess 4a. If the thickness exceeds 250 μm, the risk that the height of the solder bump 5 formed around the recess 4a will be low. Therefore, the width W of the recess 4a is preferably in the range of 5 to 250 μm. Further, when the depth D of the concave portion 4a is less than 1 μm, there is a risk that the solder bump 5 having a sufficiently large size cannot be formed at a predetermined position without good aggregation of the solder around the concave portion 4a. Increases sex. Therefore, the depth D of the recess 4a is preferably 1 μm or more. However, when the thickness of the semiconductor element connection pad 4 in the recess 4a is less than 2 μm, the connection reliability between the semiconductor element connection pad 4 and the electrode T of the semiconductor element S via the solder bump 5 is lowered. Therefore, the thickness of the semiconductor element connection pad 4 in the recess 4a is preferably 2 μm or more.

かくして、本発明の配線基板およびその製造方法によれば、絶縁基板の上面に配設された複数の短冊状の半導体素子接続パッドの幅を部分的に広げることなく短冊状の半導体素子接続パッドの上面に半田バンプを形成することにより、半導体素子接続パッドのファインピッチ化を実現することが可能な配線基板およびその製造方法を提供することができる。なお、本発明は上述の実施形態の一例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば上述の実施形態の一例では、半導体素子接続パッド４を横切るようにして凹部４ａを形成したが、図８に示すように、半導体素子接続パッド４の幅の中央部のみに凹部４ａを形成してもよい。さらに、上述の実施形態の一例では、半導体素子接続パッド４の上面に半田ペースト５Ｐを印刷塗布した後、半田ペースト５Ｐ中の半田を溶融させることにより半田バンプ５を形成したが、半導体素子接続パッド４の表面に半田めっきを施した後、その半田めっきを溶融させることにより半田バンプ５を形成するようにしても良い。   Thus, according to the wiring board and the manufacturing method thereof of the present invention, the strip-shaped semiconductor element connection pads can be formed without partially increasing the width of the plurality of strip-shaped semiconductor element connection pads disposed on the upper surface of the insulating substrate. By forming solder bumps on the upper surface, it is possible to provide a wiring board capable of realizing a fine pitch of the semiconductor element connection pads and a manufacturing method thereof. In addition, this invention is not limited to an example of above-mentioned embodiment, A various change is possible if it is a range which does not deviate from the summary of this invention. For example, in the example of the embodiment described above, the recess 4a is formed so as to cross the semiconductor element connection pad 4, but as shown in FIG. 8, the recess 4a is formed only at the center of the width of the semiconductor element connection pad 4. May be. Furthermore, in the example of the above-described embodiment, the solder paste 5P is printed on the upper surface of the semiconductor element connection pad 4, and then the solder bump 5 is formed by melting the solder in the solder paste 5P. The solder bumps 5 may be formed by performing solder plating on the surface of 4 and then melting the solder plating.

１：絶縁基板
４：半導体素子接続パッド
４ａ：凹部
５：半田バンプ 1: Insulating substrate 4: Semiconductor element connection pad 4a: Recessed portion 5: Solder bump

Claims (4)

絶縁基板の上面に短冊状の半導体素子接続パッドを有するとともに該半導体素子接続パッド上に半田を溶融および凝集させて半田バンプを形成して成る配線基板であって、前記半導体素子接続パッドは、前記半田バンプが形成された位置の上面に凹部が形成されているとともに、該凹部を中心に凝集させた半田により前記半田バンプが形成されていることを特徴とする配線基板。   A wiring board having a strip-shaped semiconductor element connection pad on the upper surface of an insulating substrate and forming solder bumps by melting and aggregating solder on the semiconductor element connection pad, wherein the semiconductor element connection pad A wiring board, wherein a concave portion is formed on an upper surface of a position where the solder bump is formed, and the solder bump is formed by solder aggregated around the concave portion. 前記凹部は、その幅が５〜２５０μｍの範囲であり、その深さが１μｍ以上であることを特徴とする請求項１記載の配線基板。   2. The wiring board according to claim 1, wherein the recess has a width of 5 to 250 [mu] m and a depth of 1 [mu] m or more. 絶縁基板の上面に形成された短冊状の半導体素子接続パッドに半田を付着させるとともに該半田を溶融および凝集させて半田バンプを形成する配線基板の製造方法であって、前記半導体素子接続パッドの前記半田バンプが形成される位置の上面に凹部を形成しておくとともに、該凹部を中心に前記半田を凝集させることにより前記半田バンプを形成することを特徴とする配線基板の製造方法。   A method of manufacturing a wiring board in which solder is adhered to a strip-shaped semiconductor element connection pad formed on an upper surface of an insulating substrate, and the solder is melted and aggregated to form a solder bump, wherein the semiconductor element connection pad includes: A method of manufacturing a wiring board, wherein a recess is formed on an upper surface of a position where a solder bump is formed, and the solder bump is formed by agglomerating the solder around the recess. 前記凹部は、その幅が５〜２５０μｍの範囲であり、その深さが１μｍ以上であることを特徴とする請求項３記載の配線基板の製造方法。   4. The method for manufacturing a wiring board according to claim 3, wherein the recess has a width in a range of 5 to 250 [mu] m and a depth of 1 [mu] m or more.
JP2010148041A 2010-06-29 2010-06-29 Wiring board and manufacturing method of the same Pending JP2012015198A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010148041A JP2012015198A (en) 2010-06-29 2010-06-29 Wiring board and manufacturing method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010148041A JP2012015198A (en) 2010-06-29 2010-06-29 Wiring board and manufacturing method of the same

Publications (1)

Publication Number Publication Date
JP2012015198A true JP2012015198A (en) 2012-01-19

Family

ID=45601314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010148041A Pending JP2012015198A (en) 2010-06-29 2010-06-29 Wiring board and manufacturing method of the same

Country Status (1)

Country Link
JP (1) JP2012015198A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018107302A (en) * 2016-12-27 2018-07-05 日立オートモティブシステムズ株式会社 Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310477A (en) * 2005-04-27 2006-11-09 Akita Denshi Systems:Kk Semiconductor device and manufacturing method therefor
JP2007109884A (en) * 2005-10-13 2007-04-26 Shinko Electric Ind Co Ltd Mounting substrate and semiconductor device
JP2008118129A (en) * 2006-11-02 2008-05-22 Samsung Electro-Mechanics Co Ltd Substrate for flip chip bonding and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310477A (en) * 2005-04-27 2006-11-09 Akita Denshi Systems:Kk Semiconductor device and manufacturing method therefor
JP2007109884A (en) * 2005-10-13 2007-04-26 Shinko Electric Ind Co Ltd Mounting substrate and semiconductor device
JP2008118129A (en) * 2006-11-02 2008-05-22 Samsung Electro-Mechanics Co Ltd Substrate for flip chip bonding and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018107302A (en) * 2016-12-27 2018-07-05 日立オートモティブシステムズ株式会社 Semiconductor device

Similar Documents

Publication Publication Date Title
JP5649788B2 (en) Printed circuit board, printed circuit board mounting structure, and printed circuit board mounting method
JP2008300691A (en) Wiring board and its manufacturing method
US20080185711A1 (en) Semiconductor package substrate
TW201417196A (en) Package substrate, package structure and methods for manufacturing same
KR20110064471A (en) Package substrate and fabricating method of the same
JP2011166081A (en) Semiconductor device, semiconductor package, interposer, method of manufacturing semiconductor device, and method of manufacturing interposer
US20100270067A1 (en) Printed circuit board and method of manufacturing the same
JP2014029972A (en) Wiring board
JP2011014644A (en) Wiring board and manufacturing method thereof
JP2013065811A (en) Printed circuit board and method for manufacturing the same
KR100764668B1 (en) Substrate for mounting flip chip and the manufacturing method thereof
JP2014504034A (en) Electronic device tape with enhanced lead cracks
JP2014045190A (en) Method for manufacturing printed-circuit board
TWI520278B (en) Manufacturing method of wafer-embedding package structure
JP2007059588A (en) Method of manufacturing wiring board, and wiring board
KR101153675B1 (en) Printed Circuit Board and Manufacturing Method Thereof
JP2012015198A (en) Wiring board and manufacturing method of the same
JP2013211497A (en) Component joint structure
US20080212301A1 (en) Electronic part mounting board and method of mounting the same
JP5933271B2 (en) Wiring board, electronic unit, and method of manufacturing wiring board
KR20110013902A (en) Package and manufacturing method thereof
JP2007027341A (en) Printed wiring board and electronic-components mounting structure
JP2016127066A (en) Printed wiring board with bump and manufacturing method of the same
JP2016162813A (en) Printed circuit board and soldering method
JP2006237367A (en) Printed wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130206

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130906

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130911

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140121