JP2012013966A - Method of driving plasma display apparatus, plasma display apparatus and plasma display system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive method of panel and a plasma display apparatus capable of satisfying requirements for higher resolution, larger scale screen and stable writing discharge.SOLUTION: The plasma display apparatus comprises: a plasma display panel 10 that has plural discharge cells including a display electrode pair constituted of a scanning electrode and a sustain electrode and data electrode; and a driver circuit that forms one field including plural sub-fields, which has a write period for applying a scanning pulse to a scanning electrode and a write pulse to a data electrode, and a sustain period for applying sustain pulses of the number corresponding to a luminance weight to the display electrode pair, and drives the plasma display panel. A data load detection circuit 37 detects a voltage drop due to a load write pulse from image data, and a data electrode driver circuit 42 controls the width of the write pulse in accordance with the voltage drop.

Description

  The present invention relates to a driving method of a plasma display panel used for a wall-mounted television or a large monitor and a plasma display device using the same.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) includes a front plate on which a plurality of display electrode pairs each composed of a pair of scan electrodes and sustain electrodes are formed, and a plurality of data. A large number of discharge cells are formed between the back plate on which the electrodes are formed. Then, ultraviolet rays are generated by gas discharge in the discharge cell, and the phosphors of red, green and blue colors are excited and emitted by the ultraviolet rays to perform color display.

  As a method of driving the panel, a subfield method is generally used in which one field period is divided into a plurality of subfields and gradation display is performed by a combination of subfields that emit light. Each subfield has an initialization period, an address period, and a sustain period. In the initialization period, an initialization discharge is generated, and an initialization operation for forming wall charges necessary for the subsequent address operation is performed. The initializing operation includes a forced initializing operation that generates an initializing discharge regardless of the operation of the immediately preceding subfield, and a selective initializing that generates an initializing discharge only in the discharge cells that have performed address discharge in the immediately preceding subfield. There is movement. In the address period, address discharge is selectively generated in the discharge cells in accordance with the image to be displayed to form wall charges. In the sustain period, a sustain pulse is alternately applied to the scan electrode and the sustain electrode to generate a sustain discharge, and the phosphor layer of the corresponding discharge cell is caused to emit light, thereby displaying an image. The light emission of the phosphor layer due to the sustain discharge is light emission related to gradation display, and the light emission accompanying the initialization operation is light emission not related to gradation display.

  A driving method for improving contrast by reducing luminance when displaying black, which is the lowest gradation among the subfield methods, and reducing light emission not related to gradation display as much as possible has been studied. For example, Patent Document 1 discloses a driving method in which the forced initialization operation is performed once per field and the forced initialization operation is performed using a slowly changing ramp waveform voltage.

  Further, in the case of a panel having a high definition and a large screen, the pixel ratio of the panel to be lit is large as in Patent Document 2 for the problem that the applied voltage required to generate a stable discharge increases. It is effective to extend the pulse width of the scanning pulse voltage and the pulse width of the address pulse voltage as the time elapses. If this method is used, a stable discharge can be generated by compensating for a voltage drop caused by an increase in the ratio of pixels to be lit.

JP 2000-242224 A JP 2007-333921 A

  On the other hand, in recent years, a panel with higher definition and a larger screen has been demanded.

  In such a panel, the number of electrodes that must be driven increases, and the impedance during driving also increases, so that power consumption tends to increase. Therefore, in the plasma display device including such a panel, the pulse width of the scan pulse voltage and the write pulse voltage of the data pulse necessary for a stable address discharge are changed according to the conventional pixel ratio of lighting. There was a problem that the technique of extending the pulse width is insufficient.

  The present invention has been made in view of the above problems, and provides a panel driving method and a plasma display device capable of achieving both higher definition, larger screen size and stable address discharge. Objective.

  In order to solve the above problems, the present invention provides a plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, a scan pulse applied to the scan electrode, and a data electrode. A drive circuit for driving a plasma display panel by forming one field with a plurality of subfields having an address period in which an address pulse is applied and a sustain period in which a number of sustain pulses corresponding to luminance weights are applied to a display electrode pair A voltage drop due to a load of the write pulse is detected from the image data, and the width of the write pulse is controlled according to the voltage drop.

  With this driving method, even for high-definition, large-screen panels, the voltage applied as the address pulse (hereinafter referred to as the data voltage) can be set small, reducing power consumption and stable address discharge. Can be performed.

  In the above control, the line having a large voltage drop in the voltage fluctuation of the write pulse may be set to have a longer write pulse width than a line having a small voltage drop.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the panel drive method and plasma display apparatus which can make high definition, large screen, and stable address discharge compatible.

1 is an exploded perspective view showing a structure of a panel used in a plasma display device according to an embodiment of the present invention. Electrode arrangement of the panel The figure which shows the drive voltage waveform impressed to each electrode of the panel The circuit block diagram of the plasma display apparatus in one embodiment of the present invention The figure which shows an example of the display pattern on the display in a certain subfield of the panel The figure which shows in more detail the display pattern on the display in a certain subfield of the panel The figure which shows an example of the panel display pattern in this invention The figure which shows the voltage drop amount which the data load detection circuit detects at the time of displaying the pattern of FIG. 5 on a panel in this invention. The figure which shows the write pulse width and data voltage which are necessary in order to perform stable write operation in this invention The figure which shows the write pulse width and data voltage which generate | occur | produce an erroneous write in this invention.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device according to one embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25.

  A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light (light on) to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device according to the embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) that are long in the row direction (line direction). Are arranged, and m data electrodes D1 to Dm (data electrodes 32 in FIG. 1) which are long in the column direction are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects with one data electrode Dj (j = 1 to m). That is, m × n discharge cells are formed in the discharge space, and a region where these discharge cells are formed becomes a display region of the panel 10. In this embodiment, n = 768, but the present invention is not limited to this value.

  Next, a method for driving panel 10 of the plasma display device in the present exemplary embodiment will be described. The panel 10 performs gradation display by dividing the one-field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  FIG. 3 is a diagram showing a driving voltage waveform applied to each electrode of panel 10 in one embodiment of the present invention. FIG. 3 shows scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period, sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm. The drive voltage waveform to be applied is shown.

  FIG. 3 shows two subfields having different waveform shapes of drive voltages applied to scan electrode SC1 through scan electrode SCn during the initialization period. The drive voltage waveforms in the other subfields are substantially the same as the drive voltage waveforms in the second subfield except that the number of sustain pulses generated in the sustain period is different.

  In the initializing period of the first subfield shown in FIG. 3, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and scan electrode SC1 through scan electrode SCn are gradually applied from voltage Vi1 to voltage Vi2. A ramp voltage L1 that rises to is applied. Thereafter, voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn, and ramp voltage L2 that gently falls from voltage Vi3 toward voltage Vi4 is applied to scan electrode SC1 through scan electrode SCn. Then, a weak initializing discharge occurs in each discharge cell, and wall charges necessary for the subsequent address operation are formed on each electrode. As an operation in the initialization period, as shown in the initialization period of the second subfield in FIG. 3, only by applying a ramp voltage L4 that gently falls to scan electrode SC1 through scan electrode SCn. Good.

  In the address period, voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vc is applied to scan electrode SC1 through scan electrode SCn. Next, a scan pulse of the negative voltage Va is applied to the scan electrode SC1 that performs the address operation first, and the positive voltage Vd is applied to the data electrode Dk corresponding to the discharge cell that should emit light in the row that performs the address operation first. Apply the write pulse. Then, an address discharge is generated in the discharge cells to which the scan pulse and the address pulse are simultaneously applied, and an address operation for accumulating wall charges in the scan electrode SC1 and the sustain electrode SU1 is performed.

  Next, a scan pulse is applied to the scan electrode SC2 that performs the second address operation, and an address pulse is applied to the data electrode Dk corresponding to the discharge cell that should emit light in the row that performs the second address operation. Then, an address discharge occurs in the discharge cell to which the scan pulse and the address pulse are simultaneously applied, and an address operation is performed. The above address operation is performed in the discharge cells of all rows, and an address discharge is selectively generated in the discharge cells to emit light to form wall charges.

  In the subsequent sustain period, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and a sustain pulse of voltage Vsus is applied to scan electrode SC1 through scan electrode SCn. Then, a sustain discharge occurs in the discharge cell in which the address discharge has occurred and emits light. Next, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vsus is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the sustain discharge has occurred, the sustain discharge occurs again to emit light.

  Similarly, the number of sustain pulses corresponding to the luminance weight is alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. Thereafter, ramp voltage L3 that increases toward voltage Vr is applied to scan electrode SC1 through scan electrode SCn. As a result, a discharge that erases unnecessary wall charges in the discharge cell is generated in the discharge cell that has generated the sustain discharge, and the sustain period ends.

  In the subsequent subfield, the discharge cell is caused to emit light by repeating substantially the same operation as that of the second subfield. Thereby, an image is displayed on the panel 10.

  In this embodiment, voltage values applied to the respective electrodes are, for example, voltage Vi1 = 145 (V), voltage Vi2 = 350 (V), voltage Vi3 = 190 (V), voltage Vi4 = −160 (V). , Voltage Va = −180 (V), voltage Vsus = 190 (V), voltage Vr = 190 (V), voltage Ve1 = 125 (V), voltage Ve2 = 130 (V), voltage Vd = 60 (V) is there. The voltage Vc can be generated by superimposing the positive voltage Vscn = 145 (V) on the negative voltage Va = −180 (V). In this case, the voltage Vc = −35 (V). However, these voltage values are merely an example. Each voltage value is desirably set to an optimal value as appropriate in accordance with the characteristics of the panel 10 and the specifications of the plasma display device.

  Next, a driving circuit of the plasma display device in this embodiment will be described. FIG. 4 is a circuit block diagram of plasma display device 30 in one embodiment of the present invention. The plasma display device 30 includes the panel 10 and a drive circuit, and the drive circuit is an image signal processing circuit 36, a data load detection circuit 37, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a control signal. A generation circuit 40 and a power supply circuit (not shown) for supplying necessary power to each circuit block are provided.

  The image signal processing circuit 36 converts the image signal into an image signal having the number of pixels and the number of gradations that can be displayed on the panel 10, and further, the light emission / non-light emission in each of the subfields is set to “1” of each bit of the digital signal, The image data is converted to image data corresponding to “0”. The data electrode drive circuit 42 converts the image data into address pulses corresponding to the data electrodes D1 to Dm and applies them to the data electrodes D1 to Dm.

  Further, according to the application pattern of the write pulse at that time, the data load detection circuit 37 detects the load applied to the power supply part to which the data pulse is applied from the light emission pattern for each subfield, and reduces the power supply capability. Detect and output to the control signal generation circuit 40.

  The control signal generation circuit 40 generates various control signals for controlling the operation of each circuit block based on the horizontal synchronization signal, the vertical synchronization signal, and the data voltage drop for each SG, and supplies them to the respective circuit blocks.

  Scan electrode drive circuit 43 creates a drive voltage waveform based on the control signal and applies it to each of scan electrode SC1 through scan electrode SCn. In the address period, a scan pulse having a pulse width according to the control signal is generated and applied to scan electrode SC1 through scan electrode SCn. In the sustain period, a sustain pulse is generated according to the control signal and applied to scan electrode SC1 through scan electrode SCn.

  Sustain electrode drive circuit 44 creates a drive voltage waveform based on the control signal, and applies it to sustain electrode SU1 through sustain electrode SUn. In the sustain period, a sustain pulse is generated according to the control signal and applied to sustain electrode SU1 through sustain electrode SUn.

  The data electrode drive circuit 42 creates a drive voltage waveform based on the control signal and applies it to each of the data electrodes D1 to Dm. In the address period, an address pulse having a pulse width according to the control signal is generated and applied to the data electrodes D1 to Dm.

  Next, the operation of the data load detection circuit 37 and the control of the write pulse width according to the load detection result in the present invention will be described in detail. FIG. 5 is a diagram showing an example of a display pattern in a certain subfield. In the figure, the pixel marked “1” is lit and the pixel marked “0” is not lit. In both FIG. 5A and FIG. 5B, the lighting ratio of the pixels is equally 50%. Here, as a feature of FIG. 5A, when attention is paid to a certain target pixel, adjacent pixels rise in the same phase. That is, adjacent pixels are in the same state. For example, when a horizontal stripe pattern is displayed, such a lighting pattern is obtained. On the other hand, the feature of FIG. 5B is that when attention is paid to a certain target pixel, adjacent pixels rise in opposite phases. That is, the target pixel and the adjacent pixel are not in the same lighting state. For example, when a checkered pattern is displayed, such a lighting pattern is obtained.

  The data electrodes D1 to Dm are driven by the data electrode drive circuit 42, but when viewed from the data electrode drive circuit 42 side, the data electrodes Dj on the panel 10 are capacitive loads. Therefore, in the address period, this capacitance must be charged and discharged every time the voltage applied to each data electrode is switched from the ground potential 0 (V) to the address pulse voltage Vd or from the address pulse voltage Vd to the ground potential 0 (V). Don't be. When the number of times of charging / discharging is large, the power consumption of the data electrode driving circuit 42 is also increased, and the power supply capability for applying the address pulse is reduced. In addition, the voltage applied to the data electrode Dj + 1 adjacent to the data electrode Dj or the data electrode Dj-1 further increases as the voltage changes in the opposite phase.

  Therefore, in FIGS. 5A and 5B, as described above, the lighting ratio of the pixels is equal to 50% in both patterns. The voltage drop is therefore equal. However, in order to accurately know the data pulse potential that is actually applied, it is necessary to take into account a decrease in power supply capability if there is a difference in load on the power supply portion to which the data pulse is applied.

  Therefore, in this example, each bit of image data corresponding to each subfield is used to detect the load value of the target pixel of the data electrode Dj from the bits of the upper / lower and left / right pixels. Further, by calculating the sum of the data of each pixel for one horizontal line, the load applied to the power supply portion to which the data pulse is applied to write the line surrounded by the scan electrode SCi and the sustain electrode SUi is detected. By doing so, a decrease in power supply capability is detected.

  A method for calculating the load value of the target pixel according to this example will be described with reference to FIG. A pixel surrounded by a circle in FIG. The target pixel C is driven by the data electrode Dj. In FIG. 6A, since neither the pixel above the target pixel C nor the target pixel is written, the voltage is not changed. For this reason, for example, the load is set to zero. Similarly, in FIG. 6B, since the pixel above the target pixel C and the target pixel are both written, the voltage is not changed, for example, the load is also set to 0.

  In FIG. 6C, since writing is not performed on the pixel above the target pixel C, but writing is performed on the target pixel C, a capacitance for changing the voltage from the ground potential 0 (V) to the write pulse voltage Vd is generated. On the other hand, since the left pixel of the target pixel C rises in phase, no capacitance is generated between the target pixel C and the left pixel. The load at this time is, for example, 1.

  In FIG. 6D, since writing is not performed on the pixel above the target pixel C, but writing is performed on the target pixel C, the voltage is changed from the ground potential 0 (V) to the write pulse voltage Vd when writing to the target pixel C. Capacity to be generated. On the other hand, since the left pixel does not change at the ground potential 0 (V), a capacitance is generated between the left pixel and the left pixel. Assume that the load at this time is 2, for example. The same applies to the case where the left pixel does not change with the write pulse voltage Vd (V).

  In FIG. 6E, since the pixel above the target pixel C does not write in the target pixel C, the capacitance that changes the voltage from the ground potential 0 (V) to the write pulse voltage Vd when the target pixel C is written. Will occur. On the other hand, the left pixel changes from the write pulse voltage Vd to the ground potential 0 (V) in a phase opposite to that of the target pixel. At this time, the capacity generated between the target pixel C and the pixel on the left is further larger than in the case of (D).

  By performing this calculation for each pixel, the load for each line can be detected, and the data voltage actually applied to the panel can be more accurately known in consideration of the decrease in power supply capability. The data load detection circuit 37 in the present embodiment detects the load amount of the data voltage in time series by this method, and outputs it to the control signal generation circuit 40.

  Next, the specific operation of the example of this embodiment will be described below. As shown in FIG. 7, in the case of displaying an image with white display from the first line to the 199th line of the scanning electrode of the panel 10, a checkered pattern display from the 200th line to the 800th line, and a white display from the 801th line to the 1080th line. Will be described as an example. The central checkered portion is as shown in FIG. 5B. Each pixel generates a very large voltage drop because the voltage applied to the adjacent data electrodes Dj + 1 and Dj-1 changes in opposite phase.

  FIG. 8 shows the data voltage supplied to the data electrode drive circuit detected by the data load detection circuit 37 in the subfield under the above-described conditions. The vertical axis represents the data voltage to be supplied, and the horizontal axis represents the number of lines, which corresponds to the pattern of FIG. From line 1 to line 199, the load applied to the data voltage supply source of the data electrode drive circuit 42 is small, so it is possible to apply a voltage equal to the supply voltage, but from line 200 to line 800, a checkered pattern is displayed. Therefore, a supply voltage drop occurs, and it is detected that the voltage that can be supplied in time series decreases as shown in the figure. Further, since the white display is returned from the 801 line, it can be detected that the voltage gradually recovers.

  Next, the address pulse width applied to the data electrode during the address period necessary for correctly lighting the pixel and the data voltage that is the voltage applied as the address pulse will be described with reference to FIG. In the panel of the present embodiment, it is known that the write pulse width and the data voltage are correlated, and that the data voltage can be set small when the write pulse width is set long. On the other hand, FIG. 10 shows the relationship between the write pulse width and the data voltage at which pixels that are not to be lit are erroneously lit. In the panel of this embodiment, the address pulse width and the data voltage have a correlation, and it is known that when the address pulse width is set long, the data voltage at which erroneous discharge occurs decreases. As described above, when the address pulse width is increased, the data voltage for correctly performing the address operation can be reduced, but on the other hand, erroneous discharge is likely to occur.

  Therefore, in the present embodiment, a decrease in supply voltage calculated from the data load detected by the data load detection circuit 37 is output to the control signal generation circuit 40. The calculation of the drop in the supply voltage from the data load is optimally set according to the power supply capability of the plasma display device displaying the panel 10.

  In addition, the control signal generation circuit 40 drives the scan electrode drive circuit 43 and the data electrode drive circuit 42 by setting an appropriate write pulse width for each scan electrode line based on the decrease in the supply voltage. That is, the write pulse width is increased on the line where the supply voltage is greatly reduced, and the write operation is performed correctly. In addition, the address pulse width is reduced in a line where the decrease in supply voltage is small, thereby suppressing the occurrence of erroneous discharge. The address cycle is set and controlled optimally according to the panel discharge characteristics, the panel structure, and the like.

  As a result, even for high-definition, large-screen panels, the voltage applied as the address pulse (hereinafter referred to as the data voltage) can be set small, reducing power consumption and enabling stable address discharge. It becomes.

  The present invention can achieve both high definition, large screen and stable address discharge, and is useful as a plasma display device and a panel driving method.

DESCRIPTION OF SYMBOLS 10 Panel 21 Front substrate 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 30 Plasma display apparatus 31 Back substrate 32 Data electrode 34 Partition 35 Phosphor layer 36 Image signal processing circuit 37 Data load detection circuit 40 control signal generation circuit 42 data electrode drive circuit 43 scan electrode drive circuit 44 sustain electrode drive circuit

Claims (3)

A plasma display panel comprising a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode;
1 in a plurality of subfields having an address period in which a scan pulse is applied to the scan electrode and an address pulse is applied to the data electrode, and a sustain period in which the number of sustain pulses corresponding to a luminance weight is applied to the display electrode pair. A drive circuit configured to drive the plasma display panel by configuring a field;
A method of driving a plasma display, comprising detecting a decrease in power supply capability due to a load of the write pulse and controlling a width of the write pulse in accordance with the voltage drop. 2. The plasma display according to claim 1, wherein a line having a large decrease in power supply capability in the voltage fluctuation of the write pulse is set to have a longer write pulse width than a line having a small decrease in power supply capability. Driving method. A plasma display panel comprising a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode;
1 in a plurality of subfields having an address period in which a scan pulse is applied to the scan electrode and an address pulse is applied to the data electrode, and a sustain period in which the number of sustain pulses corresponding to a luminance weight is applied to the display electrode pair. A drive circuit for configuring the field and driving the plasma display panel;
A circuit for detecting a decrease in power supply capability due to a load of the write pulse;
A plasma display driving apparatus, wherein a width of an address pulse is controlled in accordance with a decrease in power supply capability.