JP2012009576A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide means for reducing epitaxial layer corrosion in an alignment mark formation step.SOLUTION: Performing anisotropic etching forms a silicon-based film 22 only in a side wall of a step 21 of the alignment mark. Even if an epitaxial layer 30 is laminated throughout an alignment mark region A because the silicon-based film 22 was formed in the side wall of the step 21, growth of the epitaxial layer 30 can be suppressed in the side wall, enabling the step 21 to keep a forward tapered shape.

Description

  Embodiments described herein relate generally to a method for forming an alignment mark of a semiconductor device in a semiconductor manufacturing process.

  Conventionally, in a manufacturing method of a semiconductor device, in order to form a plurality of device patterns on a semiconductor wafer such as silicon, over 20 different mask patterns are sequentially stacked and exposed on the semiconductor wafer. During this exposure, each mask is positioned based on the alignment mark detected by the aligner, and whether or not the device pattern to be formed next is correctly superimposed on the device pattern on each chip provided on the semiconductor wafer. Check for misalignment.

  FIG. 3 is a cross-sectional view showing a conventional alignment mark forming process in a semiconductor manufacturing process. The alignment mark is usually formed by forming a step in a base insulating film, a semiconductor wafer substrate or the like by selective etching, selective oxidation or the like. As shown in FIG. 3A, a single crystal silicon substrate 10 is prepared. Resist patterning is performed on the alignment mark region A of the silicon substrate 10 by a photolithography technique, and the silicon substrate 10 is processed by an etching technique to form an alignment mark having a concave step. FIG. 3 shows two types of alignment marks, a step 11a having a deep silicon etching depth and a shallow step 11b. Thereafter, as shown in (b), an epitaxial layer 12 is deposited on the silicon substrate 10 by a CVD (vapor phase growth) method. (C), (d) is a figure which shows the process of growing the epitaxial layer 12, and (d) has shown what grew the epitaxial layer 12 to the target layer thickness especially.

Japanese Patent Laid-Open No. 2001-168007 FIG.

  In general, the alignment mark is detected based on a reflected signal by applying a laser beam to the step of the alignment mark. Therefore, unless a step having a certain depth is formed, there is a problem that the epitaxial layer erodes at the edge of the step and the laser beam is not accurately reflected at the edge.

  For example, as shown in FIG. 3D, when a thick epitaxial layer 12 is laminated on an alignment mark having a shallow step 11b, the epitaxial layer 12 erodes the step 11b during the growth process, and the edge of the step becomes dull. For this reason, when the alignment mark is detected, a signal cannot be sufficiently obtained at the edge of the step, and the overlay accuracy is lowered. On the other hand, when the step is extremely deep like the step 11a, unevenness at the time of resist application and a problem of a rate-limiting step in the etching process occur.

  Accordingly, it is an object to reduce the erosion of the epitaxial layer to the step in the alignment mark forming process and improve the alignment accuracy of the alignment mark.

  According to the embodiment of the present invention, a method for forming an alignment mark of a semiconductor device forms a step having a side wall perpendicular to a bottom surface on a silicon substrate in an alignment mark region, and a silicon-based film so as to cover the step Forming a resist on the silicon-based film so as to bury and cover the step, removing the resist and exposing the silicon-based film, and forming on the side wall of the step The method comprises an anisotropic etching process for removing the silicon film while leaving the silicon film formed.

Sectional drawing shown in process order which shows the formation method of the level | step difference of the alignment mark concerning one Embodiment of this invention. Sectional drawing which shows the lamination | stacking process of the epitaxial layer concerning one Embodiment of this invention. Sectional drawing which shows the process of laminating | stacking an epitaxial layer on the conventional alignment mark.

  Hereinafter, embodiments of the invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view showing a method of forming a step of an alignment mark according to an embodiment of the present invention in the order of steps. First, as shown in FIG. 1A, an alignment mark region A and an element region B are formed on a silicon substrate 20. A resist is applied to the surface of the silicon substrate 20 (not shown), and the nitride film and the oxide film are selectively removed by dry etching, thereby forming a concave step 21 having a depth of about 1 to 10 μm. . At this time, by performing anisotropic etching using RIE (Reactive Ion Etching), a step 21 whose side wall is substantially perpendicular to the bottom surface is formed. After the step 21 is formed, a film 22 (hereinafter referred to as a silicon-based film) made of silicon dioxide SiO ₂ is formed on the entire silicon substrate 20 by CVD (Chemical Vapor Deposition). More specifically, a silicon-based film having a thickness of about 100 to 200 nm is grown at a temperature of about 200 to 600 ° C. by a plasma CVD method and at a temperature of about 1000 ° C. by a normal CVD method. The silicon-based film 22 may be a film made of silicon nitride Si ₃ N ₄ . FIG. 1 shows an example in which the step 21 is directly formed on the silicon substrate 20, but the step 21 may be formed after providing a base insulating film made of SiO ₂ on the silicon substrate 20. I do not care.

  Next, as shown in FIG. 1B, a first resist film 23 is formed on the entire semiconductor wafer. The first resist film 23 has a thickness that can sufficiently fill the step 21 in the alignment mark region A.

  Photolithography is performed on the first resist film 23 formed in FIG. 1B, and the first resist film 23 deposited in the element region B is removed, whereby a silicon-based film on the element region B is removed. 22 is once exposed. Etching is then performed to remove the silicon-based film 22 in the element region B that is not covered with the first resist film 23, as shown in FIG.

  Further, as shown in FIG. 1D, a second resist film 24 is formed on the entire alignment region A and element region B.

  As shown in FIG. 1E, this time, the second resist film 24 on the alignment mark region A side is removed, and the silicon-based film 22 is exposed.

  Further, by performing dry etching on the alignment mark region A in FIG. 1D, the silicon-based film 22 on the alignment mark region A side is removed. Again, by performing anisotropic etching using RIE, the silicon-based film 22 remains on the step 21. Thereafter, the resist film 24 on the element region B side is peeled off.

  FIG. 2 is a cross-sectional view showing a process of laminating an epitaxial layer on the step formed in the alignment mark region A of FIG. As shown in FIG. 2A, two alignment marks having a step 21 having the same depth dimension are illustrated in the alignment mark region A. The side wall of the step 21 is covered with a silicon-based film 22 having a thickness in the direction of the central axis C of the step.

  As shown in FIG. 2B, the epitaxial layer 30 is stacked on the alignment mark region A having the step 21.

  2C and 2D show the growth process of the epitaxial layer 30 stacked in FIG. As shown in (c) and (d), since the silicon film 22 is present on the side wall of the step 21, the epitaxial layer 30 does not grow on the side wall of the step 21. Therefore, unlike the step of the conventional alignment mark, the growth of the epitaxial layer 30 in the direction of the central axis C of the step 21 is suppressed, and the forward tapered step 21 can be maintained even if the epitaxial layer 30 is stacked. For this reason, the laser beam is reflected with high accuracy, and a stable signal can be extracted.

  Furthermore, according to the method for forming the step 21 of the present embodiment, the step 21 is formed on the silicon substrate 20 by anisotropic etching, so that the semiconductor wafer can be directly aligned after the epitaxial layer 30 is overlaid. The accuracy is good.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

20 silicon substrate, 21 step, 22 silicon-based film, 23 first resist film, 24 second resist film, 30 epitaxial layer

Claims (3)

Forming a step having a side wall perpendicular to the bottom surface on the silicon substrate in the alignment mark region, and forming a silicon-based film so as to cover the step;
An etching step of forming a resist pattern on the silicon-based film and exposing the silicon-based film in the alignment mark region;
A method of forming an alignment mark for a semiconductor device, comprising an anisotropic etching step of removing the silicon film while leaving the silicon film formed on the side wall of the step.   2. The method of forming an alignment mark for a semiconductor device according to claim 1, wherein the silicon-based film is a silicon oxide film.   2. The method of forming an alignment mark for a semiconductor device according to claim 1, wherein the silicon-based film is a silicon nitride film.

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