JP2012009404A - Segment control led drive element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a segment control LED drive element which is suitable for driving a plurality of LEDs arranged in an array shape.SOLUTION: A drive element registers a group channel signal in a group channel data area and registers a current count value in a count data area when receiving a latch permission signal for a segment. The drive element updates a luminance signal in a buffer circuit via a designated channel in the group channel data area when receiving a latch permission signal for segment update. A comparison circuit outputs a drive signal for driving a LED by segment update in accordance with the registered count value, a real-time count value, and the updated luminance signal.

Description

  The present invention relates to a light emitting diode (LED) driving element, and more particularly to a driving element that performs update control based on a time segment for driving an LED backlight of a liquid crystal display (LCD).

  Compared to conventional light sources, LEDs have advantages such as long life, low power consumption, and high durability, and are therefore important targets for research and development and daily life applications.

  In recent years, LCDs have been widely used. Since the liquid crystal molecules cannot emit light, the backlight module is necessary for realizing the display function. The light source that is currently commonly used for the backlight module is a cold cathode fluorescent lamp (CCFL). However, the CCFL has a drawback that it is difficult to improve the response speed. For this reason, the future trend is to use LEDs as backlights for LCDs. Since LEDs are point light sources, a plurality of LEDs arranged in an array must be used to provide a stable light source for display. The drive element may transmit a pulse width modulation (PWM) signal to drive the LED.

  In general, in order to drive LEDs arranged in an array, a plurality of driving elements are connected in series. For example, assume an LED array has 10 LEDs in each row and 3 LEDs in each column. Each drive element has 16 channels, and each channel may drive one LED. If the LEDs in each row are driven at different times, the 10 channels of each drive element are connected to and control the 10 LEDs in the corresponding row. Therefore, 6 channels for driving LEDs are wasted in each drive element. A total of three drive elements are used. The conventional technology has a problem that data of all channels of one driving element needs to be updated simultaneously. In addition, when the number of LEDs driven by the driving element is smaller than the number of channels of the driving element, the unused channel of the driving element is wasted, and the manufacturing cost is wasted.

  In view of the above problems, in order to solve the problem that the channel of the driving element is not completely used when the LED is used as the backlight of the LCD and the manufacturing cost is wasted, the present invention provides a segment control LED driving element. I will provide a.

  The segment control LED driving element of the present invention is suitable for driving a plurality of LEDs arranged in an array. The segment control drive element receives a data clock signal, a latch permission signal, and a serial data signal and generates a drive signal. The segment control drive element includes a serial register circuit, an identification module, a counter, a control circuit, a count register circuit, a group register module, a buffer circuit, and a comparison circuit. The identification module receives the data clock signal and the latch enable signal. When the period of the latch permission signal is twice the period of the data clock signal, the identification module outputs a first permission signal. If the period of the latch permission signal is the same as the period of the data clock signal, the identification module outputs a second permission signal. The serial register circuit receives the serial data signal and outputs a group channel signal according to the first permission signal or outputs a luminance signal according to the second permission signal.

  The counter continuously receives the global clock signal, cyclically counts to a predetermined value, and outputs the count value in real time. That is, the count value is clearly less than the predetermined value. The control circuit receives the group channel signal and outputs a control signal. The count register circuit includes a plurality of count data areas. The count register circuit receives the channel selection signal and the control signal, and stores the count value in one of the count data areas according to the control signal. Each count data area has one or more designated channels.

  The group register module includes a plurality of group channel data areas. The group register module receives the channel selection signal and the control signal, and stores the serial data signal received by the serial register circuit in one of the group channel data areas according to the control signal. Each count data area corresponds to one of the group channel data areas, and each count data area and the group channel data area corresponding to the count data area have the same designated channel.

  When the buffer circuit receives the second permission signal, it caches the luminance signal in the designated channel controlled by the group channel data region. A serial data signal received by the serial register circuit is stored in the group channel data area. The comparison circuit receives the count value stored in the count data area, the count value output in real time by the counter, and the luminance signal cached by the designated channel and outputs the drive signal. . The drive signal is used to control the light intensity of the LED. When the difference between the count value output in real time by the counter and the count value stored in the count data area is larger than the luminance signal, the drive signal drives the LED.

The segment control drive element of the present invention can be applied to an LCD using an LED as a backlight. By using count register circuits, control signals, and group channel signals, the drive element only needs one counter to allow the designated channel to update data at different times. is there. This solves the problem that the data of all channels of the drive element need to be updated simultaneously. Using a group register module to control the specified channel to store the serial data signal received by the serial register circuit as a luminance signal, ensuring that only the specified channel updates the luminance signal To do. Moreover, since all the channels of each drive element are used due to the above structure of the drive elements, the problem of waste due to the presence of unused channels is solved.
The present invention will be more fully understood from the following detailed description. The following description is for illustrative purposes only and is not intended to limit the invention.

It is the schematic which illustrates the circuit connection of the segment control drive element concerning the 1st Embodiment of this invention when applied to LED arranged in the array form. 1 is a schematic circuit block diagram illustrating a segment control drive element according to a first embodiment of the invention. 2 is a schematic circuit block diagram illustrating a count register circuit and a group register module of the segment control drive element according to the first embodiment of the invention. FIG. 1 is a schematic circuit block diagram illustrating a comparison module of a segment control drive element according to a first embodiment of the invention. It is a timing diagram of segment drive of the segment control drive element concerning a 1st embodiment of the present invention. FIG. 5 is a schematic circuit block diagram illustrating a segment control drive element according to a second embodiment of the invention. It is a timing diagram of the segment drive of the segment control drive element concerning the 2nd Embodiment of this invention.

  FIG. 1 is a schematic diagram of circuit connection of segment control drive elements according to the first embodiment of the present invention when applied to LEDs arranged in an array. The segment control LED driving elements 100a and 100b are suitable for driving a plurality of LEDs 90 arranged in an array. In the present embodiment, each of the segment control drive elements 100a and 100b drives 16 channels. Each channel may comprise one or more LEDs 90. The LEDs 90 of the same channel operate synchronously. For example, in the present embodiment, each channel has only one LED 90, but the number of LEDs 90 connected to one channel is not limited in the present invention. As shown in FIG. 1, since the LED array has only 30 LEDs 90, the last two channels of the second segment control drive element 100b are not connected to the LEDs. In the present embodiment, there are 10 LEDs in each row and 3 LEDs in each column, but the present invention is not limited to this.

  As can be seen from FIG. 1, the same data clock signal DCLK1 and latch enable signal LE1 are connected to the segment control drive elements 100a and 100b, and the segment control drive element 100a receives the serial data signal SD1 (also referred to as serial data input SDI). The serial data signal SD2 (also referred to as serial data output SDO) is output. The segment control drive element 100b receives the serial data signal SD2 and outputs a serial data signal SD3. In other words, the segment control drive elements 100a and 100b are connected in series. The segment control drive elements 100a and 100b may be connected to separate rows. Thus, taking segment control drive element 100a as an example, the first 10 channels drive the first row of the LED array and the last 6 channels drive the first 6 LEDs 90 of the second row of the LED array. The LED is driven so that the segment control drive element 100b is also deduced in the same manner.

  In the present embodiment, the LED array driving method updates the luminance and drives the same row at the same time. For this reason, when the first 10 channels of the segment control drive element 100a update the luminance (also called gray scale) data, the last 6 channels are not updated. When the last 6 channels are updated, the first 10 channels are not updated. This is segment driving (updating), which is an object achieved by the present invention. However, this embodiment is not intended to limit the scope of the present invention and may be adjusted according to the actual segment update situation. It should be noted that when a channel performs luminance data segment update, channels that do not need to update luminance data are not affected. In the following embodiment, the segment control drive element 100a may update the channel luminance data, but this embodiment is not intended to limit the scope of the present invention.

  FIG. 2 is a schematic circuit block diagram illustrating the segment control drive element according to the first embodiment of the invention. The segment control drive element 100a receives the data clock signal DCLK1, the latch enable signal LE1, and the serial data signal SD1, and generates one or more drive signals DS1. Each drive signal DS1 is used to control the light intensity of the LED 90 connected to the channel. In this embodiment, all signals may be rectangular wave signals, but this is not intended to limit the scope of the present invention.

  The segment control drive element 100a of the LED 90 includes a switch 96, a switch 98, a serial register circuit 102, an identification module 103, a counter 104, a control circuit 106, a count register circuit 108, a group register module 110, a buffer circuit 112, and a comparison circuit 114. .

  The identification module 103 receives the data clock signal DCLK1 and the latch permission signal LE1. When the high level period of the latch enable signal LE1 is twice the high level period of the data clock signal DCLK1 (or the high level period of the latch enable signal LE1 includes two rising edges of the data clock signal DCLK1), the identification module 103 Outputs a first permission signal FE1. When the high level period of the latch enable signal LE1 is the same length as the high level period of the data clock signal DCLK1 (or the high level period of the latch enable signal LE1 includes one rising edge of the data clock signal DCLK1), the identification module 103 outputs a second permission signal SE1. The switch 96 is turned on according to the first permission signal FE1, and the serial register circuit 102 receives the serial data signal SD1 and outputs a group channel signal GC1. Alternatively, the switch 98 is turned on according to the second permission signal SE1, and the serial register circuit 102 receives the serial data signal SD1 and outputs the luminance signal IS1 and the serial data signal SD3.

  In the present embodiment, the latch permission signal LE1 may be a signal triggered by a falling edge, but the present embodiment is not intended to limit the scope of the present invention. That is, the latch permission signal LE1 may be a signal triggered by a rising edge. The falling edge refers to a location where a transition is made from a high level to a low level, and the rising edge refers to a location where the transition is made from a low level to a high level.

The counter 104 cyclically counts up to a predetermined value, continuously receives the global clock signal GCLK1, and outputs the count value in real time. The global clock signal GCLK1 is an internal clock signal of the segment control drive element 100a. In other words, the predetermined value is the maximum value of the count value, and the count value is less than or equal to the predetermined value. The above “cyclically counting” means that the counter 104 counts from zero to the predetermined value, and after reaching the predetermined value, returns to zero and repeats counting. For example, when the predetermined value is 4095 (2 ¹² ; 12 bits), the counter 104 counts up by 1 every time one clock is received according to the global clock signal GCLK1. The count starts from zero and goes up to 4095. After reaching 4095, the counter 104 starts counting from zero again at the next clock. The count value output by the counter 104 represents the current count value of the counter 104 that is counting, and is also referred to as a real-time count value.

  When the identification module 103 outputs the first permission signal FE1, the control circuit 106 receives the group channel signal GC1 output from the serial register circuit 102 and outputs the control signal CS1. In the present embodiment, the control signal CS1 includes 01 (ie, the first signal) and 10 (ie, the second signal), but this embodiment is not intended to limit the scope of the present invention. The number of signals included in the control signal CS1 is determined by the number of segment groups in the channel of the actual segment control drive element 100a. In the present embodiment, all the channels of the segment control drive element 100a are divided into two groups, that is, a first to tenth channel group and a first to 16th channel group. In other words, when the group channel signal GC1 is 1111 1111 1100 0000, the control circuit 106 uses the group channel signal GC1 (ie, the first signal and the last signal of 1111 1111 1100 0000) to be 10 (ie, the first Signal) in parallel. When the group channel signal GC1 is 0000 0000 0011 1111, the control circuit 106 uses the group channel signal GC1 (ie, the first and last signals of 0000 0000 0011 1111) to obtain 01 (ie, the second signal). Although output in parallel, this embodiment is not intended to limit the scope of the invention.

  FIG. 3 is a schematic circuit block diagram illustrating the count register circuit and the group register module of the segment control drive element according to the first embodiment of the invention. 2 and 3, the count register circuit 108 includes a first count data area 120 and a second count data area 122, which are connected to the control circuit 106 and the counter 104, respectively. It is not intended to limit the scope of the invention. The number of count data areas is determined by the number of segment groups in the channel of the actual segment control drive element 100a. However, the number of count data areas does not exceed the number of channels of the segment control drive element 100a.

  The identification module 103 outputs the first permission signal FE1, the control circuit 106 outputs the control signal CS1, and the count register circuit 108 latches the latch permission signal LE1 (during the high level period of the latch permission signal LE1, the high level of the data clock signal DCLK1). The current count value of the counter 104 is stored in the first count data area 120 or the second count data area 122 when the control signal CS1 is received. The first count data area 120 has the first to tenth channels as designated channels, and the second count data area 122 has the first to sixteenth channels as designated channels. For example, the count register circuit 108 receives the latch permission signal LE1 and 10 (that is, the first signal) output from the control circuit 106 in parallel (that is, 1 is input to the first count data area 120, and 0 is When input to the second count data area 122), the first count data area 120 stores the count value. The count register circuit 108 receives the latch permission signal LE1 and 01 (that is, the second signal) output from the control circuit 106 in parallel (that is, 0 is input to the first count data area 120, and 1 is the second. When input to the count data area 122), the second count data area 122 stores the count value.

  The group register module 110 includes a first group channel data area 134 and a second group channel data area 136, which are connected to the serial register circuit 102 and the control circuit 106, respectively. When the group register module 110 receives the first permission signal FE1 and the control signal CS1, the group channel signal GC1 is stored in the first group channel data area 134 or the second group channel data area 136. The number of count data areas is the same as the number of group channel data areas, and each count data area corresponds to one group channel data area. Each count data area and the group channel data area corresponding to this count data area have the same designated channel.

  In other words, the group register module 110 outputs the latch enable signal LE1 (the high level period of the latch enable signal LE1 is twice the high level period of the data clock signal DCLK1) and the control circuit 106 outputs in parallel 10 (that is, the first signal). (That is, 1 is input to the first group channel data area 134 and 0 is input to the second group channel data area 136), the first group channel data area 134 receives the group channel signal GC1. Remember. The group register module 110 generates a latch enable signal LE1 (the high level period of the latch enable signal LE1 is twice the high level period of the data clock signal DCLK1) and 01 (that is, the second signal) output from the control circuit 106 in parallel. When receiving (that is, 0 is input to the first group channel data area 134 and 1 is input to the second group channel data area 136), the second group channel data area 136 stores the group channel signal GC1. .

  The first group channel data area 134 corresponds to the first count data area 120, and the second group channel data area 136 corresponds to the second count data area 122. The first group channel data region 134 has the first to tenth channels as designated channels, and the second group channel data region 136 has the eleventh to sixteenth channels as designated channels. The group channel signal GC1 stored in the first group channel data area 134 is 1111 1111 1100 0000, and the group channel signal GC1 stored in the second group channel data area 136 is 0000 0000 0011 1111. The group channel signal GC1 is an example according to the application of FIG. 1 and is not limited thereto.

  Referring to FIG. 2 again, the buffer circuit 112 is connected to the serial register circuit 102, and upon receiving the second permission signal SE1 (that is, the output signal of the identification module 103), the luminance signal IS1 is cached (stored) in the designated channel. ) These designated channels are determined by the group channel data area in which the group channel signal GC1 is stored. For example, when the group channel signal GC1 stored in the first group channel data area 134 is 1111 1111 1100 0000, the first to tenth channels cache the luminance signal IS1, and the first to sixteenth channels are luminance. The signal IS1 is not cached.

  FIG. 4 is a schematic circuit block diagram illustrating the comparison module of the segment control drive element according to the first embodiment of the invention. Referring to FIG. 2, FIG. 3 and FIG. 4 at the same time, the comparison circuit 114 has a count value stored in the first count data area 120 and the second count data area 122, a count value output in real time by the counter 104, The luminance signal IS1 is received and one or more driving signals DS1 are output. In this embodiment, the comparison circuit 114 comprises 16 comparison modules 126, and each comparison module 126 is connected to a designated channel, but this embodiment is not intended to limit the scope of the present invention. The number of comparison modules 126 may be equal to the number of channels of segment control drive element 100a. Each comparison module 126 includes a selector 130, a subtracter 131, and a comparator 132.

  The size of the group channel signal GC1 stored in the first group channel data area 134 and the second group channel data area 136 is 16 bits, and the group channel signal GC1 is output to the designated comparison module 126 in parallel. That is, each bit of the group channel signal GC1 stored in the first group channel data area 134 and the second group channel data area 136 is transferred to the designated comparison module 126. For example, the 16th bit of the group channel signal GC1 stored in the first group channel data area 134 and the 16th bit of the group channel signal GC1 stored in the second group channel data area 136 are connected to the 16th channel. And transferred to the selector 130 of the comparison module 126.

  As described above, each selector 130 counts according to the bit of the group channel signal GC1 stored in the first group channel data area 134 and the bit of the group channel signal GC1 stored in the second group channel data area 136. The count value in the data area 120 or the count value in the second count data area 122 is selected and output.

  For example, the 16th bit of the group channel signal GC1 stored in the first group channel data area 134 received by the selector 130 and the 16th bit of the group channel signal GC1 in the second group channel data area 136 are low level and high level, respectively. In the case of the level, the selector 130 outputs the count value of the second count data area 122. The 16th bit of the group channel signal GC1 stored in the first group channel data area 134 received by the selector 130 and the 16th bit of the group channel signal GC1 of the second group channel data area 136 are at a high level and a low level, respectively. If there is, the selector 130 outputs the count value of the first count data area 120. However, this embodiment is not intended to limit the scope of the present invention.

  Each subtracter 131 subtracts the count value CNT2 of the first count data area 120 output from the selector 130 or the count value CNT1 of the second count data area 122 from the count value CNT1 output from the counter 104 in real time, and outputs the difference. To do. Each comparator 132 compares this difference with the luminance signal IS1 cached by the designated channel, and outputs the drive signal DS1 to the LED 90 connected to the designated channel. The drive signal DS1 is used to control the light intensity of the LED 90 connected to the designated channel.

If the difference is less than zero, this difference is represented by the negative complement of the predetermined value as the maximum count value of the counter 104 cyclic count up. For example, when the predetermined value is 4095 (2 ¹² ; 12 bits), the count value CNT2 of the first count data area 120 output by the selector 130 is subtracted from the count value CNT1 output by the counter 104 in real time, and the difference is − In the case of 1000, this difference is represented by 3096. When the difference between the count value stored in the first count data area 120 or the second count data area 122 and the count value output in real time by the counter 104 is smaller than the luminance signal IS1, the comparator 132 is driven at a low level. A signal DS1 is generated to drive the LED 90. If this difference is greater than or equal to the luminance signal IS1, the comparator 132 generates a high level drive signal DS1 and does not drive the LED 90.

  In the present embodiment, the size of the group channel signal GC1 (that is, the number of channels of the segment control drive element 100a) may be 16 bits, and the size of the luminance signal IS1 may be 12 bits. The serial register circuit 102 is not limited to this, but may be a 192-bit shift register (ie, 16 × 12 bits). However, this embodiment is not intended to limit the scope of the present invention.

FIG. 5 is a timing diagram of segment drive of the segment control drive element according to the first embodiment of the present invention. Referring first to FIGS. 2 and 5, the first segment is updated (ie, the first through tenth channels are driven). The identification module 103 receives the latch permission signal LE1 and the data clock signal DCLK1 at time T ₀ and outputs the first permission signal FE1. Outputs in accordance with the serial register circuits 102 when the column T ₁ through T serial data signal SD1 received at ₂ at T ₂ as a group channel signal GC1 first permission signal FE1. When the group channel signal GC1 is 1111 1111 1100 0000, the control circuit 106 receives the group channel signal GC1 and outputs 10 (that is, the first signal) in parallel.

  Next, the count register circuit 108 receives the group channel signals GC1 and 10 (that is, the first signal), and the first count data area 120 stores the group channel signal GC1. The designated channels of the first count data area 120 are the first to tenth channels. The group register module 110 receives the group channel signals GC1 and 10 (ie, the first signal), and the first group channel data area 134 stores the group channel signal GC1. The designated channels in the first group channel data area 134 are the first to tenth channels.

Identification module 103 receives a latch enable signal LE1 and the data clock signal DCLK1 at T _3, and outputs a second enable signal SE1. The serial register circuit 102 outputs the serial data signal SD1 received in the time series T _{4 to} T ₅ as the luminance signal IS1 in accordance with the second permission signal SE1. The buffer circuit 112 receives the second permission signal SE1, and transmits the luminance signal IS1 to the buffer corresponding to the designated channel (ie, the designated channel of the first group channel data region 134, ie, the first to tenth channels). Cache in the corresponding buffer). Each channel is connected to the comparison module 126. Each comparison module 126 receives the count value of the first count data area 120, then receives the count value CNT1 output from the counter 104 in real time, performs subtraction, and performs a difference. Is generated.

If this difference is less than zero, this difference is expressed in the negative complement. Next, the comparator 132 of the comparison module 126 receives the luminance signal IS1 corresponding to the channel and compares it with this difference. If the difference is less than the luminance signal IS1 corresponding to the channel, the comparator 132 outputs a low level at time T _5, and drives the LED90 connected to the channel. This achieves the purpose of driving the first to tenth channels.

  For example, when the luminance signal of the first channel is 2048, when the count value stored in the first count data area 120 is 1000 and the count value output in real time by the counter 104 is counted up from 1000, the counter 104 When the subtracter 131 subtracts the count value stored in the first count data area 120 from the count value CNT1 output in real time, the difference becomes 0, 1, 2,..., 3094, 3095 (count in real time) (The counter 104 that outputs the value counts cyclically). When the count value CNT1 output from the counter 104 in real time changes from 4095 (predetermined value) to 0, the difference becomes a negative number, and this difference is represented by a complement, that is, 3096, 3097, 3098,. That is, the difference is expressed as 0, 1, 2,..., 3094, 3095, 3096, 3097, 3098,. The rest can be deduced in the same way. Next, the comparator 132 compares this difference with 2048 of the luminance signal of the first channel. If this difference is 2048 or more, the comparator 132 outputs a high level (does not drive the LED of the first channel). If this difference is less than 2048, the comparator 132 outputs a low level (drives the LED 90 of the first channel).

  Note that the luminance signal of each channel of one group may be different, and the time length and time when the drive signal for driving the LED connected to each channel of the same group is low level may be different. However, in this embodiment, since the difference starts from zero, the time for driving the LEDs connected to each channel of the same group is the same. However, this embodiment is not intended to limit the scope of the present invention. Further, since each channel of the same group corresponds to the same count data area and the same counter, the difference received by each comparator of the same group is the same. For this reason, the LED connected to each channel of the same group is driven simultaneously after the next time.

  The timing chart of FIG. 5 is a schematic diagram of the first data update (that is, initial setting) of the segment control drive element in the present embodiment. In other words, before the first segment update of the segment control driving element 100a, the luminance signals of the first to tenth channels are zero, and before the second segment update of the segment control driving element 100a, the first to 16th channels are updated. The channel luminance signal is zero.

The second segment is updated (ie, the 11th to 16th channels are driven). Identification module 103 receives a latch enable signal LE1 and the data clock signal DCLK1 at T _6, and outputs a first enable signal FE1. Serial register circuit 102 outputs in accordance with the first permission signal FE1 serial data signal SD1 received at column T ₇ through T ₈ as a group channel signal GC1. Here, the group channel signal GC1 is 0000 0000 0011 1111 and the control circuit 106 receives the group channel signal GC1 and outputs 01 (that is, the second signal) in parallel. Next, the count register circuit 108 receives the group channel signals GC1 and 01 (that is, the second signal), and the second count data area 122 stores the group channel signal GC1. The designated channels of the second count data area 122 are the 11th to 16th channels. The group register module 110 receives group channel signals GC1 and 01 (ie, the second signal), and the second group channel data area 136 stores the group channel signal GC1. The designated channels of the second group channel data area 136 are the 11th to 16th channels.

Identification module 103 receives a latch enable signal LE1 and the data clock signal DCLK1 at T _9, and outputs a second enable signal SE1. Serial register circuit 102 outputs in accordance with the second enable signal SE1 serial data signal SD1 received at column T ₁₀ through T ₁₁ as a luminance signal IS1 (also referred to as a gray scale signal). The buffer circuit 112 receives the second permission signal SE1 and caches the luminance signal IS1 in the designated channel (ie, the designated channel of the second group channel data region 136, ie, the 11th to 16th channels).

Each channel is connected to a comparison module 126. Each comparison module 126 receives the count value in the second count data area 122 and the count value output from the counter 104 in real time, performs subtraction, and generates a difference. If this difference is less than zero, this difference is expressed in the negative complement. Next, the comparator 132 of the comparison module 126 receives the luminance signal IS1 corresponding to the channel and compares it with this difference. If the difference is less than the luminance signal IS1 corresponding to the channel, the comparator 132 outputs a low level at time T _11, drives the LED90 connected to the channel. This achieves the purpose of driving the 11th to 16th channels.

  The segment control drive elements 100a are divided into two groups for updating at different times, but this embodiment is not intended to limit the scope of the present invention. In the present embodiment, the driving sequence of the LEDs 90 arranged in an array is such that the LEDs 90 arranged in the front are first updated and driven (that is, the LEDs 90 connected to the designated channel in the first group channel data region 134). Is first updated), but this embodiment is not intended to limit the scope of the invention. For example, the LED 90 connected to the segment control drive element 100b may be updated and driven first, and then the LED 90 connected to the segment control drive element 100a may be updated and driven. While the LED 90 connected to the segment control drive element 100a is updated and driven, the LED 90 connected to the designated channel in the second group channel data area 136 is first updated and then designated in the first group channel data area 134. The LED 90 connected to the selected channel is driven to be updated.

  The segment control drive element of the present invention can divide all channels of one drive element into a plurality of groups. The number of groups in the drive element does not exceed the number of channels in the drive element. For example, the drive elements may be divided into three groups that are updated at different times. The details of the drive elements divided into three groups are illustrated below. Embodiments of drive elements that are divided into more than three groups can be deduced in a similar manner.

  FIG. 6 is a schematic circuit block diagram of a segment control drive element according to the second embodiment of the present invention. In the present embodiment, the segment control driving element 200 has 16 channels, and these channels are divided into three groups, that is, first to second channels, third to twelfth channels, and thirteenth to sixteenth channels. It has been. Each channel is connected to one corresponding LED 92, but this embodiment is not intended to limit the scope of the invention. The segment control drive element 200 includes a switch 97, a switch 99, a serial register circuit 202, an identification module 203, a counter 204, a control circuit 206, a count register circuit 208, a group register module 210, a buffer circuit 212, and a comparison circuit 214.

  The identification module 203 receives the data clock signal DCLK2 and the latch permission signal LE2. When the high level period of the latch enable signal LE2 is twice the high level period of the data clock signal DCLK2 (or the high level period of the latch enable signal LE2 includes two rising edges of the data clock signal DCLK2), the identification module 203 Outputs the first permission signal FE2. When the high level period of the latch enable signal LE2 is the same length as the high level period of the data clock signal DCLK2 (or the high level period of the latch enable signal LE2 includes one rising edge of the data clock signal DCLK2), the identification module 203 outputs a second permission signal SE2. The switch 97 is turned on according to the first permission signal FE2, and the serial register circuit 202 receives the serial data signal SDI (serial data input) and outputs the group channel signal GC2. Alternatively, the switch 99 is turned on in accordance with the second permission signal SE2, and the serial register circuit 202 receives the serial data signal SDI and outputs the luminance signal IS2 and the serial data signal SDO (serial data output). The serial data signal SDO may be transferred to the next drive element (not shown) connected in series to the segment control drive element 200.

  In the present embodiment, the latch permission signal LE2 may be a signal triggered by a falling edge, but the present embodiment is not intended to limit the scope of the present invention. That is, the latch permission signal LE2 may be a signal triggered at the rising edge. The falling edge refers to a location where a transition is made from a high level to a low level, and the rising edge refers to a location where the transition is made from a low level to a high level.

  The counter 204 cyclically counts up to a predetermined value, continuously receives the global clock signal GCLK2, and outputs the count value in real time. The global clock signal GCLK2 is an internal clock signal of the segment control drive element 200.

  When the identification module 203 outputs the second permission signal SE2, the control circuit 206 receives the group channel signal GC2 and outputs the control signal CS2. In the present embodiment, the control signal CS2 includes 100 (that is, the first signal), 010 (that is, the second signal), and 001 (that is, the third signal), but this embodiment limits the scope of the present invention. Not intended to be. The number of signals included in the control signal CS2 is determined by the number of segment groups in the channel of the actual segment control drive element 200.

  For example, when the group channel signal GC2 is 1100 0000 0000 0000, the control circuit 206 uses the group channel signal GC2 (ie, the first signal and the last signal of 1100 0000 0000 0000) to 100 (ie, the first signal). ) In parallel. When the group channel signal GC2 is 0011 1111 1111 0000, the control circuit 206 uses the group channel signal GC2 (ie, the first signal and the last signal of 0011 1111 1111 0000) to obtain 010 (ie, the second signal). Output in parallel. When the group channel signal GC2 is 0000 0000 0000 1111, the control circuit 206 uses the group channel signal GC2 (ie, the first and last signals of 0000 0000 0000 1111) to obtain 001 (ie, the third signal). Output in parallel. Although the method by which the control circuit 206 outputs the control signal CS2 according to the group channel signal GC2 includes creating a truth table in the control circuit 206, this embodiment is not intended to limit the scope of the present invention.

  When the serial register circuit 202 outputs the group channel signal GC2 in accordance with the first permission signal FE2, the count register circuit 208 sets the count value output from the counter 204 to the first count data area 220, the second count data area 222, and the third count data area 220. The count data area 224 is stored according to the first signal, the second signal, and the third signal. The designated channels of the first count data area 220 are the first to second channels, the designated channels of the second count data area 222 are the third to twelfth channels, and the third count data area 224 is designated. These channels are the thirteenth to sixteenth channels. The group register module 210 sends the group channel signal GC2 to the first group channel data region 234, the second group channel data region 236, and the third group channel data region 238 (ie, the first signal), 010 (ie, the first 2 signal) and 001 (ie, the third signal).

  The first group channel data area 234 corresponds to the first count data area 220, and the designated channels of the first group channel data area 234 are the first to second channels. The second group channel data area 236 corresponds to the second count data area 222, and the designated channels of the second group channel data area 236 are the third to twelfth channels. The third group channel data area 238 corresponds to the third count data area 224, and the designated channels of the third group channel data area 238 are the thirteenth to sixteenth channels.

  The comparison circuit 214 includes 16 comparison modules 226, and each comparison module 226 is connected to one channel. Each comparison module 226 includes a selector 230, a subtracter 231, and a comparator 232. The bit of the group channel signal GC2 stored in the first group channel data area 234, the bit of the group channel signal GC2 stored in the second group channel data area 236, and the group channel stored in the third group channel data area 238 Each selector 230 selects and outputs the count value of the first count data area 220, the count value of the second count data area 222, or the count value of the third count data area 224 according to the bit of the signal GC2. Taking the first channel as an example, the selector 230 of the comparison module 226 connected to the first channel receives the first of the group channel signal GC2 (ie, 1100 0000 0000 0000) stored in the first group channel data area 234. Bits, the first bit of the group channel signal GC2 stored in the second group channel data area 236 (ie, 0011 1111 1111 0000), and the group channel signal GC2 stored in the third group channel data area 238 (ie, 0000 0000 0000 1111) and the count value of the first count data area 220 is output. Upon receiving 100, the selector 230 outputs the count value of the first count data area 220.

  Each subtracter 231 subtracts the count value of the first count data area 220, the count value of the second count data area 222, or the count value of the third count data area 224 output from the selector 230 from the count value of the counter 204. , Output the difference. Each comparator 232 compares this difference with the luminance signal IS2 of the designated channel. If this difference is less than zero, this difference is expressed in the negative complement. When the difference between the count value stored in the first count data area 220, the second count data area 222, or the third count data area 224 and the count value output in real time by the counter 204 is smaller than the luminance signal IS2, the comparator 232 generates a low level drive signal DS2 to drive the LED 92. If this difference is greater than or equal to the luminance signal IS2, the comparator 232 generates a high level drive signal DS2 and does not drive the LED 92.

FIG. 7 is a timing diagram of segment drive of the segment control drive element according to the second embodiment of the present invention. Referring to FIGS. 6 and 7, the first segment is updated (ie, the first and second channels are driven). The identification module 203 receives the latch permission signal LE2 and the data clock signal DCLK2 at time T ₀ and outputs the first permission signal FE2. Serial register circuit 202 outputs in accordance with the first permission signal FE2 serial data signal SDI received at column T ₁ through T ₂ as a group channel signal GC2. At this time, if the group channel signal GC2 is 1100 0000 0000 0000, the control circuit 206 receives the group channel signal GC2 and outputs 100 (that is, the first signal) in parallel.

  Next, the count register circuit 208 receives the group channel signals GC2 and 100 (that is, the first signal), and the first count data area 220 stores the group channel signal GC2. The designated channels of the first count data area 220 are the first to second channels. The group register module 210 receives group channel signals GC2 and 100 (ie, the first signal), and the first group channel data area 234 stores the group channel signal GC2. The designated channels of the first group channel data area 234 are the first to second channels.

The identification module 203 receives a latch enable signal LE2 and a data clock signal DCLK2 at T _3, and outputs a second enable signal SE2. Serial register circuit 202 outputs in accordance with the second enable signal SE2 serial data signal SDI received at column T ₄ through T ₅ as the luminance signal IS2. The buffer circuit 212 receives the second permission signal SE2 and caches the luminance signal IS2 in the designated channel (ie, the designated channel of the first group channel data region 234, ie, the first to second channels). Each channel is connected to the comparison module 226. Each comparison module 226 receives the count value of the first count data area 220, then receives the count value output in real time by the counter 204, performs subtraction, and calculates the difference. Generate.

If this difference is less than zero, this difference is expressed in the negative complement. The comparator 232 of the comparison module 226 then receives the luminance signal IS2 corresponding to the channel and compares it with this difference. If the difference is less than the luminance signal IS2 corresponding to the channel, the comparator 232 outputs a low level at time T _5, and drives the LED92 connected to the channel. This achieves the purpose of driving the first and second channels.

The second segment is updated (ie, the third to twelfth channels are driven). The identification module 203 receives a latch enable signal LE2 and a data clock signal DCLK2 at T _6, and outputs a first enable signal FE2. Serial register circuit 202 outputs in accordance with the first permission signal FE2 serial data signal SDI received at column T ₇ through T ₈ as a group channel signal GC2. Here, the group channel signal GC2 is 0011 1111 1111 0000, and the control circuit 206 receives the group channel signal GC2 and outputs 010 (that is, the second signal) in parallel.

  Next, the count register circuit 208 receives the group channel signal GC2 and 010 (that is, the second signal), and the second count data area 222 stores the group channel signal GC2. The designated channels of the second count data area 222 are the third to twelfth channels. The group register module 210 receives the group channel signals GC2 and 010 (ie, the second signal), and the second group channel data area 236 stores the group channel signal GC2. The designated channels of the second group channel data region 236 are the third to twelfth channels.

The identification module 203 receives a latch enable signal LE2 and a data clock signal DCLK2 at T _9, and outputs a second enable signal SE2. Serial register circuit 202 outputs in accordance with the second enable signal SE2 serial data signal SDI received at column T ₁₀ through T ₁₁ as a luminance signal IS2 (also referred to as a gray scale signal). The buffer circuit 212 receives the second permission signal SE2 and caches the luminance signal IS2 in the designated channel (ie, the designated channel of the second group channel data region 236, ie, the third to twelfth channels).

Each channel is connected to a comparison module 226. Each comparison module 226 receives the count value in the second count data area 222 and the count value output in real time by the counter 204, performs subtraction, and generates a difference. If this difference is less than zero, this difference is expressed in the negative complement. The comparator 232 of the comparison module 226 then receives the luminance signal IS2 corresponding to the channel and compares it with this difference. If the difference is less than the luminance signal IS2 corresponding to the channel, the comparator 232 outputs a low level at time T _11, drives the LED92 connected to the channel. This achieves the purpose of driving the third to twelfth channels.

The third segment is updated (that is, the thirteenth to sixteenth channels are driven). The identification module 203 receives a latch enable signal LE2 and a data clock signal DCLK2 at T _12, and outputs a first enable signal FE2. Serial register circuit 202 outputs in accordance with the first permission signal FE2 serial data signal SDI received at column T ₁₃ through T ₁₄ as a group channel signal GC2. Here, the group channel signal GC2 is 0000 0000 0000 1111 and the control circuit 206 receives the group channel signal GC2 and outputs 001 (that is, the third signal) in parallel.

  Next, the count register circuit 208 receives the group channel signal GC2 and 001 (that is, the third signal), and the third count data area 224 stores the group channel signal GC2. The designated channels of the third count data area 224 are the thirteenth to sixteenth channels. The group register module 210 receives the group channel signal GC2 and 001 (that is, the third signal), and the third group channel data area 238 stores the group channel signal GC2. The designated channels of the third group channel data region 238 are the thirteenth to sixteenth channels.

The identification module 203 receives a latch enable signal LE2 and a data clock signal DCLK2 at time T _15, and outputs a second enable signal SE2. Serial register circuit 202 outputs in accordance with the second enable signal SE2 serial data signal SDI received at column T ₁₆ through T ₁₇ as a luminance signal IS2 (also referred to as a gray scale signal). The buffer circuit 212 receives the second permission signal SE2 and caches the luminance signal IS2 in the designated channel (ie, the designated channel of the third group channel data region 238, ie, the 13th to 16th channels).

Each channel is connected to a comparison module 226. Each comparison module 226 receives the count value in the third count data area 224 and the count value output in real time by the counter 204, performs subtraction, and generates a difference. If this difference is less than zero, this difference is expressed in the negative complement. The comparator 232 of the comparison module 226 then receives the luminance signal IS2 corresponding to the channel and compares it with this difference. If the difference is less than the luminance signal IS2 corresponding to the channel, the comparator 232 outputs a low level at time T _17, drives the LED92 connected to the channel. This achieves the purpose of driving the thirteenth to sixteenth channels.

  The timing chart of FIG. 7 is a schematic diagram of the first data update (that is, initial setting) of the drive element in the present embodiment. In other words, before the first segment update of the segment control drive element 200, the luminance signals of the first and second channels are zero, and before the second segment update of the segment control drive element 200, the third to twelfth channels. The luminance signal of the channel is zero, and the luminance signals of the thirteenth to sixteenth channels are zero before the segment control driving element 200 updates the third segment.

  In the second embodiment, the driving sequence of the LED 92 is such that the LED 92 connected to the designated channel of the first group channel data area 234 is first updated and then the designated channel of the second group channel data area 236 is designated. The LED 92 connected to is updated and driven, and finally the LED 92 connected to the designated channel of the third group channel data area 238 is updated, but this embodiment is intended to limit the scope of the present invention. However, it may be adjusted according to the actual situation. For example, the driving sequence of the LED 92 is such that the LED 92 connected to the designated channel in the third group channel data region 238 is first updated and then the LED 92 connected to the designated channel in the second group channel data region 236. May be updated and finally the LED 92 connected to the designated channel of the first group channel data region 234 may be updated. More specifically, in the drive sequence of the LED 92, the LED 92 connected to the 13th to 16th channels of the segment control drive element 200 is first updated and then connected to the 3rd to 12th channels of the segment control drive element 200. The updated LED 92 is driven to update, and finally, the LED 92 connected to the first to second channels of the segment control driving element 200 is driven to update.

  The segment control drive element of the present invention is applied to an LCD using an LED as a backlight. By using a count register circuit, control signals, and group channel signals, the drive element can update one data at different times and even one individually to allow it to be updated individually. Only a counter and a plurality of count data areas are required. The serial register circuit then uses the group register module to control the channel designated to store the serial data signal received as a luminance signal, so that only the designated channel updates the luminance signal and specifies A channel that is not done guarantees its original state. Moreover, since all the channels of each drive element are used due to the above structure of the drive elements, the problem of waste due to the presence of unused channels is solved.

100a, 100b Segment control LED drive element 96, 98 Switch 102 Serial register circuit 103 Identification module 104 Counter 106 Control circuit 108 Count register circuit 110 Group register module 112 Buffer circuit 114 Comparison circuit 120 First count data area 122 Second count data area 126 Comparison module 134 First group channel data area 136 Second group channel data area

Claims (8)

A segment control light emitting diode (LED) drive element adapted to drive a plurality of LEDs arranged in an array, the segment control drive element receiving a data clock signal, a latch enable signal, and a serial data signal A drive signal for controlling the luminous intensity of the LED,
An identification module that receives the data clock signal and the latch permission signal, identifies the latch permission signal, and selectively outputs the first permission signal or the second permission signal;
A serial register circuit that receives the serial data signal and selectively outputs a group channel signal or a luminance signal according to the first permission signal or the second permission signal;
A counter that continuously receives a global clock signal, cyclically counts to a predetermined value, and outputs the count value in real time;
A control circuit for receiving the group channel signal and outputting a control signal;
A count register having a plurality of count data areas each having one or more designated channels, and storing the count value in one of the count data areas when the first permission signal and the control signal are received Circuit,
A plurality of group channel data areas respectively corresponding to the plurality of count data areas, and storing the group channel signal in one of the group channel data areas when the first permission signal and the control signal are received; A group register module;
A buffer circuit that caches the luminance signal in the designated channel when the second permission signal is received;
A comparison circuit that receives the count value stored in the count data area, the count value that the counter outputs in real time, and the luminance signal and outputs the drive signal;
A segment control LED drive element, wherein each count data area and the group channel data area corresponding to the count data area have the same designated channel.   The control signal includes a first signal, a second signal, and a third signal. When the serial register circuit outputs the group channel signal according to the first permission signal, the count register circuit counts the counter output by the counter. A value is stored in the first count data area, the second count data area, and the third count data area in accordance with the first signal, the second signal, and the third signal, and the first count data area and the second count data area The segment control LED driving element according to claim 1, wherein each of the third count data areas has one or more designated channels.   The group register module stores the group channel signal in a first group channel data region, a second group channel data region, and a third group channel data region according to the first signal, the second signal, and the third signal, The count data area corresponds to one of the group channel data areas, and each count data area and the group channel data area corresponding to the count data area have the same designated channel. Segment control LED drive element.   The comparison circuit includes a plurality of comparison modules, each comparison module having one designated channel, the count value of the first count data area, the count value of the second count data area, and the first 3 count data area count value, 1 bit of group channel signal of the first group channel data area, 1 bit of group channel signal of the second group channel data area, and group of the third group channel data area Receives one bit of channel signal, the count value output in real time by the counter, and the luminance signal of the designated channel of the comparison module, and outputs a drive signal to the LED connected to the designated channel The segment control LED driving element according to claim 2.   Each comparison module includes a selector, a subtracter, and a comparator, and each selector has a count value in the first count data area, a count value in the second count data area, or a count value in the third count data area. In accordance with 1 bit of the group channel signal in the first group channel data area, 1 bit of the group channel signal in the second group channel data area, and 1 bit of the group channel signal in the third group channel data area. The subtracters subtract the count value of the first count data area, the count value of the second count data area, or the count value of the third count data area output from the selector from the count value of the counter. , Output a difference, and each comparator outputs the difference to the specified channel. Segment control LED driving device according to claim 4, compared to the degree signal.   When the difference is less than the luminance signal of the designated channel, the LED is driven by the segment control LED driver, and when the difference is greater than or equal to the luminance signal of the designated channel, the LED is The segment control LED drive element according to claim 5, which is not driven by the segment control LED drive element.   The segment control LED driving element according to claim 1, wherein the identification module outputs the first permission signal when the period of the latch permission signal is twice the period of the data clock signal.   The segment control LED driving element according to claim 1, wherein the identification module outputs the second permission signal when the period of the latch permission signal is the same as the period of the data clock signal.

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