JP2012008630A - Serial memory control system, method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a serial memory control system, method and program for, when a serial memory controller is reset in any mode other than an initially set address mode, achieving the matching of modes with a serial memory having no reset terminal.SOLUTION: When it is detected that a serial memory controller 12 has been reset by reset detection means 13, a serial memory 11 is restarted by using restart means 14. When a clock for achieving synchronization is disconnected, the serial memory 11 may be restarted.

Description

  The present invention relates to a serial memory control system, a serial memory control method, and a serial memory control program for controlling reading and writing of a serial memory. The present invention particularly relates to a serial memory control system, a serial memory control method, and a serial memory control program suitable for using a serial memory that can be used by switching the number of constituent bytes of an address as a data storage location.

  A system having both a serial memory and a serial memory controller that controls reading and writing of data is referred to as a serial memory control system in this specification.

  FIG. 10 shows the configuration of a serial memory control system in the first related art proposed in the past. The serial memory control system 100 includes a serial memory controller 101 and a serial memory 102.

  The serial memory controller 101 is a device that controls reading and writing of data with respect to the serial memory 102. The serial memory controller 101 often takes a form of being built as an SOC (System-on-a-chip) on one semiconductor chip as a peripheral circuit together with a CPU (Central Processing Unit).

  The serial memory controller 101 communicates with the serial memory 102 using a CS (Chip Select) signal 111, a CLK (clock) signal 112, an SI (Serial Input) signal 113, and an SO (Serial Output) signal 114. Here, the CS signal 111 is a signal for the serial memory controller 101 to select a specific memory. When the CS signal 111 is activated by the serial memory controller 101, the serial memory 102 enters a communication standby state.

  The CLK signal 112 is a clock signal and is sent from the serial memory controller 101 to the serial memory 102. The serial memory 102 reads / writes data (Read and Write) in synchronization with the CLK signal 112.

  The SI signal 113 is a serial input signal and is used for receiving a command, an address, and data. The SO signal 114 is used for data transmission from the serial memory 102.

  FIG. 11 shows an example of a serial communication format in the 3-byte address mode in the first related technology. Here, the 3-byte address mode is an addressing mode in which an address is designated by 3 bytes.

  In the write operation shown in FIG. 6A, when the CS signal 111 shown in FIG. 4A changes from the H (high) level to the L (low) level, the write operation shown in FIG. Transmission of the CLK signal 112 from the serial memory controller 101 to the serial memory 102 is started. The numbers starting from “0” shown in FIG. 5B are serial numbers from the start of output of the CLK signal 112.

  In the field in which the CLK signal 112 in FIG. 7B outputs a clock from “0” to “7”, the command for designating the write operation is the SI signal 113 as shown in FIG. The data is sent from the controller 101 to the serial memory 102. Thereafter, an SI signal 113 for designating an address by 3 bytes is sent to the serial memory 102. After the end of the addressing mode, write data is sent from the serial memory controller 101 to the serial memory 102 as the SI signal 113.

 FIG. 11B shows various signals during a read operation. When the CS signal 111 shown in FIG. 6D changes from the H (high) level to the L (low) level, the CLK signal 112 shown in FIG. 5E is sent from the serial memory controller 101 to the serial memory 102. Be started.

  As a result, in the field in which the CLK signal 112 outputs a clock from “0” to “7”, the command specifying the read operation is the SI signal 113 as shown in FIG. It is sent to the serial memory 102. Thereafter, an SI signal 113 for designating an address by 3 bytes is sent to the serial memory 102. After completion of the addressing mode, read data designated as the SO signal 114 is sent from the serial memory 102 to the serial memory controller 101 as shown in FIG.

  Incidentally, the capacity of the serial memory 102 used in the first related technology is 128 megabits, that is, 16 megabytes or less. If the capacity of the serial memory 102 is 16 megabytes, 24-bit address information is required for address designation. For this reason, a 3-byte address field has been defined in the SI signal 113. This is called the 3-byte address mode.

  However, since then, there has been a market demand for capacity expansion for the serial memory 102, and for example, a memory of 256 megabits or more has been developed. When the serial memory 102 has a capacity of 256 megabits or more, addressing of 25 bits or more is required to access the latter 128 megabits. For this reason, in the 3-byte address mode used in the first related technique, it is impossible to specify the address for the data stored in the serial memory 102.

  In order to solve such a problem, a second related technique has been proposed. In the second related technique, the address field is further expanded by 1 byte to 4 bytes. Such an access method is referred to as a 4-byte address mode.

  FIG. 12 shows a normal startup sequence in the serial memory control device adopting the second related technique. The serial memory control system 100A includes a serial memory controller 101A having both a 3-byte address mode and a 4-byte address mode, and a serial memory 102A having a memory capacity of 128 megabits or more. ing.

  The serial memory controller 101A is compatible with the serial memory 102 (see FIG. 10) having a memory capacity of 128 megabits. For this reason, the serial memory 102A is activated in the 3-byte address mode together with the serial memory controller 101A (step S201).

  In the 3-byte address mode, an address can be specified only up to a capacity of 128 megabits for the serial memory 102A. Therefore, when designating an address in a 256 megabit address area, the serial memory controller 101 transmits a command to shift to the 4-byte address mode to the serial memory 102A (step S202).

  When the serial memory 102A receives this shift command to the 4-byte address mode, the serial memory 102A shifts to the 4-byte address mode (step S203), the address field is expanded to 4 bytes, and communication starts. The serial memory controller 101 transmits a transition command to the 4-byte address mode in step S202, and then transitions to the 4-byte address mode (step S204). Therefore, thereafter, communication in the 4-byte address mode becomes possible between the serial memory controller 101A and the serial memory 102A (step S205).

  This second related technique has a problem that normal communication with the serial memory 102A may not be possible if the serial memory controller 101A after shifting to the 4-byte address mode is reset for some reason. It was.

  FIG. 13 is a diagram for explaining a problem caused by resetting a serial memory controller employing the second related technology. In FIG. 13, the same parts as those in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In step S203 described with reference to FIG. 12, the serial memory 102A shifts to the 4-byte address mode, and in step S204, the serial memory controller 101A also shifts to the 4-byte address mode. Therefore, thereafter, as shown in step S205, communication in the 4-byte address mode becomes possible between the serial memory controller 101A and the serial memory 102A.

  Assume that the serial memory controller 101A is reset for some reason in a state where communication in the 4-byte address mode is possible (step S206). Then, after the reset is released, the serial memory controller 101A returns to the initial state again and starts operation in the 3-byte address mode (step S207).

  On the other hand, the serial memory 102A remains in the 4-byte address mode shifted in step S203. As a result, the operation modes of the serial memory controller 101A and the serial memory 102A are inconsistent (step S208), and there is a possibility that normal communication cannot be performed.

  FIG. 14 is a diagram for explaining the reason why normal communication cannot be performed when a mismatch occurs in the operation mode. This will be described with reference to FIG.

  FIG. 14A shows a write operation for the serial memory 102A. The serial memory controller 101A is in a 3-byte address mode after reset as shown in FIG. On the other hand, the serial memory 102A is in a 4-byte address mode as shown in FIG.

  For this reason, a command is output from the serial memory controller 101A at the first byte where communication is started (see FIG. 11C), and the serial memory 102A is also subjected to a write operation. Recognize The serial memory controller 101A transmits address information in the 3-byte address mode with the next 3 bytes from the second byte to the fourth byte.

  However, the serial memory 102A recognizes that it is in the 4-byte address mode. Therefore, the serial memory 102A recognizes up to the first write data of the fifth byte as an address. As a result, the serial memory 102A recognizes an address that is completely different from the address designated by the serial memory controller 101A with 3 bytes. In addition, since the first write data is erroneously recognized as an address (NG: No Good) and the second write data is recognized as write data, the data written to the serial memory 102A is also different. It will be.

  On the other hand, FIG. 14B shows a read operation from the serial memory 102A. Also in this case, the serial memory controller 101A is in the 3-byte address mode after reset as shown in FIG. On the other hand, the serial memory 102A is in a 4-byte address mode as shown in FIG.

  Therefore, the serial memory controller 101A designates an address using 3 bytes from the second byte to the fourth byte in order to read data from the serial memory 102A. However, since the serial memory 102A recognizes that it is in the 4-byte address mode, the address is recognized using 4 bytes from the second byte to the fifth byte. As a result, the address to be read becomes an unexpected address of the serial memory controller 101A. The serial memory controller 101A inputs data as read data from the 5th byte, but the serial memory 102A outputs read data from the 6th byte. It will be different.

  Therefore, as a third related technique for solving such a problem, a technique has been proposed in which a main microcomputer sends a reset release signal for forcibly releasing a reset to a sub microcomputer in a predetermined case. (For example, refer to Patent Document 1). If the main microcomputer is the serial memory control system 100A and the sub microcomputer is the serial memory 102A in the third related technique, the serial memory 102A can be operated in the original 3-byte address mode.

  However, the serial memory 102A does not include a reset terminal. For this reason, the serial memory 102A cannot be reset or released from the serial memory controller 101A, and it is impossible to prevent the occurrence of problems due to mode mismatch using the third related technique.

JP 2000-235487 A (paragraph 0048, FIG. 1)

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a serial mode capable of matching the mode with a serial memory having no reset terminal when the serial memory controller is reset in an address mode other than the initially set address mode. To provide a memory control system, method and program.

  In the present invention, (b) a serial memory that reads / writes serial data in synchronization with the clock; (b) a serial memory controller as a circuit that reads / writes data from / to the serial memory; A serial memory control system comprises reset detection means for detecting when the memory controller is reset, and (d) restart means for restarting the serial memory when the reset detection means detects reset. To do.

  In the present invention, (a) the serial memory controller as a circuit for reading / writing data to / from the serial memory for reading / writing serial data in synchronization with the clock without resetting the physical reset terminal itself is reset. (B) a serial memory control method comprising: (b) a restart step for restarting the serial memory when a reset of the serial memory controller is detected in the reset detection step. Comprise.

  Further, in the present invention, (a) a serial memory controller as a circuit for reading and writing data to and from a serial memory that does not have a physical reset terminal itself and that reads and writes serial data in synchronization with a clock A clock disconnection detecting step for detecting the disconnection of the synchronization clock transmitted to the memory; and (b) the serial memory described above when the disconnection of the synchronization clock is detected in the clock disconnection detecting step. The serial memory control method includes a restarting step for restarting.

  Furthermore, according to the present invention, as a serial memory control program in a computer, (a) reading / writing data to / from a serial memory that does not have a physical reset terminal and reads / writes serial data in synchronization with a clock. A reset detection process for detecting when the serial memory controller as a circuit is reset; and (b) restarting the serial memory when a reset of the serial memory controller is detected in the reset detection process. It is characterized by executing a restart process.

  In the present invention, as a serial memory control program in a computer, (a) a circuit for reading / writing data from / to a serial memory that does not have a physical reset terminal itself and reads / writes serial data in synchronization with a clock A clock loss detection process in which the serial memory controller detects the disconnection of the synchronization clock transmitted to the serial memory, and (b) the synchronization clock transmission interruption described in the clock loss detection process. And a restart process for restarting the serial memory at the time when the error is detected.

  As described above, according to the present invention, when the serial memory controller is reset, the power supply to the serial memory is controlled to restart the serial memory. As a result, the serial memory controller and the serial memory are each in the initial address mode, and the communication abnormality due to the mismatch of the address modes can be easily eliminated.

It is a claim corresponding | compatible figure of the serial memory control system of this invention. It is a claim corresponding | compatible figure of the serial memory control method of this invention. It is a claim corresponding | compatible figure of the other serial memory control method of this invention. It is a claim correspondence diagram of the serial memory control program of the present invention. It is a claim corresponding | compatible figure of the other serial memory control program of this invention. 1 is a system configuration diagram showing a configuration of a serial memory control system in an embodiment of the present invention. It is a flowchart showing the process of the serial memory control system after the power supply of SOC of this Embodiment is turned on. It is a system block diagram showing the structure of the serial memory control system in the modification of this invention. It is a flowchart showing the process of the serial memory control system after the power supply of SOC of this modification is turned on. It is a system block diagram showing the structure of the serial memory control system in the 1st related technique proposed conventionally. It is the timing figure which showed an example of the format of the serial communication at the time of 3 byte address mode in 1st related technology. It is explanatory drawing which showed the normal starting sequence in the serial memory control apparatus which employ | adopted the 2nd related technique. It is explanatory drawing which showed the problem which arises by reset of the serial memory controller which employ | adopted the 2nd related technique. It is explanatory drawing which shows the reason why normal communication cannot be performed when the second related technology is employed and a mismatch occurs in the operation mode.

  FIG. 1 shows a claim correspondence diagram of the serial memory control system of the present invention. The serial memory control system 10 according to the present invention includes a serial memory 11, a serial memory controller 12, a reset detection unit 13, and a restart unit 14. Here, the serial memory 11 reads and writes serial data in synchronization with the clock. The serial memory controller 12 is a circuit that reads and writes data from and to the serial memory 11. The reset detecting means 13 detects when the serial memory controller 12 is reset. The restarting means 14 restarts the serial memory 11 described above when the reset detecting means 13 detects a reset.

  FIG. 2 is a diagram corresponding to the claims of the serial memory control method of the present invention. The serial memory control method 20 of the present invention includes a reset detection step 21 and a restart step 22. Here, in the reset detection step 21, the serial memory controller as a circuit for reading / writing data from / to the serial memory that does not have a physical reset terminal itself and that reads / writes serial data in synchronization with the clock is reset. This is detected when In the restart step 22, when the reset of the serial memory controller is detected in the reset detection step 21, the serial memory is restarted.

  FIG. 3 shows a claim correspondence diagram of another serial memory control method of the present invention. Another serial memory control method 30 of the present invention includes a clock loss detection step 31 and a restart step 32. Here, in the clock interruption detection step 31, the serial memory controller as a circuit for reading / writing data to / from the serial memory that does not have a physical reset terminal itself and that reads / writes serial data in synchronization with the clock is described above. The disconnection of the synchronization clock transmitted to the serial memory is detected. In the restart step 32, the serial memory is restarted at the time when the clock disconnection detection step 31 detects the disconnection of the synchronization clock.

  FIG. 4 shows a claim correspondence diagram of the serial memory control program of the present invention. The serial memory control program 40 of the present invention causes a computer to execute a reset detection process 41 and a restart process 42. Here, in the reset detection processing 41, the serial memory controller as a circuit for reading / writing data to / from the serial memory that does not have a physical reset terminal and that reads / writes serial data in synchronization with the clock is reset. This is detected when In the restart process 42, when the reset of the serial memory controller is detected in the reset detection process 41, the serial memory is restarted.

  FIG. 5 shows a claim correspondence diagram of another serial memory control program of the present invention. Another serial memory control program 50 of the present invention causes the computer to execute a clock loss detection process 51 and a restart process 52. Here, in the clock loss detection processing 51, the serial memory controller as a circuit for reading / writing data from / to the serial memory that does not have a physical reset terminal itself and that reads / writes serial data in synchronization with the clock is described above. The disconnection of the synchronization clock transmitted to the serial memory is detected. In the restart process 52, the serial memory is restarted when the clock disconnection detection process 51 detects the disconnection of the synchronization clock.

  <Embodiment of the Invention>

  Next, an embodiment of the present invention will be described.

  FIG. 6 shows the configuration of the serial memory control system according to the embodiment of the present invention. The serial memory control system 300 according to the present embodiment includes an SOC (System-on-a-chip) 301 and a serial memory 302, a reset signal detection unit 303, and a power supply unit 304.

  Among these, the SOC 301 is an integrated circuit in which a series of required functions are integrated on one semiconductor chip, and in this embodiment, a serial memory controller 311 and a reset signal transmission unit 312 are incorporated. The serial memory 302 includes a power supply terminal 321 for supplying power to the serial memory 302.

  The serial memory controller 311 performs communication with the serial memory 302 using a CS (Chip Select) signal 331, a CLK (clock) signal 332, an SI (Serial Input) signal 333, and an SO (Serial Output) signal 334. The CS signal 331 is a signal for the serial memory controller 101 to select a specific memory. When the CS signal 331 is activated by the serial memory controller 311, the serial memory 302 enters a communication standby state.

  The CLK signal 332 is a clock signal and is sent from the serial memory controller 311 to the serial memory 302. The serial memory 302 reads and writes data (Read and Write) in synchronization with the CLK signal 332.

  The SI signal 333 is a serial input signal and is used for receiving a command, an address, and data. The SO signal 334 is used for data transmission from the serial memory 302.

  The reset signal sending unit 312 outputs a reset signal 341 according to the apparatus state. When the reset signal 341 is output from the reset signal sending unit 312, the reset signal detection unit 303 detects this and outputs a power control signal 342. The power supply unit 304 detects the voltage level of the power supply control signal 342 and controls the supply of the power supply 343 to the serial memory 302 according to this. The serial memory 302 is activated and operates as a memory when a power supply 343 having a predetermined voltage is supplied to the power supply terminal 321.

  Here, the reset signal sending unit 312 outputs an L level reset signal 341L in a state where the power of the SOC 301 is turned off and a state where the serial memory controller 311 is reset. The reset signal transmission unit 312 outputs an H level reset signal 341H in a state where the reset of the serial memory controller 311 is cancelled.

  The reset signal detection unit 303 detects the voltage level of the reset signal 341 from the reset signal transmission unit 312. As a result, when the reset signal 341H is at the H level, the power control signal 342H at the H level is output. When the reset signal 341L is at L level, the power control signal 342L at L level is output.

  When the power supply unit 304 receives the H level power control signal 342 </ b> H, the power supply unit 304 supplies the power 343 to the power terminal 321 of the serial memory 302. When the power supply unit 304 receives the L-level power control signal 342L, the supply of power to the power terminal 321 is stopped.

  The control of the reset signal detection unit 303 and the power supply unit 304 based on the logic state of the reset signal 341 output from the reset signal transmission unit 312 described above is performed according to a predetermined procedure. When the reset signal detection unit 303 and the power supply unit 304 are incorporated in the SOC 301, the CPU incorporated in the SOC 301 can perform such control based on a predetermined control program. The reset signal detection unit 303 and the power supply unit 304 can be easily configured as external components of the SOC 301 by using transistors or switching elements such as FETs (Field Effect Transistors).

  FIG. 7 shows a process flow of the serial memory control system after the SOC power is turned on. This will be described with reference to FIG.

  Assume that the SOC 301 is normally activated by a power source (not shown) (start). As a result, the reset signal sending unit 312 built in the SOC 301 outputs an H level reset signal 341H. The reset signal detection unit 303 performs detection processing of the reset signal 341 (step S401), and determines whether this is the H level reset signal 341H (step S402). If the reset signal is 341H (Y), the output power control signal 342 is set to H level (step S403). The power control signal 342H is supplied to the power supply unit 304, and the H level power supply 343H starts to be supplied to the power supply terminal 321 (step S404).

  Thus, when the SOC 301 starts normally, the serial memory controller 311 enters the 3-byte address mode at the first time, and the serial memory 302 also enters the 3-byte address mode when the power is turned on. Therefore, the serial memory controller 311 and the serial memory 302 have the same operation mode.

  Thereafter, the processing returns to step S401, but the reset signal sending unit 312 outputs the reset signal 341H of H level in a state where the serial memory controller 311 is not reset. Therefore, as long as the serial memory controller 311 does not reset, the H level power supply 343H is supplied to the power supply terminal 321. In this state, the serial memory controller 311 and the serial memory 302 communicate in the 3-byte address mode using the CS signal 331, the CLK signal 332, the SI signal 333, and the SO signal 334, and can shift to the 4-byte address mode. It is.

  Thereafter, it is assumed that the serial memory controller 311 is reset by the SOC 301 after the power is turned on for some reason. When the serial memory controller 311 is reset, the reset signal sending unit 312 outputs an L level reset signal 341L. The reset signal detection unit 303 detects this change (step S401), and determines whether the reset signal 341 is at the H level (step S402). In this case, since it is at the L level (N), the reset signal detection unit 303 outputs the L level power supply control signal 342L (step S405).

  When the power supply unit 304 receives the L-level power control signal 342L, the power supply unit 304 stops supplying the power that has been supplied to the power terminal 321 when the H-level power control signal 342H has been input (step S406). ). And it returns to the process of step S401 again. Therefore, in a state where the L level reset signal 341L is output from the reset signal sending unit 312, the state where the power supply to the serial memory 302 is stopped is held.

  Thereafter, it is assumed that the reset of the serial memory controller 311 is released at a predetermined time. Then, the reset signal sending unit 312 switches from the output of the L level reset signal 341L to the output of the H level reset signal 341H. The reset signal detection unit 303 detects this change (step S401), and determines whether the reset signal 341 is at the H level (step S402). In this case, since it is at the H level (Y), the reset signal detection unit 303 outputs the H level power supply control signal 342H (step S403). The power control signal 342H is supplied to the power supply unit 304, and the H level power supply 343H starts to be supplied to the power supply terminal 321 (step S404).

  As a result, the serial memory 302 is activated. The serial memory 302 operates in the initial 3-byte address mode at the time of activation. At this time, the serial memory controller 311 also starts operation in the initial 3-byte address mode by reset. Therefore, the serial memory controller 311 and the serial memory 302 have the same operation mode.

  As described above, even if the serial memory controller 311 and the serial memory 302 operate in the 3-byte address mode, or after that both operate in the 4-byte address mode, the serial memory controller 311 is reset. Then, the power supply of the serial memory 302 is cut off once. For this reason, when the reset of the serial memory controller 311 is subsequently released, the serial memory controller 311 and the serial memory 302 start operation again in the 3-byte address mode as an initial state. For this reason, it is possible to prevent the occurrence of communication abnormality due to the operation mode mismatch between the serial memory controller 311 and the serial memory 302.

  As described above, according to this embodiment, when the serial memory controller 311 is reset, the power of the serial memory 302 is once turned off and restarted. As a result, the operation mode mismatch between the serial memory controller 311 and the serial memory 302 does not occur, and erroneous recognition of address information can be prevented.

  In the present embodiment, the reset signal detection unit 303 and the power supply unit 304 are provided externally to the SOC 301 to control the power supply of the serial memory 302. As a result, there is an advantage that even if the memory address becomes 4 bytes or more, it is not necessary to change the software.

  <Modification of the invention>

  FIG. 8 shows the configuration of a serial memory control system according to a modification of the present invention. In FIG. 8, the same parts as those in FIG. 6 of the previous embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The serial memory control system 300 </ b> A according to this modification includes an SOC 301 </ b> A, a serial memory 302, a clock (CLK) disconnection detection unit 501, and a power supply unit 304. Here, the SOC 301A does not include the reset signal sending unit 312 shown in FIG. For this reason, the serial memory control system 300A does not include the reset signal detection unit 303 illustrated in FIG. 6, but includes a clock loss detection unit 501 instead. The clock disconnection detection unit 501 receives the CLK signal 332 and detects the disconnection.

  That is, in the serial memory control system 300A of the modified example, the CLK signal 332 output from the serial memory controller 311 is used as a technique for detecting the reset of the serial memory controller 311. The CLK signal 332 is a synchronization signal for synchronizing communication between the serial memory controller 311 and the serial memory 302. Therefore, if the circuit is configured such that the CLK signal 332 stops when the serial memory controller 311 is reset, this reset can be detected.

  Therefore, the clock disconnection detecting unit 501 always inputs the CLK signal 332, and when the input of the CLK signal 332 is interrupted, the logic of the power control signal 342 is changed from H level to L level. The clock loss detection unit 501 can be realized with a known circuit configuration using, for example, a general-purpose logic IC (Integrated Circuit). The power supply unit 304 that receives the power control signal 342 from the clock loss detection unit 501 can be configured as the same circuit as in the previous embodiment.

  FIG. 9 shows the flow of processing of the serial memory control system after the SOC power is turned on in this modification. This will be described with reference to FIG.

  Assume that the SOC 301A is normally activated by a power source (not shown) (start). Then, transmission of the CLK signal 332 from the serial memory controller 311 to the serial memory 302 is started as described with reference to FIG. This CLK signal 332 is also input to the clock loss detection unit 501.

  When the clock loss detection unit 501 periodically detects the CLK signal 332, the clock loss detection unit 501 holds the logic of the power control signal 342 at the H level. On the other hand, if a state in which the CLK signal 332 does not arrive even after a predetermined time that can be expected from the period appears, the clock loss detection unit 501 assumes that the serial memory controller 311 has been reset and the power supply control signal 342 The logic is switched from H level to L level.

  Therefore, the clock loss detection unit 501 determines whether or not the CLK signal 332 is periodically input (step S601), and if it is detected periodically (Y), the H level power control signal 342H. Is output (step S602). The power control signal 342H is supplied to the power supply unit 304. As a result, the H level power supply 343H starts to be supplied to the power supply terminal 321 (step S603).

  Thus, when the SOC 301 starts normally, the serial memory controller 311 enters the 3-byte address mode at the first time, and the serial memory 302 also enters the 3-byte address mode when the power is turned on. Therefore, the serial memory controller 311 and the serial memory 302 have the same operation mode.

  Thereafter, the process returns to step S601, but the CLK signal 332 is continuously output in a state where the serial memory controller 311 is not reset. Therefore, as long as the serial memory controller 311 does not reset, the H level power supply 343H is supplied to the power supply terminal 321. In this state, the serial memory controller 311 and the serial memory 302 communicate in the 3-byte address mode using the CS signal 331, the CLK signal 332, the SI signal 333, and the SO signal 334, and can shift to the 4-byte address mode. It is.

  Thereafter, it is assumed that the serial memory controller 311 is reset by the SOC 301 after the power is turned on for some reason. When the serial memory controller 311 is reset, the output of the CLK signal 332 is stopped at this time (step S601: N). Accordingly, the clock loss detection unit 501 changes the power supply control signal 342 from the H level to the L level when a slight time has elapsed since this time (step S604).

  When the power supply unit 304 receives the L-level power supply control signal 342L, the power supply unit 304 stops supplying the power that has been supplied to the power supply terminal 321 when the H-level power supply control signal 342H has been input (step S605). ). And it returns to the process of step S601 again. Therefore, in a state where the L-level power control signal 342L is output from the clock disconnection detection unit 501, the state where the power supply to the serial memory 302 is stopped is held.

  Thereafter, it is assumed that the reset of the serial memory controller 311 is released at a predetermined time. Then, the output of the CLK signal 332 is started from the serial memory controller 311 (step S601: Y), and the clock loss detection unit 501 that inputs this outputs the power control signal 342H of H level again (step S602). The power supply control signal 342H is supplied to the power supply unit 304, and the H level power supply 343H starts to be supplied to the power supply terminal 321 (step S603).

  As a result, the serial memory 302 is activated. The serial memory 302 operates in the initial 3-byte address mode at the time of activation. At this time, the serial memory controller 311 also starts operation in the initial 3-byte address mode by reset. Therefore, the serial memory controller 311 and the serial memory 302 have the same operation mode.

  As described above, according to the serial memory control system 300A of this modified example, even if the SOC 301A does not include the dedicated reset signal transmission unit 312 (see FIG. 6) for the serial memory controller 311, the CLK signal 332 The serial memory 302 can be restarted by detecting a reset by disconnection. Therefore, it is possible to prevent the occurrence of an address mode mismatch between the serial memory controller 311 and the serial memory 302 without using a special configuration of the SOC 301A.

  In the embodiment and the modification described above, the CPU exists only on the SOCs 301 and 301A side, but the present invention is not limited to this. For example, there may be a CPU that controls the entire serial memory control system 300, 300A, and this CPU controls the restart of the serial memory by a predetermined serial memory control program.

  Some or all of the embodiments described above are described as in the following supplementary notes, but are not limited to the following descriptions.

(Appendix 1)
A serial memory that reads and writes serial data in synchronization with the clock;
A serial memory controller as a circuit for reading and writing data to and from this serial memory;
Reset detecting means for detecting when the serial memory controller is reset;
A serial memory control system comprising: restarting means for restarting the serial memory when the reset detecting means detects a reset.

(Appendix 2)
The serial memory has an address mode between a first address mode in which an address is represented by a specific number of bytes initially set and a second address mode in which an address is represented by a number of bytes different from the first address mode. The serial memory control system according to appendix 1, further comprising a migration command receiving means for receiving a migration command for migrating the data.

(Appendix 3)
The restarting means is means for turning off the power of the serial memory when the serial memory controller is reset and turning on the power of the serial memory when the reset is released. The serial memory control system described.

(Appendix 4)
The restarting means turns off the power of the serial memory when the clock signal supplied to the serial memory from the serial memory controller is cut off, and turns on the power of the serial memory when the supply of the clock signal is started. The serial memory control system according to appendix 1, wherein the serial memory control system is a means for turning on the device.

(Appendix 5)
Additional note 1 wherein the serial memory controller and reset signal sending means for detecting the reset of the serial memory controller and inverting the logic of a signal to be output are formed on one semiconductor chip. Serial memory control system.

(Appendix 6)
The first address mode is a 3-byte address mode in which addresses are communicated in a 3-byte configuration, and the second address mode is a 4-byte address mode in which addresses are communicated in a 4-byte configuration. The serial memory control system described.

(Appendix 7)
The serial memory control system according to claim 1, wherein the serial memory does not include a physical reset terminal.

(Appendix 8)
Reset detection step that detects when the serial memory controller as a circuit that reads and writes data to and from the serial memory that does not have a physical reset terminal itself and that reads and writes serial data in synchronization with the clock is reset When,
A serial memory control method comprising: a restarting step of restarting the serial memory when the reset of the serial memory controller is detected in the reset detecting step.

(Appendix 9)
The serial memory controller as a circuit for reading / writing data to / from the serial memory that reads / writes serial data in synchronization with the clock without itself having a physical reset terminal itself A clock loss detection step for detecting a transmission interruption;
A serial memory control method comprising: a restarting step of restarting the serial memory at the time when the clock disconnection detecting step detects the disconnection of the synchronization clock.

(Appendix 10)
The serial memory control method according to appendix 8 or 9, wherein the restarting step is a power supply control step of temporarily interrupting and restarting power supply to the power supply terminal of the serial memory.

(Appendix 11)
On the computer,
Reset detection processing that detects when a serial memory controller is reset as a circuit that reads and writes data to and from serial memory that reads and writes serial data in synchronization with the clock without itself having a physical reset terminal When,
A serial memory control program for executing a restart process for restarting the serial memory when a reset of the serial memory controller is detected in the reset detection process.

(Appendix 12)
On the computer,
The serial memory controller as a circuit for reading / writing data to / from the serial memory that reads / writes serial data in synchronization with the clock without itself having a physical reset terminal itself A clock loss detection process for detecting a transmission interruption,
A serial memory control program for executing a restart process for restarting the serial memory when a disconnection of the synchronization clock is detected in the clock disconnection detection process.

10, 300, 300A Serial memory control system 11, 302, 312 Serial memory 12, 311 Serial memory controller 13 Reset detection means 14 Restart means 20, 30 Serial memory control method 21 Reset detection steps 22, 32 Restart steps 31 Clock loss detection step 40, 50 Serial memory control program 41 Reset detection processing 42, 52 Restart processing 51 Clock loss detection processing 301, 301A SOC
303 Reset Signal Detection Unit 304 Power Supply Unit 321 Power Supply Terminal 332 CLK Signal 341 Reset Signal 342 Power Control Signal 343 Power Supply 501 Clock Disconnection Detection Unit

Claims (10)

A serial memory that reads and writes serial data in synchronization with the clock;
A serial memory controller as a circuit for reading and writing data to and from this serial memory;
Reset detecting means for detecting when the serial memory controller is reset;
A serial memory control system comprising: restarting means for restarting the serial memory when the reset detecting means detects a reset.   The serial memory has an address mode between a first address mode in which an address is represented by a specific number of bytes initially set and a second address mode in which an address is represented by a number of bytes different from the first address mode. 2. The serial memory control system according to claim 1, further comprising a migration command receiving means for receiving a migration command for migrating the memory.   The restarting means is means for turning off the power of the serial memory when the serial memory controller is reset and turning on the power of the serial memory when the reset is released. The serial memory control system according to 1.   The restarting means turns off the power of the serial memory when the clock signal supplied to the serial memory from the serial memory controller is cut off, and turns on the power of the serial memory when the supply of the clock signal is started. 2. The serial memory control system according to claim 1, wherein the serial memory control system is a means for turning on the memory.   2. The serial memory controller and reset signal sending means for detecting the reset of the serial memory controller and inverting the logic of a signal to be output are formed on one semiconductor chip. The serial memory control system described.   2. The serial memory control system according to claim 1, wherein the serial memory does not include a physical reset terminal. Reset detection step that detects when the serial memory controller as a circuit that reads and writes data to and from the serial memory that does not have a physical reset terminal itself and that reads and writes serial data in synchronization with the clock is reset When,
A serial memory control method comprising: a restarting step of restarting the serial memory when the reset of the serial memory controller is detected in the reset detecting step. The serial memory controller as a circuit for reading / writing data to / from the serial memory that reads / writes serial data in synchronization with the clock without itself having a physical reset terminal itself A clock loss detection step for detecting a transmission interruption;
A serial memory control method comprising: a restarting step of restarting the serial memory at the time when the clock disconnection detecting step detects the disconnection of the synchronization clock. On the computer,
Reset detection processing that detects when a serial memory controller is reset as a circuit that reads and writes data to and from serial memory that reads and writes serial data in synchronization with the clock without itself having a physical reset terminal When,
A serial memory control program for executing a restart process for restarting the serial memory when a reset of the serial memory controller is detected in the reset detection process. On the computer,
The serial memory controller as a circuit for reading / writing data to / from the serial memory that reads / writes serial data in synchronization with the clock without itself having a physical reset terminal itself A clock loss detection process for detecting a transmission interruption,
A serial memory control program for executing a restart process for restarting the serial memory when a disconnection of the synchronization clock is detected in the clock disconnection detection process.

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