JP2010141425A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To convert a data authentication part and an inter-apparatus authentication part into an integrated circuit without increasing power consumption. <P>SOLUTION: The semiconductor integrated circuit device includes: the data authentication part 11 configured on a chip, for authenticating data and decrypting the encrypted data from a source apparatus; the inter-apparatus authentication part 12 configured on the chip, for performing authentication between apparatuses with the source apparatus; and power supply parts 31-33 capable of individually controlling power to be supplied to the data authentication part and power to be supplied to the inter-apparatus authentication part and supplying a power supply voltage to the inter-apparatus authentication part at least when the inter-apparatus authentication part performs the authentication with the source apparatus. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device suitable for a receiving device that performs inter-device authentication and receives video information.

  Conventionally, digitization of video information, audio information and the like (hereinafter referred to as AV information) has been promoted. Digital broadcasting such as BS digital broadcasting and terrestrial digital broadcasting has also been started, and digitized AV information (AV data) has been broadcast as digital content. As devices for recording such digital AV data, DVD recorders, hard disk recorders, semiconductor memory recorders and the like are also widespread.

  In digital recording, it is possible to create a copy without degrading original AV data, and from the viewpoint of copyright protection, there is an increasing need to be able to restrict copying of digital content. In consideration of such copyright protection function and transmission for improving image quality, and further handling of the cable, HDMI (which transmits an uncompressed video signal and a sound signal and a control signal through a single cable) High-Definition Multimedia Interface) has been adopted. Note that HDMI is disclosed in, for example, Patent Document 1.

In HDMI, TMDS (Transition Minimized Differential Signaling) which is a transmission standard in the physical layer is adopted. Also, in HDMI, DDC (Display Data Channel) is adopted in order to automatically identify various electrical specifications of a display by a source device such as a recording device. In this DDC, I ² C (I Square Sea) bus type two-wire serial transmission is adopted. For automatic recognition using the DDC, an extended display identification data (EDID) standard is adopted as a standard for electrical specifications and the like.

  An HDMI receiving device (HDMI RX) that receives a signal from a source device such as a digital recording device includes an EDID unit in addition to a data authentication unit that receives a TMDS signal. The EDID unit handles EDID information for confirming the performance and function of a receiver device such as a display device. The EDID unit transmits EDID information to the source device via the DDC to enable inter-device authentication, and is operable when the source device is accessed.

  For this reason, the EDID unit needs to be always supplied with power when the source device is accessed, regardless of the operating state of the receiver device such as power on or off. Therefore, the EDID unit is driven by DDC 5 V, which is a power supply voltage supplied from the source device via the DDC.

  In recent years, with an increase in the number of source devices that output HDMI-compatible output, receiver devices such as digital television receivers having a plurality of HDMI ports have become widespread. In such a receiver device, an EDID section is provided for each HDMI port to enable transmission of EDID information to a source device corresponding to each HDMI port.

Generally, an E ² PROM storing EDID information is employed as the EDID portion. Accordingly, when a plurality of HDMI ports are provided, a plurality of E ² PROMs constituting the EDID are prepared, and a changeover switch for selecting one of the plurality of E ² PROMs is required. For systems with such a plurality of ^E 2 PROM is the size of the apparatus, from the viewpoint of low power consumption, by integrating a plurality of ^E 2 PROM, a plurality of EDID corresponding to the plurality of HDMI ports It is advantageous to configure the parts on one LSI.

In view of this, an SoC (system on chip) that constitutes a digital television receiver has been developed in which a data authentication unit and an EDID unit are incorporated. However, in such a system, it is necessary to constantly supply power to the SoC in order to supply power to the EDID unit, and there is a problem that power consumption increases.
JP 2007-108198 A

  An object of the present invention is to provide a semiconductor integrated circuit device in which a data authentication unit and an EDID unit can be integrated without increasing power consumption.

  A semiconductor integrated circuit device according to one aspect of the present invention is configured on a chip, performs data authentication, and decrypts encrypted data from a source device, and is configured on the chip, the source device The inter-device authentication unit for performing authentication between devices, and the power supplied to the data authentication unit and the power supplied to the inter-device authentication unit can be individually controlled, and at least the inter-device authentication unit In the case of performing authentication with the source device, a power supply unit that supplies a power supply voltage to the inter-device authentication unit is provided.

  According to the present invention, the data authentication block and the EDID block can be integrated into an integrated circuit without increasing power consumption.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a semiconductor integrated circuit device according to the first embodiment of the present invention.

  A semiconductor integrated circuit device 10 in FIG. 1 represents an SOC (system on chip) constituting an HDMI receiving device. This semiconductor integrated circuit device 10 has three input TMDS signals and corresponds to four HDMI ports. In the present embodiment, the number of inputs is not limited to this.

  The semiconductor integrated circuit device 10 includes a data authentication block 11 and an EDID block 12. The data authentication block 11 performs HDCP (High-bandwidth Digital Content Protection system) authentication and outputs video data and audio data based on the input TMDS signal. The EDID block 12 as an inter-device authentication unit handles EDID information for the source device to confirm the performance and function of the receiver device, transmits EDID information to the source device, and for HDCP authentication from the source device. Information (hereinafter referred to as HDCP authentication information) is supplied to the data authentication block 11.

  The data authentication block 11 is controlled by the control unit 20 (not shown). TMDS signals are input to the physical layer (PHY) units 14A to 14C via terminals T1 to T3, respectively. The physical layer units 14 </ b> A to 14 </ b> C convert the TMDS signal, which is a differential signal, into a digital signal by processing the input TMDS signal and output the digital signal to the selector 15. The selector 15 receives a channel selection signal from the control unit 20, selects one of the outputs of the physical layer units 14 </ b> A to 14 </ b> C based on the channel selection signal, and outputs it to the demultiplexer 16. The demultiplexer 16 separates video data, audio data, and the like from the input signal and outputs them to the HDCP authentication unit 17.

As will be described later, the HDCP receiver 18 receives HDCP authentication information transmitted via the I ² C bus of the selected channel among the DDC 4 channels via the selector 23. The HDCP receiver 18 outputs the received HDCP authentication information to the HDCP authentication unit 17.

  Data input from the demultiplexer 16 to the HDCP authentication unit 17 is encrypted by HDCP. The HDCP authentication unit 17 is provided with HDCP authentication information for the encrypted data from the HDCP receiver 18. The key ROM 19 stores an authentication key for decrypting the encrypted data. The HDCP authentication unit 17 performs HDCP authentication using the HDCP information from the HDCP receiver 18 and the authentication key from the key ROM 19. As a result, the HDCP authentication unit 17 decrypts the encrypted data and outputs the video data and audio data of the selected channel.

  In the present embodiment, the power supply voltage is supplied from the power supply circuit 31 to the data authentication block 11 via the switch 32. The switch 32 is turned on / off in response to, for example, turning on / off the main power supply of the system. For example, when applied to a display device, the switch 32 displays the TMDS signal from the source device connected to the HDMI port. In this case, the data authentication block 11 is turned on and turned on.

  A data authentication system clock is supplied from the clock oscillator 29 to each unit in the data authentication block 11. The clock oscillator 29 is supplied with the output of the crystal oscillator 30 and can generate a data authentication system clock and an EDID system clock. The clock oscillator 29 is controlled by the oscillation control signal from the oscillation controller 36 to oscillate or stop the EDID system clock.

  In addition, the control unit 20 generates and outputs a hot plug signal (HOT PLUG) that informs the source device that HDMI connection is possible.

  On the other hand, the EDID block 12 includes an EDID memory unit 21, EDID receivers 22A to 22D, selectors 23 and 25, and a switch 24. The EDID memory unit 21 has a storage area for storing EDID information, and can be configured by an SRAM or the like, for example. In the example of FIG. 1, the EDID memory unit 21 can store and process four EDID information corresponding to four-channel HDMI ports.

  In this case, the difference between the four EDID information is only the physical address, and for one EDID information and the remaining EDID information, there is address data and a physical address in which a physical address that is difference information of the physical address exists. Only data may be stored. In this case, the necessary storage capacity in the EDID memory unit 21 can be reduced. Thereby, even when the number of EDID channels increases, an increase in the storage capacity of the EDID memory unit 21 can be suppressed, and it is relatively easy to increase the number of EDID channels in terms of LSI design.

  Note that, by configuring the EDID memory unit 21 with an SRAM, the EDID information can be easily rewritten according to the function / performance of the receiver device.

The EDID information transmitted from the EDID memory unit 21 to the source device is transmitted via the I ² C bus of the DDC. In FIG. 1, four I ² C buses of channels A to C are provided, and each I ² C bus can be connected to four source devices (not shown). Each I ² C bus of channels A to D transmits SCL (serial clock), SDA (serial data), and ACK (acknowledge) (SCL / SDA / ACK_DDC_A to D) of the DDC.

The EDID receivers 22A to 22D are connected to the I ² C bus of each channel via terminals T4 to T7, respectively, and in response to an EDID information read request from the source device, EDID information from the EDID memory unit 21 is It can be supplied to a source device connected via an I ² C bus.

The EDID receivers 22 </ b> A to 22 </ b> D can receive HDCP authentication information from the source device and supply the HDCP authentication information to the selector 23. The selector 23 receives a channel selection signal from the control unit 20 and selects an I ² C bus to be connected to the HDCP receiver 18. The selector 23 supplies the HDCP authentication information from the source device corresponding to the channel selection signal to the HDCP receiver 18.

  In the present embodiment, since the EDID block 12 is incorporated in the semiconductor integrated circuit device 10, the DDC 5V supplied via the DDC cannot be used as a power source. In the present embodiment, a power supply voltage is supplied from the power supply circuit 33 to the EDID block 12. The power supply circuit 33 always generates a power supply voltage and supplies it to the EDID block 12 regardless of the operation state of the data authentication block. The EDID block 12 is supplied with an EDID system clock from a clock oscillator 29, which will be described later, so that each unit operates.

  The power supply circuit 33 can supply a power supply voltage to each part other than the data authentication block 11 and the EDID block 12.

  As described above, in this embodiment, the power supply circuits 31 and 33 are provided, and the data authentication block 11 and the EDID block 12 can independently supply the power supply voltage. As a result, even when the data authentication block 11 is turned off, the EDID block 12 can be turned on. When there is an access from the source device, the EDID block 12 and the source device It is possible to reliably transmit and receive EDID information.

  Furthermore, in this embodiment, when there is no access to the EDID block 12 from the source device, the power consumption of the EDID block 12 can be suppressed by stopping the supply of the EDID system clock. ing.

  In the present embodiment, the supply stop of the EDID system clock is controlled by an MCU (microcontroller unit) 28. On the other hand, the start of the supply of the EDID system clock is executed with the DDC 5V transmitted by the DDC as a trigger. The MCU 28 outputs an oscillation stop signal for stopping the oscillation of the EDID system clock to the oscillation control unit 36 when the main power supply of the system is turned off. When the oscillation stop signal is input, the oscillation control unit 36 outputs an oscillation control signal for stopping the oscillation of the EDID system clock of the clock oscillator 29 to the clock oscillator 29.

  The four channels DDC 5V of channels A to C are supplied to the I / O control unit 27 and also to the oscillation stop cancellation unit 35 through the terminal T9 of the semiconductor integrated circuit device 10. The oscillation stop canceling unit 35 determines whether or not there is an access to the EDID block 12 from the source device by detecting the transmission of DDC 5V. When detecting the DDC 5V, the oscillation stop canceling unit 35 outputs an oscillation stop canceling signal for canceling the oscillation stop to the oscillation control unit 36. When the oscillation stop cancellation signal is input, the oscillation control unit 36 cancels the oscillation stop of the EDID system clock of the clock oscillator 29 and outputs an oscillation control signal for oscillation to the clock oscillator 29. That is, the MCU 28 and the oscillation stop cancellation unit 35 constitute a clock control unit that controls oscillation and stop of the EDID system clock.

  The clock oscillator 29 oscillates or stops oscillation of the EDID system clock based on the oscillation control signal. The EDID system clock from the clock oscillator 29 is supplied to the oscillation stabilization circuit 37. The oscillation stabilization circuit 37 supplies the clock from the clock oscillator 29 to the MCU 28 and determines whether or not the EDID system clock is stably oscillated based on the data from the MCU 28. The oscillation stabilization circuit 37 supplies the EDID system clock to the EDID block 12 when the oscillation of the EDID system clock from the clock oscillator 29 is stabilized.

  The oscillation stabilization circuit 37 has a delay function that does not supply the EDID system clock to the EDID block until the oscillation is stabilized immediately after the oscillation starts. As a result, it is possible to prevent an unstable system clock from being supplied to the EDID block 12 at the time of oscillation start-up and restarting, thereby preventing each circuit of the EDID block 12 from malfunctioning.

  Thus, the oscillation of the EDID system clock from the clock oscillator 29 is controlled based on the detection result of the 4-channel DDC 5V. That is, when the DDC 5V is not transmitted from the source device, the oscillation of the EDID system clock is stopped and the current flowing in the EDID block 12 is suppressed so as to suppress the power consumption of the EDID block 12. On the other hand, when DDC 5V is transmitted from the source device, the EDID block 12 is operated by restarting oscillation of the EDID system clock so that the source device can read the EDID information.

  The I / O control unit 27 outputs the input DDC 5V to the control unit 20 via the selector 25. The selector 25 selects the DDC 5V of the channel based on the channel selection signal from the EDID memory unit 21 and outputs it to the control unit 20.

  As described above, the control unit 20 outputs a hot plug signal. The switch 24 selects the hot plug signal of the selected channel based on the channel selection signal from the EDID memory unit 21 and outputs it to the I / O control unit 26. The I / O control unit 26 is controlled by the EDID memory unit 21 and outputs a hot plug signal from the terminal T8 to the corresponding source device via the corresponding channel.

Further, the MCU 28 can control writing of each EDID information to the EDID memory unit 21 via the internal bus 34. Although FIG. 1 shows an example in which EDID information is written using the internal bus 34, writing can also be performed using another interface such as an I ² C bus. When the EDID memory unit 21 is configured by an SRAM, the MCU 28 initializes the EDID memory unit 21 every time a power supply voltage is supplied to the EDID block 12.

Further, the MCU 28 may control the selector 25 by transmitting a channel selection signal via an I ² C bus (not shown). Further, the MCU 28 may control the switch 24 by transmitting a channel selection signal via an I ² C bus (not shown). Further, the MCU 28 may output a hot plug signal regardless of the hot plug signal output from the control unit 20.

  In the present embodiment, an HDMI input switch 13 is provided. The switch 13 selects one of the two-input TMDS signals and supplies it to the physical layer unit 14C. The MCU 28 supplies a control signal to the switch 13 via the terminal T10 to control selection of the switch 13. By selecting the TMDS signal to be input using the external switch 13, it is possible to cope with an input larger than the number of data authentication block inputs.

  Next, the operation of the embodiment configured as described above will be described.

  Now, it is assumed that an image from a source device connected to the HDMI port is displayed in a display device in which the semiconductor integrated circuit device 10 of FIG. 1 is incorporated. Here, the source device connected to the HDMI port is turned on. By turning on the main power supply of the display device, the switch 32 is also turned on, and the power supply voltage from the power supply circuit 31 is supplied to the data authentication block 11. The power supply voltage of the power supply circuit 33 is always supplied to the EDID block 12 and other circuit portions.

  The control unit 20 generates a channel selection signal based on the user's selection operation and supplies it to each unit. When the power supply of the source device is turned on, DDC 5V is supplied from the source device to the oscillation stop cancellation unit 35 via the DDC. The oscillation stop cancellation unit 35 detects that the source device has accessed, and outputs the detection result to the oscillation control unit 36. The oscillation control unit 36 controls the clock oscillator 29 to generate not only the data authentication system clock but also the EDID system clock. Thereby, the MCU 28 and the EDID block 12 also start operation.

The control unit 20 generates a hot plug signal notifying that HDMI connection is possible and outputs the hot plug signal to the corresponding source device via the switch 24 and the I / O control unit 26. The EDID receivers 22A to 22D read and respond to the EDID information stored in the EDID memory unit 21 in accordance with a read request for the EDID information input via the I ² C bus of each channel A to D from the source device. Output to the source device. Thereby, the source device acquires information on the receiver device, and authentication between the devices is performed.

  The DDC 5V from the device designated by the channel selection signal is supplied to the control unit 20 via the selector 25. Also, HDCP authentication information from the source device designated by the channel selection signal is supplied to the HDCP receiver 18 via the selector 23.

  The TMDS signal from the device specified by the channel selection signal is converted into a digital signal by the physical layer units 14A to 14C, then selected by the selector 15, and supplied to the demultiplexer 16. The demultiplexer 16 separates video data, audio data, and the like from the input signal and supplies them to the HDCP authentication unit 17.

  The HDCP authentication unit 17 receives HDCP authentication information from the HDCP receiver 18 and an authentication key from the key ROM 19 to perform HDCP authentication. As a result, the encrypted data from the demultiplexer 16 is decrypted, and video data and audio data are output from the HDCP authentication unit 17. In this way, the display device as the receiver device can display the video from the source device.

  Here, it is assumed that the main power supply of the system is turned off, the switch 32 is turned off, and the supply of the power supply voltage to the data authentication block 11 is stopped. In this case, the MCU 28 gives an oscillation stop signal to the oscillation control unit 36. As a result, the oscillation control unit 36 stops the oscillation of the clock oscillator 29.

  In other words, in this case, the power supply voltage from the power supply circuit 33 is supplied to the EDID block 12 but the EDID system clock from the clock oscillator 29 is not supplied. Therefore, the EDID block 12 stops operating and power consumption is reduced.

  Also in this case, the power supply voltage is supplied from the power supply circuit 33 to the EDID block 12 and other circuit portions. Here, it is assumed that the power of the source device connected to the HDMI port is turned on, and any one of the four channels A to D is transmitted to the semiconductor integrated circuit device 10. When detecting that the DDC 5V has been transmitted, the oscillation stop cancellation unit 35 outputs an oscillation stop cancellation signal to the oscillation control unit 36 based on the detection result. The oscillation control unit 36 resumes the oscillation of the EDID system clock of the clock oscillator 29. The clock from the clock oscillator 29 is supplied to the MCU 28 via the oscillation stabilization circuit 37, and the MCU 28 starts its operation. Further, the EDID system clock from the oscillation stabilization circuit 37 is supplied to the EDID block 12, and the operation of the EDID block 12 is resumed.

  That is, for example, even when the main power supply of the system is off, the power supply circuit 33 constantly supplies the power supply voltage to the EDID block 12, and by restarting the supply of the EDID system clock, the EDID block 12 is operated, Device authentication by exchanging EDID information with a device can be enabled.

  Thus, in this embodiment, the power supply system of the HDMI receiving apparatus is divided into two systems for the data authentication block and for the EDID block, and the power supply can be controlled for each block. The power supply for the data authentication block can be turned on and off, and the power supply for the EDID block is always turned on. As a result, regardless of the state of the data authentication block, EDID information can be transmitted to and from the source device, thereby enabling inter-device authentication.

  Further, simply supplying a constant power supply voltage to the EDID block increases power consumption in the EDID block even when there is no access from the source device. Therefore, when the DDC 5V is detected and the DDC 5V is not transmitted, the system clock for the EDID block is stopped. This prevents current from flowing through the EDID block when there is no access from the source device, thereby reducing power consumption.

  The oscillation stabilization circuit has a delay function that delays the supply of the system clock to the EDID block until oscillation is stabilized. This prevents an unstable system clock from being supplied at the time of oscillation start and restart. If an unstable system clock is supplied to the EDID block, the stored contents of the storage device of the EDID block may change, or each circuit of the EDID block may malfunction. By providing a delay function of clock generation, it is possible to prevent malfunctions in the EDID block.

  FIG. 2 is a block diagram showing a semiconductor integrated circuit device 10 'according to a modification of the first embodiment. In FIG. 2, the same components as those in FIG.

FIG. 1 shows an example in which the MCU 28 writes the EDID information to the EDID memory unit 21 using the internal bus 34, but the EDID information is written by the bus control unit 42 which is an I ² C bus controller. Also good.

  FIG. 3 is a block diagram showing a second embodiment of the present invention. In FIG. 3, the same components as those of FIG.

  This embodiment is different from the semiconductor integrated circuit device 10 of the first embodiment in that the semiconductor integrated circuit device 40 in which the MCU 28 and the oscillation stop cancellation unit 35 are omitted and the bus control unit 42 is added is adopted. In the present embodiment, an external MCU 41 is employed outside the semiconductor integrated circuit device 40.

  In the first embodiment, the clock supply to the EDID block 12 is controlled by the MCU 28, the oscillation stop cancellation unit 35, and the oscillation control unit 36. However, in this embodiment, the clock supply to the EDID block 12 is controlled by the external MCU 41. To do.

  The external MCU 41 generates an oscillation control signal for controlling the oscillation of the clock oscillator 29 and supplies it to the terminal T11 of the semiconductor integrated circuit device 40. The oscillation control signal input via the terminal T11 is supplied to the clock oscillator 29. The DDCs 5V of the four channels A to D are supplied to the I / O control unit 27 and also supplied to the external MCU 41. The external MCU 41 generates an oscillation control signal for causing the clock oscillator 29 to oscillate the EDID system clock when the DDC 5V is transmitted, and causes the clock oscillator 29 to oscillate the EDID system clock when the DDC 5V is not transmitted. An oscillation control signal for stopping is generated.

  In the first embodiment, the oscillation stop canceling unit 35 for detecting transmission of DDC 5V as an external event input and restarting oscillation is provided. The clock supply to the MCU 28 and the clock supply to the EDID block 12 were resumed by the oscillation stop cancellation unit 35. On the other hand, in the present embodiment, the external MCU 41 with sufficiently low power consumption is adopted, and the detection of the DDC 5V and the oscillation control of the clock oscillator 29 are performed only by the external MCU 41.

The external MCU 41 controls the writing of EDID information to the EDID memory unit 21. In this case, the external MCU 41 accesses the EDID memory unit 21 via the bus control unit 42. The bus control unit 42 performs bus transmission control between the external MCU 41 and the EDID memory unit 21. For example, when the external MCU 41 and the EDID memory unit 21 are connected by an I ² C bus, the bus control unit 42 performs control corresponding to the I ² C bus. It is also possible to connect the external MCU 41 and the switch 13 by an I ² C bus. In this case, there is an advantage that the interface between the external MCU 41 and the EDID memory unit 21 and the interface between the external MCU 41 and the switch 13 can be shared. The bus control unit 42 may employ an interface other than the I ² C bus (for example, UART).

Further, the external MCU 41 may control the selector 25 using a channel selection signal via an I ² C bus (not shown). The external MCU 41 may control the switch 24 using a channel selection signal via an I ² C bus (not shown). Further, the external MCU 41 may output a hot plug signal regardless of the hot plug signal output from the control unit 20.

  In the embodiment configured as described above, as in the first embodiment, the supply and stop of the EDID system clock to the EDID block 12 are performed based on detection of the DDC 5V. In the present embodiment, the DDC 5V of each channel is supplied to the external MCU 41. The external MCU 41 detects an access from the source device by the DDC 5V and generates an oscillation control signal corresponding to the detection result. That is, the external MCU 41 checks the input state of the DDC 5V, stops the generation of the EDID system clock when the DDC 5V is not transmitted, and generates the EDID system clock only when the DDC 5V is transmitted. The clock oscillator 29 is controlled. Thereby, the power consumption of the EDID block 12 can be reduced.

As described above, also in this embodiment, the same effect as that of the first embodiment can be obtained. Further, by using a common I ² C bus, for example, as an interface between the external MCU and the EDID memory unit and between the external MCU and an external switch, it is possible to make the terminals common.

  FIG. 4 is a block diagram showing a third embodiment of the present invention. 4, the same components as those in FIGS. 2 and 3 are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 4 shows a semiconductor integrated circuit device 50 that can correspond to either the semiconductor integrated circuit device 10 ′ incorporating the MCU 28 or the semiconductor integrated circuit device 40 using the external MCU 41. In the semiconductor integrated circuit device 50 of FIG. 4, the thick line portion indicates a circuit portion that is activated when the external MCU 41 is not present. The circuit portion indicated by the bold line is not active when the external MCU 41 is present.

  In FIG. 4, a broken line portion indicates a circuit portion that is activated when an external MCU 41 is present. The circuit portion indicated by the broken line is not active when the external MCU 41 does not exist.

  In the semiconductor integrated circuit device 50, an MCU enable for setting the thick line portion to be active or the broken line portion to be active is supplied to the terminal T12. In the semiconductor integrated circuit device 50, when the MCU enable of the terminal T12 is H level, for example, the thick line portion is activated, and when the terminal T12 is L level, the broken line portion is activated.

  That is, when the MCU enable is at the H level, the semiconductor integrated circuit device 50 has the same configuration as the semiconductor integrated circuit device 10 ′ of FIG. 2, and when the MCU enable is at the L level, the semiconductor integrated circuit device 50 is 3 of the semiconductor integrated circuit device 40.

  Thus, in the present embodiment, the same semiconductor as in the second or third embodiment is used by using the common semiconductor integrated circuit device 50 regardless of whether or not an external MCU is available. An integrated circuit device can be configured.

Note that the example of FIG. 4 uses an I ² C bus as an interface between the built-in MCU 28 and the EDID memory unit 21. Thereby, the common terminal T10 can be used by adopting the I ² C bus as an interface for controlling the switch 13.

  In FIG. 4, the circuits corresponding to the semiconductor integrated circuit devices 10 ′ and 40 have been described. However, by adding a terminal or the like, either the semiconductor integrated circuit device 10 of FIG. 1 or the semiconductor integrated circuit device 40 of FIG. Obviously, it is possible to construct an HDMI receiving apparatus that supports the above.

  In each of the above embodiments, the power supply voltage is always supplied to the EDID block and the power consumption is reduced by stopping the supply of the system clock to the EDID block. The voltage may be directly turned on / off, and the supply of the power supply voltage to the EDID block may be stopped when there is no access from the source device.

  In each of the above embodiments, an example of a plurality of inputs has been described. However, the present invention can be similarly applied to a case of one input. In the case of one input, the selector and switch for selecting the input can be omitted.

1 is a block diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention. The block diagram which shows the modification of 1st Embodiment. The block diagram which shows the 2nd Embodiment of this invention. The block diagram which shows the 3rd Embodiment of this invention.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 10 ... Semiconductor integrated circuit device, 11 ... Data authentication block, 12 ... EDID block, 21 ... EDID memory part, 28 ... MCU, 29 ... Clock oscillator, 31, 33 ... Power supply circuit, 35 ... Oscillation stop cancellation part, 36 ... Oscillation Control unit.

Claims (5)

A data authentication unit configured on the chip and performing data authentication to decrypt the encrypted data from the source device;
An inter-device authentication unit configured on the chip and for performing authentication between devices with the source device;
The power supplied to the data authentication unit and the power supplied to the inter-device authentication unit can be individually controlled, and at least the inter-device authentication is performed when the inter-device authentication unit performs authentication with the source device. A power supply section for supplying power supply voltage to the section;
A semiconductor integrated circuit device comprising: A system clock is supplied to the inter-device authentication unit, and control is performed so that the system clock is supplied to the inter-device authentication unit only when the inter-device authentication unit performs authentication with the source device. Clock generator,
The semiconductor integrated circuit device according to claim 1, further comprising:   The semiconductor integrated circuit device according to claim 2, wherein the clock generation unit is controlled by a clock control unit provided on the chip or an external controller provided outside the chip.   4. The semiconductor integrated circuit device according to claim 3, wherein the clock control unit or the external controller controls the clock generation unit based on a power supply voltage supplied from the source device.   The clock control unit can be switched between active and inactive, and the control by the external controller can be switched so that the clock generation unit can be controlled regardless of the presence or absence of the external controller. The semiconductor integrated circuit device according to claim 3 or 4.

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