JP2012004979A - Active clamp circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active clamp circuit that reduces an operation period thereof.SOLUTION: According to one embodiment, an active clamp circuit is provided that comprises a first switch element, a first resistor, a first diode, and a control circuit. The first diode breaks down by the overvoltage applied to both ends of the first switch element. The first resistor detects the current of the first diode. The control circuit controls the current of the first switch element by amplifying electric voltages at both ends of the first resistor.

Description

  Embodiments described herein relate generally to an active clamp circuit.

  When an inductive load such as a solenoid valve or a motor is driven on or off, an induced voltage is generated by the energy stored in the inductive load when it is off. In order to prevent a switch or the like from being destroyed by this induced voltage, an active clamp circuit that clamps the induced voltage to a specified value and absorbs energy accumulated in the inductive load is used.

JP 2004-32893 A

However, the clamp voltage depends on the magnitude of the current flowing through the active clamp circuit, and is high at the start of the clamp operation and decreases with time. In addition, for example, when the Zener diode is broken and clamped, the clamp voltage changes due to variations in the current / voltage characteristics of the Zener diode.
Since the active clamp operation period is a dead time during which the inductive load cannot be driven, a shorter one is desirable.

  Provided is an active clamp circuit in which an active clamp operation period is shortened.

  According to the embodiment, there is provided an active clamp circuit including a first switch element, a first diode, a first resistor, and a control circuit. The first diode breaks down due to an overvoltage applied to both ends of the first switch element. The first resistor detects a current of the first diode. The control circuit amplifies the voltage across the first resistor to control the current of the first switch element.

FIG. 3 is a circuit diagram illustrating the configuration of a drive circuit including an active clamp circuit according to the first embodiment. FIG. 2 is a waveform diagram of main signals of the active clamp circuit shown in FIG. 1, where (a) is a control signal In, (b) is a drive signal Drv2, (c) is a drive signal Drv1, and (d) is a first switch. The element current Id, (e) is the voltage Out across the first switch element. FIG. 7 is a waveform diagram of main signals of an active clamp circuit when there is no control circuit, where (a) is a control signal In, (b) is a current Id of the first switch element, and (c) is a current of the first switch element. This is the voltage Out at both ends. 6 is a circuit diagram illustrating another configuration of the active clamp circuit according to the first embodiment; FIG. 6 is a circuit diagram illustrating another configuration of the active clamp circuit according to the first embodiment; FIG. 6 is a circuit diagram illustrating another configuration of the active clamp circuit according to the first embodiment; FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1 is a circuit diagram illustrating the configuration of a drive circuit including an active clamp circuit according to the first embodiment.
FIG. 1 illustrates a configuration in the case where the active clamp circuit 1 is applied to the drive circuit 2.

  The active clamp circuit 1 switches the first switch element M1 on or off depending on the level of the control signal In. Further, the first diode Dz1 breaks down due to an overvoltage applied to both ends of the first switch element M1, and the voltage Out at both ends of the first switch element M1 is clamped to a specified clamp voltage. The current Iz1 of the first diode Dz1 is detected by the first resistor R1. The voltage across the first resistor R1 is amplified by the control circuit 3, and the current Id of the first switch element M1 is controlled.

The first switch element M1 is composed of an N-channel MOSFET (hereinafter referred to as NMOS).
A control signal In is input to the gate of the first switch element M1 via the resistor R4 and the inverters Inv1 and Inv2. The inverter Inv1 outputs a drive signal Drv2 obtained by inverting the control signal In. The inverter Inv2 outputs a drive signal Drv1 obtained by inverting the drive signal Drv2. The drive signal Drv1 is in phase with the control signal In. The drive signal Drv1 is input to the gate of the first switch element M1 via the resistor R4. The first switch element M1 is switched on or off according to the level of the control signal In.

  The cathode of the first diode Dz1 is connected to the drain of the first switch element M1. The anode of the diode Df1 is connected to the anode of the first diode Dz1, and the cathode of the diode Df1 is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the ground Gnd.

  The first diode Dz1 breaks down due to overvoltage. Therefore, the voltage across the first switch element M1 is clamped to a voltage at which the first diode Dz1 breaks down. At that time, the current Iz1 flows through the first diode Dz1.

  When the voltage at which the first diode Dz1 breaks down is Vz1, the forward voltage of the diode Df1 is Vf1, and the voltage across the first resistor R1 is Vr1, the voltage Out across the first switch element M1 is clamped. The voltage Vclamp is Vz1 + Vf1 + Vr1.

The first diode Dz1 is configured by, for example, a Zener diode. In FIG. 1, the structure by one Zener diode is illustrated as 1st diode Dz1. However, an arbitrary number of Zener diodes may be connected in series according to a voltage for clamping the voltage Out across the first switch element M1.
The diode Df1 is used for temperature compensation of the first diode Dz1.

  The first resistor R1 detects a current Iz1 that flows when the first diode Dz1 breaks down. That is, when the first diode Dz1 breaks down, the current Iz1 flows through the first resistor R1, and a voltage is output across the first resistor R1.

  The control circuit 3 amplifies the voltage across the first resistor R1 and outputs a current, and inputs the output current of the amplifier circuit N2 to control the current Id of the first switch element M1. And a mirror 4.

  The amplifier circuit N2 is composed of an npn transistor. The voltage across the first resistor R1 is input to the base of the amplifier circuit N2 via the resistor R3. The resistor R3 is inserted to delay the voltage input to the base of the amplifier circuit N2 and adjust the timing.

  Further, second diodes Df2 and Df3 are connected between both ends of the first resistor R1 in order to protect the base and emitter of the amplifier circuit N2. The voltage across the first resistor R1 is suppressed to Vdf2 + Vdf3 or less by the second diodes Df2, Df3. Here, Vdf2 and Vdf3 are forward voltages of the second diodes Df2 and Df3, respectively. However, if the base-emitter voltage of the amplifier circuit N2 is VbeN2 and the voltage across the resistor R3 is Vr3, it is necessary to satisfy Vdf2 + Vdf3> Vr3 + VbeN2.

  The collector of the amplifier circuit N2 is connected to the reference side of the current mirror 4. The output side of the current mirror 4 is connected to the gate of the first switch element M1. The output current of the amplifier circuit N2 is turned back by the current mirror 4 to control the first switch element M1.

The current mirror 4 includes resistors R5 to R7 and transistors P1 to P3.
The transistors P1 to P3 are pnp transistors. The power supply voltage Vdd is supplied to the emitter of the transistor P1 through the resistor R5. The power supply voltage Vdd is supplied to the emitter of the transistor P2 via the resistor R6. The power supply voltage Vdd is supplied to the bases of the transistors P1 and P2 via the resistor R7.

The collector of the transistor P3 is connected to the bases of the transistors P1 and P2. The base of the transistor P3 is connected to the collector of the transistor P1, and the collector of the transistor P3 is connected to the ground Gnd.
The collector of the transistor P1 and the base of the transistor P3 are connected to the collector of the amplifier circuit N2 as the reference side of the current mirror 4. The collector of the transistor P2 is connected to the gate of the first switch element M1 on the output side.

  Further, the second switch element M2 is connected between the gate of the first switch element M1 and the ground. The gate of the second switch element M2 is connected to the output of the inverter Inv1. A drive signal Drv2 obtained by inverting the control signal In is input to the gate of the second switch element M2.

  The transistor N1 is connected between the gate of the second switch element M2 and the ground Gnd. The transistor N1 is an npn transistor. The collector of the transistor N1 is connected to the gate of the second switch element M2. The emitter of the transistor N1 is connected to the ground Gnd. The voltage across the first resistor R1 is input to the base of the transistor N1 via the resistor R2.

The resistor R2 is inserted to delay the voltage input to the base of the transistor N1 and adjust the timing.
The second diodes Df2 and Df3 also protect the transistor N1. When the base-emitter voltage of the transistor N1 is VbeN1, and the voltage across the resistor R2 is Vr2, it is necessary to satisfy Vf2 + Vf3> Vr2 + VbeN1.

The drive circuit 2 is a circuit that drives the inductive load L by the active clamp circuit 1 described above. A voltage Vbat is supplied to one end of the inductive load L, and the other end is connected to the ground Gnd via the active clamp circuit 1.
Depending on the level of the control signal In of the active clamp circuit 1, the first switch element M1 is switched on or off, and the current flowing through the inductive load L is controlled. The current flowing through the inductive load L is a combined current of the current Id of the first switch element M1 of the active clamp circuit 1 and the current Iz1 of the first diode Dz1.

FIG. 2 is a waveform diagram of main signals of the active clamp circuit shown in FIG. 1, where (a) is a control signal In, (b) is a drive signal Drv2, (c) is a drive signal Drv1, and (d) is a drive signal Drv1. The current Id of the first switch element, (e) is the voltage Out across the first switch element.
In FIG. 2, a waveform diagram of main signals when a rectangular wave that changes between a high level and a low level is input as the control signal In of the active clamp circuit 1 is schematically shown.

Next, the operation of the active clamp circuit 1 will be described with reference to FIGS. 1 and 2A to 2E.
As shown in FIGS. 2A and 2C, when the control signal In is at a high level, the drive signal Drv1 input to the gate of the first switch element M1 is at a high level. In addition, the drive signal Drv2 input to the gate of the second switch element M2 is at a low level (FIG. 2B). The second switch element M2 is turned off. Further, the first switch element M1 is turned on, and a current Id flows through the first switch element M1 (FIG. 2D). Further, the voltage Vbat is supplied to the inductive load L, and a current flows. Inductive load L is driven. The voltage Out across the first switch element M1 is approximately 0 V (FIG. 2 (e)).

  When the control signal In switches from the high level to the low level (FIG. 2 (a)), the drive signal Drv1 becomes the low level (FIG. 2 (c)). The drive signal Drv2 becomes a high level (FIG. 2B), and the second switch element M2 is turned on. Further, the first switch element M1 is turned off, and an induced voltage is generated in the inductive load L. When the voltage Out across the first switch element M1 exceeds a specified value, the first diode Dz1 breaks down. The voltage Out across the first switch element M1 is clamped to the clamp voltage Vclamp = Vz1 + Vf1 + Vr1 by the breakdown of the first diode Dz1 (FIG. 2 (e)).

The current Iz1 of the first diode Dz1 is detected by the first resistor R1, and a voltage corresponding to the current Iz1 is generated at both ends of the first resistor R1.
The voltage across the first resistor R1 is amplified by the amplifier circuit N2, and the output current is turned back by the current mirror 4 and input to the gate of the first switch element M1. The current Id of the first switch element M1 is controlled by the control circuit 3 that amplifies the voltage across the first resistor R1.

  When the first switch element M1 is switched from on to off, the voltage Out across the first switch element M1 rises due to the induced voltage caused by the inductive load L. The induced voltage due to the inductive load L is proportional to the product of the rate of change of the current of the inductive load L with respect to time and the inductance of the inductive load L.

Immediately after the first switch element M1 is switched from on to off, the current of the inductive load L changes suddenly, so that a high induced voltage is generated by the inductive load L. For this reason, the current Iz1 immediately after the breakdown of the first diode Dz1 is large, and the voltage across the first resistor R1 is also high.
In addition, the current of the inductive load L flows due to the energy accumulated in the inductive load L. Therefore, the current of the inductive load L decreases with the passage of time after the first switch element M1 is switched from on to off (FIG. 2 (d)).

  In the control circuit 3, second diodes Df2 and Df3 are connected between both ends of the first resistor R1. Therefore, the voltage at both ends of the first both ends R1 is suppressed to the forward voltage Vf2 + Vf3 of the second diodes Df2, Df3. Since the control circuit 3 amplifies the suppressed voltage and controls the first switch element M1, the current Id of the first switch element M1 that flows immediately after the first diode Dz1 breaks down is also suppressed. .

In addition, the control circuit 3 controls the first switch element M1 by amplifying the voltage between both ends of the first resistor R1. Therefore, even if the current Iz1 of the first diode Dz1 decreases, the current Id of the first switch element M1 can be controlled.
In this way, the control circuit 3 suppresses a sudden change in the current of the inductive load L immediately after the first switch element M1 of the inductive load L is switched from on to off, Suppresses the rate of current decrease.

Accordingly, it is possible to suppress the sudden increase in the induced voltage of the inductive load L immediately after the first switch element M1 is switched from on to off, and to further suppress the rate of decrease of the induced voltage that decreases with the passage of time ( FIG. 2 (e)).
When the energy stored in the inductive load L is consumed, the current Id of the first switch element M1 becomes 0 (FIG. 2 (d)). The induced voltage also becomes 0, and the voltage Out across the first switch element M1 becomes the voltage Vbat supplied to the inductive load L (FIG. 2 (e)).

In this way, in the active clamp circuit 1, the control circuit 3 amplifies the voltage across the first resistor R1 to control the current Id of the first switch element M1, so that the clamp voltage Vclamp The decrease can be suppressed to a constant value.
Therefore, the active clamp operation period during which the current Id flows through the first switch element M1 can be reduced.

The operation of the control circuit 3 of the active clamp circuit 1 can be understood in more detail by considering the operation without the control circuit 3.
3A and 3B are waveform diagrams of main signals of the active clamp circuit when there is no control circuit. FIG. 3A is a control signal In, FIG. 3B is a current Id of the first switch element, and FIG. Is the voltage Out across the switch element.
3A to 3C, the control circuit 3 of the active clamp circuit 1 shown in FIG. 1 is removed, and the first switch element M1 is controlled by the voltage across the first resistor R1. The waveform is schematically represented.

As shown in FIGS. 3A to 3C, the current Id of the first switch element and the voltage Out across the first switch element when the control signal In is at the high level are respectively shown in FIG. (D) is the same as FIG. 2 (e).
When the control signal In switches from high level to low level, the first diode Dz1 breaks down. The voltage Out across the first switch element M1 is clamped to a clamp voltage (initial) (FIG. 3C).

In the absence of the control circuit 3, the clamp voltage (initial) immediately after the breakdown of the first diode Dz1 is high because the current Iz1 of the first diode Dz1 is large.
As the energy stored in the inductive load L is consumed, the current of the inductive load L decreases, and the current Id of the first switch element M1 decreases (FIG. 3B). The current Iz1 of the first diode Dz1 also decreases, and the clamp voltage also decreases (FIG. 3c)).

When the current Id of the first switch element M1 becomes 0 and the active clamp operation ends (FIG. 3B), the clamp of the voltage Out at the first end is released, and the voltage Out at the first end is induced. Voltage Vbat supplied to the capacitive load L (FIG. 3C).
The clamp voltage (final) immediately before the end of the active clamp operation is lower than the clamp voltage (initial) at the start of the active clamp operation.

  The active clamp operation period is a period in which energy stored in the inductive load L is consumed, and is determined by the current of the inductive load L and the clamp voltage. In order to shorten the active clamp operation period, it is necessary to increase the current of the inductive load L and increase the clamp voltage.

  As described above, the clamp voltage (initial) at the start of the active clamp operation is increased. Further, since the current Iz1 of the first diode Dz1 is increased, the variation of the clamp voltage due to variations in the characteristics of the first diode Dz1, for example, the current characteristics with respect to the voltage, is also increased.

Therefore, if the clamp voltage (initial) at the start of the active clamp operation is set to a value limited by a withstand voltage or the like in the absence of the control circuit 3, the clamp voltage (final) immediately before the end of the active clamp operation is set to a low value. turn into.
Thus, in the absence of the control circuit 3, the active clamp operation period is limited by the clamp voltage (initial) and cannot be shortened.

On the other hand, in the active clamp circuit 1 according to the first embodiment, the control circuit 3 can suppress the decrease of the clamp voltage Vclamp and make it constant. In addition, since the current Iz1 of the first diode Dz1 can be reduced, fluctuations in the clamp voltage due to variations in the characteristics of the first diode Dz1 can be reduced.
Therefore, according to the active clamp circuit 1, the active clamp operation period can be shortened.

FIG. 4 is a circuit diagram illustrating another configuration of the active clamp circuit according to the first embodiment. In FIG. 4, the same elements as those in FIG. 1 are denoted by the same reference numerals as those in FIG.
The active clamp circuit 1a has a configuration in which the control circuit 3 of the active clamp circuit 1 shown in FIG. 1 is replaced with a control circuit 3a.

The control circuit 3a has a configuration in which the current mirror 4 of the control circuit 3 in FIG. 1 is replaced with a current mirror 4a. Other elements are the same as those of the active clamp circuit 1 of FIG. The current mirror 4a is composed of P-channel MOSFETs (hereinafter referred to as PMOS) M3 and M4.
The active clamp circuit 1a can also shorten the active clamp operation period.

FIG. 5 is a circuit diagram illustrating another configuration of the active clamp circuit according to the first embodiment. In FIG. 4, the same elements as those in FIG. 1 are denoted by the same reference numerals as those in FIG.
The active clamp circuit 1b has a configuration in which the control circuit 3 of the active clamp circuit 1 shown in FIG. 1 is replaced with a control circuit 3b.

The control circuit 3b has a configuration in which a second resistor R8 is added in series to the drain of the second switch element M2 of the control circuit 3 of FIG. The second resistor R8 delays the turn-on of the second switch element M2.
When the control signal In is switched from the high level to the low level, the drive signal Drv1 becomes the low level and the drive signal Drv2 becomes the high level.

  For this reason, the second switch element M2 tends to be turned on, but the turn-on is delayed because the second resistor R8 is connected. The turn-off of the first switch element M1 is delayed, and the change in the current Id of the first switch element M1 is alleviated. And the change of the electric current of the inductive load L is also relieved, and the sudden change of the induced voltage is relieved. In addition, ringing that may occur at the rise of the induced voltage and the peak of the induced voltage due to ringing are reduced.

For example, as represented by the broken line in FIG. 2E, the rise of the voltage Out across the first switch element M1 is delayed. Therefore, the current change of the inductive load L is relaxed, the induced voltage is reduced, and the possibility that the induced voltage has a peak is reduced. Therefore, it is possible to increase the setting of the clamp voltage limited by the withstand voltage.
Thus, according to the active clamp circuit 1b, it is possible to further reduce the active clamp operation period in which the current Id flows through the first switch element M1.

FIG. 6 is a circuit diagram illustrating another configuration of the active clamp circuit according to the first embodiment. In FIG. 6, the same elements as those of FIG. 1 are denoted by the same reference numerals as those of FIG.
The active clamp circuit 1c has a configuration in which the control circuit 3 of the active clamp circuit 1 shown in FIG. 1 is replaced with a control circuit 3c.

The control circuit 3c has a configuration in which the transistor N1 and the second diodes Df2 and Df3 configured by the npn transistor of the control circuit 3 in FIG. 1 are replaced with the second diode Dz2 configured by NMOS M5 and a Zener diode, respectively. is there. Other elements are the same as those of the active clamp circuit 1 of FIG.
The active clamp operation period can also be shortened by the active clamp circuit 1c.

  Although the case where the active clamp circuits 1 to 1 c are applied to the drive circuit 2 has been described as an example, the active clamp circuits 1 and 1 a to 1 c can drive an inductive load even with a configuration other than the drive circuit 2. For example, the active clamp circuits 1, 1a to 1c can be used as a low side switch of a switching circuit constituted by a high side switch and a low side switch.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1, 1a-1c Active clamp circuit 2 Drive circuit 3, 3a-3c Control circuit 4, 4a Current mirror Df2, Df3, Dz2 Second diode Dz1 First diode Inv1, Inv2 Inverter L Inductive load M1 First switch Element M2 Second switch element N1, P1 to P3 Transistor N2 Amplifier circuit R1 First resistor R2 to R7 Resistor R8 Second resistor

Claims (4)

A first switch element;
A first diode that breaks down due to an overvoltage applied across the first switch element;
A first resistor for detecting a current of the first diode;
A control circuit for amplifying the voltage across the first resistor to control the current of the first switch element;
An active clamp circuit comprising: The control circuit includes:
An amplifier circuit that amplifies the voltage across the first end and outputs a current;
A current mirror circuit for controlling the current of the first switch element by inputting the output current of the amplifier circuit;
The active clamp circuit according to claim 1, further comprising: The control circuit includes:
A second switch element that is controlled by a voltage across the first resistor and controls a current of the first switch element;
A second resistor connected in series to the second switch element and delaying turn-on of the second switch element;
The active clamp circuit according to claim 1, comprising:   4. The active clamp circuit according to claim 1, wherein the control circuit further includes a second diode that suppresses an increase in voltage across the first resistor. 5.

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