JP2012003673A - Inter-cpu communication system and inter-cpu communication method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimally control weight processing in inter-CPU communication depending on waiting time of synchronization.SOLUTION: In an inter-CPU communication system 800 in which a transmission side CPU and a reception side CPU perform data communication with each other through a memory 104, the transmission side CPU includes: a memory area determination part 351 for determining whether a free space exists in the memory 104; a data writing part 352 for writing data in the memory 104, when a free space exists; the reception side CPU determination part 353 for determining a state of the reception side CPU, when a free space does not exist; and a transmission side control part 354 for instructing the data writing part 352 to be in a waiting state until a free space in the memory 104 is available when a state of the reception side CPU is in an execution state of data reading processing, and transmitting a reading start request to the reception side CPU to instruct the reception side CPU to start execution of the data reading processing when a state of the reception side CPU is not in an execution state of the data reading processing.

Description

  The present invention relates to an inter-CPU communication system and an inter-CPU communication method in which a plurality of CPUs (Central Processing Units) communicate via a memory.

  Conventionally, in an inter-CPU communication method in which a plurality of CPUs perform data communication via a memory, a method has been proposed that simplifies control of inter-CPU communication by adding a dedicated FIFO memory between the CPUs (for example, Patent Document 1). Also, by adding a flag indicating the use state of the shared memory used for inter-CPU communication, the two inter-CPU interrupts required for the start of transmission and the completion of reception are limited to one inter-CPU interrupt. A method has also been proposed (for example, Patent Document 2).

JP 58-169277 A JP 05-081185 A

  In the conventional system, even when a FIFO (First-In First-Out) memory is used or a shared memory is used, an inter-CPU interrupt is used to synchronize between CPUs. With the increase in the number of CPUs, the improvement in CPU clock, and the improvement in memory speed due to advances in semiconductor technology, the CPU arithmetic processing itself has been executed at a very high speed. However, the interrupt processing cannot be accelerated compared with the CPU arithmetic processing. Therefore, when an inter-CPU interrupt is used for synchronization of inter-CPU communication, a large delay occurs, and there is a problem that high speed due to parallel execution of a plurality of CPUs cannot be utilized. Further, when a busy loop is used for synchronization between CPUs instead of interrupts, there is a problem that it is impossible to perform processing other than communication between CPUs.

  The present invention has been made in order to solve the above-described problems, and reduces the delay time due to inter-CPU communication and enables optimal control of wait processing in stages according to the synchronization waiting time. For the purpose.

In the inter-CPU communication system according to the present invention, data is transmitted between the transmitting CPU and the receiving CPU via a memory shared by a transmitting CPU that transmits data and a receiving CPU that receives data. In an inter-CPU communication system that performs communication,
The sending CPU is
A memory area determination unit that determines whether or not there is a free area in the memory;
A data writing unit that executes a data writing process for writing data to the memory when the memory region determining unit determines that there is a free space in the memory;
A receiving-side CPU determining unit that determines a state of the receiving-side CPU when the memory region determining unit determines that there is no free space in the memory;
When the receiving CPU determination unit determines that the state of the receiving CPU is an execution state of a data read process for reading data from the memory, the data writing unit writes data until there is a free space in the memory. Reading to cause the receiving CPU to start executing the data reading process when the receiving CPU determining unit determines that the receiving CPU state is not the execution state of the data reading process. And a transmission-side control unit that transmits a start request to the reception-side CPU.

  In the inter-CPU communication system in which the transmission side CPU and the reception side CPU communicate with each other via the memory, the transmission side CPU has a memory area determination unit that determines whether there is an empty area in the memory, A data writing unit for writing data to the memory, a receiving side CPU determining unit for determining the state of the receiving side CPU when there is no free space, and a memory for when the state of the receiving side CPU is an execution state of the data reading process The data writing unit is put in a waiting state until a free space is created in the receiver, and when the receiving CPU is not in the data reading process execution state, a read start request is issued to cause the receiving CPU to start executing the data reading process. And a transmission side control unit for transmission to the CPU, so that a waiting state for waiting for a free area in the memory is selected according to the state of the reception side CPU. Since bets can, it is possible to reduce the delay time due to the wait state for communication between CPU.

1 is a system configuration diagram of an inter-CPU communication system 800 according to Embodiment 1. FIG. 3 is a functional block diagram of an inter-CPU communication system 800 according to Embodiment 1. FIG. 3 is a diagram illustrating an example of a hardware configuration of an inter-CPU communication system 800 according to Embodiment 1. FIG. 7 is a flowchart showing a transmission-side inter-CPU communication control process (data transmission process) of the transmission-side CPU in the inter-CPU communication system 800 according to the first embodiment. 12 is a flowchart illustrating another example of a transmission-side CPU communication control process (data transmission process) of a transmission-side CPU in the inter-CPU communication system 800 according to Embodiment 1. 4 is a flowchart showing a receiving-side CPU communication control process by the receiving-CPU communication control unit 321 of the receiving CPU according to Embodiment 1; 10 is a flowchart showing a transmission side CPU communication control process of an inter-CPU communication control unit 321 according to the second embodiment. 10 is a flowchart illustrating a case where a continuation flag 311 is set only when the transmission-side CPU communication control process of the CPU-CPU communication control unit 321 according to the second embodiment is in a wait state due to a busy loop. FIG. 10 is a block configuration diagram of an inter-CPU communication system 800 in a third embodiment. 12 is a flowchart of a transmission side scheduling control method (transmission side scheduling control process) of the inter-CPU communication system 800 according to Embodiment 3. 10 is a flowchart of a receiving side scheduling control method (receiving side scheduling control process) of the inter-CPU communication system 800 according to the third embodiment. FIG. 10 is a flowchart showing an operation of timeout time determination processing according to the third embodiment. FIG. 10 is a functional block diagram of an inter-CPU communication system 800 in a fourth embodiment. FIG. 10 is a flowchart showing an example of a transmission-side inter-CPU communication method of an inter-CPU communication system 800 in a fourth embodiment. FIG. 10 is a flowchart showing an example of a receiving-side inter-CPU communication method of an inter-CPU communication system 800 in a fourth embodiment. FIG. 9 is a configuration diagram of an inter-CPU communication system having an asymmetric multi-CPU configuration according to a fifth embodiment.

Embodiment 1 FIG.
FIG. 1 is a system configuration diagram of an inter-CPU communication system 800 according to the first embodiment. A system configuration of the inter-CPU communication system 800 will be described with reference to FIG. In the present embodiment, the inter-CPU communication system 800 is a symmetric multi-CPU system in which a plurality of CPUs perform data communication via a memory. Further, an apparatus (computer, computer apparatus) including the inter-CPU communication system 800 is assumed.

  The inter-CPU communication system 800 includes a plurality of CPUs (CPU 101 (CPU # 0), CPU 102 (CPU # 1), CPU 103 (CPU #n)), a memory 104, an IO device 105, and a bus 111. In FIG. 1, the inter-CPU communication system 800 includes three CPUs 101, 102, and 103. However, the present invention is not limited to this, and any number of CPUs may be provided as long as the number of CPUs is two or more. The memory 104 is a shared memory that can be accessed from all the CPUs included in the inter-CPU communication system 800. The IO device 105 is a shared IO device that can be accessed from all the CPUs included in the inter-CPU communication system 800. The bus 111 is a bus that connects all the CPUs 101, 102, 103, the memory 104, and the IO device 105 included in the inter-CPU communication system 800.

  The plurality of CPUs 101, 102, and 103 included in the inter-CPU communication system 800 exchange data with each other via the memory 104. The inter-CPU communication system 800 is a CPU that performs data communication between a transmission-side CPU and a reception-side CPU via a memory 104 that is shared by a transmission-side CPU that transmits data and a reception-side CPU that receives data. It is an example of an inter-communication system. The inter-CPU communication system 800 (inter-CPU communication system) is a system in which an inter-CPU communication method described later operates.

  FIG. 2 is a functional block diagram of the inter-CPU communication system 800 according to the first embodiment. The function blocks of the CPU 101 and the memory 104 will be described with reference to FIG. It is assumed that the CPUs 101, 102, and 103 included in the inter-CPU communication system 800 have the same configuration (the same configuration as the CPU 101). The CPU 101 operates as a transmitting CPU when transmitting data, and operates as a receiving CPU when receiving data.

  The CPU 101 includes an operation system (OS 301) that operates on the CPU 101, tasks 302, 303, and 304 that operate on the OS 301, an inter-CPU interrupt register 308, a timer register 309, and an inter-CPU communication control unit 321.

  The inter-CPU interrupt register 308 is used for processing for generating an inter-CPU interrupt described later. The timer register 309 is used for processing for generating time measurement and a specified time lapse interrupt, which will be described later.

  The inter-CPU communication control unit 321 controls data communication between CPUs performed via the memory 104. The inter-CPU communication control unit 321 includes a hang-on control unit 322.

  The hang-on control unit 322 performs the following functions when the CPU 101 becomes a CPU that transmits data (hereinafter referred to as a transmission-side CPU), that is, when the CPU 101 becomes a transmission-side CPU. That is, the hang-on control unit 322 includes the following functional blocks.

The sending CPU
(1) A memory area determination unit 351 that determines whether or not there is an empty area in the memory 104;
(2) A data writing unit 352 that executes a data writing process for writing data to the memory 104 when the memory region determining unit 351 determines that there is an empty area in the memory 104;
(3) A reception-side CPU determination unit 353 that determines the state of the reception-side CPU (reception-side CPU) when the memory region determination unit 351 determines that there is no free space in the memory 104;
(4) When the receiving CPU determination unit 353 determines that the state of the receiving CPU is an execution state of the data reading process for reading data from the memory 104, the data writing unit 352 is used until the memory 104 has a free space. Reading to make the receiving CPU start executing the data reading process when the receiving CPU determining unit 353 determines that the receiving CPU is not in the data reading process execution state. A transmission side control unit 354 that transmits a start request to the CPU on the reception side;
Is provided.

  When the receiving CPU determining unit 353 determines that the receiving CPU state is the execution state of the data reading process, the transmitting control unit 354 causes the data writing unit 352 to wait busy until the memory 104 has a free space. By making it (busy loop), the data write processing is waited. The transmission-side control unit 354 causes the reception-side CPU to start executing the data reading process when the reception-side CPU determination unit 353 determines that the state of the reception-side CPU is not the execution state of the data reading process. A read start request is transmitted to the receiving CPU by inter-CPU interruption. The transmission-side control unit 354 transmits a read start request to the reception-side CPU by an inter-CPU interrupt, and then waits for a data write process by an inter-CPU interrupt (that is, a wait state by a transmission waiting semaphore 306 described later) To do.

  The hang-on control unit 322 performs the following functions when the CPU 101 is a CPU that receives data (hereinafter referred to as a receiving CPU), that is, when the CPU 101 is a receiving CPU. That is, the hang-on control unit 322 includes the following functional blocks.

The receiving CPU
(1) a memory state determination unit 361 that determines whether data is stored in the memory 104;
(2) a data read unit 362 that executes a data read process for reading data from the memory 104 when the memory state determination unit 361 determines that data is stored in the memory 104;
(3) A transmission side CPU determination unit 363 that determines the state of the transmission side CPU when the memory state determination unit 361 determines that no data is stored in the memory 104;
(4) When the transmission side CPU determination unit 363 determines that the state of the transmission side CPU is the execution state of the data writing process, the data reading unit 362 waits for the data reading process until the data is stored in the memory 104. When the transmission side CPU determination unit 363 determines that the state of the transmission side CPU is not the execution state of the data write process, a write start request for starting the execution of the data write process is transmitted to the data write unit 352 Receiving side control unit 364 for transmitting to the side CPU;
Is provided.

  When the transmission side CPU determination unit 363 determines that the state of the transmission side CPU is the execution state of the data writing process, the reception side control unit 364 keeps the data reading unit 362 busy until data is stored in the memory 104. By waiting (busy loop), the data read processing is waited. In addition, when the transmission side CPU determination unit 363 determines that the state of the transmission side CPU is not the execution state of the data writing process, the reception side control unit 364 causes the data writing unit 352 to start executing the data writing process. Is sent to the sending CPU by an inter-CPU interrupt. The reception-side control unit 364 transmits a write start request to the transmission-side CPU by an inter-CPU interrupt, and waits for a data read process by an inter-CPU interrupt (that is, a wait state by a reception waiting semaphore 307 described later). To do.

  The transmission side control unit 354 and the reception side control unit 364 expect that the waiting state will be released early when the communication partner is executing communication processing, and wait in a busy loop, and the communication partner is in a sleep state or a semaphore wait state (that is, In the case of (sleep state), after notifying by an interrupt between CPUs, it sets itself to a wait state by a semaphore. As a result, when it is expected that the time until the data full release or the time until the data empty release is short, wait in the busy loop, and the time until the data full release or the time until the data empty release is expected to be delayed. Can be controlled to be in a state of waiting by an inter-CPU interrupt (wait state by a semaphore). Here, the data full release means that a free area is created in the memory, and the data empty release means that data is stored in the memory.

  The memory 104 includes a communication memory 305, a transmission waiting semaphore 306, a reception waiting semaphore 307, a continuation flag 311, and a ready flag 312.

  The communication memory 305 is a memory on the memory 104, and is a memory for data communication between CPUs. The transmission side CPU transmits the data to be transmitted by writing it in the memory 104, and the reception side CPU receives the data by reading the data written in the memory 104. That is, the transmitting CPU and the receiving CPU perform data transmission / reception (communication) via the memory 104.

  The transmission waiting semaphore 306 is used for causing the sending CPU to perform an inter-CPU interrupt (data writing process transmitted from the receiving CPU to the sending CPU) when there is no free space in the communication memory (data full state). This is a semaphore variable used to wait for data write processing until an interrupt is received.

  The reception waiting semaphore 307 causes the receiving CPU to perform an inter-CPU interruption (data reading process transmitted from the transmitting CPU to the receiving CPU) when data is not stored in the communication memory (in a data empty state). This is a semaphore variable used to wait for the data reading process until it receives an interrupt.

  In the case of a semaphore wait using the transmission waiting semaphore 306 or the reception waiting semaphore 307, the task to be waited once abandons the CPU and switches execution to another executable task. At this time, the semaphore (the transmission waiting semaphore 306 or the reception waiting semaphore 307) is set to a value (for example, value zero) indicating that the data writing process or the data reading process cannot be executed. When an inter-CPU interrupt is received in this state, the corresponding semaphore (transmission wait semaphore 306 or reception wait semaphore 307) is counted up, and the task waiting for the corresponding semaphore (data write processing task or data read) The processing task is ready to be executed, and is rescheduled and restarted by the OS 301. The OS 301 manages whether or not the task is waiting for processing.

  The continuation flag 311 is a flag indicating that data transmission is continuously performed. The continuation flag 311 is an example of a transmission side state flag indicating the state of the transmission side CPU. The transmission side CPU determination unit 363 determines the state of the transmission side CPU based on the continuation flag 311. For example, when the continuation flag 311 is on (when the continuation flag 311 is set), the transmission side CPU determination unit 363 is executing the data writing process (that is, continuously executing data transmission). ). The case where the transmission side CPU is executing the data writing process (that is, continuously executing the data transmission) includes the case where the transmission side CPU is in a busy loop and waiting for the data writing process.

  For example, when the continuation flag 311 is off (when the continuation flag 311 is cleared), the transmission-side CPU determination unit 363 determines that the transmission-side CPU is not executing the data writing process. If the sending CPU is not executing the data writing process, the data writing unit (data writing process) is in the sleep state, or the data writing unit (data writing process) is in a wait state by the transmission waiting semaphore 306 and is in another state. Shows when the task is running. The other task here means a task other than the inter-CPU communication control unit 321 (for example, tasks 302, 303, 304, etc.).

  The ready flag 312 is a flag indicating that data reception is waited in a busy loop. The ready flag 312 is an example of a reception side state flag indicating the state of the reception side CPU. The reception side CPU determination unit 353 determines the state of the reception side CPU based on the ready flag 312. For example, when the ready flag 312 is on, the reception-side CPU determination unit 353 determines that the reception-side CPU is executing a data reading process (that is, executing data reception). The fact that the receiving CPU is executing the data reading process (that is, executing the data receiving) includes the case where the receiving CPU is in a busy loop and waiting for the data reading process.

  Further, for example, when the ready flag 312 is off, the reception-side CPU determination unit 353 determines that the reception-side CPU is not executing the data reading process. When the receiving CPU is not executing the data reading process, the data reading unit (data reading process) is in the sleep state, or the data reading unit (data reading process) is in a wait state by the reception waiting semaphore 307 and is in another state. Shows when the task is running.

  The busy loop is a process of waiting for a change in the predetermined value by checking a predetermined value (for example, a value such as a flag indicating the state of the memory 104) by a continuous loop.

  FIG. 3 is a diagram illustrating an example of a hardware configuration of the inter-CPU communication system 800 according to the first embodiment.

  FIG. 3 is a diagram illustrating an example of hardware resources of the device 890 including the inter-CPU communication system 800 according to the following embodiment. In FIG. 3, an apparatus 890 including the inter-CPU communication system 800 includes a plurality of CPUs 911 (also referred to as a central processing unit, a central processing unit, a processing unit, an arithmetic unit, a microprocessor, a microcomputer, and a processor) that execute a program. CPU 911 (101), CPU 911 (102), CPU 911 (103)). The CPU 911 is connected to the ROM 913, the RAM 914, the communication board 915, the display device 901, the keyboard 902, the mouse 903, the FDD 904, the CDD 905, the printer device 906, the scanner device 907, and the magnetic disk device 920 via the bus 111. Control the device. These hardware devices (ROM 913, RAM 914, communication board 915, display device 901, keyboard 902, mouse 903, FDD 904, CDD 905, printer device 906, scanner device 907, magnetic disk device 920, etc.) are examples of the IO device 105. is there. Instead of the magnetic disk device 920, a storage device such as an optical disk device or a memory card read / write device may be used.

  The RAM 914 is an example of a volatile memory. The storage media of the ROM 913, the FDD 904, the CDD 905, and the magnetic disk device 920 are an example of a nonvolatile memory. These are examples of a storage device or a storage unit.

  The communication board 915, the keyboard 902, the scanner device 907, the FDD 904, the display device 901, and the like are examples of an input unit and an input device. Further, a touch panel or the like may be provided as an input device. Further, the communication board 915, the display device 901, the printer device 906, and the like are examples of an output unit and an output device.

  The communication board 915 is connected to a facsimile machine, a telephone set, a LAN, and the like. The communication board 915 may be connected not only to the LAN but also to a WAN (wide area network) such as the Internet or ISDN.

  The magnetic disk device 920 stores an operating system 921 (OS 301), a window system 922, a program group 923, and a file group 924. The programs in the program group 923 are executed by the CPU 911, the operating system 921, and the window system 922.

  The program group 923 stores programs for executing functions described as “˜unit” and “˜means” in the description of the embodiments described below. The program is read and executed by the CPU 911. The file group 924 includes information, data, signal values, variable values, and parameters that are described as “determination results of”, “calculation results of”, and “processing results of” in the description of the embodiments described below. Are stored as items “˜file”, “˜database”, and “˜data”. “˜file”, “˜database”, and “˜data” are stored in a recording medium such as a disk or a memory. Information, data, signal values, variable values, and parameters stored in a storage medium such as a disk or memory are read out to the main memory or cache memory by the CPU 911 via a read / write circuit, and extracted, searched, referenced, compared, Used for CPU operations such as calculation, calculation, processing, output, printing, and display. Information, data, signal values, variable values, and parameters are temporarily stored in the main memory, cache memory, and buffer memory during the CPU operations of extraction, search, reference, comparison, operation, calculation, processing, output, printing, and display. Is remembered.

  In addition, the arrows in the flowcharts described in the following description of the embodiments mainly indicate input / output of data and signals. The data and signal values are the RAM 914 memory, the FDD 904 flexible disk, the CDD 905 compact disk, and the magnetic field. The data is recorded on a recording medium such as a magnetic disk of the disk device 920, another optical disk, a mini disk, and a DVD (Digital Versatile Disk). Data and signals are transmitted online via the bus 111, signal lines, cables and other transmission media.

  In addition, what is described as “to part” in the description of the embodiment described below may be “to circuit”, “to device”, “to device”, “means”, and “to step”. ”,“ ˜procedure ”, or“ ˜processing ”. That is, what is described as “˜unit” may be realized by firmware stored in the ROM 913. Alternatively, it may be implemented only by software, or only by hardware such as elements, devices, substrates, and wirings, by a combination of software and hardware, or by a combination of firmware. Firmware and software are stored as programs in a recording medium such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, and a DVD. The program is read by the CPU 911 and executed by the CPU 911. That is, the program causes the computer to function as “to part” described below. Alternatively, the procedure or method of “to part” described below is executed by a computer.

  Next, the operation of the inter-CPU communication control method of the inter-CPU communication system 800 according to the present embodiment will be described.

  FIG. 4 is a flowchart showing a transmission-side CPU communication control process (also referred to as a data transmission process) by the CPU-side communication control unit 321 of the transmission-side CPU according to the first embodiment. In FIG. 4, it is assumed that the transmission-side CPU communication control process is a process executed by the CPU 101. The functional blocks described below (hang-on control unit 322 (memory area determination unit 351, data writing unit 352, reception-side CPU determination unit 353, transmission-side control unit 354, etc.)) are stored in the storage device. It is read out and executed by the CPU 101.

  When the CPU 101 starts data transmission processing for inter-CPU communication, the hang-on control unit 322 sets the continuation flag 311 in S401a. In step S <b> 401, the hang-on control unit 322 (data writing unit 352) writes data to be transmitted to the communication memory 305 of the memory 104. In this case, the CPU 101 is an example of a transmission side CPU.

  In S402, the hang-on control unit 322 (reception-side CPU determination unit 353) determines the ready flag 312. If the hang-on control unit 322 (reception-side CPU determination unit 353) determines that the ready flag 312 is not set (No in S402), the process proceeds to S403.

  If the hang-on control unit 322 (reception-side CPU determination unit 353) determines that the ready flag 312 is set (Yes in S402), the process proceeds to S404.

  If the ready flag 312 is not set in S402, this means that the task that receives the communication data (the data reading unit 362 of the receiving CPU) is not in the sleep state or is in the wait state by the reception waiting semaphore 307. (Sleep state). Accordingly, in S403, the hang-on control unit 322 interrupts the CPU on the receiving side with a data read start request to wake up the task (data reading unit 362 of the receiving CPU) that receives the communication data of inter-CPU communication ( This is transmitted as a data read start request X1). In the receiving CPU, a receiving task (data reading unit 362 of the receiving CPU) is woken up by an inter-CPU interrupt (data reading start request X1), or the receiving waiting semaphore 307 is counted up and the receiving task (receiving) The wait state of the data reading unit 362) of the side CPU is released (S461 described later). Here, to wake up a task or “˜part” means to start (wake up) the task or “˜part” (the same applies hereinafter).

  When the ready flag 312 is set in S402, it means that the task for receiving communication data (the data reading unit 362 of the receiving CPU) is being executed (including a case where the busy loop is in the wait state). . Therefore, the notification (inter-CPU interrupt (data read start request X1)) to the receiving CPU by the hang-on control unit 322 becomes unnecessary.

  In S404, the hang-on control unit 322 checks whether transmission of all data is completed. If transmission of all data has been completed (Yes in S404), the process proceeds to S411. If transmission of all data has not been completed (No in S404), the process proceeds to S405.

  When the transmission of all data is completed (Yes in S404), the hang-on control unit 322 clears the continuation flag 311 in S411 and completes the transmission-side inter-CPU communication control process.

  If transmission of all data has not been completed (No in S404), in S405, the hang-on control unit 322 (memory area determination unit 351) checks whether data full has occurred in the communication memory 305 of the memory 104. To do. That is, the memory area determination unit 351 determines whether there is a free area in the communication memory 305 of the memory 104.

  If data full has not occurred in the communication memory 305 of the memory 104 (No in S405), the process returns to S401 and repeats the data transmission process. When data full occurs in the communication memory 305 of the memory 104, the hang-on control unit 322 (data writing unit 352) cannot continue to transmit (write) data. If data full has occurred in the communication memory 305 of the memory 104 (Yes in S405), the process proceeds to S406.

  In step S <b> 406, the hang-on control unit 322 (reception-side CPU determination unit 353) determines the ready flag 312. That is, the hang-on control unit 322 (reception side CPU determination unit 353) determines the state of the reception side CPU.

  If the hang-on control unit 322 (reception-side CPU determination unit 353) determines that the ready flag 312 is not set (No in S406), the process proceeds to S406a. If the hang-on control unit 322 (reception-side CPU determination unit 353) determines that the ready flag 312 is set (Yes in S406), the process proceeds to S410.

  When the ready flag 312 is set, the receiving CPU is continuously trying to receive data (that is, the receiving CPU is busy executing the data reading process or the receiving CPU is busy with the data reading process). Means waiting. As described above, since the data reading process of the receiving CPU is being executed, it is estimated that an empty area should be formed in the communication memory 305 of the memory 104 in a short time.

  In S410, the hang-on control unit 322 (transmission-side control unit 354) places the data writing unit 352 in a waiting state for data writing processing until a free area is created in the memory. In other words, the hang-on control unit 322 (transmission-side control unit 354) waits for the communication memory 305 to be free in a busy loop. The hang-on control unit 322 (transmission side control unit 354) loops until the data full in the communication memory 305 is resolved.

  If the hang-on control unit 322 (reception side control unit 354) determines in S410 that the communication memory 305 has a free area, the hang-on control unit 322 releases the busy wait state, and the process returns to S401 to execute the data transmission process.

  The fact that the ready flag 312 is not set in S406 means that the task (data reading unit 362 of the receiving CPU) that receives communication data is in a wait state (sleep state) by the reception waiting semaphore 307. When the task that receives the communication data (the reception data reading unit 362 of the reception side CPU) is in the wait state (sleep state) by the reception waiting semaphore 307, the reception side CPU other than the hang-on control unit 322 (reception data reading unit 362) Since another task is being executed, it is estimated that the time until the data reception process (data read process) starts increases. That is, when the ready flag 312 is set (when the received data reading unit 362 is executing or busy waiting), when the ready flag 312 is not set (when the received data reading unit 362 is sleeping, or The time until the data reading unit 362 starts the data reading process is shorter than that during the waiting due to the reception waiting semaphore.

  Therefore, when the ready flag 312 is not set, the hang-on control unit 322 (transmission-side control unit 354) does not busy wait for the data writing process, and the CPU for starting the reception data reading process of the receiving CPU. In addition to executing the interim interrupt, its own data write processing (data transmission processing) is put into a wait state by the transmission waiting semaphore 306, and processing for switching the processing of the transmitting CPU to another task is executed.

  In S406a, the hang-on control unit 322 (transmission side control unit 354) clears the continuation flag 311.

  In S406b, the hang-on control unit 322 (transmission side control unit 354) sends a data read start request to the reception side CPU to wake up the task (communication data read unit 362 of the reception side CPU) that receives communication data for inter-CPU communication. It is transmitted as an inter-CPU interrupt (data read start request X1).

  In step S <b> 407, the hang-on control unit 322 (transmission side control unit 354) sets the data writing process to a wait state by the transmission waiting semaphore 306. When the hang-on control unit 322 (transmission side control unit 354) receives an inter-CPU interrupt (data write request X2) from the reception side CPU (S409), the hang-on control unit 322 releases the wait state by the transmission waiting semaphore 306 in the data write processing. Returning to S401, data transmission processing is executed.

  In S409a, the hang-on control unit 322 (transmission side control unit 354) sets the continuation flag 311, returns the process to S401, and continues the data transmission process.

  In the transmission side inter-CPU communication control method shown in FIG. 4, the continuation flag 311 is set when the inter-CPU communication control unit 321 is being executed (including the case where the inter-CPU communication control unit 321 is in a wait state due to a busy loop), and the CPU When the inter-communication control unit 321 is in a wait state by the transmission waiting semaphore 306, the continuation flag 311 is cleared.

  However, for example, in the transmission-side CPU communication control process, the continuation flag 311 may be set only when the CPU communication control unit 321 is in a wait state due to a busy loop. In the case of the above processing, S401a (continuation flag setting processing), S406a (continuation flag clearing processing), and S409a (continuation flag setting processing) are not required. Then, the hang-on control unit 322 (transmission-side control unit 354) sets the continuation flag 311 in the case of Yes in S406 (when the ready flag 312 is set), and then starts the busy loop processing of S410. (See FIG. 5).

  This is the end of the description of the transmission-side CPU communication control process. Next, the communication control process between the receiving CPUs of the receiving CPU will be described.

  FIG. 6 is a flowchart showing the inter-reception CPU communication control processing by the inter-CPU communication control unit 321 of the reception CPU according to the present embodiment. In FIG. 6, it is assumed that the receiving-side CPU communication control process is a process executed by the CPU 101. The functional blocks described below (hang-on control unit 322 (memory state determination unit 361, data reading unit 362, transmission side CPU determination unit 363, reception side control unit 364, etc.)) are stored in the storage device, and the CPU 101 It is read out and executed by the CPU 101.

  When the CPU 101 starts data reception processing for communication between CPUs (reception-side CPU communication control processing), the hang-on control unit 322 sets (turns on) the ready flag 312 in S451. In this case, the CPU 101 is an example of a receiving CPU.

  In S452, the hang-on control unit 322 (memory state determination unit 361) checks whether data full has occurred in the communication memory 305 of the memory 104. That is, the hang-on control unit 322 (memory state determination unit 361) checks whether there is a free area in the communication memory 305 of the memory 104. If the hang-on control unit 322 (memory state determination unit 361) determines that the memory 104 (communication memory 305) is full of data (Yes in S452), the process proceeds to S453. If the hang-on control unit 322 (memory state determination unit 361) determines that the memory 104 (communication memory 305) is not full of data (No in S452), the process proceeds to S456.

  In step S453, the hang-on control unit 322 (data reading unit 362) executes data reception processing for receiving (reading) data from the communication memory 305. Next, in S454, the hang-on control unit 322 (transmission-side CPU determination unit 363) checks whether or not the continuation flag 311 is set.

  If the hang-on control unit 322 (transmission-side CPU determination unit 363) determines that the continuation flag 311 is set (Yes in S454), the process proceeds to S463. If the hang-on control unit 322 (transmission-side CPU determination unit 363) determines that the continuation flag 311 is not set (No in S454), the process proceeds to S455.

  In S454, the fact that the continuation flag 311 is not set means that the task for transmitting communication data (the hang-on control unit 322 (data writing unit 352) of the transmission side CPU) is not activated, or This means that it is in a wait state (sleep state) by the transmission waiting semaphore 306.

  Therefore, in S455, the hang-on control unit 322 issues an inter-CPU interrupt (data write start request) to wake up a task for transmitting communication data for inter-CPU communication (data writing unit 352 of the sending CPU). X2) is transmitted to the transmitting CPU. In the transmission side CPU, a transmission task (data writing unit 352 of the transmission side CPU) is woken up by an inter-CPU interrupt (data write start request X2), or the transmission waiting semaphore 306 is counted up and the transmission task (transmission) The wait state of the data writing unit 352) of the side CPU is released (see S409).

  In S455, after the hang-on control unit 322 executes an inter-CPU interrupt (data write start request X2) for the transmitting CPU, the process proceeds to S463.

  In S454, the continuation flag 311 is set, which means that the task that transmits communication data in the transmission side CPU (data writing unit 352 of the transmission side CPU) is in a wake-up state, but the memory 104 is full of data and is busy loop. This means that the data writing process is in a wait state. Therefore, the notification (inter-CPU interrupt (data write start request X2)) to the transmitting CPU by the hang-on control unit 322 is not necessary. In other words, the fact that the continuation flag 311 is set in S454 means that the sending CPU is waiting in a busy loop until the communication memory 305 is available. At this time, the process proceeds to S463.

  In step S463, the hang-on control unit 322 (data reading unit 362) checks whether reception of all data is completed. If the hang-on control unit 322 (data reading unit 362) determines that the reception of all data has been completed (Yes in S463), the process proceeds to S464. If the hang-on control unit 322 (data reading unit 362) determines that the reception of all data has not been completed (No in S463), the process returns to S452.

  In S464, since the reception of all data has been completed, the hang-on control unit 322 clears the ready flag 312 and ends the receiving-side inter-CPU communication control process.

  As described above, when the hang-on control unit 322 determines that the memory 104 (communication memory 305) is not full of data (No in S452), the process proceeds to S456. In S <b> 456, the hang-on control unit 322 (memory state determination unit 361) determines whether data is stored in the communication memory 305 of the memory 104. That is, the hang-on control unit 322 (memory state determination unit 361) determines whether or not the memory 104 (communication memory 305) is data empty.

  If the hang-on control unit 322 (memory state determination unit 361) determines that the data is empty in S456 (Yes in S456), the process proceeds to S457. If the hang-on control unit 322 (memory state determination unit 361) determines that the data is not empty (No in S456), the process proceeds to S462, and the hang-on control unit 322 (data reading unit 362) performs data reception processing. The

  In S457, the hang-on control unit 322 (transmission side CPU determination unit 363) determines the state of the transmission side CPU. That is, the hang-on control unit 322 (transmission-side CPU determination unit 363) checks whether or not the continuation flag 311 is set. In S457, when the hang-on control unit 322 (transmission-side CPU determination unit 363) determines that the continuation flag 311 is set (Yes in S457), the process returns to S456. If the hang-on control unit 322 (transmission-side CPU determination unit 363) determines that the continuation flag 311 is not set (No in S457), the process proceeds to S458.

  The fact that the continuation flag 311 is set in S456 indicates that the data writing unit 352 (data transmission processing) of the transmission side CPU is continuously executing even if the memory 104 is data empty. . Therefore, since it is estimated that the data empty of the memory 104 is canceled within a short time, the hang-on control unit 322 (reception side control unit 364) performs the busy loop until the data empty of the memory 104 (communication memory 305) is canceled. The data reception process (data read process) is set to the wait state.

  That is, when the hang-on control unit 322 (reception side control unit 364) determines that the continuation flag 311 is set, the data reception process (data read-out) is performed in a busy loop until the data empty of the memory 104 (communication memory 305) is eliminated. Process) is set to the wait state.

  The fact that the continuation flag 311 is not set in S457 means that the memory 104 is data empty and is in a sleep state in which the task for transmitting communication data (data writing unit 352 of the sending CPU) is not activated, Alternatively, this means that the transmission wait semaphore 306 is in a wait state (sleep state). If the task for transmitting communication data (data writing unit 352 of the sending CPU) is not activated or is in a wait state (sleeping state) by the transmission waiting semaphore 306, the sending CPU performs data transmission processing. (Data writing process) It is estimated that the time until the start becomes longer. Therefore, the receiving CPU waits for the elapse of a predetermined time according to the following procedure (S458 to S461) and shifts to the wait state by the reception waiting semaphore 307, and the processing of the CPU 101 is changed from the data receiving processing to the processing of other tasks. The data reception process is switched to the wait state.

  The reception side CPU (reception side control unit 364 (second timeout time storage unit)) stores the second timeout time in the storage device in advance. The second timeout time defines the upper limit of the continuous execution time of the busy loop from S456 to S458.

  As described above, when the transmission CPU determination unit 363 determines in S457 that the state of the transmission CPU is not the execution state of the data writing process (the continuation flag 311 is not set), the hang-on control is performed in S458. The unit 322 (reception side control unit 364) first determines whether or not the second time-out period has elapsed since it was determined in S456 that the memory is data empty. That is, in S458, the hang-on control unit 322 (reception side control unit 364) checks whether a timeout has occurred using the specified time (second timeout time) stored in the storage device.

  If the second timeout time has not elapsed in S458 (no timeout has occurred) (No in S458), the hang-on control unit 322 (reception side control unit 364) returns the process to S456, and the memory 104 Until the data is stored in (communication memory 305), the data reading unit 362 is set in a waiting state (busy wait state) for data reading processing by a busy loop.

  When the second timeout time has elapsed in S458 (when a timeout has occurred) (Yes in S458), the hang-on control unit 322 (reception side control unit 364) advances the process to S459.

  In S459, the hang-on control unit 322 (reception side control unit 364) clears the ready flag 312. In S459a, the hang-on control unit 322 (reception side control unit 364) sends a data write start request to the transmission side CPU to wake up a task (data transmission unit 352 of the transmission side CPU) that transmits communication data for inter-CPU communication. It is transmitted as an inter-CPU interrupt (data write start request X2).

  In S460, the hang-on control unit 322 (reception side control unit 364) sets the data reading process to the wait state by the reception waiting semaphore 307. When the hang-on control unit 322 (reception side control unit 364) receives an inter-CPU interrupt (data read start request X1) from the transmission side CPU in a wait state by the reception waiting semaphore 307 of the data read process (S461), the data read is performed. The wait state by the process reception waiting semaphore 307 is released, and the process proceeds to S461a. In S461a, the hang-on control unit 322 (reception side control unit 364) sets the ready flag 312 and proceeds to S462. The reception side control unit 364 is an example of a reception side scheduling unit.

  In S462, the hang-on control unit 322 (data reading unit 362) executes a data reading process (data receiving process) for reading data from the memory 104 (communication memory 305).

  In S457 to S458, if the continuation flag 311 is not set and a timeout has occurred, the memory 104 is in a data empty state, but the data writing process of the sending CPU is sleeping, and This means that data has not been stored in the memory 104 after the elapse of time (second timeout time). As described above, when the task for transmitting the communication data (data writing unit 352 of the transmission side CPU) is not activated or is in the wait state (sleep state) by the transmission waiting semaphore 306, the communication data It is estimated that there is a high possibility that the time until the transmission (writing) process starts will be long.

  Therefore, in S459a to S460, the hang-on control unit 322 (reception side control unit 364) executes an inter-CPU interrupt for starting the data writing process of the transmission side CPU, and its own data reception process is a reception waiting semaphore. The waiting state is set to 307, and the data reading process of the receiving CPU is switched to the process of another task.

  As described above, when the reception of all data is completed in S463, the hang-on control unit 322 clears the ready flag 312 in S464, and completes the data reception process of the inter-CPU communication.

  If the data reception processing for the next inter-CPU communication can be started immediately, the hang-on control unit 322 does not perform the clear processing of the ready flag 312 in S464, thereby interrupting the CPU from the receiving CPU ( It is also possible not to send the data read start request X1).

  In the present embodiment, the following inter-CPU communication method (inter-CPU communication system 800) has been described.

The inter-CPU communication method according to the present embodiment is the following means in the inter-CPU communication method in which two or more CPUs (101, 102, 103,...) Perform data communication via the memory 104. It is characterized by providing.
(A) Hang-on control means (hang-on control unit 322) for controlling whether to wait for data full elimination waiting on the transmission side by communication between CPUs and waiting for data empty on the receiving side by interrupt between CPUs or by busy loop Inter-CPU communication control means (inter-CPU communication control unit 321).
(B) A continuation flag 311 indicating that data transmission is continuously performed.
(C) A ready flag 312 indicating waiting for data reception in a busy loop.

  In the inter-CPU communication system according to the present embodiment, the hang-on control means (hang-on control unit 322) waits in a busy loop until the timeout occurs by setting the timeout time using the second timeout time, and after the timeout occurs Is characterized in that it is automatically switched to wait by an inter-CPU interrupt.

  As described above, according to the inter-CPU communication system 800 of the present embodiment, the hang-on control unit (hang-on control unit 322) in the inter-CPU communication control unit (inter-CPU communication control unit 321) is connected to the continuation flag 311 and the ready flag 311. Based on the value of the flag 312, control is performed by switching between a wait by a busy loop and a wait by an interrupt between CPUs. Therefore, when the CPU (transmission side CPU, reception side CPU) continuously transmits and receives data, high-speed communication between CPUs can be performed without receiving a delay due to an inter-CPU interrupt.

  If the continuous data processing continues, the next inter-CPU communication can be continued without using the inter-CPU interrupt by not clearing the ready flag (312) in S464. Therefore, since it is possible to perform control in anticipation of starting data reception of the next inter-CPU communication in a short time, it is possible to eliminate a delay due to an inter-CPU interrupt.

  In the present embodiment, a memory area determination unit 351, a data writing unit 352, a reception-side CPU determination unit 353, a transmission-side control unit 354, a memory state determination unit 361, a data reading unit 362, and a transmission-side CPU included in the hang-on control unit 322. The determination unit 363 and the reception-side control unit 364 have been described as being configured as independent functional blocks. However, the functional block may be configured as one functional block. The memory area determination unit 351, the data writing unit 352, the reception-side CPU determination unit 353, and the transmission-side control unit 354 are configured as one functional block, and the memory state determination unit 361, the data reading unit 362, and the transmission-side CPU determination unit 363 are used. And the receiving side control unit 364 may be configured as one functional block. Alternatively, all functional blocks may be independent functional blocks. Alternatively, these functional blocks may be configured in any other combination.

Embodiment 2. FIG.
In the first embodiment, a timeout process (S458 in FIG. 6) is added to the hang-on control means (reception-side CPU communication control process of the hang-on control part 322) of the reception-side CPU communication control means (inter-CPU communication control part 321). Thus, the setting and clearing of the ready flag 312 are controlled. That is, in the communication control process between the receiving CPUs, the upper limit of the busy loop execution time is controlled by the timeout process, and the execution of the busy loop is controlled mainly by the receiving CPU.

  In the present embodiment, a case will be described in which timeout processing is executed by the hang-on control means (transmission-side inter-CPU communication control process of the hang-on control section 322) of the transmission-side CPU communication control means (inter-CPU communication control section 321). .

  The configuration of the inter-CPU communication system 800 (inter-CPU communication system, inter-CPU communication method) according to the present embodiment is the same as that in FIG.

  In the present embodiment, the transmission-side CPU communication control process of the inter-CPU communication control unit 321 is obtained by changing a part of the operation of the transmission-side inter-CPU communication control process of FIG. FIG. 7 is a flowchart showing a transmission-side CPU communication control process of the inter-CPU communication control unit 321 according to the present embodiment. 7, the same operations as those in FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 7, the processing between S401 to S405 is the same as that in FIG. In addition, the hang-on control unit 322 (transmission side control unit 354 (first timeout time storage unit)) of the inter-CPU communication control unit 321 according to the present embodiment stores the first timeout time in the storage device in advance. In S405, if the hang-on control unit 322 determines that the memory 104 (communication memory 305) is full of data, the process proceeds to S501.

  In step S <b> 501, the hang-on control unit 322 (reception-side CPU determination unit 353) determines the ready flag 312. That is, the hang-on control unit 322 (reception side CPU determination unit 353) determines the state of the reception side CPU.

  If the hang-on control unit 322 (reception-side CPU determination unit 353) determines that the ready flag 312 is not set (No in S501), the process proceeds to S406a. The processing from S406a to S409a is the same as that in FIG.

  If the hang-on control unit 322 (reception-side CPU determination unit 353) determines that the ready flag 312 is set (Yes in S501), the process proceeds to S503.

  In S503, the hang-on control unit 322 (transmission-side control unit 354) sets the first timeout time stored in the storage device as the timeout time for continuing the busy loop waiting for data full resolution.

  In step S504, the hang-on control unit 322 (transmission-side control unit 354) determines whether the data full in the memory 104 (communication memory 305) has been eliminated. If it is determined that the data full has been resolved (Yes in S504), the process returns to S401 to execute the data transmission process (data writing process). If it is determined that the data full has not been resolved (No in S504), the process proceeds to S505.

  In step S505, the hang-on control unit 322 (transmission side control unit 354) determines whether or not a data full resolution waiting timeout has occurred due to the first timeout time. In other words, the hang-on control unit 322 (transmission side control unit 354) determines that the data write process is performed when it is determined that the state of the reception side CPU is the execution state of the data read process (the ready flag 312 is set). A wait state is set, and it is determined whether or not the first time-out period has elapsed since the start of the wait state of the data writing process.

  If it is determined that the data full resolution waiting timeout has not occurred (No in S505), the process returns to S504, and the processes from S504 to S505 are repeated until the data full in the memory 104 (communication memory 305) is resolved. That is, since the hang-on control unit 322 (transmission side control unit 354) is executing the data write process of the reception side CPU (including the busy wait of the data write process), it is expected that the data full will be eliminated in a short time. The data write processing (data transmission processing) loops busy until the first timeout time elapses.

  If it is determined that a data full resolution waiting timeout has occurred (Yes in S505), the process proceeds to S406a, and the hang-on control unit 322 (transmission side control unit 354) performs communication control processing between the transmission side CPUs (data write processing (data transmission processing (data transmission processing)). Processing)) is set to a wait state by the transmission waiting semaphore 306.

  The inter-CPU communication control unit 321 according to the present embodiment has the following characteristics. The transmission side control unit 354 stores the first timeout time in the storage device in advance. When the receiving CPU determination unit 353 determines that the receiving CPU is not in the data reading process execution state (No in S501), the data reading start request X1 is transmitted to the receiving CPU (S406b), and waiting for transmission. The semaphore 306 puts the data writing process in a wait state. When the reception-side CPU determination unit 353 determines that the state of the reception-side CPU is the execution state of the data read process (Yes in S501), the transmission-side control unit 354 determines whether or not the first timeout time has elapsed. If the first time-out period has not elapsed, the data write process waits (busy loop) until there is an empty area in the memory 104. If the first time-out period elapses, data read starts. The request X1 is transmitted to the receiving CPU (S406b), and the data write processing by the transmission waiting semaphore 306 is waited. The transmission side control unit 354 is an example of a transmission side scheduling unit.

  In the transmission side inter-CPU communication method shown in FIG. 7, the continuation flag 311 is set when the inter-CPU communication control unit 321 is executing (including the case where the inter-CPU communication control unit 321 is in a wait state due to a busy loop), and the inter-CPU communication It is assumed that the continuation flag 311 is cleared when the communication control unit 321 is in the wait state by the transmission waiting semaphore 306.

  However, for example, in the transmission-side CPU communication control process, the continuation flag 311 may be set only when the inter-CPU communication control unit 321 is in a wait state due to a busy loop (that is, the process of FIG. 5). FIG. 8 is a flowchart illustrating a case where the continuation flag 311 is set only when the transmission-side CPU communication control processing of the CPU-to-CPU communication control unit 321 according to the present embodiment is in a wait state due to a busy loop. That is, FIG. 8 is a flowchart showing processing in which part of FIG. 5 is changed.

  In the case of the above process, S406a (continuation flag clearing process) and S409a (continuation flag setting process) in FIG. 7 are not required. Then, the hang-on control unit 322 (transmission-side control unit 354) sets the continuation flag 311 when S501 is Yes (when the ready flag 312 is set) (S502), and thereafter the busy loop processing of S504 to S505 Execute. The hang-on control unit 322 (transmission side control unit 354) clears the continuation flag 311 in S506 when the busy loop process is exited in S504 to S505 due to the elapse of the first timeout period (timeout occurrence).

  As described above, in the present embodiment, the timeout processing is inserted into the transmission-side CPU communication control means, so that the execution and termination of the busy loop can be controlled in the transmission-side CPU.

Embodiment 3 FIG.
In the first embodiment and the second embodiment described above, based on the continuation flag 311 and the ready flag 312, the wait loop wait and the semaphore wait wait are switched. In the present embodiment, a method for controlling scheduling of the OS 301 at the time of busy loop execution will be described.

  FIG. 9 is a block configuration diagram of an inter-CPU communication system 800 in the present embodiment. 9, the same functional blocks as those in FIG. 2 described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 9, in addition to the configuration of FIG. 2, the inter-CPU communication control unit 321 includes a scheduling control unit 601, an interrupt / context switch delay measurement unit 602, and a busy loop time setting unit 603. Further, as a timeout time of the scheduling control time of the busy loop, a third timeout time 611 (third timeout time) waiting for data full resolution, a fourth timeout time 612 (fourth timeout time) waiting for data full resolution, a data empty waiting time A 5 timeout period 613 (fifth timeout period) and a data empty waiting sixth timeout period 614 (sixth timeout period) are provided in advance. That is, the inter-CPU communication control unit 321 of the inter-CPU communication system 800 previously stores the data full resolution waiting third timeout time 611, the data full resolution waiting fourth timeout time 612, the data empty waiting fifth timeout time 613, and the data empty waiting. A sixth timeout time 614 is determined and stored in a storage device (which may be a local memory of the CPU 101). The inter-CPU communication control unit 321 is an example of a third timeout time storage unit, a fourth timeout time storage unit, a fifth timeout time storage unit, and a sixth timeout time storage unit.

  FIG. 10 shows a transmission side scheduling control method (transmission side scheduling control process) of the inter-CPU communication system according to the present embodiment. The operation of the transmission side scheduling control method by the scheduling control unit 601 of the inter-CPU communication system will be described with reference to FIG.

  In the inter-CPU communication method described in the present embodiment, it is assumed that the continuation flag 311 is a method (that is, the method shown in FIG. 5 or FIG. 8) that is set during a busy loop of data write processing of the receiving CPU. Therefore, a case where FIG. 8 described in the second embodiment is partly changed will be described. The same processes as those described in FIG. 8 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 10, S401 to S502 are the same as the processing of FIG. In S502, when the hang-on control unit 322 sets the continuation flag 311, the process proceeds to S701.

  In step S <b> 701, the scheduling control unit 601 sets a third timeout period 611 waiting for data full resolution. In step S <b> 702, the scheduling control unit 601 sets a fourth timeout period 612 waiting for data full resolution. In the inter-CPU communication control method in the inter-CPU communication control system 801, a method for determining the time to be set as the data full resolution wait third timeout time 611 and the data full resolution wait fourth timeout time 612 will be described later. The scheduling control unit 601 may be an example of the transmission side control unit 354.

  In step S <b> 703, the scheduling control unit 601 issues a scheduling lock instruction to the OS 301 and prohibits switching to other tasks. In step S <b> 704, the scheduling control unit 601 checks whether the data full in the memory 104 (communication memory 305) has been eliminated. At this time, the scheduling control unit 601 may be the memory area determination unit 351. If the data full has not been resolved (No in S704), the scheduling control unit 601 proceeds to S705.

  In S705, the scheduling control unit 601 checks whether a third timeout for waiting for data full has occurred. If no timeout has occurred, the scheduling control unit 601 returns to S704 and waits in a busy loop until the data full is cleared. And That is, the data full cancellation is waited by the busy loop while the scheduling lock state executed in S703 is maintained. Note that interrupts can be received even in the scheduling lock state.

  In step S <b> 705, the scheduling control unit 601 determines whether a third timeout period for waiting for data full resolution has elapsed since the occurrence of the first wait state. When the third timeout waiting for data full resolution due to the third timeout period 611 waiting for data full resolution occurs in S705, the scheduling control unit 601 issues a scheduling lock release instruction to the OS 301 in S706 to enable task switching by the OS 301. To do. Subsequently, the scheduling control unit 601 switches the busy loop scheduling to Yield scheduling that repeats rescheduling between tasks of the same priority in the OS 301. The scheduling control unit 601 proceeds to S707.

  In step S707, the scheduling control unit 601 checks whether the data full has been resolved. If the data full has not been eliminated, the scheduling control unit 601 checks in step S708 whether a fourth timeout has occurred waiting for data full elimination due to the fourth timeout time 612 waiting for data full elimination, and if no timeout has occurred. Returns to S707, and enters a second waiting state in which data full cancellation is waited in a busy loop based on Yield scheduling. That is, the data full cancellation is waited by the busy loop in the scheduling lock release state executed in S706 (second waiting state).

  In S704 or S707, when the data full is resolved, the scheduling control unit 601 returns to S401 and performs data transmission. The processing after S401 is the same as the processing described in FIG. 5 or FIG.

  In step S <b> 708, the scheduling control unit 601 determines whether a fourth timeout period has elapsed since the second wait state has occurred and the data full resolution wait time has elapsed. If the fourth timeout waiting for data full resolution due to the fourth timeout period 612 waiting for data full resolution occurs in S708, the scheduling control unit 601 returns to S506 in FIG. 8, clears the continuation flag 311 and waits for busy loop ( The second waiting state is terminated.

  This is the end of the description of the transmission side scheduling control method of the transmission side inter-CPU communication method according to the present embodiment. The scheduling control unit 601 is an example of a first scheduling unit and a second scheduling unit.

  FIG. 11 is a flowchart of the receiving side scheduling control method (receiving side scheduling control process) of the inter-CPU communication system 800 according to the present embodiment. The operation of the receiving side scheduling control method in the scheduling control unit 601 of the inter-CPU communication system 800 according to the present embodiment will be described using FIG.

  11 is a process obtained by partially changing the process of FIG. 6 described in the first embodiment. The process different from that of FIG. 6 is described. The same processes as those described in FIG. The description is omitted.

  In FIG. 11, S451 to S452 are the same as the processing of FIG. If the hang-on control unit 322 determines in S452 that data is not full in the memory 104 (communication memory 305) (No in S452), the process proceeds to S752.

  In step S <b> 752, the scheduling control unit 601 on the reception side sets a data empty waiting fifth timeout period 613. In step S753, the scheduling control unit 601 on the reception side sets the sixth timeout period 614 waiting for data empty. In the inter-CPU communication method in the inter-CPU communication system 800, a method of determining the times to be set as the data empty waiting fifth timeout time 613 and the data empty waiting sixth timeout time 614 will be described later. The scheduling control unit 601 may be the reception side control unit 364.

  Next, in S754, the scheduling control unit 601 on the receiving side issues a scheduling lock instruction to the OS 301 and prohibits the OS 301 from switching to another task. Next, in S755, the scheduling control unit 601 on the receiving side checks whether the data is empty. The scheduling control unit 601 may be the memory state determination unit 361.

  If it is not data empty (No in S755), the scheduling control unit 601 on the receiving side proceeds to S462. The processing after S462 is the same as the processing in FIG.

  In the case of data empty (Yes in S755), the scheduling control unit 601 on the receiving side checks in S756 whether the fifth timeout waiting for data empty due to the fifth timeout time 613 waiting for data empty has occurred. If the fifth timeout waiting for data empty has not occurred (No in S756), the receiving side scheduling control unit 601 returns to S755. In other words, the scheduling control unit 601 on the reception side remains in the scheduling lock state of the OS 301 instructed in S754, and enters a third waiting state that waits for data empty due to a busy loop. As in the case of the transmission side CPU, it is assumed that the interrupt can be received even in the scheduling lock state.

  In S756, the scheduling control unit 601 on the receiving side determines whether or not the fifth timeout period for waiting for data full resolution has elapsed since the occurrence of the third wait state. When the fifth timeout waiting for data full resolution due to the fifth timeout time 613 waiting for data full resolution occurs in S756, the scheduling control unit 601 on the receiving side issues a scheduling lock release instruction to the OS 301 in S757, and the task switching by the OS 301 is performed. Enable.

  If the fifth timeout waiting for data empty has occurred (Yes in S756), the process proceeds to S757. In step S757, the scheduling control unit 601 on the reception side issues a scheduling lock release instruction for causing the OS 301 to release the scheduling lock, and enables task switching. Then, the scheduling control unit 601 on the reception side switches busy loop scheduling to Yield scheduling that repeats rescheduling between tasks of the same priority in the OS 301.

  In S758, the scheduling control unit 601 on the reception side checks whether the memory 104 (communication memory 305) is data empty. If it is not data empty (No in S758), the scheduling control unit 601 on the receiving side proceeds to S462. The processing after S462 is the same as the processing in FIG.

  In the case of data empty (Yes in S758), the scheduling control unit 601 on the receiving side checks in S759 whether or not a data empty waiting sixth timeout due to the data empty waiting sixth timeout time 614 has occurred. If the sixth timeout waiting for data empty has not occurred (No in S759), the scheduling control unit 601 on the receiving side returns to S758. In other words, the scheduling control unit 601 on the receiving side sets the fourth waiting state to wait for the data empty state in the busy loop based on the Yield scheduling.

  If the sixth timeout waiting for data empty has occurred (Yes in S759), the scheduling control unit 601 on the receiving side proceeds to S459 in FIG. 6, clears the ready flag 312 and ends the busy loop wait. The processing after S459 is the same as the processing in FIG. The scheduling control unit 601 is an example of a third scheduling unit and a fourth scheduling unit.

  Next, processing for determining the timeout time will be described. FIG. 12 is a flowchart showing the operation of the timeout time determination process according to the third embodiment.

  Referring to FIG. 12, the determination of the timeout time to be set as the third timeout time 611 waiting for data full resolution, the fourth timeout time 612 waiting for data full resolution, the fifth timeout time 613 waiting for data empty, and the sixth timeout time 614 waiting for data empty A method (calculation method) will be described. FIG. 12 shows operations of the interrupt / context switch delay measuring unit 602 and the busy loop time setting unit 603 for determining the timeout time.

  The interrupt / context switch delay measurement unit 602 and the busy loop time setting unit 603 operate only once at the time of system startup, determine a timeout time, and store it in the storage device. Alternatively, the interrupt / context switch delay measurement unit 602 and the busy loop time setting unit 603 may periodically operate to periodically update the timeout time stored in the storage device.

  In step S <b> 801, the interrupt / context switch delay measurement unit 602 performs settings for generating a timer interrupt for measuring a delay time due to an interrupt. In the interrupt / context switch delay time measuring method by the interrupt / context switch delay measuring unit 602, the timer interrupt generation time 751 that is the time when the timer interrupt is generated and the interrupt handler is actually called. The difference from the “interrupt handler call time 752” is defined as an interrupt delay time 701.

  In step S802, the interrupt / context switch delay measuring unit 602 generates a timer interrupt and stores the timer interrupt generation time 751 in the storage device. In step S <b> 803, when an interrupt handler due to the occurrence of a timer interrupt is called by the OS 301, the interrupt / context switch delay measurement unit 602 stores the time when the interrupt handler is called as an interrupt handler call time 752. Store in the device.

  In step S804, the interrupt / context switch delay measurement unit 602 calculates a difference between the timer interrupt occurrence time 751 and the interrupt handler call time 752 stored in the storage device, and calculates the calculated difference as “interrupt delay time 701. Is stored in the storage device.

  In step S805, the OS 301 performs context switching from the interrupt handler to the task. In step S806, the interrupt / context switch delay measurement unit 602 measures the time for context switching from the interrupt handler to the task, stores the time as “context switch time 702” in the storage device, and sets the context switch time as the context switch time. 753 is stored in the storage device.

  The busy loop time setting unit 603 performs the following processing for each timeout time (data full resolution waiting third timeout time 611, data full resolution waiting fourth timeout time 612, data empty waiting fifth timeout time 613, and data empty waiting sixth timeout). Time 614) is determined and stored in the storage device.

  In S807, the busy loop time setting unit 603 calculates a value that is twice the difference between the “interrupt delay time 701” calculated in S804 and the “context switch time 702” calculated in S806, and eliminates data full. This is set as the waiting third timeout period 611. This is because it is more efficient to wait for the state change with the scheduling lock if the inter-CPU communication is performed in a time shorter than the time for performing the context switch twice and switching to the original task. In this example, a value twice the difference between the “time 701” and the “context switch time 702” is set as a timeout time in the scheduling lock state (the third timeout time 611 waiting for data full resolution).

  The busy loop time setting unit 603 also determines the time for the data empty waiting fifth timeout time 613 by the same determination method as the data full resolution waiting third timeout time 611. That is, the busy loop time setting unit 603 sets a value twice the difference between the interrupt delay time 701 and the context switch time 702 as the timeout time in the scheduling lock state (the fifth timeout time 613 waiting for data full resolution). .

  Next, in S808, the busy loop time setting unit 603 sets a value that is twice the difference between the context switch time 753 in S806 and the timer interrupt generation time 751 in S802 as the data full resolution wait fourth timeout time 612. To do. This is because it is more efficient to wait for a state change in the busy loop if communication between CPUs is performed in a time corresponding to the time of context switch after receiving the timer interrupt. In this example, a value twice as large as the difference between the generation times 751 is used as a busy loop timeout time (fourth timeout time 612 waiting for data full resolution). The busy loop time setting unit 603 also sets the data empty waiting sixth timeout time 614 to the same time as the data full resolution waiting fourth timeout time 612.

  As described above, since the inter-CPU communication control unit 321 includes the scheduling control unit 601, the wait method for inter-CPU communication can be changed in stages. In addition, an appropriate wait method can be taken according to the delay time. The interrupt / context switch delay measuring means (interrupt / context switch delay measuring section 602) and the busy loop time setting means (busy loop time setting section 603) are used to set each wait time (timeout time) to the hardware performance of the system. Thus, it is possible to automatically set an appropriate time according to the performance of the OS 301.

  In the present embodiment, the inter-CPU communication system 800 having the following characteristics has been described.

An inter-CPU communication method (inter-CPU communication system 800) comprising the following means in addition to the hang-on control unit 322 in the inter-CPU communication control means (inter-CPU communication control unit 321).
(A) A transmission side scheduling control means (scheduling) that waits so as not to switch to another task by locking the scheduling of the OS 301 for a certain period of time when waiting for data full resolution waiting on the transmission side by communication between CPUs in a busy loop. Control unit 601).
(B) If the data full on the transmission side is not resolved during the scheduling lock of the OS 301 in (a) above, a stage is obtained by waiting by Yield scheduling that repeats rescheduling between tasks of the same priority in the OS 301. The transmission side scheduling control means (scheduling control unit 601) for controlling the priority of the busy loop.
(C) When waiting for a data empty on the receiving side by communication between CPUs in a busy loop, as in the case of transmission, the reception waits without switching to another task by locking the scheduling of the OS 301 for a certain period of time. Side scheduling control means (scheduling control unit 601).
(D) If the data empty on the receiving side is not resolved during the scheduling lock of the OS 301 in (c) above, a stage is obtained by waiting by Yield scheduling that repeats rescheduling between tasks of the same priority in the OS 301. Receiving-side scheduling control means (scheduling control unit 601) for controlling the priority of busy loops.

In addition to the hang-on control means (hang-on control part 322) and the scheduling control means (scheduling control part 601), the following means are provided in the inter-CPU communication control means (inter-CPU communication control part 321). The inter-CPU communication method (inter-CPU communication system 800).
(A) Interrupt delay measurement means (interrupt / context switch delay measurement unit 602) that measures an interrupt response delay time (interrupt delay time 701) from the occurrence of a timer interrupt to the call of an interrupt handler of the OS 301.
(B) Context switch measuring means (interrupt / context switch delay measuring unit 602) that measures a context switch delay time (context switch time 702) between tasks of the OS 301.
(C) A busy loop that determines a timeout time of a busy loop based on the interrupt response delay time (interrupt delay time 701) and the context switch delay time (context switch time 702) measured in (a) and (b). Time setting means (busy loop time setting unit 603).

Embodiment 4 FIG.
A method for shortening the delay time of inter-CPU communication by changing the inter-CPU interrupt process of the inter-CPU communication system 800 described in the first embodiment will be described.

  FIG. 13 is a functional block diagram of the inter-CPU communication system according to the fourth embodiment. 13, the same functional blocks as those in FIG. 9 described above are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 13, in addition to the configuration of FIG. 9, the inter-CPU communication control unit 321 includes a pre-CPU interrupt unit 650.

  FIG. 14 is a flowchart showing a part of the inter-CPU communication method of the inter-CPU communication system according to the fourth embodiment. The flow shown in FIG. 14 is a partial modification of the flow shown in FIG. 4 described above. The operation of the pre-CPU interrupt means (pre-CPU interrupt unit 650) on the transmission side of the inter-CPU communication system 800 according to the present embodiment will be described using FIG.

  As described in S401 to S403 of FIG. 4, the inter-CPU interrupt (data read start request X1) is an inter-CPU interrupt for notifying that data transmission has been performed from the transmitting CPU to the receiving CPU. there were.

  In this embodiment, when the continuation flag 311 is set by the hang-on control unit 322 in S401a, the pre-CPU interrupt unit 650 checks whether the ready flag 312 is set in S1002. If the ready flag 3121 is set (Yes in S1002), the process proceeds to S1004, and the hang-on control unit 322 executes data transmission processing. If the ready flag 3121 is not set (No in S1002), the process proceeds to S1003.

  In S1003, the pre-CPU interrupt unit 650 transmits an inter-CPU interrupt (data read start request X1) to the receiving CPU. Thereafter, the process proceeds to S1004, and the hang-on control unit 322 executes a data transmission process. The hang-on control unit 322 transmits data in S1004, and then proceeds to S404. In the processing after S404, similar to the processing described in FIG. 4, the procedure after the all data transmission completion check is performed.

  With the above processing, even if an inter-CPU interrupt (data read start request X1) is processed by the receiving CPU before data transmission, the receiving task waits for data empty in a busy loop, so that inter-CPU communication can be performed. .

  FIG. 15 is a flowchart showing a part of the inter-CPU communication method of the inter-CPU communication system according to the fourth embodiment. The flow shown in FIG. 15 is a partial modification of the flow shown in FIG. The operation of the pre-CPU interrupt means (pre-CPU interrupt unit 650) on the receiving side of the inter-CPU communication system 800 according to the present embodiment will be described using FIG.

  As described in S453 to S455 of FIG. 6, the inter-CPU interrupt (data write start request X2) is an inter-CPU interrupt for notifying that data reception has been performed from the receiving CPU to the transmitting CPU. there were.

  In this embodiment, when it is determined that data full has occurred in S452 (Yes in S452), the pre-CPU interrupt unit 650 checks whether the continuation flag 311 is set (S1051). If the continuation flag 311 is set (Yes in S1051), the process proceeds to S1053, and the hang-on control unit 322 executes data reception processing. If the continuation flag 311 is not set (No in S1051), the process proceeds to S1052.

  In S1052, the pre-CPU interrupt unit 650 transmits an inter-CPU interrupt (data write start request X2) to the transmitting CPU. Thereafter, the process proceeds to S1053, and the hang-on control unit 322 executes data reception processing. The hang-on control unit 322 performs data reception (data read processing) in S1053, and then proceeds to S463. In the processing after S463, similar to the processing described with reference to FIG.

  With the above processing, even if an inter-CPU interrupt (data write start request X2) is processed by the transmitting CPU before data reception, the transmitting task waits for data full cancellation in a busy loop, and therefore, inter-CPU communication can be performed. .

  In the present embodiment, the inter-CPU communication system 800 including the following features has been described.

In addition to the hang-on control means (hang-on control section 322), the following communication means is provided in the inter-CPU communication control means (inter-CPU communication control section 321) (inter-CPU communication system 800). .
(A) In inter-CPU communication, an inter-CPU interrupt means for sending an inter-CPU interrupt that wakes up a reception-side task before the data transmission processing, not after the data transmission processing (pre-inter-CPU interrupt unit 650) .
(B) In inter-CPU communication, an inter-CPU interrupt means for sending an inter-CPU interrupt that wakes up a transmission-side task before the data reception process, not after the data reception process (pre-CPU interrupt unit 650) .

  As described above, the inter-CPU communication system 800 according to the present embodiment has pre-CPU interrupt means (pre-CPU interrupt section 650) in the inter-CPU communication control means (inter-CPU communication control section 321). Therefore, it is possible to send an inter-CPU interrupt with a long delay time to the other CPU in advance and wait for the transmission / reception of inter-CPU communication in a busy loop in response to the inter-CPU interrupt, so that high-speed inter-CPU communication is performed. Can do.

Embodiment 5 FIG.
In the first to fourth embodiments, the inter-CPU communication method (inter-CPU communication control method) in the inter-CPU communication system 800 having a symmetric multi-CPU configuration as shown in FIG. In this embodiment, an inter-CPU communication system 801 having an asymmetric multi-CPU configuration in which CPUs are connected by a two-port memory or a FIFO memory (inter-CPU communication control method) described in the first to fourth embodiments. ) Will be explained.

  FIG. 16 is a configuration diagram of an inter-CPU communication system 801 having an asymmetric multi-CPU configuration according to the present embodiment. Each CPU (101, 102, 103) includes a local memory (221, 222, 223) for its own CPU and a bus (211, 212, 213) for its own CPU.

  Each CPU (101, 102, 103) is connected by a 2-port memory or a FIFO memory (204, 205) via a bus (bus for own CPU (211, 212, 213)) possessed by each CPU. . The inter-CPU communication system 801 includes the communication memory 305, the transmission waiting semaphore 306, the reception waiting semaphore 307, the continuation flag 311, and the ready flag 312 in FIG. 2 on the 2-port memory or the FIFO memory (204, 205).

  With the above configuration, the above-described inter-CPU communication control unit (inter-CPU communication control unit 321) according to the first to fourth embodiments can perform the same operation as the above-described first to fourth embodiments. That is, even in a system (apparatus) having an asymmetric multi-CPU configuration, high-speed CPU communication can be performed by applying the above-described CPU communication method (CPU communication control method) according to the first to fourth embodiments. it can.

  The inter-CPU communication system 801 of the present embodiment differs from the above-described inter-CPU communication method (inter-CPU communication control method) of the first to fourth embodiments, not data communication using a memory in the same CPU bus. The present invention is characterized by being applied to data communication using a two-port memory or a FIFO memory for connecting buses.

  As mentioned above, although Embodiment 1-5 was demonstrated, you may implement combining 2 or more embodiment among these. Alternatively, one of these embodiments may be partially implemented. Or you may implement combining two or more embodiment among these partially.

  In the description of the first to fifth embodiments, the memory area determination unit 351, the data writing unit 352, the reception-side CPU determination unit 353, the transmission-side control unit 354, and the like included in the hang-on control unit 322 in the inter-CPU communication control unit 321. The memory state determination unit 361, the data reading unit 362, the transmission side CPU determination unit 363, and the reception side control unit 364 have been described as being configured as independent functional blocks. Further, the scheduling control unit 601, the interrupt / context switch delay measurement unit 602, the busy loop time setting unit 603, and the pre-CPU interrupt unit 650 in the inter-CPU communication control unit 321 have been described as independent function blocks. . However, the functional block may be configured as one functional block, for example, or may be configured as three functional blocks by combining the functional blocks described above. The functional blocks may be configured by combining the functions described above.

  101, 102, 103 CPU, 104 memory, 105 IO device, 111 bus, 204, 205 2-port memory or FIFO memory, 221, 222, 223 Local memory for own CPU, 211, 212, 213 Bus for own CPU, 301 OS, 302, 303, 304 Task, 305 Communication memory, 306 Transmission waiting semaphore, 307 Reception waiting semaphore, 308 Inter-CPU interrupt register, 309 Timer register, 311 Continuation flag, 312 Ready flag, 321 Inter-CPU communication control unit 322 Hang-on control unit, 351 Memory area determination unit, 352 Data writing unit, 353 Reception side CPU determination unit, 354 Transmission side control unit, 361 Memory state determination unit, 362 Data reading unit, 363 Transmission side CPU determination unit 364 receiving side control unit, 601 scheduling control unit, 602 interrupt / context switch delay measurement unit, 603 busy loop time setting unit, 611 third full timeout time waiting for data full resolution, 612 fourth timeout time waiting for data full resolution, 613 data empty Wait 5th timeout time, 614 Data empty wait 6th timeout time, 650 Pre-CPU interrupt unit, 701 Interrupt delay time, 702 Context switch time, 751 Timer interrupt generation time, 752 Interrupt handler call time, 753 Context Switch time, 800 CPU communication system, 890 device, 901 display device, 902 keyboard, 903 mouse, 904 FDD, 905 CDD, 906 printer device, 907 scanner device, 9 1 CPU, 913 ROM, 914 RAM, 915 communication board, 920 a magnetic disk device, 921 operating system, 922 Window system, 923 Program group, 924 File group, X1 data read start request, X2 data write start request.

Claims (10)

Data is transmitted between the transmitting CPU and the receiving CPU via a memory shared by the transmitting CPU (Central Processing Unit) that transmits data and the receiving CPU that receives the data. In the inter-CPU communication system that performs communication of
The sending CPU is
A memory area determination unit that determines whether or not there is a free area in the memory;
A data writing unit that executes a data writing process for writing data to the memory when the memory region determining unit determines that there is a free space in the memory;
A receiving-side CPU determining unit that determines a state of the receiving-side CPU when the memory region determining unit determines that there is no free space in the memory;
When the receiving CPU determination unit determines that the state of the receiving CPU is an execution state of a data read process for reading data from the memory, the data writing unit writes data until there is a free space in the memory. Reading to cause the receiving CPU to start executing the data reading process when the receiving CPU determining unit determines that the receiving CPU state is not the execution state of the data reading process. An inter-CPU communication system comprising: a transmission-side control unit that transmits a start request to the reception-side CPU. The inter-CPU communication system is:
A receiving side state flag indicating the state of the receiving side CPU;
The receiving CPU determination unit
2. The inter-CPU communication system according to claim 1, wherein the state of the receiving CPU is determined based on the value of the receiving state flag. The transmission side control unit
A first timeout time storage unit that stores the first timeout time in the storage device in advance;
When the receiving CPU determining unit determines that the state of the receiving CPU is the execution state of the data reading process, the data writing unit is set to a waiting state for the data writing process, and the waiting state for the data writing process is set. It is determined whether or not the first timeout time stored in the first timeout time storage unit has elapsed from the start time. If the first timeout time has not elapsed, there is an empty area in the memory. The data write processing wait state is continued until possible, and when the first time-out period has elapsed, a transmission side scheduling unit is provided that transmits the read start request to the reception side CPU. Item 3. The communication system between CPUs according to Item 1 or 2. The transmission side control unit
A third timeout time storage unit that stores the third timeout time in the storage device in advance;
A fourth timeout time storage unit that stores the fourth timeout time in the storage device in advance;
When the receiving CPU determining unit determines that the state of the receiving CPU is an execution state of the data reading process, the data writing unit is set to the first of the data writing process after scheduling locking of the transmitting CPU. The third time-out time stored in the third time-out time storage unit has elapsed since the start of the first wait state of the data writing process, and the third time-out If the time has not elapsed, a first scheduling unit that continues the first waiting state of the data writing process until an empty area is created in the memory; and
When the third timeout period has elapsed, the first waiting state of the data writing process is terminated, the scheduling lock is released, and then the data writing unit is set to a second waiting state of the data writing process, It is determined whether or not the fourth time-out time stored in the fourth time-out time storage unit has elapsed since the start of the second wait state of the data writing process, and the fourth time-out time has elapsed. If not, the second waiting state of the data writing process is continued until free space is created in the memory, and the read start request is transmitted to the receiving CPU when the fourth time-out period has elapsed. The inter-CPU communication system according to claim 1, further comprising: a second scheduling unit that performs the second scheduling unit. The receiving CPU is
A memory state determination unit for determining whether data is stored in the memory;
A data reading unit that executes a data reading process of reading data from the memory when the memory state determination unit determines that data is stored in the memory;
A transmission side CPU determination unit for determining a state of the transmission side CPU when the memory state determination unit determines that data is not stored in the memory;
When the transmission side CPU determination unit determines that the state of the transmission side CPU is the execution state of the data write process, the data read unit is set in a wait state for the data read process until data is stored in the memory. When the transmission side CPU determination unit determines that the state of the transmission side CPU is not the execution state of the data writing process, a transmission start request for causing the data writing unit to start executing the data writing process is sent to the transmission side The inter-CPU communication system according to any one of claims 1 to 4, further comprising a reception-side control unit that transmits to the CPU. The inter-CPU communication system further includes:
A transmission side state flag indicating the state of the transmission side CPU;
The transmitting CPU determination unit
6. The inter-CPU communication system according to claim 5, wherein the state of the transmission side CPU is determined based on the transmission side state flag. The receiving side control unit
A second timeout time storage unit for storing the second timeout time in the storage device in advance;
When the transmission side CPU determination unit determines that the state of the transmission side CPU is not the execution state of the data writing process, from the time when the memory state determination unit determines that no data is stored in the memory It is determined whether or not a second timeout period has elapsed. If the second timeout period has not elapsed, the data reading unit is placed in a wait state for data reading processing until data is stored in the memory. 7. The inter-CPU communication system according to claim 5, further comprising: a receiving side scheduling unit that transmits the write start request to the transmitting side CPU when the second time-out period elapses. The receiving side control unit
A fifth time-out time storage unit that stores the fifth time-out time in the storage device in advance;
A sixth time-out time storage unit for storing the sixth time-out time in the storage device in advance;
When the transmitting CPU determining unit determines that the state of the transmitting CPU is an execution state of the data reading process, the receiving CPU is scheduled and locked, and then the data reading unit is set to the third data reading process. And determines whether or not the fifth timeout time stored in the fifth timeout time storage unit has elapsed since the start of the third waiting state of the data writing process, and the fifth timeout If the time has not elapsed, a third scheduling unit that continues the third waiting state of the data read processing until the data is stored in the memory;
When the fifth time-out period has elapsed, the third waiting state of the data reading process is terminated, the scheduling lock is released, and then the data reading unit is set to a fourth waiting state of the data reading process, It is determined whether or not the sixth timeout time stored in the sixth timeout time storage unit has elapsed since the start of the fourth wait state of the data reading process, and the sixth timeout time has elapsed. If not, the fourth wait state of the data reading process is continued until data is stored in the memory, and when the sixth timeout period has elapsed, the write start request is sent to the transmitting CPU. The inter-CPU communication system according to claim 5 or 6, further comprising a fourth scheduling unit for transmission. Data is transmitted between the transmitting CPU and the receiving CPU via a memory shared by the transmitting CPU (Central Processing Unit) that transmits data and the receiving CPU that receives the data. In the inter-CPU communication method of the inter-CPU communication system that performs communication of
A memory area determination step in which a memory area determination unit of the transmission side CPU determines whether or not there is a free area in the memory;
A data writing step of executing a data writing process of writing data to the memory when the data writing unit of the transmitting CPU determines that the memory area has a free space in the memory area determining step;
A reception-side CPU determination unit that determines a state of the reception-side CPU when the reception-side CPU determination unit of the transmission-side CPU determines that the memory has no free space in the memory region determination step;
When the transmission-side control unit of the transmission-side CPU determines that the state of the reception-side CPU is an execution state of a data read process for reading data from the memory by the reception-side CPU determination step, an empty area in the memory The data writing process is put into a waiting state for data writing processing until the data is received, and when the receiving CPU determining step determines that the receiving CPU is not in the data reading processing execution state, data is sent to the receiving CPU. An inter-CPU communication method of an inter-CPU communication system, comprising: a transmission-side control step of transmitting a read start request for starting execution of read processing to the reception-side CPU. The inter-CPU communication method of the inter-CPU communication system is:
A memory state determination step of determining whether or not the memory state determination unit of the receiving CPU stores data in the memory;
A data reading step of executing a data reading process of reading data from the memory when the data reading unit of the receiving CPU determines that the data is stored in the memory by the memory state determining step;
A transmission-side CPU determination unit that determines a state of the transmission-side CPU when the transmission-side CPU determination unit of the reception-side CPU determines that data is not stored in the memory by the memory state determination step;
When the receiving-side control unit of the receiving-side CPU determines that the state of the transmitting-side CPU is the execution state of the data writing process in the transmitting-side CPU determination step, the data is stored until the data is stored in the memory. The reading process is set to a waiting state for the data reading process, and when the transmitting CPU determining process determines that the transmitting CPU is not in the data writing process, the data writing process is started in the data writing process. 10. The inter-CPU communication method of the inter-CPU communication system according to claim 9, further comprising: a reception-side control step of transmitting a write start request for making the request to the transmission-side CPU.

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