JP2011513812A5 - - Google Patents

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Publication number
JP2011513812A5
JP2011513812A5 JP2010547658A JP2010547658A JP2011513812A5 JP 2011513812 A5 JP2011513812 A5 JP 2011513812A5 JP 2010547658 A JP2010547658 A JP 2010547658A JP 2010547658 A JP2010547658 A JP 2010547658A JP 2011513812 A5 JP2011513812 A5 JP 2011513812A5
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JP
Japan
Prior art keywords
memory circuit
circuit
operation mode
feedback signal
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2010547658A
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English (en)
Japanese (ja)
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JP2011513812A (ja
JP5522690B2 (ja
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Publication date
Priority claimed from US12/034,888 external-priority patent/US7800974B2/en
Application filed filed Critical
Publication of JP2011513812A publication Critical patent/JP2011513812A/ja
Publication of JP2011513812A5 publication Critical patent/JP2011513812A5/ja
Application granted granted Critical
Publication of JP5522690B2 publication Critical patent/JP5522690B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2010547658A 2008-02-21 2009-01-16 メモリ回路中の調整可能なパイプライン Active JP5522690B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/034,888 US7800974B2 (en) 2008-02-21 2008-02-21 Adjustable pipeline in a memory circuit
US12/034,888 2008-02-21
PCT/US2009/031202 WO2009105295A1 (en) 2008-02-21 2009-01-16 Adjustable pipeline in a memory circuit

Publications (3)

Publication Number Publication Date
JP2011513812A JP2011513812A (ja) 2011-04-28
JP2011513812A5 true JP2011513812A5 (https=) 2012-03-08
JP5522690B2 JP5522690B2 (ja) 2014-06-18

Family

ID=40985862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010547658A Active JP5522690B2 (ja) 2008-02-21 2009-01-16 メモリ回路中の調整可能なパイプライン

Country Status (4)

Country Link
US (1) US7800974B2 (https=)
JP (1) JP5522690B2 (https=)
CN (1) CN101946237B (https=)
WO (1) WO2009105295A1 (https=)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8291201B2 (en) * 2008-05-22 2012-10-16 International Business Machines Corporation Dynamic merging of pipeline stages in an execution pipeline to reduce power consumption
US8332590B1 (en) * 2008-06-25 2012-12-11 Marvell Israel (M.I.S.L.) Ltd. Multi-stage command processing pipeline and method for shared cache access
US8488405B2 (en) 2011-07-18 2013-07-16 Texas Instruments Incorporated Process variability tolerant programmable memory controller for a pipelined memory system
US8587356B2 (en) 2011-12-15 2013-11-19 Freescale Semiconductor, Inc. Recoverable and reconfigurable pipeline structure for state-retention power gating
US8941427B2 (en) 2011-12-15 2015-01-27 Freescale Semiconductor, Inc. Configurable flip-flop
CN103218029B (zh) * 2013-04-09 2015-06-17 电子科技大学 一种超低功耗处理器流水线结构
KR102033291B1 (ko) * 2013-06-14 2019-10-17 삼성전자 주식회사 반도체 장치 및 그 구동 방법
US9256276B2 (en) * 2013-09-27 2016-02-09 Intel Corporation Utilization of processor capacity at low operating frequencies
US9263100B2 (en) * 2013-11-29 2016-02-16 Freescale Semiconductor, Inc. Bypass system and method that mimics clock to data memory read timing
CN109885154B (zh) * 2019-02-28 2023-06-23 江西天漪半导体有限公司 一种带旁路通道的低功耗寄存器
US11061836B2 (en) * 2019-06-21 2021-07-13 Micron Technology, Inc. Wave pipeline including synchronous stage
US11967360B2 (en) * 2021-09-22 2024-04-23 Arm Limited Dynamically adjustable pipeline for memory access

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5809552A (en) * 1992-01-29 1998-09-15 Fujitsu Limited Data processing system, memory access device and method including selecting the number of pipeline stages based on pipeline conditions
JPH1173770A (ja) * 1997-08-27 1999-03-16 Matsushita Electron Corp 半導体記憶装置
DE69923769T2 (de) * 1998-04-01 2006-02-02 Mosaid Technologies Incorporated, Kanata Asynchrones halbleiterspeicher-fliessband
US6272609B1 (en) * 1998-07-31 2001-08-07 Micron Electronics, Inc. Pipelined memory controller
US6560725B1 (en) * 1999-06-18 2003-05-06 Madrone Solutions, Inc. Method for apparatus for tracking errors in a memory system
JP4345204B2 (ja) * 2000-07-04 2009-10-14 エルピーダメモリ株式会社 半導体記憶装置
JP2002329395A (ja) * 2001-04-27 2002-11-15 Mitsubishi Electric Corp 同期型半導体装置
US20030226000A1 (en) * 2002-05-30 2003-12-04 Mike Rhoades Collapsible pipeline structure and method used in a microprocessor
US20070271449A1 (en) * 2006-05-19 2007-11-22 International Business Machines Corporation System and method for dynamically adjusting pipelined data paths for improved power management
US8122232B2 (en) * 2007-06-21 2012-02-21 Arm Limited Self programming slave device controller

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