JP2011258975A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring arrangement structure capable of increasing a process margin.SOLUTION: A semiconductor device comprises: a first wiring layer that is formed on a substrate, and includes a plurality of first wirings 6; a contact layer that is formed on the first wiring layer, and includes a plurality of veer contacts 10 connected to the first wirings 6; and a second wiring layer that is formed on the contact layer, and includes a plurality of second wirings 14 connected to the veer contacts 10. A contact pitch is larger than the minimum wiring pitch of the first wirings 6 or the minimum wiring pitch of the second wirings 14.

Description

  The present invention relates to a semiconductor device having a multilayer wiring structure including wirings stacked one above the other and contacts connecting them, and a method for manufacturing the same.

  In recent years, with the increase in functionality and integration of semiconductor devices, a multilayer wiring structure in which a plurality of wirings are stacked in the vertical direction is frequently used. In general, when forming a contact used for connection of wiring or wirings stacked on top and bottom, a hole for wiring or contact is formed in the interlayer insulating film based on the design rule of the multilayer wiring structure, and the hole is formed in this hole. It is formed by embedding a conductive member or the like. Alternatively, in other cases, a material film used for wiring or the like is formed, and the wiring material film is etched to form a desired wiring.

With regard to such wiring arrangement, various patterns are designed from the viewpoint of efficiency and space saving.
For example, a wiring structure of a semiconductor device such as a gate array type for general-purpose design will be described with reference to FIG. In this structure, there is a wide wiring for a reinforced power source called a power ring (or power ring) 40 outside the macro cell. Further, the signal wiring, the power supply wiring, and the ground wiring are arranged in the macro cell inside the power supply ring 40. The lower first wiring 41 and the upper second wiring 42 which are orthogonal to each other are connected via a via 43. In this structure, priority is given to the degree of freedom of design, and the wirings 41 and 42 and the vias 43 in each wiring layer are designed to be placed on a square grid (indicated by dotted lines in the drawing) that is uniform in the X and Y directions. ing. That is, the wiring pitch and the via pitch can have the same minimum dimension.
When wirings and vias are arranged on a square grid, changing the wiring direction has little influence on the design, and a process confirmation pattern can be formed without considering the wiring directionality. Therefore, the types of process TEGs can be reduced, and a TEG (Test Element Group) can be easily created.

  As another wiring structure, for example, as described above, the first layer wiring is added to the wiring grid formed in the X direction and the second layer wiring in the Y direction, so that the third layer and the fourth layer are formed. There has also been proposed one in which wiring is designed on an oblique wiring grid so as to have angles of 45 degrees and 135 degrees with respect to the X direction (see, for example, Patent Documents 1 to 3).

  By the way, when the wiring structure as described above is formed, generally, a hole is formed in the insulating film and the conductive member is embedded, or the wiring material film is etched and processed. Lithography technology is often used for forming a resist mask used in the formation of holes and the etching of wiring material films. However, with recent miniaturization of wiring patterns, various problems in lithography technology have occurred. In particular, there is a case where a square grid (also referred to as “uniform grid”) wiring design method cannot be adopted. The reason is the problem of resist receding (shrink) described below.

Generally, when a pattern is miniaturized, a difference between a design dimension and an actual resist pattern dimension (hereinafter referred to as “CD (Critical Dimension) shift”) increases.
FIG. 14 is a diagram showing the wiring width dependence of the CD shift in the length direction of the wiring. That is, FIG. 14 is a diagram showing the relationship between the wiring width and the CD shift amount in the length direction of the wiring. Here, the wiring is an isolated wiring.
As shown in FIG. 14, the CD shift amount tends to increase as the wiring width of the isolated wiring becomes narrower. This is presumably because the resist cut shape deteriorates when the remaining opening area of the resist is reduced. For example, when the wiring width of the isolated wiring is 0.4 μm, the CD shift amount is 0.02 μm. However, when the wiring width is 0.2 μm, the CD shift amount is 0.06 μm. In order to reduce the influence of the CD shift on the transferred pattern shape, the amount of resist receding (CD shift amount) is estimated at the design stage, and the mask (eg, chrome mask) pattern is designed to be larger by the CD shift amount. Method (mask bias technology). For example, when an isolated wiring having a width of 0.2 μm and a length of 700 μm is formed, a chrome mask is formed with a length of 700.06 μm including a CD shift amount of 0.06 μm shown in FIG. When exposure is performed using this mask, the developed resist pattern recedes in the wiring length direction, and becomes the same dimension as the design dimension (length is 700 μm). In FIG. 14, areas that can be handled by the square grid are indicated by diagonal lines. When the mask bias technique is applied in consideration of CD shift when the wiring width is narrower than 0.15 μm, the wirings that are not originally in contact with each other are arranged to be in contact with each other. That is, since the CD shift becomes larger than the margin of the wiring interval, there arises a problem that the wiring cannot be designed on the square grid.
Further, a method of adding a correction pattern to the corner portion of the mask pattern is used to correct the CD shift due to the decrease in the corner portion of the resist pattern.

JP 2001-142931 A JP 2000-82743 A JP 09-148444 A

  As described above, it has been found that there is a problem if the mask bias technique is applied to the wiring arrangement on the square grid when the wiring width of the isolated wiring is less than 0.15 μm. Due to the miniaturization of the pattern, it is difficult to correct the CD shift by a mask bias technique or a method of adding a correction pattern. That is, as the wiring width becomes narrower, the CD shift amount increases, but since the patterns become finer and denser, the wiring interval margin is small and a mask pattern corrected by the CD shift amount cannot be formed. Therefore, it is difficult to perform correction using the mask bias technique.

  In the case of a multilayer wiring structure, the process margin of the via is smaller than the process margin of the wiring, and there is a problem that defects are likely to occur in the via opening process. This is due to the low data rate of vias. FIG. 15 is a diagram illustrating the dependency of the data rate of the device area on the wiring length. The device region has a size of 17 μm × 17 μm. In this device region, a case where a wiring having a wiring width of 0.1 μm and a via having a size of 0.1 μm × 0.1 μm are arranged with a minimum pitch of 200 nm will be described. When the wiring length of the first layer wiring or the second layer wiring is 500 nm which is the minimum length, the wiring data rate is about 27%, and when the wiring length is 17 μm which is the device region limit, the wiring data rate is 50%. Become. Therefore, the wiring data rate is about 27 to 50%. On the other hand, as shown in FIG. 15, it can be seen that the via data rate is two orders of magnitude smaller than the wiring data rate. Since the via data rate is low in this way, the light intensity is weak and the optical contrast is lowered in the exposure for forming the via. When the diameter dimension of the via to be formed is small in such a state where the optical contrast is lowered, the DOF (depth of focus) is remarkably lowered as shown in FIG. To do. FIG. 16 is a diagram illustrating the via dimension dependency of DOF. Considering the density dependency of via etching, the isolation characteristics of isolated vias are particularly deteriorated, and an extreme increase in etching time including a loading effect occurs. Therefore, the amount of variation in the etching process with respect to the resist dimension variation is increased, and the via cannot be formed with high reproducibility.

  Accordingly, the present invention provides a semiconductor device having an improved wiring structure so as to solve the above-described problems and allow accurate pattern formation with a sufficient margin.

  A semiconductor device according to the present invention includes a first wiring layer including a plurality of first wirings formed on the substrate, and a plurality of contacts formed on the first wiring layer and connected to the first wirings. And a second wiring layer including a plurality of second wirings formed on the contact layer and connected to the contacts. The contact pitch obtained by adding the diagonal length of the contacts and the interval between adjacent contacts is the minimum interval among the intervals between the adjacent first wires and the wiring width of the first wires. It is larger than the added first minimum wiring pitch or the second minimum wiring pitch obtained by adding the minimum spacing among the spacings between the second wirings adjacent to each other and the wiring width of the second wiring. It is what.

  In the semiconductor device according to the present invention, it is preferable that the contact pitch is √2 times or more the first minimum wiring pitch or the second minimum wiring pitch.

  In the semiconductor device of the present invention, it is preferable that the first minimum wiring pitch or the second minimum wiring pitch is less than 150 nm.

  In the semiconductor device of the present invention, it is preferable that the minimum design dimension of the wiring width of the first wiring or the second wiring is smaller than the minimum design dimension of the contact.

  In the semiconductor device of the present invention, it is preferable that the minimum finished dimension of the wiring width of the first wiring or the second wiring is smaller than the minimum finished dimension of the contact.

A manufacturing method of a semiconductor device according to the present invention is a manufacturing method of a semiconductor device having a multilayer wiring,
Forming a first interlayer insulating film on the substrate;
Forming a first wiring trench in the first interlayer insulating film;
Forming a first wiring by embedding a conductive film in the first wiring trench;
Forming a second interlayer insulating film on the first interlayer insulating film and the first wiring;
Forming a via hole connected to the first wiring in the second interlayer insulating film;
Forming a via contact by embedding a conductive film in the via hole;
Forming a third interlayer insulating film on the second interlayer insulating film and the via contact;
Forming a second wiring trench connected to the via contact in the third interlayer insulating film;
Forming a second wiring by embedding a conductive film in the second wiring trench,
The via contact is formed with a contact pitch larger than a minimum wiring pitch of the first wiring or a minimum wiring pitch of the second wiring.

A manufacturing method of a semiconductor device according to the present invention is a manufacturing method of a semiconductor device having a multilayer wiring,
Forming a first interlayer insulating film on the substrate;
Forming a first wiring trench in the first interlayer insulating film;
Forming a first wiring by embedding a conductive film in the first wiring trench;
Forming a second interlayer insulating film on the first interlayer insulating film and the first wiring;
Forming a second wiring trench in the second interlayer insulating film;
Forming a via hole connected to the first wiring in the second interlayer insulating film below the second wiring trench;
Forming a via contact and a second wiring by embedding a conductive film in the via hole and the second wiring groove,
The via contact is formed with a contact pitch larger than a minimum wiring pitch of the first wiring or a minimum wiring pitch of the second wiring.

  In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the contacts are formed with a contact pitch of √2 times or more of a minimum wiring pitch of the first wiring or a minimum wiring pitch of the second wiring.

  In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the first wiring or the second wiring is formed so that a minimum wiring pitch is less than 150 nm.

  In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the via contact is formed so that the dimension of the via contact is larger than the minimum dimension of the wiring width of the first wiring or the second wiring.

  In the present invention, the minimum wiring pitch dimension of the first or second wiring of the semiconductor device is smaller than the minimum pitch dimension of the contacts. Accordingly, since the contacts can be formed with a pitch larger than the arrangement of the first or second wiring, a process margin in forming the contacts can be secured to some extent. Therefore, an accurate pattern can be formed.

It is a cross-sectional schematic diagram for demonstrating the semiconductor device in Embodiment 1 of this invention. FIG. 5 is a schematic top view for illustrating the wiring structure of the semiconductor device in the first embodiment of the present invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device by Embodiment 1 of this invention. FIG. 3 is a cross-sectional view for explaining a wiring structure formed by a dual damascene method in the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 4. In Embodiment 1 of this invention, it is a top view which shows the example which has arrange | positioned the wiring and the via | veer on the square grid. In Embodiment 1 of this invention, it is a figure which shows the wiring pitch dependence of the utilization factor of the power supply wiring arrange | positioned on a square grid. In Embodiment 1 of this invention, it is a top view which shows the signal wiring arrange | positioned by an on-grid, and the signal wiring arrange | positioned by an off-grid. It is a cross-sectional schematic diagram for demonstrating the semiconductor device in Embodiment 2 of this invention. It is a top schematic diagram for demonstrating the wiring structure of the semiconductor device in Embodiment 2 of this invention. In Embodiment 2 of this invention, it is a top view which shows the example which has arrange | positioned wiring and a via | veer on a square grid. It is a graph for demonstrating the relationship between the misalignment of the semiconductor device in Embodiment 2 of this invention, and via resistance. It is a top view for demonstrating the wiring structure of the semiconductor device which has a power supply ring. It is a figure which shows the wiring width dependence of CD shift in the length direction of wiring. It is a figure which shows the wiring length dependence of the data rate of a device area | region. It is a figure which shows the via dimension dependence of DOF.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is simplified or omitted.

Embodiment 1 FIG.
FIG. 1 is a schematic cross-sectional view for explaining the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a schematic top view for explaining the wiring structure of the semiconductor device according to the first embodiment of the present invention. It is.

  As shown in FIGS. 1 and 2, in the semiconductor device according to the first embodiment, the substrate 2 is not shown, but transistors, wiring layers, and the like are formed as necessary. A first interlayer insulating film 4 constituting a first wiring layer is formed on the substrate 2, and a first wiring 6 is formed in the insulating film 4. The film thickness of the first interlayer insulating film 4 and the first wiring 6 is about 200 nm. A second interlayer insulating film 8 constituting a via layer is formed on the first interlayer insulating film 4 and the first wiring 6. A via contact (hereinafter referred to as “via”) 10 is formed in the second interlayer insulating film 8 so as to penetrate the second interlayer insulating film 8 and connect to the first wiring 6. The film thickness of the second interlayer insulating film 8 and the via 10 is about 200 nm. A third interlayer insulating film 12 constituting the second wiring layer is formed on the second interlayer insulating film 8 and the via 10, and a second wiring 14 is formed in the third interlayer insulating film 12. . The film thickness of the third interlayer insulating film 12 and the second wiring 14 is about 200 nm. The second wiring 14 is connected to the via 10 as necessary. In other words, necessary portions of the first wiring 6 and the second wiring 14 are electrically connected by the via 10.

FIG. 2 shows only the wirings 6, 14 and the via 10 without the insulating films 4, 8, 12 in each layer. In FIG. 2, the hatched portion in the lower left direction indicates the first wiring 6, and the hatched portion in the lower right direction indicates the second wiring 14. In addition, a symbol portion in which “×” is written in □ represents the via 10. In addition, the via 10 is a portion where the second wiring 14 and the first wiring 6 overlap above and below, and therefore, the first and second wirings 6 and 14 are connected by the via 10 in this portion. . FIG. 2 shows a location where the first wiring 6 and the second wiring 14 are arranged in parallel.
For simplicity, the horizontal direction in FIG. 2 will be referred to as “length” and the vertical direction as “width” unless otherwise specified.

With reference to FIG. 2, the wiring structure of the semiconductor device in the first embodiment will be specifically described.
For example, the wiring lengths L ₆ and L ₁₄ of the first wiring 6 and the second wiring ₁₄ are 500 nm, and the wiring widths W ₆ and W ₁₄ are 100 nm. The spacing _{S 6} of the first wiring 6 adjacent thereto and the first wiring 6 is 100 nm, spacing _{S 14} of the second wiring 14 adjacent to the second wiring 14 is 100 nm. Further, the distance between the first wiring 6 and the next first wiring 6, that is, the wiring pitch P ₆ that is the total distance of the wiring width W ₆ of the first wiring 6 and the interval S ₆ between the first wirings _6. Is 200 nm, and the distance from the second wiring 14 to the next second wiring 14, that is, the wiring pitch P _14, which is the total distance of the wiring width W ₁₄ and the interval S ₁₄ , is also 200 nm.

In the via layer, the via 10 adjacent to the one via 10 is arranged in a diagonal direction of the one via 10, that is, in a direction oblique to the first and second wirings 6 and 14 by about 45 degrees. Has been. The width W ₁₀ and the length L ₁₀ of the via 10 are 100 nm, like the wiring widths W ₆ and W ₁₄ . The length of the via 10 in the diagonal direction, that is, the diameter R ₁₀ is √2 times the wiring widths W ₆ and W ₁₄ and is 140 nm. Further, adjacent to the diagonal directions, the spacing _{S 10} between the via 10 and the via 10, √2 times the wiring interval _{S 6, S 14,} that is, 140 nm. Thus, the pitch _{P 10} is the length to the next via 10 adjacent to the via 10 in the diagonal direction is 280 nm. When arranging the wiring and vias on a square grid, by arranging the vias 10 so via pitch P ₁₀ is √2 times the wiring pitch as described above, the degree of integration of the vias 10 is the highest. In the structure shown in FIG. 2, by uniformly arranging the vias 10 with a pitch P ₁₀ of √2 times the wiring pitch on a square grid (280 nm), it is possible to improve the process margin of the via 10, the wiring and the via The misalignment with the can be reduced.

Next, a method for manufacturing the semiconductor device, specifically, a method for forming a multilayer wiring structure will be described.
FIG. 3 is a process sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention. Specifically, it is a process sectional view for explaining a method of forming a wiring structure by a single damascene method.
First, as shown in FIG. 3A, a first interlayer insulating film 4 is formed to a thickness of 200 nm on a substrate 2 on which a semiconductor element (for example, a transistor) is formed. Next, a first wiring trench 5 is formed in the first interlayer insulating film 4 by lithography and dry etching. Then, a conductive film such as a Cu film is deposited in the first wiring trench 5 and on the first interlayer insulating film 4, and an unnecessary conductive film is removed by CMP using the first interlayer insulating film 4 as a stopper film. As a result, the conductive film is embedded in the trench 5 and the first wiring 6 is formed.
Next, as shown in FIG. 3B, a second interlayer insulating film 8 is formed to a thickness of 200 nm on the first interlayer insulating film 4 and the first wiring 6. Next, a via hole 9 connected to the first wiring 6 is formed in the second interlayer insulating film 8 by lithography and dry etching. Then, like the first wiring 6, a via 10 is formed by embedding a conductive film in the via hole 9. Here, the via 10 is formed with a contact pitch larger than the minimum wiring pitch of the first wiring 6 or the minimum wiring pitch of the second wiring 14 described later.
Next, as shown in FIG. 3C, a third interlayer insulating film 12 is formed on the second interlayer insulating film 8 and the via 10. Next, a second wiring trench 13 connected to the via 10 is formed in the third interlayer insulating film 12 by lithography and dry etching. Then, like the first wiring 6, the second wiring 14 is formed by embedding a conductive film in the second wiring groove 13.
Through the above steps, the semiconductor device shown in FIGS. 1 and 2 is obtained.

Although FIG. 1 shows a cross-sectional structure of a multilayer wiring formed by a single damascene method, a multilayer wiring can be formed by a dual damascene method as shown in FIGS. FIG. 4 is a cross-sectional view for explaining a wiring structure formed by the dual damascene method in the semiconductor device according to the first embodiment. FIG. 5 is a process sectional view for explaining the method for manufacturing the semiconductor device shown in FIG.
As shown in FIG. 4, a second interlayer insulating film 15 is formed on the first interlayer insulating film 4 and the first wiring 6. A via 10 connected to the first wiring 6 and a second wiring 14 connected to the via 10 are formed in the second interlayer insulating film 15. The film thickness of the second interlayer insulating film 15 is about 400 nm, for example.

Next, a method for manufacturing the semiconductor device shown in FIG. 4 will be described.
First, the first wiring 6 is formed in the first interlayer insulating film 4 on the substrate 2 by using a method similar to the method shown in FIG.
Next, as shown in FIG. 5A, a second interlayer insulating film 15 is formed to a thickness of 400 nm on the first interlayer insulating film 4 and the first wiring 6. Next, a second wiring trench 16 is formed in the second interlayer insulating film 15 by lithography and dry etching. Subsequently, a via hole 17 connected to the first wiring 6 is formed in the second interlayer insulating film 15 below the second wiring groove 16 by lithography and dry etching.
Next, as shown in FIG. 5B, a conductive film such as a Cu film is deposited in the via hole 17, the second wiring groove 16, and the second interlayer insulating film 15, and the second interlayer insulating film An unnecessary conductive film is removed by CMP using 15 as a stopper film. As a result, the conductive film is embedded in the via hole 17 and the groove 16, and the via 10 and the second wiring 14 are formed in the second interlayer insulating film 15.
Note that the above-described single damascene method and dual damascene method can be applied to a semiconductor device according to a second embodiment to be described later.

  FIG. 6 is a plan view showing an example in which wirings and vias are arranged on a square grid in the first embodiment. Unlike FIG. 2, the wiring 6 and the wiring 14 are not arranged in parallel. As shown in FIG. 6, the first wiring 6 and the second wiring 14 are arranged with a minimum pitch of 200 nm on a square grid (indicated by a dotted line in the drawing) with a pitch of 200 nm. The first wiring 6 and the second wiring 14 are connected by a via 10 at a predetermined location. The vias 10 are arranged at a pitch of √2 times the minimum wiring pitch 200 nm (that is, 280 nm) or more. In the structure shown in FIG. 6 as well, by arranging the vias 10 on the square grid with a pitch of √2 times or more of the wiring pitch, the process margin of the vias 10 can be improved and the misalignment between the wirings and vias can be reduced. be able to.

  As described above, in the first embodiment, vias are arranged so that the via pitch is larger than the minimum wiring pitch. Thereby, a sufficient space can be provided between the vias 10. Therefore, a correction pattern can be added to the via portion, or correction by a mask bias technique can be performed. Therefore, it is possible to form a wiring that secures a via process margin even in a wiring structure to be miniaturized.

FIG. 7 is a diagram showing the wiring pitch dependence of the usage rate of the power supply wirings arranged on the square grid in the first embodiment. FIG. 8 is a plan view showing signal wirings arranged on the grid and signal wirings arranged off-grid. In FIG. 7, the power supply wiring usage rate when the signal wiring is arranged on the grid and the power supply wiring usage rate when the signal wiring is arranged on the off-grid are compared.
In a semiconductor device, power supply wirings are arranged at different wiring pitches. Here, the usage rate of the power supply wiring arranged at a pitch of 200 nm is assumed to be 100%. The power supply wiring with a wider wiring pitch has a lower usage rate.
Further, a case will be described in which the signal wiring arrangement is prioritized over the power supply wiring arrangement. When the signal wiring 19a is arranged on the grid, that is, on the power mesh, it is not necessary to change the arrangement of the power wiring 18 for the signal wiring 19a. On the other hand, if the signal wiring 19b is arranged off-grid, it is necessary to change the arrangement of the power supply wiring with respect to the signal wiring 19b. That is, instead of the on-grid power wiring 18b, the power wiring 18a must be arranged off-grid. If the off-grid power supply wiring 18a is formed in this way, the power supply mesh is substantially broken.
With the recent increase in the degree of integration of transistors, it is necessary to accurately control the off current, and the power supply voltage is lowered. In generations after the 130 nm node, the power supply voltage becomes 1.5 V or less, and potential drops are likely to occur. In order to prevent this potential drop, a uniform supply of power supply voltage is required.
If the present invention is applied to the signal wiring, the signal wiring can be arranged on the grid, so that the usage rate of the power wiring arranged on the grid can be improved, and the breakage of the power mesh can be prevented. Can do. Therefore, it is possible to realize a power supply structure that can supply the power supply voltage uniformly.

  In the present invention, the wiring width, wiring length, and wiring pitch of the first and second wirings are not limited to those described in the first embodiment. Further, the width, diameter, and pitch of the contacts (via 10 in the first embodiment) are not limited to those described in the first embodiment. However, the contact pitch must be longer than the wiring pitch.

Further, the case where adjacent vias are arranged in the diagonal direction of each via has been described. However, the via arrangement position is not limited to the diagonal direction, and the vias closest to one via may be arranged in an oblique direction, that is, such that the distance is longer than the wiring pitch. That's fine.
That is, wiring and vias can be arranged on an irregular grid in which the X direction and the Y direction are unequal. In this case, the vias connecting the wirings are arranged at a pitch larger than the minimum wiring pitch. Further, if the via pitch is larger than the minimum pitch of the wiring, the wiring and the via may be arranged at a place other than the grid. That is, the wiring and vias may be arranged off-grid. As shown in FIG. 14, when the wiring width of the isolated wiring is less than 0.15, it cannot be handled by the square grid, and in this case, it can be handled by the off-grid. (The same applies to Embodiment 2 described later).

Embodiment 2. FIG.
FIG. 9 is a schematic cross-sectional view for explaining the semiconductor device according to the second embodiment of the present invention. FIG. 10 is a schematic top view for explaining the wiring structure of the semiconductor device according to the second embodiment.
As shown in FIGS. 9 and 10, the semiconductor device according to the second embodiment is similar to the semiconductor device described in the first embodiment. However, the via of the semiconductor device in the second embodiment is formed larger than the wiring width. This will be specifically described below.

  In the semiconductor device according to the second embodiment, the first interlayer insulating film 24 constituting the first wiring layer is formed on the substrate 22 as in the semiconductor device according to the first embodiment. A first wiring 26 is formed in the first interlayer insulating film 24. The film thickness of the first interlayer insulating film 24 and the first wiring 26 is about 200 nm. A second interlayer insulating film 28 constituting a via layer is formed on the first interlayer insulating film 24, and a via 30 is formed in the second interlayer insulating film 28. The via 30 is connected to a predetermined location of the first wiring 26. The film thickness of the second interlayer insulating film 28 and the via 30 is about 200 nm. A third interlayer insulating film 32 constituting the second wiring layer is formed on the second interlayer insulating film 28, and a second wiring 34 is formed in the third interlayer insulating film 32. The film thickness of the third interlayer insulating film 32 and the second wiring 34 is about 200 nm. In addition, the second wiring 34 is connected to a predetermined location of the via 30, whereby the first wiring 26 and the second wiring 34 are electrically connected.

FIG. 10 shows only the wirings 26 and 34 and the via 30 with the insulating films 24, 28 and 32 in each layer omitted. In FIG. 10, the hatched portion in the lower left direction indicates the first wiring 26, and the hatched portion in the lower right direction indicates the second wiring 34. In addition, a symbol portion in which “×” is written in □ represents the via 30. In addition, the via 30 is a portion where the second wiring 34 and the first wiring 26 overlap above and below, and therefore, the first and second wirings 26 and 34 are connected by the via 30 in this portion. . FIG. 10 shows a location where the first wiring 26 and the second wiring 34 are arranged in parallel.
For simplicity, the horizontal direction in FIG. 10 will be referred to as “length” and the vertical direction will be referred to as “width” unless otherwise specified.

Referring to FIG. 10, the first wiring 26 and the second wiring 34 have the same wiring length, wiring width, wiring spacing, and wiring pitch as the first wiring 6 and the second wiring 14 in the first embodiment, respectively. Have. Specifically, the wiring lengths L ₂₆ and L ₃₄ are 500 nm, the wiring widths W ₂₆ and W ₃₄ are 100 nm, the wiring intervals S ₂₆ and S ₃₄ are 100 nm, and the wiring pitches P ₂₆ and P ₃₄ are 200 nm.

The width W ₃₀ and the length L ₃₀ of the via 30 are about 127 nm, which is about 27 nm larger than the wiring widths W ₂₆ and W ₃₄ . Further, the diagonal direction of the via 30, that is, the length of the diameter R ₃₀ is about 180 nm, and is slightly larger than √2 times of the wiring widths W ₂₆ and W ₃₄ . In addition, here, the via 30 has an interval S ₃₀ between the vias diagonally adjacent to each other and 100 nm. Therefore, the pitch P ₃₀ that is the distance between the diagonally adjacent via 30 and the next via ₃₀ is 280 nm, that is, √2 times the minimum wiring pitch P ₂₆ , P ₃₄ . When arranging the wiring and vias on a square grid, by arranging the vias 30 so via pitch P ₃₀ is √2 times the wiring pitch as described above, the degree of integration of the vias 30 is the highest. In the structure shown in FIG. 10, by uniformly arranging the vias 30 with a pitch P ₃₀ of √2 times the wiring pitch on a square grid (280 nm), it is possible to improve the process margin of the via 30, the wiring and the via The misalignment with the can be reduced.
FIG. 11 is a plan view showing an example in which wirings and vias are arranged on a square grid in the second embodiment. Unlike FIG. 10, the wiring 26 and the wiring 34 are not arranged in parallel. As shown in FIG. 11, the first wiring 26 and the second wiring 34 are arranged at a minimum pitch of 200 nm on a square grid (indicated by a dotted line in the drawing) with a pitch of 200 nm. The first wiring 26 and the second wiring 34 are connected by a via 30 at a predetermined location. The vias 30 are arranged with a pitch of √2 times (that is, 280 nm) or more of the minimum wiring pitch 200 nm. In the structure shown in FIG. 11 as well, by arranging the vias 30 on the square grid with a pitch of √2 times or more of the wiring pitch, the process margin of the vias 30 can be improved, and the misalignment between the wiring and the vias is reduced. be able to.

FIG. 12 is a diagram illustrating the relationship between the amount of misalignment of vias and the via resistance in the second embodiment. For comparison, data of the first embodiment having the same via size and wiring width are shown.
As shown in FIG. 12, in the semiconductor device according to the first embodiment having the same width via and wiring, for example, when a misalignment occurs of about 30 nm, the via resistance rapidly increases and the misalignment is zero. It is about 5Ω larger than that at (zero). On the other hand, in the semiconductor device according to the second embodiment, for example, even when a misalignment occurs of about 30 nm, the amount of change in via resistance is small, and an increase in via resistance due to misalignment is suppressed. . That is, in the semiconductor device according to the second embodiment, the via 30 is larger than the first and second wiring widths W ₂₆ and W ₃₄ as compared with the semiconductor device according to the first embodiment. Also, the tolerance can be increased for the combination of the first and second wirings 26 and 34. Therefore, a greater margin can be obtained with respect to the alignment accuracy of lithography than in the first embodiment. With such tolerance, the insulating film resistance of the via opening can be set low, so that the process margin of the semiconductor device can be increased.

As described above, also in the second embodiment, vias are arranged so that the via pitch is larger than the minimum wiring pitch. Thereby, a sufficient space can be provided between the vias 10. Therefore, it is possible to form a pattern after adding a correction pattern to the via portion or performing correction using a mask bias technique. Therefore, an accurate pattern can be formed with a large process margin.
Further, in the second embodiment, by setting the via size to be larger than the wiring width, it is possible to make the margin of matching between the wiring and the via larger than that in the first embodiment.

In the second embodiment, the case where the finished width dimension W ₃₀ of the via 30 is larger than the finished width dimensions W ₂₆ and W _{34 of the} wirings ₂₆ and ₃₄ has been described. However, for example, when forming a fine via, there may be a case where the via cannot be formed as designed due to a decrease in optical contrast or the like. However, according to the second embodiment, at least in the design dimension, the width W _{30 of the} via 30 is made larger than the wirings 26 and 34 and the widths W ₂₆ and W ₃₄ . Therefore, even if the via 30 actually formed is somewhat smaller than the design dimension, an increase in via resistance can be suppressed.

In the second embodiment, the case where the width W _{30 of the} via 30 is formed to be approximately 27 nm larger than the wiring widths W ₂₆ and W _{34 of} the first and second wirings ₂₆ and ₃₄ has been described. However, in the present invention, the difference in width between the via 30 and the wirings 26 and 34 is not limited to this size. However, it is preferable that the difference in width is about 20% to about 40% of the wiring width.
Others are the same as those in the first embodiment, and thus description thereof is omitted.

  Note that the first wiring 6 and the first interlayer insulating film 4, and the first wiring 26 and the first interlayer insulating film 24 in the first and second embodiments correspond to the “first wiring layer” in the claims. . The second wiring 14 and the third interlayer insulating film 12, and the second wiring 34 and the third interlayer insulating film 32 correspond to the “second wiring layer”. The vias 10 and 32 correspond to “contact” or “via contact”. Further, the via 10 and the second interlayer insulating film 8, and the via 30 and the second interlayer insulating film 28 correspond to “contact layers”.

Further, for example, the diameter R ₃₀ of the vias 10 and 30 in the first and second embodiments corresponds to the “diagonal length of the contact” in the claims, and the via intervals S ₁₀ and S ₃₀ are: This corresponds to “interval between contacts”, and the via pitches P ₁₀ and P ₃₀ correspond to “contact pitch”. The widths W ₆ and W ₂₆ of the first wirings ₆ and ₂₆ correspond to the “wiring width of the first wiring”, and the intervals S ₆ and S ₂₆ between the first wirings ₆ and ₂₆ are “between the first wirings”. The pitches P ₆ and P ₂₆ of the first wirings ₆ and ₂₆ correspond to the “first minimum wiring pitch”. The widths W ₁₄ and W ₃₄ of the second wirings ₁₄ and ₃₄ correspond to the “wiring width of the second wiring”, and the intervals S ₁₄ and S ₃₄ between the second wirings ₁₄ and ₃₄ are “between the second wirings”. The pitches P ₁₄ and P ₃₄ of the second wirings ₁₄ and ₃₄ correspond to the “second minimum wiring pitch”.

2, 22 Substrate 4, 24 First interlayer insulating film 5, 13, 16 Wiring groove 6, 26 First wiring 8, 28 Second interlayer insulating film 9, 17 Via hole 10, 30 Via 12, 32 Third interlayer insulating film 14, 34 Second wiring 18, 18a, 18b Power supply wiring 19a, 19b Signal wiring 20 Via

Claims (9)

A substrate,
A first wiring layer including a plurality of first wirings formed on the substrate;
A contact layer formed on the first wiring layer and including a plurality of contacts connected to the first wiring;
A second wiring layer formed on the contact layer and including a plurality of second wirings connected to the contact;
The contact pitch obtained by adding the diagonal length of the contact and the interval between adjacent contacts is:
A minimum interval among the intervals between the first wirings adjacent to each other; a wiring width of the first wiring;
The first minimum wiring pitch plus
A minimum interval among the intervals between the second wirings adjacent to each other; a wiring width of the second wiring;
The second minimum wiring pitch,
A semiconductor device characterized by being larger than the above. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the contact pitch is not less than √2 times the first minimum wiring pitch or the second minimum wiring pitch. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first minimum wiring pitch or the second minimum wiring pitch is less than 150 nm. The semiconductor device according to claim 1,
A semiconductor device, wherein a minimum design dimension of a wiring width of the first wiring or the second wiring is smaller than a minimum design dimension of the contact. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein a minimum finished dimension of a wiring width of the first wiring or the second wiring is smaller than a minimum finished dimension of the contact. A method of manufacturing a semiconductor device having multilayer wiring,
Forming a first interlayer insulating film on the substrate;
Forming a first wiring trench in the first interlayer insulating film;
Forming a first wiring by embedding a conductive film in the first wiring trench;
Forming a second interlayer insulating film on the first interlayer insulating film and the first wiring;
Forming a via hole connected to the first wiring in the second interlayer insulating film;
Forming a via contact by embedding a conductive film in the via hole;
Forming a third interlayer insulating film on the second interlayer insulating film and the via contact;
Forming a second wiring trench connected to the via contact in the third interlayer insulating film;
Forming a second wiring by embedding a conductive film in the second wiring trench,
The method of manufacturing a semiconductor device, wherein the via contact is formed with a contact pitch larger than a minimum wiring pitch of the first wiring or a minimum wiring pitch of the second wiring. A method of manufacturing a semiconductor device having multilayer wiring,
Forming a first interlayer insulating film on the substrate;
Forming a first wiring trench in the first interlayer insulating film;
Forming a first wiring by embedding a conductive film in the first wiring trench;
Forming a second interlayer insulating film on the first interlayer insulating film and the first wiring;
Forming a second wiring trench in the second interlayer insulating film;
Forming a via hole connected to the first wiring in the second interlayer insulating film below the second wiring trench;
Forming a via contact and a second wiring by embedding a conductive film in the via hole and the second wiring groove,
The method of manufacturing a semiconductor device, wherein the via contact is formed with a contact pitch larger than a minimum wiring pitch of the first wiring or a minimum wiring pitch of the second wiring. In the manufacturing method of the semiconductor device according to claim 6 or 7,
A method of manufacturing a semiconductor device, wherein the first wiring or the second wiring is formed so that a minimum wiring pitch is less than 150 nm. In the manufacturing method of the semiconductor device according to claim 6,
The method of manufacturing a semiconductor device, wherein the via contact is formed so that a dimension of the via contact is larger than a minimum dimension of a wiring width of the first wiring or the second wiring.

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