JP2011254044A - Method for producing a heat dissipation substrate for mounting in semiconductor - Google Patents

Method for producing a heat dissipation substrate for mounting in semiconductor Download PDF

Info

Publication number
JP2011254044A
JP2011254044A JP2010128721A JP2010128721A JP2011254044A JP 2011254044 A JP2011254044 A JP 2011254044A JP 2010128721 A JP2010128721 A JP 2010128721A JP 2010128721 A JP2010128721 A JP 2010128721A JP 2011254044 A JP2011254044 A JP 2011254044A
Authority
JP
Japan
Prior art keywords
layer
layers
plating
heat dissipation
base material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010128721A
Other languages
Japanese (ja)
Other versions
JP5522786B2 (en
Inventor
Fumio Oshita
文夫 大下
Masahiro Yamaguchi
雅弘 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TAKAMATSU MEKKI KK
Original Assignee
TAKAMATSU MEKKI KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TAKAMATSU MEKKI KK filed Critical TAKAMATSU MEKKI KK
Priority to JP2010128721A priority Critical patent/JP5522786B2/en
Publication of JP2011254044A publication Critical patent/JP2011254044A/en
Application granted granted Critical
Publication of JP5522786B2 publication Critical patent/JP5522786B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

PROBLEM TO BE SOLVED: To provide a method for producing a highly reliable heat dissipation substrate for mounting in semiconductor which has stable heat dissipation functionality and mechanical strength, and which is free from interlayer peeling because metal layers are formed in integrated form.SOLUTION: The method for producing a heat dissipation substrate forms a heat dissipation substrate by forming one or more metal layers on two surfaces of a base material, that is to be a center part of layer thickness, by plating them so that they are vertically symmetric. Bonding metal materials are not used for other than the base material and the vertically symmetric metal layers formed in integrated form, which are uniform, and plated around the base material, do not cause interlayer peeling and realize stable heat dissipation functionality and mechanical strength.

Description

この発明は、LED等の半導体素子を保持するとともに、それに蓄熱するのを防止する機能を果たす半導体搭載用放熱基板の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor-mounted heat dissipation substrate that functions to hold a semiconductor element such as an LED and prevent it from storing heat.

LED(発光ダイオード)や半導体集積回路等では、最近の高密度化および高出力化により放熱量が増加する傾向にある。LEDについてみると(図11の左図参照))、そのLEDは、サファイア基板の上にそれが搭載されているが、これであると、LEDの発光部から発する熱が熱伝導率の悪いサファイア基板との間に溜まりやすく(図12の左図参照)、多くの半導体素子ではその蓄熱があると機能が低下し、特にLEDではその輝度と低反射率で弊害が生じることから、それを受ける部分に熱伝動性の良好な金属製の放熱基板が使用される(図11の右図参照)。たとえば、銅やモリブデン、タングステン、チタン、モリブデン等のメタルウエハーと称する金属である。そして、主にモリブデン(Mo)を銅(Cu,Cu)でサンドイッチしたもの(DMD)が良好であることが知られている(図12の右図参照)。   In LEDs (light emitting diodes), semiconductor integrated circuits, and the like, the amount of heat radiation tends to increase due to recent increases in density and output. As for the LED (see the left figure of FIG. 11), the LED is mounted on a sapphire substrate, but if this is the case, the heat generated from the light emitting part of the LED has poor thermal conductivity. It tends to accumulate between the substrate (see the left figure in FIG. 12), and in many semiconductor elements, the function is reduced when there is heat storage, especially in the case of LEDs, which has a negative effect due to its brightness and low reflectance. A metal heat radiating substrate having good heat conductivity is used for the portion (see the right figure in FIG. 11). For example, a metal called a metal wafer such as copper, molybdenum, tungsten, titanium, or molybdenum. And it is known that what mainly sandwiched molybdenum (Mo) with copper (Cu, Cu) (DMD) is good (see the right figure of FIG. 12).

放熱基板に要求される性質ないし性能等については、優れた熱伝動性が求められる他に、熱による歪みがない安定性と高い機械的強度、機械加工性が要求される。また、半導体素子を取り付ける接着やロウ付け等に適すること、耐薬品性に優れていること等が求められるときもある。これらの性質は、従来、図11、図12の各右図に示す如く複数の金属層の結合により総合的に発揮するよう開発が進められる(特許文献1、特許文献2)。この多層構造を取る手段としては、従来圧延方法や熱間一軸加工法が用いられていた。   As for the properties or performances required for the heat dissipation substrate, in addition to excellent thermal conductivity, stability without thermal distortion, high mechanical strength, and machinability are required. In addition, it is sometimes required to be suitable for bonding or brazing for attaching a semiconductor element, and to be excellent in chemical resistance. Conventionally, development has been progressed so that these properties are comprehensively exhibited by the combination of a plurality of metal layers as shown in the right diagrams of FIGS. 11 and 12 (Patent Documents 1 and 2). Conventionally, a rolling method or a hot uniaxial machining method has been used as means for taking this multilayer structure.

特開平6−268115号公報JP-A-6-268115 特許第3862737号公報Japanese Patent No. 3862737

圧延方法や熱間一軸加工法は、いずれも複数枚の合せ金属材(グラッド材、グラッド金属とも称する))を重ねて圧縮することにより熱可塑性により偏平化するとともに合せ材どうしを加熱圧着してグラッド層を形成するものであるが、その接着には過熱温度、時間、圧縮強さ等の条件整合が難しく剥離しないという信頼性に乏しく、剥離が発生すると、機械的強度や放熱性能に支承(剥離部分に蓄熱する)をきたし、盛り上がりでパッケージ基板や半導体素子との結合が不安定となる等という問題があった。   In both the rolling method and the hot uniaxial processing method, a plurality of laminated metal materials (also referred to as grad materials and grad metals) are overlapped and compressed to flatten due to thermoplasticity, and the laminated materials are thermocompression bonded. Although it forms a grad layer, it is difficult to match the conditions such as overheating temperature, time, and compressive strength, and it is not reliable that it will not peel off. When peeling occurs, it is supported by mechanical strength and heat dissipation performance ( There is a problem in that, for example, heat is accumulated in the peeled portion, and the coupling with the package substrate and the semiconductor element becomes unstable due to the rise.

また、異種金属の接合に伴う反りを防ぐ方法として、中心部となる母材を中心としてその上下両面に対称になるよう多種金属の合せ金属材が配置される。しかしながら、それでも熱変形の異なる異種金属を同時に過熱圧縮するため、グラッド層の厚みに偏在が生じたり層にうねりやコロニーが生じたりしやすく、これらの発生も全体的な反りの原因となり、また、機械的強度や放熱性能に支承を招く要因となるという問題もあった。   Further, as a method for preventing warpage accompanying the joining of different kinds of metals, a multi-metal laminated metal material is arranged so as to be symmetrical with respect to the upper and lower surfaces around the base material as the center. However, since dissimilar metals with different thermal deformations are simultaneously heat-compressed, uneven distribution in the thickness of the grad layer and undulation and colony are likely to occur in the layer, and these occurrences also cause overall warpage, There has also been a problem that it becomes a factor inducing mechanical strength and heat dissipation performance.

この発明は、上記のような実情に鑑みて、合せ材を用いなく、用いても層の中心部の基材にのみ用いることにして鋭意研究を重ねてきたもので、各金属層が不離一体に形成されるために、層間において剥離が生じなく、安定した放熱性および機械的強度を保持する信頼性の高い半導体搭載用放熱基板の製造方法を提供することを課題とした。   In view of the above situation, the present invention has been earnestly studied by using only the base material at the center of the layer without using a laminated material. Therefore, an object of the present invention is to provide a highly reliable method for manufacturing a semiconductor-mounted heat dissipation substrate that does not cause separation between layers and maintains stable heat dissipation and mechanical strength.

上記の課題を解決するために、この発明は、層厚の中心部となる基母材の両面に1以上の金属層をめっきにより上下対称の配置となるように形成することを特徴とする半導体搭載用放熱基板の製造方法を提供する。   In order to solve the above-mentioned problems, the present invention is characterized in that one or more metal layers are formed on both surfaces of a base material which is the central portion of the layer thickness so as to be vertically symmetrically arranged by plating. Provided is a method for manufacturing a mounting heat dissipation board.

半導体搭載用放熱基板を上記のように形成したから、基母材は、合せ材の金属片単独又は合せ材の両面に多種金属の合せ材を貼りあわせてこれに使用されるもので、これには、圧延方法や熱間一軸加工法等が使用されるが、この基母材をコアとしてその両面に確実に金属層がめっきにより形成される。   Since the semiconductor mounting heat dissipating board is formed as described above, the base matrix is used for this purpose by bonding a single metal piece of a composite material or a multi-metal composite material on both sides of the composite material. In this method, a rolling method, a hot uniaxial processing method, or the like is used, and a metal layer is reliably formed by plating on the both surfaces using the base base material as a core.

以上説明したように、この発明によれば、基母材以外では合せ金属材を用いなく、これを中心にめっきにより各金属層が不離一体に形成されるために、層間において剥離が生じなく、上下均等且つ対称を正確に形成した構造となることとも相まって、安定した放熱性および機械的強度を保持する信頼性の高い半導体搭載用放熱基板の製造方法を提供することができる。   As described above, according to the present invention, a metal member other than the base material is not used, and since each metal layer is formed in a single piece by plating around this, no separation occurs between the layers, Combined with the structure in which the upper and lower parts are evenly and accurately formed, it is possible to provide a highly reliable method for manufacturing a semiconductor-mounted heat dissipation board that maintains stable heat dissipation and mechanical strength.

この発明の第1実施例に係る半導体搭載用放熱基板の製造方法 を矢印順に且つ断面模式的に示す説明図である。It is explanatory drawing which shows the manufacturing method of the semiconductor mounting heat dissipation board concerning 1st Example of this invention in order of an arrow and a cross-section typically. 同製造方法による半導体搭載用放熱基板の斜視図である。It is a perspective view of the semiconductor mounting heat dissipation board by the manufacturing method. 同半導体搭載用放熱基板の使用状態を示す断面模式的に示す説明図である。It is explanatory drawing which shows typically the cross section which shows the use condition of the heat sink for semiconductor mounting. 第2実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 2nd Example. 第3実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 3rd Example. 第4実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 4th Example. 第5実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 5th Example. 第6実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 6th Example. 第7実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 7th Example. 第8実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 8th Example. 従来例の説明図である。It is explanatory drawing of a prior art example. 従来例の説明図である。It is explanatory drawing of a prior art example.

この発明は、層厚のコアとなる合せ金属材からなる基母材1,2の両面にめっき層8,8を形成し且つ上下対称に形成してめっき層半導体搭載用放熱基板Pを製造するものである(図3)。
基母材は、一枚の金属の単一基母材1である場合と、複数枚のサンドイッチ構造の複合基母材2である場合とがある。いずれも、合せ材として金属薄片が使用され、複合基母材2の場合であると、圧延加工法や熱間一軸加工法等により加圧して一体化される。
In the present invention, the plated layers 8 and 8 are formed on both surfaces of the base base materials 1 and 2 made of a laminated metal material to be a core having a layer thickness, and are formed symmetrically in the vertical direction to manufacture the plated layer semiconductor mounting heat dissipation substrate P. (FIG. 3).
The base material may be a single metal single base material 1 or a composite base material 2 having a plurality of sandwich structures. In both cases, metal flakes are used as the bonding material, and in the case of the composite base material 2, they are integrated by being pressed by a rolling method, a hot uniaxial processing method, or the like.

基母材1,2の金属には、比較的熱伝導率の小さいモリブデン(Mo)やタングステン(W)などが使用される。なお、こうして重合された原多層材は、ウエハーのチップ化と同じくカッティングにより縦横に細分される。   Molybdenum (Mo), tungsten (W), or the like having a relatively low thermal conductivity is used for the metals of the base materials 1 and 2. The raw multi-layer material thus polymerized is subdivided vertically and horizontally by cutting, as in the case of wafer chip formation.

こうして造られた基母材1,2の両面には、上下対称に比較的熱伝導率の良好な他の金属層がめっきにより形成される。それら金属層の厚みについては、例えば、Au層であると0.05〜1.5μm、Ni又はNi合金層であると0.02〜10μm、Au・Sn合金層であると、0.2〜10μm、Sn層であると0.2〜5.0μm、Cu層であると0.2〜40μmであることが良好である。また、このうち、特にAu層7が外面であると、酸化しにくいので、パッケージ基板10やLED発光体12等(図3参照)との接着性が良好であり望ましい。 半導体搭載用放熱基板Pの他の部品との接着については、表面がAu層7,7又はSn層11,11であるきは、Ag系又はAu・Sn系のペーストないし接着剤が好適に使用される。   On both surfaces of the base base materials 1 and 2 thus manufactured, other metal layers having relatively good thermal conductivity are formed by plating in a vertically symmetrical manner. Regarding the thickness of these metal layers, for example, 0.05 to 1.5 μm for the Au layer, 0.02 to 10 μm for the Ni or Ni alloy layer, and 0.2 to 0.2 for the Au / Sn alloy layer. 10 μm, Sn layer is preferably 0.2 to 5.0 μm, and Cu layer is preferably 0.2 to 40 μm. Of these, particularly when the Au layer 7 is on the outer surface, it is difficult to oxidize, so that the adhesiveness to the package substrate 10, the LED light emitter 12 and the like (see FIG. 3) is preferable. For bonding the semiconductor mounting heat dissipation board P to other components, if the surface is the Au layer 7, 7 or the Sn layer 11, 11, an Ag-based or Au-Sn-based paste or adhesive is preferably used. The

めっきは、電解、無電解、イオンプレーティング(IP)法等が望ましいが、めっきであれば特に限定するものではない。いずれにしても、めっきによって各金属層の厚みが上下対称で均一な層に形成され、各層が緊密に結合する。また、Cu金属層の形成については、Cuめっきの他に、Cuイオンプレーティング法を最適に用いることができる。   Plating is preferably electrolysis, electroless, ion plating (IP) method or the like, but is not particularly limited as long as it is plating. In any case, the thickness of each metal layer is formed into a uniform layer with vertical symmetry by plating, and the layers are tightly coupled. For forming the Cu metal layer, a Cu ion plating method can be optimally used in addition to Cu plating.

イオンプレーティング法は、乾式のめっきで湿式とは違い僅かな表面改質でめっき加工が可能である。Moは非常にめっきが密着しにくい金属である。面粗さを失わずにCuめっきを付ける場合は、イオンプレーティング法が最適である。この場合、Moの上にCuめっきをする際に薄膜の銅をIPで付けてから、電解若しくは無電解でCuめっきを施す工程とするので上記目的が達成される。つまり、Moの金属片の上にCu層をイオンプレーティング法により例えば0.2μm程度形成し、その上にCuめっき(電解又は無電解)で施すのが最善な方法である。無電解めっきは、電解めっきと比較してめっきの均一性が良い。めっきの効率は電解めっき>無電解>銅めっき(電解・無電解)となる。   The ion plating method can be plated with a slight surface modification, unlike dry, wet plating. Mo is a metal that is very difficult to adhere to plating. When applying Cu plating without losing surface roughness, the ion plating method is optimal. In this case, when Cu is plated on Mo, a thin film of copper is attached by IP, and then the Cu plating is performed electrolytically or electrolessly, thereby achieving the above object. That is, the best method is to form a Cu layer on the Mo metal piece by, for example, about 0.2 μm by the ion plating method, and apply Cu plating (electrolytic or electroless) thereon. Electroless plating has better plating uniformity than electrolytic plating. The plating efficiency is electrolytic plating> electroless> copper plating (electrolysis / electroless).

図1ないし図3は実施例1を示し、複合基母材2となる広い原材としては、Mo層3をCu層4,4でサンドイッチした3層構造のものを使用する(図1)。それには基母材2のCu層4,4の面を研磨機18で研磨してからNiめっきをその両面に施しNi層5,5(層厚1.0μm)を形成し、さらにその両Ni層5,5にAuめっきを施し両面がAu層7,7(層厚2μm)として形成する。めっき工程を経て広く製造されためっき元材は縦横カンティングにより細分化されて加工される。図2がこうして加工された製品としての放熱基板Pを示すが円形とは限らない。   FIG. 1 to FIG. 3 show Example 1, and a wide raw material to be a composite base material 2 is a three-layer structure in which a Mo layer 3 is sandwiched between Cu layers 4 and 4 (FIG. 1). For this purpose, the surfaces of the Cu layers 4 and 4 of the base material 2 are polished by a polishing machine 18 and then Ni plating is performed on both surfaces to form Ni layers 5 and 5 (layer thickness 1.0 μm). The layers 5 and 5 are plated with Au, and both surfaces are formed as Au layers 7 and 7 (layer thickness 2 μm). A plating base material widely manufactured through a plating process is subdivided and processed by vertical and horizontal canting. Although FIG. 2 shows the heat dissipation board P as a product thus processed, it is not necessarily circular.

図3はLEDを搭載した使用状態を示したもので、パッケージ基板10の上に接着剤14を介して半導体搭載用放熱基板Pが搭載され、その上に接着剤16を介してLED12が搭載される。いずれも、表面がAu層7,7であるので、接着剤14,16の乗りが良く接着性が良好である。また、Au層7で反射してLED12の反射効率が良好であり、反射しなくても金属層の光の通りが良く蓄熱量が少ないという利点がある。   FIG. 3 shows a use state in which LEDs are mounted. A semiconductor mounting heat dissipation substrate P is mounted on the package substrate 10 via an adhesive 14, and the LEDs 12 are mounted thereon via an adhesive 16. The In any case, since the surfaces are the Au layers 7 and 7, the adhesives 14 and 16 are easily mounted and the adhesiveness is good. In addition, there is an advantage that the reflection efficiency of the LED 12 is reflected by the Au layer 7 and the light of the metal layer is good and the heat storage amount is small even if it is not reflected.

図4において、前記実施例に対して前記Au層7,7がその合金となっている違いがある。つまり、めっきを施すことによりAu・Sn合金層9,9として両面を形成して放熱基板Pが形成される。この実施例の場合も、Auの性質等から上記と同じ利点がある。以下においても同じである。   In FIG. 4, there is a difference that the Au layers 7 and 7 are alloys thereof with respect to the embodiment. That is, the heat dissipation substrate P is formed by forming both surfaces as Au / Sn alloy layers 9 and 9 by plating. This embodiment also has the same advantages as described above due to the nature of Au. The same applies to the following.

図5において、その放熱基板Pは、実施例1に対してそのNi層5,5がSn層11,11になっている違いがある。   In FIG. 5, the heat dissipation substrate P is different from the first embodiment in that the Ni layers 5 and 5 are Sn layers 11 and 11.

図6において、その放熱基板Pは、複合基母材2の両面にAu層7,7をさらにその上にSn層11,11が形成される。   In FIG. 6, the heat dissipation substrate P has Au layers 7 and 7 formed on both sides of the composite base material 2, and Sn layers 11 and 11 formed thereon.

図7において、その放熱基板Pは、Mo層3を合せ金属材の単一基母材1としたもので、まずその両面にCu層4,4をめっき(Cuイオンプレーティングによることもできる)を施した場合と、Mo層3の両面にNi層5,5とCu層4,4を順次めっきした場合とに分けて製造される。それぞれについて次の如くである。   In FIG. 7, the heat dissipation substrate P is a single base matrix 1 made of a metal material with the Mo layer 3 combined. First, Cu layers 4 and 4 are plated on both surfaces (also by Cu ion plating). And the case where the Ni layers 5 and 5 and the Cu layers 4 and 4 are sequentially plated on both surfaces of the Mo layer 3. Each is as follows.

前者については、両面のCu層4,4にNi層5,5を、さらにAu層7,7を順次めっきして形成して放熱基板Pを製造した。また、後者については、その両面のCu層4,4にNi層5,5、Au層7,7を順次めっきで形成して放熱基板Pを製造した。   As for the former, the Ni layers 5 and 5 and the Au layers 7 and 7 were successively formed on the Cu layers 4 and 4 on both sides, and the heat dissipation substrate P was manufactured. In the latter case, Ni layers 5 and 5 and Au layers 7 and 7 were sequentially formed on the Cu layers 4 and 4 on both sides thereof to manufacture the heat dissipation substrate P.

図8においてもMo層3を単一基母材1としたもので、この場合も、まずその両面にCu層4,4をめっき(Cuイオンプレーティングによることもできる)を施した場合と、Mo層3の両面にNi層5,5とCu層4,4を順次めっきした場合とに分けられる。それぞれについて次の如くである。   Also in FIG. 8, the Mo layer 3 is a single base matrix 1, and also in this case, the Cu layers 4 and 4 are first plated on both surfaces (also by Cu ion plating), It is divided into the case where Ni layers 5 and 5 and Cu layers 4 and 4 are sequentially plated on both surfaces of the Mo layer 3. Each is as follows.

すなわち、前者については、両面のCu層4,4の上にNi層5,5をめっきにより形成し、その上にそれぞれAu・Sn合金層9,9をめっきし、放熱基板Pの原材を形成した。また、後者については、両面のCu層4,4の上にNi層5,5をさらにその上にAu・Sn合金層9,9を形成して放熱基板Pの原材を構成した。   That is, as for the former, Ni layers 5 and 5 are formed on the Cu layers 4 and 4 on both sides by plating, and Au / Sn alloy layers 9 and 9 are plated on the Ni layers 5 and 5, respectively. Formed. In the latter case, Ni layers 5 and 5 were formed on the Cu layers 4 and 4 on both sides, and Au / Sn alloy layers 9 and 9 were further formed thereon to constitute the raw material of the heat dissipation substrate P.

図9において、Mo層3としての基母材1の両面にCu層4,4をめっきにより形成した場合と、Ni層5,5とCu層4,4を順次めっきにより形成した場合とに分けられて製造した。それぞれについてさらに次の如くである。   9, the case where the Cu layers 4 and 4 are formed on both surfaces of the base material 1 as the Mo layer 3 by plating and the case where the Ni layers 5 and 5 and the Cu layers 4 and 4 are sequentially formed by plating are divided. Manufactured. Each is further described as follows.

つまり、前者では、Cu層4,4にNi層5,5をめっきで形成し、この上にSn層11,11とAu層7,7がめっきにより形成して放熱基板Pの原材が作られる。また、後者では、Cu層4,4の上にNi層5,5を、その上にSn層11,11とAu層7,7をそれぞれめっきにより形成して放熱基板Pの原材が作られる。   In other words, in the former, the Ni layers 5 and 5 are formed on the Cu layers 4 and 4 by plating, and the Sn layers 11 and 11 and the Au layers 7 and 7 are formed thereon by plating, so that the raw material of the heat dissipation substrate P is made. It is done. In the latter case, the Ni layers 5 and 5 are formed on the Cu layers 4 and 4, and the Sn layers 11 and 11 and the Au layers 7 and 7 are formed thereon by plating, whereby the raw material of the heat dissipation substrate P is made. .

図10において、この場合も、前記と同じであって、Mo層3としての単一基母材1の両面にCu層4,4をめっきにより形成した場合と、Ni層5,5とCu層4,4を順次めっきにより形成した場合とに分けられ、それぞれについてさらにめっきが施される。   10, in this case as well, the Cu layers 4 and 4 are formed on both surfaces of the single base material 1 as the Mo layer 3 by plating, and the Ni layers 5 and 5 and the Cu layer. 4 and 4 are sequentially formed by plating, and further plating is performed for each.

前者の場合であると、Cu層4,4にNi層5,5をめっきにより形成し、その上にAu層7,7とSn層11,11を順次めっきにより形成して放熱基板Pの原材が形成される。また、後者であると、Cu層4,4の上にNi層5,5をめっきにより形成し、Ni層5,5の上にAu層7,7とSn層11,11が順次めっきにより形成して放熱基板Pの原材が作られる。   In the former case, the Ni layers 5 and 5 are formed on the Cu layers 4 and 4 by plating, and the Au layers 7 and 7 and the Sn layers 11 and 11 are sequentially formed on the Ni layers 5 and 5 by plating. A material is formed. In the latter case, Ni layers 5 and 5 are formed on the Cu layers 4 and 4 by plating, and Au layers 7 and 7 and Sn layers 11 and 11 are sequentially formed on the Ni layers 5 and 5 by plating. Thus, the raw material of the heat dissipation board P is made.

P 半導体搭載用放熱基板
1 単一基母材
2 複合基母材
3 Mo層
4 Cu層
5 Ni層
7 Au層
9 Au・Sn合金層
11 Sn層
P Semiconductor Heat Dissipation Board 1 Single Base Base Material 2 Composite Base Base Material 3 Mo Layer 4 Cu Layer 5 Ni Layer 7 Au Layer 9 Au / Sn Alloy Layer 11 Sn Layer

この発明は、LED等の半導体素子を保持するとともに、それに蓄熱するのを防止する機能を果たす半導体搭載用放熱基板の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor-mounted heat dissipation substrate that functions to hold a semiconductor element such as an LED and prevent it from storing heat.

LED(発光ダイオード)や半導体集積回路等では、最近の高密度化および高出力化により放熱量が増加する傾向にある。LEDについてみると(図11の左図参照))、そのLEDは、サファイア基板の上にそれが搭載されているが、これであると、LEDの発光部から発する熱が熱伝導率の悪いサファイア基板との間に溜まりやすく(図12の左図参照)、多くの半導体素子ではその蓄熱があると機能が低下し、特にLEDではその輝度と低反射率で弊害が生じることから、それを受ける部分に熱伝導性の良好な金属製の放熱基板が使用される(図11の右図参照)。たとえば、銅やモリブデン、タングステン、チタン等のメタルウエハーと称する金属である。そして、主にモリブデン(Mo)を銅(Cu,Cu)でサンドイッチしたもの(DMD)が良好であることが知られている(図12の右図参照)。 In LEDs (light emitting diodes), semiconductor integrated circuits, and the like, the amount of heat radiation tends to increase due to recent increases in density and output. As for the LED (see the left figure of FIG. 11), the LED is mounted on a sapphire substrate, but if this is the case, the heat generated from the light emitting part of the LED has poor thermal conductivity. It tends to accumulate between the substrate (see the left figure in FIG. 12), and in many semiconductor elements, the function is reduced when there is heat storage, especially in the case of LEDs, which has a negative effect due to its brightness and low reflectance. A metal heat dissipation board with good thermal conductivity is used for the portion (see the right figure in FIG. 11). For example, a metal called a metal wafer such as copper, molybdenum, tungsten, or titanium . And it is known that what mainly sandwiched molybdenum (Mo) with copper (Cu, Cu) (DMD) is good (see the right figure of FIG. 12).

放熱基板に要求される性質ないし性能等については、優れた熱伝導性が求められる他に、熱による歪みがない安定性と高い機械的強度、機械加工性が要求される。また、半導体素子を取り付ける接着やロウ付け等に適すること、耐薬品性に優れていること等が求められるときもある。これらの性質は、従来、図11、図12の各右図に示す如く複数の金属層の結合により総合的に発揮するよう開発が進められる(特許文献1、特許文献2)。この多層構造を取る手段としては、従来、圧延方法や熱間一軸加工法が用いられていた。 As for the properties or performances required for the heat dissipation substrate, excellent thermal conductivity is required, and stability without thermal distortion, high mechanical strength, and machinability are required. In addition, it is sometimes required to be suitable for bonding or brazing for attaching a semiconductor element, and to be excellent in chemical resistance. Conventionally, development has been progressed so that these properties are comprehensively exhibited by the combination of a plurality of metal layers as shown in the right diagrams of FIGS. 11 and 12 (Patent Documents 1 and 2). Conventionally, a rolling method or a hot uniaxial working method has been used as means for taking this multilayer structure.

特開平6−268115号公報JP-A-6-268115 特許第3862737号公報Japanese Patent No. 3862737

圧延方法や熱間一軸加工法は、いずれも複数枚の合せ金属材(グラッド材、グラッド金属とも称する))を重ねて圧縮することにより熱可塑性により偏平化するとともに合せ材どうしを加熱圧着してグラッド層を形成するものであるが、その接着には加熱温度、時間、圧縮強さ等の条件整合が難しく剥離しないという信頼性に乏しく、剥離が発生すると、機械的強度や放熱性能に支障(剥離部分に蓄熱する)をきたし、盛り上がりでパッケージ基板や半導体素子との結合が不安定となる等という問題があった。 In both the rolling method and the hot uniaxial processing method, a plurality of laminated metal materials (also referred to as grad materials and grad metals) are overlapped and compressed to flatten due to thermoplasticity, and the laminated materials are thermocompression bonded. Although it forms a grad layer, it is difficult to match conditions such as heating temperature, time, compressive strength, etc., and it is difficult to peel off. If peeling occurs, it will hinder mechanical strength and heat dissipation performance ( There is a problem in that, for example, heat is accumulated in the peeled portion, and the coupling with the package substrate and the semiconductor element becomes unstable due to the rise.

また、異種金属の接合に伴う反りを防ぐ方法として、中心部となる母材を中心としてその上下両面に対称になるよう多種金属の合せ金属材が配置される。しかしながら、それでも熱変形の異なる異種金属を同時に加熱圧縮するため、グラッド層の厚みに偏在が生じたり、層にうねりやコロニーが生じたりしやすく、これらの発生も全体的な反りの原因となり、また、機械的強度や放熱性能に支障を招く要因となるという問題もあった。 Further, as a method for preventing warpage accompanying the joining of different kinds of metals, a multi-metal laminated metal material is arranged so as to be symmetrical with respect to the upper and lower surfaces around the base material as the center. However, since dissimilar metals with different thermal deformations are heated and compressed at the same time, the thickness of the grad layer is likely to be unevenly distributed , and undulations and colonies are likely to occur in the layer. , there is a problem that a factor causing a problem in mechanical strength and heat radiation performance.

この発明は、上記のような実情に鑑みて、合せ材を用いなく、用いても層の中心部の基材にのみ用いることにして鋭意研究を重ねてきたもので、各金属層が不離一体に形成されるために、層間において剥離が生じなく、安定した放熱性および機械的強度を保持する信頼性の高い半導体搭載用放熱基板の製造方法を提供することを課題とした。   In view of the above situation, the present invention has been earnestly studied by using only the base material at the center of the layer without using a laminated material. Therefore, an object of the present invention is to provide a highly reliable method for manufacturing a semiconductor-mounted heat dissipation substrate that does not cause separation between layers and maintains stable heat dissipation and mechanical strength.

上記の課題を解決するために、この発明は、層厚の中心部となる基母材の両面に1以上の金属層をめっきにより上下対称の配置となるように形成することを特徴とする半導体搭載用放熱基板の製造方法を提供する。   In order to solve the above-mentioned problems, the present invention is characterized in that one or more metal layers are formed on both surfaces of a base material which is the central portion of the layer thickness so as to be vertically symmetrically arranged by plating. Provided is a method for manufacturing a mounting heat dissipation board.

半導体搭載用放熱基板を上記のように形成したから、基母材は、合せ材の金属片単独又は合せ材の両面に多種金属の合せ材を貼りあわせてこれに使用されるもので、これには、圧延方法や熱間一軸加工法等が使用されるが、この基母材をコアとしてその両面に確実に金属層がめっきにより形成される。   Since the semiconductor mounting heat dissipating board is formed as described above, the base matrix is used for this purpose by bonding a single metal piece of a composite material or a multi-metal composite material on both sides of the composite material. In this method, a rolling method, a hot uniaxial processing method, or the like is used, and a metal layer is reliably formed by plating on the both surfaces using the base base material as a core.

以上説明したように、この発明によれば、基母材以外では合せ金属材を用いなく、これを中心にめっきにより各金属層が不離一体に形成されるために、層間において剥離が生じなく、上下均等且つ対称を正確に形成した構造となることとも相まって、安定した放熱性および機械的強度を保持する信頼性の高い半導体搭載用放熱基板の製造方法を提供することができる。   As described above, according to the present invention, a metal member other than the base material is not used, and since each metal layer is formed in a single piece by plating around this, no separation occurs between the layers, Combined with the structure in which the upper and lower parts are evenly and accurately formed, it is possible to provide a highly reliable method for manufacturing a semiconductor-mounted heat dissipation board that maintains stable heat dissipation and mechanical strength.

この発明の第1実施例に係る半導体搭載用放熱基板の製造方法を矢印順に且つ断面模式的に示す説明図である。It is explanatory drawing which shows the manufacturing method of the semiconductor mounting heat dissipation board concerning 1st Example of this invention in order of an arrow and a cross section typically. 同製造方法による半導体搭載用放熱基板の斜視図である。It is a perspective view of the semiconductor mounting heat dissipation board by the manufacturing method. 同半導体搭載用放熱基板の使用状態を示す断面模式的に示す説明図である。It is explanatory drawing which shows typically the cross section which shows the use condition of the heat sink for semiconductor mounting. 第2実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 2nd Example. 第3実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 3rd Example. 第4実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 4th Example. 第5実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 5th Example. 第6実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 6th Example. 第7実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 7th Example. 第8実施例に係る図1に対応する説明図である。It is explanatory drawing corresponding to FIG. 1 which concerns on 8th Example. 従来例の説明図である。It is explanatory drawing of a prior art example. 従来例の説明図である。It is explanatory drawing of a prior art example.

この発明は、層厚のコアとなる合せ金属材からなる基母材1又は2の両面にめっき層8,8を形成し且つ上下対称に形成してめっき層半導体搭載用放熱基板Pを製造するものである(図3)。
基母材は、一枚の金属の単一基母材1である場合と、複数枚のサンドイッチ構造の複合基母材2である場合とがある。いずれも、合せ材として金属薄片が使用され、複合基母材2の場合であると、圧延加工法や熱間一軸加工法等により加圧して一体化される。
In the present invention, plating layers 8 and 8 are formed on both surfaces of a base metal 1 or 2 made of a laminated metal material to be a core having a layer thickness, and are formed symmetrically in the vertical direction to manufacture a heat sink P for mounting a plating layer semiconductor. (FIG. 3).
The base material may be a single metal single base material 1 or a composite base material 2 having a plurality of sandwich structures. In both cases, metal flakes are used as the bonding material, and in the case of the composite base material 2, they are integrated by being pressed by a rolling method, a hot uniaxial processing method, or the like.

基母材1又は2の金属には、比較的熱伝導率の小さいモリブデン(Mo)やタングステン(W)などが使用される。なお、こうして重合された原多層材は、ウエハーのチップ化と同じくカッティングにより縦横に細分される。 For the metal of the base material 1 or 2, molybdenum (Mo), tungsten (W) or the like having a relatively low thermal conductivity is used. The raw multi-layer material thus polymerized is subdivided vertically and horizontally by cutting, as in the case of wafer chip formation.

こうして造られた基母材1又は2の両面には、上下対称に比較的熱伝導率の良好な他の金属層がめっきにより形成される。それら金属層の厚みについては、例えば、Au層であると0.05〜1.5μm、Ni又はNi合金層であると0.02〜10μm、Au・Sn合金層であると、0.2〜10μm、Sn層であると0.2〜5.0μm、Cu層であると0.2〜40μmであることが良好である。また、このうち、特にAu層7が外面であると、酸化しにくいので、パッケージ基板10やLED発光体12等(図3参照)との接着性が良好であり望ましい。半導体搭載用放熱基板Pの他の部品との接着については、表面がAu層7,7又はSn層11,11であるきは、Ag系又はAu・Sn系のペーストないし接着剤が好適に使用される。 On the both surfaces of the base material 1 or 2 thus produced, other metal layers having relatively good thermal conductivity are formed by plating in a vertically symmetrical manner. Regarding the thickness of these metal layers, for example, 0.05 to 1.5 μm for the Au layer, 0.02 to 10 μm for the Ni or Ni alloy layer, and 0.2 to 0.2 for the Au / Sn alloy layer. 10 μm, Sn layer is preferably 0.2 to 5.0 μm, and Cu layer is preferably 0.2 to 40 μm. Of these, particularly when the Au layer 7 is on the outer surface, it is difficult to oxidize, so that the adhesiveness to the package substrate 10, the LED light emitter 12 and the like (see FIG. 3) is preferable. For bonding the semiconductor mounting heat dissipation board P to other components, if the surface is the Au layer 7, 7 or the Sn layer 11, 11, an Ag-based or Au-Sn-based paste or adhesive is preferably used. The

めっきは、電解、無電解、イオンプレーティング(IP)法等が望ましいが、めっきであれば特に限定するものではない。いずれにしても、めっきによって各金属層の厚みが上下対称で均一な層に形成され、各層が緊密に結合する。また、Cu金属層の形成については、Cuめっきの他に、Cuイオンプレーティング法を最適に用いることができる。   Plating is preferably electrolysis, electroless, ion plating (IP) method or the like, but is not particularly limited as long as it is plating. In any case, the thickness of each metal layer is formed into a uniform layer with vertical symmetry by plating, and the layers are tightly coupled. For forming the Cu metal layer, a Cu ion plating method can be optimally used in addition to Cu plating.

イオンプレーティング法は、乾式のめっきで湿式とは違い僅かな表面改質でめっき加工が可能である。Moは非常にめっきが密着しにくい金属である。面粗さを失わずにCuめっきを付ける場合は、イオンプレーティング法が最適である。この場合、Moの上にCuめっきをする際に薄膜の銅をIPで付けてから、電解若しくは無電解でCuめっきを施す工程とするので上記目的が達成される。つまり、Moの金属片の上にCu層をイオンプレーティング法により例えば0.2μm程度形成し、その上にCuめっき(電解又は無電解)で施すのが最善な方法である。無電解めっきは、電解めっきと比較してめっきの均一性が良い。めっきの効率は電解めっき>無電解>銅めっき(電解・無電解)となる。   The ion plating method can be plated with a slight surface modification, unlike dry, wet plating. Mo is a metal that is very difficult to adhere to plating. When applying Cu plating without losing surface roughness, the ion plating method is optimal. In this case, when Cu is plated on Mo, a thin film of copper is attached by IP, and then the Cu plating is performed electrolytically or electrolessly, thereby achieving the above object. That is, the best method is to form a Cu layer on the Mo metal piece by, for example, about 0.2 μm by the ion plating method, and apply Cu plating (electrolytic or electroless) thereon. Electroless plating has better plating uniformity than electrolytic plating. The plating efficiency is electrolytic plating> electroless> copper plating (electrolysis / electroless).

図1ないし図3は実施例1を示し、複合基母材2となる広い原材としては、Mo層3をCu層4,4でサンドイッチした3層構造のものを使用する(図1)。それには基母材2のCu層4,4の面を研磨機18で研磨してからNiめっきをその両面に施しNi層5,5(層厚1.0μm)を形成し、さらにその両Ni層5,5にAuめっきを施し両面がAu層7,7(層厚2μm)として形成する。めっき工程を経て広く製造されためっき原材は縦横カンティングにより細分化されて加工される。図2がこうして加工された製品としての放熱基板Pを示すが円形とは限らない。 FIG. 1 to FIG. 3 show Example 1, and a wide raw material to be a composite base material 2 is a three-layer structure in which a Mo layer 3 is sandwiched between Cu layers 4 and 4 (FIG. 1). For this purpose, the surfaces of the Cu layers 4 and 4 of the base material 2 are polished by a polishing machine 18 and then Ni plating is performed on both surfaces to form Ni layers 5 and 5 (layer thickness 1.0 μm). The layers 5 and 5 are plated with Au, and both surfaces are formed as Au layers 7 and 7 (layer thickness 2 μm). A plating raw material widely manufactured through a plating process is subdivided and processed by vertical and horizontal canting. Although FIG. 2 shows the heat dissipation board P as a product thus processed, it is not necessarily circular.

図3はLEDを搭載した使用状態を示したもので、パッケージ基板10の上に接着剤14を介して半導体搭載用放熱基板Pが搭載され、その上に接着剤16を介してLED12が搭載される。いずれも、表面がAu層7,7であるので、接着剤14,16の乗りが良く接着性が良好である。また、Au層7で反射してLED12の反射効率が良好であり、反射しなくても金属層の光の通りが良く蓄熱量が少ないという利点がある。   FIG. 3 shows a use state in which LEDs are mounted. A semiconductor mounting heat dissipation substrate P is mounted on the package substrate 10 via an adhesive 14, and the LEDs 12 are mounted thereon via an adhesive 16. The In any case, since the surfaces are the Au layers 7 and 7, the adhesives 14 and 16 are easily mounted and the adhesiveness is good. In addition, there is an advantage that the reflection efficiency of the LED 12 is reflected by the Au layer 7 and the light of the metal layer is good and the heat storage amount is small even if it is not reflected.

図4において、前記実施例に対して前記Au層7,7がその合金となっている違いがある。つまり、めっきを施すことによりAu・Sn合金層9,9として両面を形成して放熱基板Pが形成される。この実施例の場合も、Auの性質等から上記と同じ利点がある。以下においても同じである。   In FIG. 4, there is a difference that the Au layers 7 and 7 are alloys thereof with respect to the embodiment. That is, the heat dissipation substrate P is formed by forming both surfaces as Au / Sn alloy layers 9 and 9 by plating. This embodiment also has the same advantages as described above due to the nature of Au. The same applies to the following.

図5において、その放熱基板Pは、実施例1に対してそのNi層5,5がSn層11,11になっている違いがある。   In FIG. 5, the heat dissipation substrate P is different from the first embodiment in that the Ni layers 5 and 5 are Sn layers 11 and 11.

図6において、その放熱基板Pは、複合基母材2の両面にAu層7,7をさらにその上にSn層11,11が形成される。   In FIG. 6, the heat dissipation substrate P has Au layers 7 and 7 formed on both sides of the composite base material 2, and Sn layers 11 and 11 formed thereon.

図7において、その放熱基板Pは、Mo層3を合せ金属材の単一基母材1としたもので、まずその両面にCu層4,4をめっき(Cuイオンプレーティングによることもできる)を施した場合と、Mo層3の両面にNi層5,5とCu層4,4を順次めっきした場合とに分けて製造される。それぞれについて次の如くである。   In FIG. 7, the heat dissipation substrate P is a single base matrix 1 made of a metal material with the Mo layer 3 combined. First, Cu layers 4 and 4 are plated on both surfaces (also by Cu ion plating). And the case where the Ni layers 5 and 5 and the Cu layers 4 and 4 are sequentially plated on both surfaces of the Mo layer 3. Each is as follows.

前者については、両面のCu層4,4にNi層5,5を、さらにAu層7,7を順次めっきして形成して放熱基板Pを製造した。また、後者については、その両面のCu層4,4にNi層5,5、Au層7,7を順次めっきで形成して放熱基板Pを製造した。   As for the former, the Ni layers 5 and 5 and the Au layers 7 and 7 were successively formed on the Cu layers 4 and 4 on both sides, and the heat dissipation substrate P was manufactured. In the latter case, Ni layers 5 and 5 and Au layers 7 and 7 were sequentially formed on the Cu layers 4 and 4 on both sides thereof to manufacture the heat dissipation substrate P.

図8においてもMo層3を単一基母材1としたもので、この場合も、まずその両面にCu層4,4をめっき(Cuイオンプレーティングによることもできる)を施した場合と、Mo層3の両面にNi層5,5とCu層4,4を順次めっきした場合とに分けられる。それぞれについて次の如くである。   Also in FIG. 8, the Mo layer 3 is a single base matrix 1, and also in this case, the Cu layers 4 and 4 are first plated on both surfaces (also by Cu ion plating), It is divided into the case where Ni layers 5 and 5 and Cu layers 4 and 4 are sequentially plated on both surfaces of the Mo layer 3. Each is as follows.

すなわち、前者については、両面のCu層4,4の上にNi層5,5をめっきにより形成し、その上にそれぞれAu・Sn合金層9,9をめっきし、放熱基板Pの原材を形成した。また、後者については、両面のCu層4,4の上にNi層5,5をさらにその上にAu・Sn合金層9,9を形成して放熱基板Pの原材を構成した。   That is, as for the former, Ni layers 5 and 5 are formed on the Cu layers 4 and 4 on both sides by plating, and Au / Sn alloy layers 9 and 9 are plated on the Ni layers 5 and 5, respectively. Formed. In the latter case, Ni layers 5 and 5 were formed on the Cu layers 4 and 4 on both sides, and Au / Sn alloy layers 9 and 9 were further formed thereon to constitute the raw material of the heat dissipation substrate P.

図9において、Mo層3としての基母材1の両面にCu層4,4をめっきにより形成した場合と、Ni層5,5とCu層4,4を順次めっきにより形成した場合とに分けられて製造した。それぞれについてさらに次の如くである。   9, the case where the Cu layers 4 and 4 are formed on both surfaces of the base material 1 as the Mo layer 3 by plating and the case where the Ni layers 5 and 5 and the Cu layers 4 and 4 are sequentially formed by plating are divided. Manufactured. Each is further described as follows.

つまり、前者では、Cu層4,4にNi層5,5をめっきで形成し、この上にSn層11,11とAu層7,7がめっきにより形成して放熱基板Pの原材が作られる。また、後者では、Cu層4,4の上にNi層5,5を、その上にSn層11,11とAu層7,7をそれぞれめっきにより形成して放熱基板Pの原材が作られる。   In other words, in the former, the Ni layers 5 and 5 are formed on the Cu layers 4 and 4 by plating, and the Sn layers 11 and 11 and the Au layers 7 and 7 are formed thereon by plating, so that the raw material of the heat dissipation substrate P is made. It is done. In the latter case, the Ni layers 5 and 5 are formed on the Cu layers 4 and 4, and the Sn layers 11 and 11 and the Au layers 7 and 7 are formed thereon by plating, whereby the raw material of the heat dissipation substrate P is made. .

図10において、この場合も、前記と同じであって、Mo層3としての単一基母材1の両面にCu層4,4をめっきにより形成した場合と、Ni層5,5とCu層4,4を順次めっきにより形成した場合とに分けられ、それぞれについてさらにめっきが施される。   10, in this case as well, the Cu layers 4 and 4 are formed on both surfaces of the single base material 1 as the Mo layer 3 by plating, and the Ni layers 5 and 5 and the Cu layer. 4 and 4 are sequentially formed by plating, and further plating is performed for each.

前者の場合であると、Cu層4,4にNi層5,5をめっきにより形成し、その上にAu層7,7とSn層11,11を順次めっきにより形成して放熱基板Pの原材が形成される。また、後者であると、Cu層4,4の上にNi層5,5をめっきにより形成し、Ni層5,5の上にAu層7,7とSn層11,11が順次めっきにより形成して放熱基板Pの原材が作られる。   In the former case, the Ni layers 5 and 5 are formed on the Cu layers 4 and 4 by plating, and the Au layers 7 and 7 and the Sn layers 11 and 11 are sequentially formed on the Ni layers 5 and 5 by plating. A material is formed. In the latter case, Ni layers 5 and 5 are formed on the Cu layers 4 and 4 by plating, and Au layers 7 and 7 and Sn layers 11 and 11 are sequentially formed on the Ni layers 5 and 5 by plating. Thus, the raw material of the heat dissipation board P is made.

P 半導体搭載用放熱基板
1 単一基母材
2 複合基母材
3 Mo層
4 Cu層
5 Ni層
7 Au層
9 Au・Sn合金層
11 Sn層
P Semiconductor Heat Dissipation Board 1 Single Base Base Material 2 Composite Base Base Material 3 Mo Layer 4 Cu Layer 5 Ni Layer 7 Au Layer 9 Au / Sn Alloy Layer 11 Sn Layer

Claims (8)

合せ金属材からなる基母材の両面に1以上の金属層をめっきにより上下対称の配置となるように形成することを特徴とする半導体搭載用放熱基板の製造方法。   A method for manufacturing a semiconductor-mounted heat dissipation substrate, wherein one or more metal layers are formed on both surfaces of a base metal material made of a laminated metal material so as to have a vertically symmetrical arrangement by plating. 基母材が、中心のMo層の両面にCu層を形成した複合基母材、若しくはMo層の単一基母材であることを特徴とする請求項1記載の半導体搭載用放熱基板の製造方法。   2. A semiconductor-mounted heat dissipation substrate according to claim 1, wherein the base material is a composite base material in which Cu layers are formed on both sides of the central Mo layer, or a single base material of the Mo layer. Method. 前記複合基母材の両面のCu層に、それぞれNi層とAu層とを順次めっきにより形成することを特徴とする請求項2記載の半導体搭載用放熱基板の製造方法。   3. The method for manufacturing a semiconductor-mounted heat dissipation substrate according to claim 2, wherein a Ni layer and an Au layer are sequentially formed on the Cu layers on both surfaces of the composite base material by plating. 前記複合基母材の両面のCu層の上にNi層をめっきにより形成し、さらにその上に、Au層若しくはAu・Sn合金層をめっきにより形成することを特徴とする請求項2記載の半導体搭載用放熱基板の製造方法。   3. The semiconductor according to claim 2, wherein an Ni layer is formed on the Cu layers on both sides of the composite base material by plating, and an Au layer or an Au / Sn alloy layer is further formed thereon by plating. Manufacturing method of mounting heat dissipation board. 前記複合基母材の両面のCu層4,4の上にSn層とAu層とをいずれかを外面になるようそれぞれめっきにより順次形成したことを特徴とする請求項2記載の半導体搭載用放熱基板の製造方法。   3. The heat radiation for mounting a semiconductor according to claim 2, wherein one of an Sn layer and an Au layer is sequentially formed on the Cu layers (4, 4) on both surfaces of the composite base material by plating so as to be an outer surface. A method for manufacturing a substrate. Mo層の単一基母材の両面にCu層をめっきにより形成し、Cu層の上にNi層をめっきにより形成し、さらに両Ni層の上にAu・Sn合金層をめっきで形成するか、若しくは、Au層とSn層とをいずれかが外側になるようにめっきにより形成することを特徴とする請求項2記載の半導体搭載用放熱基板の製造方法。   Whether a Cu layer is formed by plating on both surfaces of a single base material of the Mo layer, a Ni layer is formed by plating on the Cu layer, and an Au / Sn alloy layer is formed by plating on both Ni layers 3. The method for manufacturing a semiconductor-mounted heat dissipation substrate according to claim 2, wherein the Au layer and the Sn layer are formed by plating so that one of them is on the outside. Mo層の単一基母材の両面にNi層とCu層とをそれぞれめっきにより形成し、さらに、Ni層の上にAu層若しくはAu・Sn合金層をめっきで形成することを特徴とする請求項2記載の半導体搭載用放熱基板の製造方法。   The Ni layer and the Cu layer are respectively formed on both surfaces of the single base material of the Mo layer by plating, and further, the Au layer or the Au / Sn alloy layer is formed on the Ni layer by plating. Item 3. A method for manufacturing a semiconductor-mounted heat dissipation board according to Item 2. Mo層の単一基母材の両面にNi層とCu層とをそれぞれめっきにより形成し、さらに、Cu層の上にNi層をめっきにより形成し、Ni層の上に、Au層とSn層とをいずれか外側になるように順次めっきにより形成することを特徴とする請求項2記載の半導体搭載用放熱基板の製造方法。   An Ni layer and a Cu layer are formed by plating on both surfaces of a single base material of the Mo layer, and further, an Ni layer is formed by plating on the Cu layer, and an Au layer and an Sn layer are formed on the Ni layer. The method for manufacturing a semiconductor mounting heat dissipation board according to claim 2, wherein the first and second electrodes are sequentially plated so as to be on the outer side.
JP2010128721A 2010-06-04 2010-06-04 Manufacturing method of heat dissipation board for semiconductor mounting Active JP5522786B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010128721A JP5522786B2 (en) 2010-06-04 2010-06-04 Manufacturing method of heat dissipation board for semiconductor mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010128721A JP5522786B2 (en) 2010-06-04 2010-06-04 Manufacturing method of heat dissipation board for semiconductor mounting

Publications (2)

Publication Number Publication Date
JP2011254044A true JP2011254044A (en) 2011-12-15
JP5522786B2 JP5522786B2 (en) 2014-06-18

Family

ID=45417713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010128721A Active JP5522786B2 (en) 2010-06-04 2010-06-04 Manufacturing method of heat dissipation board for semiconductor mounting

Country Status (1)

Country Link
JP (1) JP5522786B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016111206A1 (en) * 2015-01-07 2016-07-14 新日鉄住金マテリアルズ株式会社 Heat dissipation substrate
KR101902254B1 (en) * 2017-07-10 2018-10-01 주식회사 제이티엔유 Heat radiating substrate for high power LED
KR20190006936A (en) * 2018-08-30 2019-01-21 주식회사 제이티엔유 Heat radiating substrate for high power LED
KR101918915B1 (en) * 2017-07-12 2019-02-11 (주)엠씨피 Manufacturing method of high power LED radiator plate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152961A (en) * 1978-05-24 1979-12-01 Hitachi Ltd Semiconductor device
JPH11340381A (en) * 1998-05-21 1999-12-10 Nec Corp Semiconductor device and its manufacture
JP2004259770A (en) * 2003-02-24 2004-09-16 Kyocera Corp Ceramic substrate for thermoelectric exchange module

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152961A (en) * 1978-05-24 1979-12-01 Hitachi Ltd Semiconductor device
JPH11340381A (en) * 1998-05-21 1999-12-10 Nec Corp Semiconductor device and its manufacture
JP2004259770A (en) * 2003-02-24 2004-09-16 Kyocera Corp Ceramic substrate for thermoelectric exchange module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016111206A1 (en) * 2015-01-07 2016-07-14 新日鉄住金マテリアルズ株式会社 Heat dissipation substrate
KR101902254B1 (en) * 2017-07-10 2018-10-01 주식회사 제이티엔유 Heat radiating substrate for high power LED
KR101918915B1 (en) * 2017-07-12 2019-02-11 (주)엠씨피 Manufacturing method of high power LED radiator plate
KR20190006936A (en) * 2018-08-30 2019-01-21 주식회사 제이티엔유 Heat radiating substrate for high power LED
KR101976627B1 (en) 2018-08-30 2019-08-28 주식회사 제이티엔유 Heat radiating substrate for high power LED

Also Published As

Publication number Publication date
JP5522786B2 (en) 2014-06-18

Similar Documents

Publication Publication Date Title
TWI695778B (en) Bonded body, power module substrate with heat sink, heat sink, method of producing bonded body, method of producing power module substrate with heat sink and method of producing heat sink
JP5807935B1 (en) Heat dissipation board and semiconductor module using it
TWI787554B (en) Carbonaceous member with metal layer, and thermal conduction plate
JP2019502251A (en) Heat dissipation plate material for high output elements
WO2011058849A1 (en) Substrate for mounting light-emitting element and method for producing same
JP2011254044A (en) Method for producing a heat dissipation substrate for mounting in semiconductor
TWI750332B (en) Substrate for power module with heat sink attached
JP2008192823A (en) Manufacturing apparatus and manufacturing method for circuit board, and cushion sheet used for the manufacturing method
JP2022169595A (en) Substrate for mounting electronic element and electronic device
WO2015104954A1 (en) Electronic circuit device
JP2011071260A (en) Laminating material and manufacturing method thereof, and insulated laminating material and manufacturing method thereof
TWI463710B (en) Mrthod for bonding heat-conducting substraye and metal layer
WO2012001767A1 (en) Process for producing radiating substrate for semiconductor mounting
TWI407536B (en) Method for manufacturing heat dissipation bulk of semiconductor device
JP2012109288A (en) Wafer for led
JP2011082502A (en) Substrate for power module, substrate for power module with heat sink, power module, and method of manufacturing substrate for power module
JP2014192272A (en) Metal substrate for LED
JP7039933B2 (en) Bond, Insulated Circuit Board, Insulated Circuit Board with Heat Sink, Heat Sink, and Joined Body Manufacturing Method, Insulated Circuit Board Manufacturing Method, Heat Sinked Insulated Circuit Board Manufacturing Method, Heat Sink Manufacturing Method
JP6780561B2 (en) Manufacturing method of joint, manufacturing method of insulated circuit board, and joint, insulated circuit board
JP2017165629A (en) Method for manufacturing joined body and method for manufacturing substrate for power module
TW200818415A (en) LTCC substrate structure
WO2024014532A1 (en) Multilayer assembly, semiconductor device using same, and method for manufacturing same
TWI500190B (en) A wafer used for led and manufacturing method of the wafer
CN103840043A (en) LED-used wafer and manufacturing method thereof
JP6396703B2 (en) Manufacturing method of heat dissipation component for semiconductor element

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130409

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140109

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140206

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140311

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140402

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140404

R150 Certificate of patent or registration of utility model

Ref document number: 5522786

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250