JP2011250646A - Rectification circuit and control circuit of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a rectification circuit which does not cause low forward voltage drop nor counterflow.SOLUTION: In a rectification circuit, when a potential at one end of a current path of a fourth semiconductor element is identical to or exceeds a potential at one end of a current path of a second semiconductor element, the current path of a first semiconductor element and the second semiconductor element becomes conductive, and a potential at a fifth control end to which the potential at one end of the current path of the first semiconductor element is transferred drops, with the current path of a fifth semiconductor element being non-conductive. If the potential at one end of the current path of the fourth semiconductor element is less than the potential at one end of the current path of the second semiconductor element, the current path of the first semiconductor element becomes non-conductive, and the potential at the fifth control end to which the potential at one end of the current path of the first semiconductor element is transferred rises, allowing one end of the current path of the fifth semiconductor element to which the current path of the fifth semiconductor element is conductive as well as the other end of the current path of the fifth semiconductor element to act as a rectification action current path.

Description

  The present invention relates to a diode circuit, an ORingFET diode application circuit, and the like realized by a low-loss rectifier circuit in which an FET is highly controlled, and to a diode circuit suitable for a rectifier circuit such as a switching power supply to which the diode circuit is applied.

In a conventional rectifying diode, a normal PN-junction silicon diode has a forward voltage drop of about 0.6 V to 0.7 V. In recent years, a low voltage drive device used in an information processing apparatus. In, the power loss is large.
Even in the case of a Schottky barrier diode having a relatively small forward voltage drop, the forward voltage drop is about 0.4 V to 0.5 V, and the magnitude of power loss is not significantly different from that of a silicon diode. Further, since this diode has a small reverse withstand voltage, it is not suitable for high voltage rectification.
In the OR diode circuit, a DC power source (for example, a DC / DC converter) having a small power capacity is connected in parallel by a diode to obtain a large power (a large current), or similarly a device connected in parallel is used as a spare device. In other words, a plurality of power supply outputs are connected in parallel through diodes.
Recently, in order to suppress power loss (high heat generation) of information processing devices, these devices are driven at a low voltage. Therefore, since a DC power supply having a low output voltage (12 V is becoming standard) is used, when a normal PN junction silicon diode or Schottky barrier diode is used for the OR diode circuit, the order of the DC power supply voltage is reduced. The rate of directional voltage drop is large and the power loss is large. Therefore, a low-loss rectifier circuit using a FET with a low conduction resistance can be considered.
Further, when a FET (a field-effect transistor) used in a synchronous rectifier circuit having a rectifying action is controlled, a complicated circuit is obtained. A switching power supply diode used for the same purpose is required to have a high frequency response.

JP 2004-320873 A

The operation of Patent Document 1 is as follows.
(1) When the source potential of the FET 1 is lower than the drain potential or when the terminal 12 is open, the emitter potential of the bipolar transistor 3 is lower than the base potential, so that the bipolar transistor 3 is non-conductive. The collector potential of the transistor 3 is high and the FET 1 becomes conductive.
(2) When the emitter potential of the bipolar transistor 3 is higher than the base potential, the bipolar transistor 3 becomes conductive. Therefore, the collector potential of the bipolar transistor 3 is lowered and the FET 1 becomes non-conductive.
(3) When the emitter potential of the bipolar transistor 3 further increases, the emitter potential of the bipolar transistor 3 in the path of the emitter of the bipolar transistor 3 → the base → the resistance element 9 → the resistance element 6 → the base of the bipolar transistor 2 If a base is applied and the diode 4 is not inserted between the base and emitter of the bipolar transistor 2, the base of the bipolar transistor 2 becomes a high potential and is destroyed.
(4) In the above (3), since the diode 4 is present, the bipolar transistor 2 is not destroyed, but the diode 4 becomes conductive (equivalent to current flowing from the terminal 12 to the terminal 11) and does not function as a backflow prevention circuit.
(5) Application of potential by the resistance element 7 does not function. That is, the circuit of the resistance element 7 may be open.
As described above, the operation of Patent Document 1 is basically different from the operation of the present invention described later.

In view of the above situation, the present invention is a rectifier circuit that reliably prevents backflow, and realizes an ORingFET diode application circuit, a diode circuit suitable for a switching power supply circuit, and the like.

In order to achieve the above object, the present invention has the following configuration.
(1) A rectifier circuit according to claim 1 is:
A first semiconductor element having a first control end and having one end and the other end of a current path;
A second semiconductor element having a second control end and having one end and the other end of a current path;
A third semiconductor element having a third control end and having one end and the other end of a current path;
A fourth semiconductor element having a fourth control end and having one end and the other end of a current path;
A fifth semiconductor element having a fifth control end and having one end and the other end of a current path;
A first resistance element and a second resistance element;
An external bias potential is applied to the first control end, the second control end, the third control end, and the fourth control end via the second resistance element,
The one end of the current path of the first semiconductor element is configured to flow a current supplied from an external DC power source through the first resistance element,
The other end of the current path of the second semiconductor element is configured such that a current supplied from an external DC power source flows through the other end of the first semiconductor element.
The one end of the current path of the third semiconductor element is configured to flow a current supplied from an external DC power source through the second resistance element,
The other end of the current path of the fourth semiconductor element is configured so that a current supplied from an external DC power source flows through the other end of the third semiconductor element.
A potential at one end of the current path of the second semiconductor element is configured to be transmitted to one end of the current path of the fifth semiconductor element;
The potential of one end of the current path of the fourth semiconductor element is configured to be transmitted to the other end of the current path of the fifth semiconductor element,
When the potential of one end of the current path of the fourth semiconductor element is equal to or exceeds the potential of one end of the current path of the second semiconductor element, the current paths of the first semiconductor element and the second semiconductor element are conductive, The potential of the fifth control terminal to which the potential of one end of the current path of the first semiconductor element is transmitted decreases, and the current path of the fifth semiconductor element is non-conductive,
When the potential of one end of the current path of the fourth semiconductor element is less than the potential of one end of the current path of the second semiconductor element, the current path of the first semiconductor element is non-conductive, and the current of the first semiconductor element The potential of the fifth control terminal to which the potential of one end of the path is transmitted rises, and the one end of the current path of the fifth semiconductor element and the current path of the fifth semiconductor element in which the current path of the fifth semiconductor element is conducted The other end of the rectifier is a rectifying current path.
(2) The rectifier circuit according to claim 2 is the rectifier circuit according to claim 1,
A parallel connection circuit of a constant voltage element and a first capacitor element is inserted between one end of the first semiconductor element and the fifth control end, the connection portion of the parallel connection circuit and the fifth control end, A series connection circuit of a rectifying element and a third resistance element is inserted between one end of the second semiconductor element, and the constant voltage element is in a direction opposite to the potential polarity supplied by the first resistance element, The element is characterized in that it is forward with the potential polarity supplied by the first resistance element.
(3) The rectifier circuit according to claim 3 is the rectifier circuit according to claim 1 or 2,
A second capacitor element is inserted between one end and the other end of the current path of the second semiconductor element.
(4) The rectifier circuit according to claim 4 is the rectifier circuit according to any one of claims 1 to 3,
And a sixth semiconductor element having a sixth control end and having one end and the other end of a current path, wherein the sixth semiconductor element is provided between one end of the first semiconductor element and one end of the second semiconductor element. And the other end of the sixth semiconductor element are inserted, and a potential is applied to the sixth control terminal to make the sixth semiconductor element conductive or non-conductive.
(5) A control circuit according to claim 5 is:
A first semiconductor element having a first control end and having one end and the other end of a current path;
A second semiconductor element having a second control end and having one end and the other end of a current path;
A third semiconductor element having a third control end and having one end and the other end of a current path;
A fourth semiconductor element having a fourth control end and having one end and the other end of a current path;
A first resistance element and a second resistance element;
An external bias potential is applied to the first control end, the second control end, the third control end, and the fourth control end via the second resistance element,
The one end of the current path of the first semiconductor element is configured to flow a current supplied from an external DC power source through the first resistance element,
The other end of the current path of the second semiconductor element is configured such that a current supplied from an external DC power source flows through the other end of the first semiconductor element.
The one end of the current path of the third semiconductor element is configured to flow a current supplied from an external DC power source through the second resistance element,
The other end of the current path of the fourth semiconductor element is configured so that a current supplied from an external DC power source flows through the other end of the third semiconductor element.
The potential of one end of the current path of the second semiconductor element is configured to be transmitted to one end of the current path of the fifth semiconductor element existing outside,
The potential of one end of the current path of the fourth semiconductor element is configured to be transmitted to the other end of the current path of the fifth semiconductor element existing outside,
When the potential of one end of the current path of the fourth semiconductor element is equal to or exceeds the potential of one end of the current path of the second semiconductor element, the current paths of the first semiconductor element and the second semiconductor element are conductive, The electric potential at one end of the current path of the first semiconductor element is transmitted, the electric potential at the fifth control terminal of the fifth semiconductor element existing outside is lowered, and the electric current path of the fifth semiconductor element existing outside is not Continuity,
When the potential of one end of the current path of the fourth semiconductor element is less than the potential of one end of the current path of the second semiconductor element, the current path of the first semiconductor element is non-conductive, and the current of the first semiconductor element The potential of the fifth control terminal of the fifth semiconductor element existing outside to which the potential of one end of the path is transmitted rises, and the current path of the fifth semiconductor element existing outside the second semiconductor element existing outside the conductor is conducted. One end of the current path of the fifth semiconductor element and the other end of the current path of the fifth semiconductor element existing outside the fifth semiconductor element are controlled as a rectifying current path.
(6) The control circuit according to claim 6 is the control circuit according to claim 5,
A parallel connection circuit of a constant voltage element and a first capacitance element is inserted between one end of the first semiconductor element and a fifth control terminal of the fifth semiconductor element existing outside, and the parallel connection circuit and the first 5 A series connection circuit of a rectifying element and a third resistance element is inserted between the connection portion of the control end and one end of the second semiconductor element, and the constant voltage element is a potential supplied by the first resistance element. The rectifying element has a reverse direction to the polarity, and the rectifying element has a forward direction to the potential polarity supplied by the first resistance element.
(7) The control circuit according to claim 7 is the control circuit according to claim 5 or 6,
A second capacitor element is inserted between one end and the other end of the current path of the second semiconductor element.
(8) The control circuit according to claim 8 is the control circuit according to any one of claims 5 to 7,
And a sixth semiconductor element having a sixth control end and having one end and the other end of a current path, wherein the sixth semiconductor element is provided between one end of the first semiconductor element and one end of the second semiconductor element. And the other end of the sixth semiconductor element are inserted, and a potential is applied to the sixth control terminal to make the sixth semiconductor element conductive or non-conductive.
(9) The rectifier circuit according to claim 9 is the rectifier circuit according to any one of claims 1 to 4,
The first semiconductor element, the second semiconductor element, the third semiconductor element, the fourth semiconductor element, and the fifth semiconductor element are N-channel FETs,
One end of the current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a drain, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is a source,
One end of the current path of the fifth semiconductor element is a source and the other end is a drain;
When the sixth semiconductor element is included, the sixth semiconductor element is an N-channel FET, and one end of the current path of the sixth semiconductor element is a drain and the other end is a source.
(10) The rectifier circuit according to claim 10 is the rectifier circuit according to any one of claims 1 to 4,
The first semiconductor element, the second semiconductor element, the third semiconductor element, the fourth semiconductor element, and an NPN bipolar transistor;
One end of a current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a collector, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is an emitter,
The fifth semiconductor element is an N-channel FET, and one end of the fifth semiconductor element current path is a source and the other end is a drain.
When the sixth semiconductor element is included, the sixth semiconductor element is an NPN bipolar transistor, and one end of the current path of the sixth semiconductor element is a collector and the other end is an emitter.
(11) The rectifier circuit according to claim 11 is the rectifier circuit according to any one of claims 1 to 4,
The first semiconductor element, the second semiconductor element, the third semiconductor element, the fourth semiconductor element, and the fifth semiconductor element are P-channel FETs;
One end of the current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a drain, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is a source,
One end of the current path of the fifth semiconductor element is a source and the other end is a drain;
When the sixth semiconductor element is included, the sixth semiconductor element is a P-channel FET, and one end of the current path of the sixth semiconductor element is a drain and the other end is a source.
(12) The rectifier circuit according to claim 12 is the rectifier circuit according to any one of claims 1 to 4,
The first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element are PNP-type bipolar transistors,
One end of a current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a collector, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is an emitter,
The fifth semiconductor element is a P-channel FET;
One end of the current path of the fifth semiconductor element is a source and the other end is a drain;
When the sixth semiconductor element is included, the sixth semiconductor element is a PNP bipolar transistor, and one end of the current path of the sixth semiconductor element is a collector and the other end is an emitter.
(13) The control circuit according to claim 13 is the control circuit according to any one of claims 5 to 8,
The first semiconductor element, the second semiconductor element, the third semiconductor element, the fourth semiconductor element, and the fifth semiconductor element existing outside are N-channel FETs,
One end of the current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a drain, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is a source,
One end of the current path of the fifth semiconductor element existing outside is a source and the other end is a drain,
When the sixth semiconductor element is included, the sixth semiconductor element is an N-channel FET, and one end of the current path of the sixth semiconductor element is a drain and the other end is a source.
(14) The control circuit according to claim 14 is the control circuit according to any one of claims 5 to 8,
The first semiconductor element, the second semiconductor element, the third semiconductor element, the fourth semiconductor element, and an NPN bipolar transistor;
One end of a current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a collector, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is an emitter,
The fifth semiconductor element existing outside is an N-channel FET, one end of the fifth semiconductor element current path is a source, and the other end is a drain.
When the sixth semiconductor element is included, the sixth semiconductor element is an NPN bipolar transistor, and one end of the current path of the sixth semiconductor element is a collector and the other end is an emitter.
(15) A control circuit according to claim 15 is the control circuit according to any one of claims 5 to 8,
The first semiconductor element, the second semiconductor element, the third semiconductor element, the fourth semiconductor element, and the fifth semiconductor element existing outside are P-channel FETs,
One end of the current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a drain, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is a source,
One end of the current path of the fifth semiconductor element existing outside is a source and the other end is a drain,
When the sixth semiconductor element is included, the sixth semiconductor element is a P-channel FET, and one end of the current path of the sixth semiconductor element is a drain and the other end is a source.
(16) A control circuit according to claim 16 is the control circuit according to any one of claims 5 to 8,
The first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element are PNP-type bipolar transistors,
One end of a current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a collector, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is an emitter,
The fifth semiconductor element present outside is a P-channel FET,
One end of the current path of the fifth semiconductor element existing outside is a source and the other end is a drain,
When the sixth semiconductor element is included, the sixth semiconductor element is a PNP bipolar transistor, and one end of the current path of the sixth semiconductor element is a collector and the other end is an emitter.

(A) Since the rectifier circuit according to the present invention uses a semiconductor element having a control terminal for the rectification current path, the forward voltage drop due to rectification is extremely small, and the power loss is extremely low.
(B) The rectifier circuit according to the present invention uses a semiconductor element having a control end for a rectification current path, the control circuit compares the potentials at both ends of the rectification current path, and the conduction / non-conduction of the current path of the semiconductor element. Therefore, there is no backflow of current in the rectified current path.
(C) Since the control circuit according to the present invention controls the rectification current path by a combination of semiconductor elements having control ends, there is no backflow of current from the other end of the rectification current path to one end.
(D) The control circuit according to the present invention can cut off the rectification current path at high speed by additionally including the first capacitor element and the second capacitor element.

These are the circuit block diagrams which show 1st Embodiment of the rectifier circuit by this invention, and a control circuit. These are the circuit block diagrams which show 2nd Embodiment of the rectifier circuit by this invention, and a control circuit. These are the circuit block diagrams which show 3rd Embodiment of the rectifier circuit by this invention, and a control circuit.

(1) First Embodiment (1-1) Circuit Configuration FIG. 1 shows a rectifier circuit according to a first embodiment of the present invention and a fifth semiconductor element constituting a rectifier current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls N channel type FETQ5.
In FIG. 1, a portion surrounded by a broken line is the control circuit constituting a part of the rectifier circuit. The control circuit includes an N-channel FET Q1 that is a first semiconductor element, an N-channel FET Q2 that is a second semiconductor element, an N-channel FET Q3 that is a third semiconductor element, an N-channel FET Q4 that is a fourth semiconductor element, The resistor element R1 is a first resistor element and the resistor element R2 is a second resistor element.

The circuit configuration of the present invention will be described below with reference to FIG.
There is a terminal T1 (corresponding to an anode referred to as a diode) for inputting the positive potential of the DC power supply, and a terminal T2 (corresponding to a cathode referred to as a diode) for outputting the positive potential of the DC power supply.
The terminal T1 is connected to the source S of an N-channel FET Q5, which is a fifth semiconductor element, and the drain D of the FET Q5 is connected to the terminal T2. The current flows from the terminal T1 to the terminal T2, that is, from the source S to the drain D of the FET Q5. The current from the drain D to the source S is controlled to be cut off.

Further, a drain D that is one end of an N-channel FET Q2 that is a second semiconductor element is connected to the terminal T1, and an N-channel FET Q4 drain D that is a fourth semiconductor element is connected to the terminal T2.

The source which is the other end of the N channel type FET Q1 is connected to the source which is the other end of the N channel type FET Q2, and the source which is the other end of the N channel type FET Q3 is connected to the source which is the other end of the N channel type FET Q4. Has been.
A drain D that is one end of the FET Q1 is connected to a fifth control terminal of an N-channel FET Q5 that is a fifth semiconductor element.

The gate G of the first control terminal of the FET Q1, the second control terminal of the FET Q2, the third control terminal of the FET Q3, and the fourth control terminal of the FET Q4 is connected, and this connection is connected to the drain D which is one end of the FET Q3. Has been.
The drain D, which is one end of the FET Q3, is connected to one end of a resistance element R2, which is a second resistance element, and the other end of the resistance element R2 supplies a bias potential to the gate G of the FET Q1, FET Q2, FET Q3, and FET Q4. It is connected to a terminal T3 to which an external DC power supply is applied.

The drain D, which is one end of the FET Q1, is connected to one end of the resistance element R1, which is the first resistance element, and the other end of the resistance element R1 is connected to the drain D, which is one end of the FET Q1, and the source S, which is the other end of the FET Q2. Is connected to a terminal T3 for applying.
In the claims, the term “externally present” is used in the claims that describe the control circuit. This means that the corresponding items are not included in the claims, and are specific. Specifically, a fifth semiconductor element is shown. This is similarly cited from other embodiments.

(1) First Embodiment (1-2) Circuit Operation The circuit operation of the rectifier circuit and the control circuit according to the first embodiment of the present invention will be described with reference to FIG.
A current path from the source to the drain of the FET Q5 is a rectification current path.
The rectifier circuit in the circuit of FIG. 1 of the present invention comprises a diode having the source (terminal T1) of the FET Q5 as an anode and the drain (terminal T2) of the FET Q5 as a cathode, and the source potential of the FET Q5 and the drain potential of the FET Q5 are The control circuit compares and controls the potential applied to the gate G of the FET Q5, and controls conduction / non-conduction of the FET Q5.

In the description of the circuit operation of the present invention, the potential of each element is the drain potential of the FET Q2 as the reference potential (= potential of the terminal T1). Each element operates with a DC positive potential applied to the terminal T3.
Although it is not necessary to ground the drain D of the FET Q2, when the drain D of the FET Q2 is grounded, the potential of the drain D becomes the ground potential.

One end of an external DC power supply for external load operation is connected to the terminal T1, and one end of the external load is connected to the terminal T2. Although not shown in the circuit of FIG. 1, the other end of the external DC power supply and the other end of the external load are connected by another current path, and the external DC power supply and the external load are connected. Configure the current path.
In the description of the present invention, one end of the external DC power source has a positive potential and the other end of the external DC power source has a negative potential.

(1-2-1) Operation for turning off the FET Q5 When the drain D of the FET Q4 is open, no current flows through the current paths of the FET Q3 and the FET Q4. Therefore, no current flows through the resistance element R2, the drain potential of the FET Q3 is the same as the potential of the terminal T3, the gate potentials of the FET Q1 and FET Q2 are also the same potential as the drain potential of the FET Q3, and the gate potentials of the FET Q1 and FET Q2 Are applied with a potential sufficient to make the FETs Q1 and Q2 conductive, and the FETs Q1 and Q2 are conductive.

  If FETQ1 and FETQ2 are conductive, the drain potential of FETQ1 is approximately 0V, the potential of the fifth control terminal of FETQ5 to which this potential is applied is also approximately 0V, and FETQ5 is nonconductive.

At this time, no current flows from the drain D of the FET Q5 to the source S of the FET Q5.
Accordingly, the circuit of FIG. 1 operates with the terminal T1 as the anode of the diode and the terminal T2 as the cathode of the diode.

When the terminal T1 and the terminal T2 are at the same potential (the drain D of the FET Q2 and the drain D of the FET Q4 are at the same potential, and the source S of the FET Q5 and the drain D of the FET Q5 are the same), This means that T1 and the terminal T2 are at the same potential, but even when the FET Q5 is non-conductive, a current flows from the terminal T3 through the path of the resistance element R2, FET Q3, FET Q4, and terminal T2.

The resistance value r2 of the resistance element R2 is small and a large amount of current flows through the resistance element R2, but the voltage drop due to the resistance value r2 is small.
The resistance value r1 of the resistance element R1 is larger than the resistance value r2, and the current flowing through the resistance element R2 is small, but the voltage drop due to the resistance value r1 is large.
The setting of the resistance value r1 and the resistance value r2 depends on the threshold voltage of the gate G of the FETQ1, FETQ2, FETQ3, and FETQ4 that are the first to fourth control terminals at which the FETQ1, FETQ2, FETQ3, and FETQ4 start to conduct. However, when the FETQ1, FETQ2, FETQ3, and FETQ4 have the same characteristics, the resistance value r1> the resistance value r2 is set.
It is preferable from the viewpoint of temperature characteristics that the FETs Q1 to Q4 have the same characteristics.

Although depending on the setting of the resistance value r2 and the characteristics of the FET Q3, since the drain D of the FET Q3 and the gate G of the FET Q3 are connected, negative feedback is applied from the drain D of the FET Q3 to the gate G of the FET Q3. The gate potential is balanced to be around 2V. Therefore, the FET Q3 is in a conductive state. Note that a potential exceeding 2 V is applied to the terminal T3.

Since the FET Q4 is grounded at the drain, the gate potential becomes conductive at about 0.5V, but a potential of about 2V similar to the FET Q3 is applied to the gate G of the FET Q4, and the FET Q4 is conductive.

The FET Q1 and FET Q2 are also in a conductive state to which a gate potential is applied in the same manner as the FET Q3 and FET Q4. Therefore, the drain potential that is one end of the FET Q1 is approximately 0 V, the potential of the fifth control terminal of the FET Q5 to which this potential is applied is also approximately 0 V, and the FET Q5 is non-conductive.

(1-2-2) Operation for making FET Q5 conductive When the drain potential of FET Q5 falls below the source potential of FET Q5, the drain potential of FET Q4 connected to the drain of FET Q5 also falls, and the gate potential of FET Q4 also falls.

  The potential at which the drain potential of the FET Q5 is lower than the source potential of the FET Q5 may be about several mV to several tens of mV. However, the FET Q5 body diode causes the drain potential of the FET Q5 to exceed about 0.6 V from the source potential of the FET Q5. There is no.

When the drain potential of the FET Q4 is lowered, the gate potential of the FET Q4 is also lowered, and the gate potential of the FET Q1 having the same potential as the FET Q4 gate potential is also lowered.
Therefore, the FET Q1 becomes non-conductive. Even if the gate potential of the FET Q1 drops from about 2V to about several mV, the FET Q1 becomes non-conductive.

When the FET Q1 is turned off, no current flows through the resistance element R1 even if the FET Q2 is turned on by the body diode.
Therefore, the drain potential of the FET Q1 and the potential of one end of the resistance element R1 are the same as the potential of the terminal T3.

  For this reason, the gate potential of the FET Q5 becomes the same potential as the potential of the terminal T3, and the FET Q5 becomes conductive.

When the FET Q5 becomes conductive, a current flows from the source to the drain of the FET Q5, that is, from the terminal T1 to the terminal T2.
The source S of the FET Q5 constitutes the anode of the diode, and the drain of the FET Q5 constitutes the cathode of the diode.

Even if the gate potential of the FET Q1 decreases and the FET Q1 becomes non-conductive, the FETs Q3 and Q4 are conductive.
The gate potentials of FETQ1, FETQ2, FETQ3, and FETQ4 as seen from the drain potential of FETQ2 (reference potential of the control circuit) are the same.
Therefore, the gate potentials of the FETs Q1 to Q4 all decrease from the reference potential.

However, since the drain potential of the FET Q4 is lowered, the source potential of the FET Q4 is also lowered, the source potential of the FET Q3 is the same as the source potential of the FET Q4, and the gate potential of the FET Q3 with respect to the source potential of the FET Q3 remains unchanged. (Does not drop.)
Accordingly, since the gate potential of the FET Q3 is relatively higher than the gate potential of the FET Q1, the FET Q3 is conductive and the FET Q1 is non-conductive.

(2) Second Embodiment (2-1) Circuit Configuration FIG. 2 shows a rectifier circuit according to a second embodiment of the present invention and a fifth semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls N channel type FETQ5.
In FIG. 2, the portion surrounded by a broken line is the control circuit constituting a part of the rectifier circuit. The control circuit includes an NPN bipolar transistor Q1 as a first semiconductor element, an NPN bipolar transistor Q2 as a second semiconductor element, an NPN bipolar transistor Q3 as a third semiconductor element, an NPN bipolar transistor Q4 as a fourth semiconductor element, The resistor element R1 is a first resistor element and the resistor element R2 is a second resistor element.

The circuit configuration of the present invention will be described below with reference to FIG.
There is a terminal T1 (corresponding to an anode referred to as a diode) for inputting the positive potential of the DC power supply, and a terminal T2 (corresponding to a cathode referred to as a diode) for outputting the positive potential of the DC power supply.
The terminal T1 is connected to the source S of an N-channel FET Q5, which is a fifth semiconductor element, and the drain D of the FET Q5 is connected to the terminal T2. The current flows from the terminal T1 to the terminal T2, that is, from the source S to the drain D of the FET Q5. The current from the drain D to the source S is controlled to be cut off.

Further, a collector C that is one end of an NPN bipolar transistor Q2 that is a second semiconductor element is connected to the terminal T1, and an NPN bipolar transistor Q4 collector C that is a fourth semiconductor element is connected to the terminal T2.

The emitter E which is the other end of the NPN bipolar transistor Q1 is connected to the emitter E which is the other end of the NPN bipolar transistor Q2, and the other end of the NPN bipolar transistor Q3 is connected to the emitter E which is the other end of the NPN bipolar transistor Q4. Emitter E is connected.
The collector C which is one end of the NPN bipolar transistor Q1 is connected to the fifth control terminal of the N-channel FET Q5 which is the fifth semiconductor element.

The base B which is the first control terminal of the NPN bipolar transistor Q1, the second control terminal of the NPN bipolar transistor Q2, the third control terminal of the NPN bipolar transistor Q3, and the fourth control terminal of the NPN bipolar transistor Q4 is connected. This part is connected to the collector C which is one end of the NPN bipolar transistor Q3.
The collector C, which is one end of the NPN bipolar transistor Q3, is connected to one end of a resistance element R2 as a second resistance element. The other end of the resistance element R2 is connected to the NPN bipolar transistor Q1, the NPN bipolar transistor Q2, and the NPN bipolar transistor. Q3 and NPN bipolar transistor Q4 are connected to terminal T3 to which an external DC power supply for supplying a bias potential is applied to base B of NPN bipolar transistor Q4.

The collector C, which is one end of the NPN bipolar transistor Q1, is connected to one end of the resistance element R1, which is the first resistance element, and the other end of the resistance element R1 is the collector C, which is one end of the NPN bipolar transistor Q1, and the NPN bipolar transistor Q2. Is connected to a terminal T3 for applying a potential to the emitter E which is the other end of the terminal.

(2) Second Embodiment (2-2) Circuit Operation The circuit operation of the rectifier circuit and control circuit according to the second embodiment of the present invention will be described with reference to FIG.
A current path from the source to the drain of the FET Q5 is a rectification current path.
The rectifier circuit in the circuit of FIG. 2 of the present invention comprises a diode having the source (terminal T1) of the FET Q5 as an anode and the drain (terminal T2) of the FET Q5 as a cathode, and the source potential of the FET Q5 and the drain potential of the FET Q5 are The control circuit compares and controls the potential applied to the gate G of the FET Q5, and controls conduction / non-conduction of the FET Q5.

In the description of the circuit operation of the present invention, the potential of each element is the collector potential of the NPN bipolar transistor Q2 as the reference potential (= the potential of the terminal T1). Each element operates with a DC positive potential applied to the terminal T3.
There is no need to ground the collector C of the NPN bipolar transistor Q2, but when the collector C of the NPN bipolar transistor Q2 is grounded, the potential of the collector C becomes the ground potential.

One end of an external DC power supply for external load operation is connected to the terminal T1, and one end of the external load is connected to the terminal T2. Although not shown in the circuit of FIG. 2, the other end of the external DC power supply and the other end of the external load are connected by another current path, and the external DC power supply and the external load are connected. Configure the current path.
In the description of the present invention, one end of the external DC power source has a positive potential and the other end of the external DC power source has a negative potential.

(2-2-1) Operation for turning off FET Q5 When the collector C of the NPN bipolar transistor Q4 is open, no current flows through the current paths of the NPN bipolar transistor Q3 and the NPN bipolar transistor Q4. Therefore, no current flows through the resistance element R2, the collector potential of the NPN bipolar transistor Q3 is the same as the potential of the terminal T3, and the base potentials of the NPN bipolar transistor Q1 and the NPN bipolar transistor Q2 are also the collector potential of the NPN bipolar transistor Q3. The base potential of the NPN bipolar transistor Q1 and the base potential of the NPN bipolar transistor Q2 are applied with potentials sufficient to make the NPN bipolar transistor Q1 and the NPN bipolar transistor Q2 conductive, and the NPN bipolar transistor Q1, The NPN bipolar transistor Q is in a conductive state.

  If the NPN bipolar transistor Q1 and the NPN bipolar transistor Q2 are conductive, the collector potential of the NPN bipolar transistor Q1 is approximately 0V, and the potential at the fifth control terminal of the FET Q5 to which this potential is applied is also approximately 0V. Becomes non-conductive.

At this time, no current flows from the drain D of the FET Q5 to the source S of the FET Q5.
Accordingly, the circuit of FIG. 2 operates with the terminal T1 as the anode of the diode and the terminal T2 as the cathode of the diode.

When the terminals T1 and T2 are at the same potential (the collector C of the NPN bipolar transistor Q2 and the collector C of the NPN bipolar transistor Q4 are the same potential, the source S of the FET Q5 and the drain D of the FET Q5 are the same). This means that the terminal T1 and the terminal T2 have the same potential depending on the external conditions. Even when the FET Q5 is non-conductive, the path from the terminal T3 to the resistor element R2, the NPN bipolar transistor Q3, the NPN bipolar transistor Q4, and the terminal T2 Current flows.

The resistance value r2 of the resistance element R2 is small and a large amount of current flows through the resistance element R2, but the voltage drop due to the resistance value r2 is small.
The resistance value r1 of the resistance element R1 is larger than the resistance value r2, and the current flowing through the resistance element R2 is small, but the voltage drop due to the resistance value r1 is large.
The setting of the resistance value r1 and the resistance value r2 depends on the current amplification factor hfe of the NPN bipolar transistor Q1, the NPN bipolar transistor Q2, the NPN bipolar transistor Q3, and the NPN bipolar transistor Q4, but the NPN bipolar transistor Q1, the NPN bipolar transistor Q2, When the NPN bipolar transistor Q3 and the NPN bipolar transistor Q4 have the same characteristics, the resistance value r1> resistance value r2 is set.
It is also preferable from the viewpoint of temperature characteristics that the bipolar transistors Q1 to Q4 have the same characteristics.

Since the bipolar transistor Q3 is connected to the collector C and the base B, it appears that the base B and the emitter E of the bipolar transistor Q3 form a PN junction between one end of the resistance element R2 and the other end of the bipolar transistor Q4. Looks like it has been inserted into.
However, even if the collector C and the base B are connected, the bipolar transistor Q3 operates as a bipolar transistor.

Since the bipolar transistor Q3 is connected to the collector C and the base B, even when the bipolar transistor Q3 is in a conductive state, the potential difference between the collector C and the emitter E of the bipolar transistor Q3 is not substantially 0 V, but the base B and the emitter E. It becomes the same potential difference as the potential difference between them.

Since the collector C and the base B of the bipolar transistor 3 are connected, a negative feedback circuit is formed, negative feedback is applied from the collector C of the bipolar transistor Q3 to the base B, and the base potential of the bipolar transistor Q3 is balanced.

The base current of the bipolar transistor Q3 is small due to the hfe of the bipolar transistor Q3, and a minimum base current for making the bipolar transistor Q3 conductive is conducted. Therefore, the potential difference between the base B and the emitter E of the bipolar transistor Q3 is about 0.6V. . This potential is a balanced potential due to negative feedback from the collector C to the base B of the bipolar transistor Q3.

The base potential of the bipolar transistor Q3 is applied to the base B of the bipolar transistors Q2 to Q4, and the bipolar transistors Q1 to Q4 are in a conductive state. Therefore, the collector potential which is one end of the bipolar transistor Q1 is approximately 0V, the potential of the fifth control terminal of the FET Q5 to which this potential is applied is also approximately 0V, and the FET Q5 is non-conductive.

(2-2-2) Operation for making FET Q5 conductive When the drain potential of FET Q5 falls below the source potential of FET Q5, the collector potential of bipolar transistor Q4 connected to the drain of FET Q5 also falls, and the base potential of bipolar transistor Q4 Also decreases.

  The potential at which the drain potential of the FET Q5 is lower than the source potential of the FET Q5 may be about several mV to several tens of mV, but it is not lowered by about 0.6 V or more due to the FET Q5 body diode.

When the collector potential of the bipolar transistor Q4 is lowered, the base potential of the bipolar transistor Q4 is also lowered, and the base potentials of the bipolar transistor Q1 and the bipolar transistor Q2 that are the same potential as the base potential of the bipolar transistor Q4 are also lowered.
Therefore, bipolar transistors Q1 and Q2 are non-conductive. Since the base potentials of the bipolar transistors Q1 and Q2 are about 0.6V, the bipolar transistors Q1 and Q2 become non-conductive even if they are lowered by several mV.

When the bipolar transistor Q1 becomes non-conductive, no current flows through the resistance element R1.
Therefore, the collector potential of the bipolar transistor Q1 and the potential of one end of the resistance element R1 are the same as the potential of the terminal T3.

  For this reason, the gate potential of the FET Q5 becomes the same potential as the potential of the terminal T3, and the FET Q5 becomes conductive.

When the FET Q5 becomes conductive, a current flows from the source to the drain of the FET Q5, that is, from the terminal T1 to the terminal T2.
The source S of the FET Q5 constitutes the anode of the diode, and the drain of the FET Q5 constitutes the cathode of the diode.

Even if the base potentials of the bipolar transistors Q1 and Q2 are lowered and the bipolar transistors Q1 and Q2 are turned off, the bipolar transistors Q3 and Q4 are turned on.
The bipolar transistor Q1, the bipolar transistor Q2, the bipolar transistor Q3, and the bipolar transistor Q have the same gate potential as viewed from the collector potential of the bipolar transistor Q2 (reference potential of the control circuit).
Accordingly, the base potentials of the bipolar transistors Q1 to Q4 are all lowered from the reference potential.

However, since the collector potential of the bipolar transistor Q4 is lowered, the emitter potential of the bipolar transistor Q3 is also lowered, and the base potential of the bipolar transistor Q3 with respect to the emitter potential of the bipolar transistor Q3 remains unchanged. Also, the base potential of the bipolar transistor Q4 with respect to the collector potential of the bipolar transistor Q4 remains unchanged. (Does not drop.)
Accordingly, since the base potentials of the bipolar transistors Q3 and Q4 are relatively higher than the base potentials of the bipolar transistors Q1 and Q2, the bipolar transistors Q3 and Q4 are conductive.

(3) Third Embodiment (3-1) Circuit Configuration FIG. 3 shows a rectifier circuit according to a third embodiment of the present invention and a fifth semiconductor element constituting a rectified current path in the rectifier circuit. It is a circuit block diagram which shows the control circuit which controls N channel type FETQ5.
In FIG. 3, a portion surrounded by a broken line is the control circuit constituting a part of the rectifier circuit. The control circuit includes an NPN bipolar transistor Q1 as a first semiconductor element, an NPN bipolar transistor Q2 as a second semiconductor element, an NPN bipolar transistor Q3 as a third semiconductor element, an NPN bipolar transistor Q4 as a fourth semiconductor element, The resistor element R1 is a first resistor element and the resistor element R2 is a second resistor element.

The above circuit configuration is the same as that of FIG. 2 which is the second embodiment according to the present invention. However, the following elements (1) to (3) are selectively shown in FIG. To the control circuit (shown in a portion surrounded by a broken line).
(1) A Zener diode Ze that is a constant voltage element, a capacitor C1 that is a first capacitance element, a diode D that is a rectifying element, and a resistance element R3 that is a third resistance element.
(2) A capacitor C2 that is a second capacitor element.
(3) An NPN bipolar transistor Q6 as a sixth semiconductor element, a resistance element R4 as a fourth resistance element, and a resistance element R5 as a fifth resistance element.

The circuit configuration of the present invention will be described below with reference to FIG.
However, the same parts as those of the circuit of FIG. 2 are denoted by the same reference numerals as those of the elements of FIG. 2, and the description of FIG. And the circuit configuration added by (3) will be described.

(Description of (1) above)
The parallel connection circuit of the Zener diode Ze and the capacitor C1 is provided between the collector C that is one end of the NPN bipolar transistor Q1 and the connection portion of the terminal T4 and the gate G that is the fifth control terminal of the FET Q5 that is the fifth semiconductor element. The direction of the zener diode connected is the direction in which the cathode is connected to the collector C which is one end of the NPN bipolar transistor Q1.

The anode of the Zener diode Ze is connected to the anode of a diode D that is a rectifying element, the cathode of the diode D is connected to one end of a resistance element R3 that is a third resistance element, and the other end of the resistance element R3 is It is connected to the collector C which is one end of the NPN bipolar transistor Q2.

(Explanation of (2) above)
A capacitor C2, which is a second capacitive element, is connected between one end (collector C) of the NPN bipolar transistor Q2, which is the second semiconductor element, and the other end (emitter E) of the NPN bipolar transistor Q2.

(Description of (3) above)
One end (collector C) of an NPN bipolar transistor Q6, which is a sixth semiconductor element, is connected to one end (collector C) of the NPN bipolar transistor Q1, and one end (collector C) of the NPN bipolar transistor Q2 is connected to one end (collector C) of the sixth semiconductor element. The other end (emitter E) of an NPN bipolar transistor Q6 is connected.

  A resistance element R5, which is a fifth resistance element, is connected between the terminal T5 and the base B, which is the sixth control terminal of the NPN bipolar transistor Q6, and between one end of the NPN bipolar transistor Q2 and the base B of the NPN bipolar transistor Q6, A resistance element R4, which is a fourth resistance element, is connected.

  Except for the addition of the respective elements (the above (1) to (3)), there is no difference from the rectifier circuit and the control circuit of FIG. 2 according to the second embodiment.

  Each element described in the above (1), (2) and (3) can be selected and added for each unit of (1), (2) and (3). Each element described in (1), (2), (3) can be used for the control circuit at the same time, but only one of (1), (2), (3) can be selected, It can be used in multiple combinations.

(3) Third Embodiment (3-2) Circuit Operation The circuit operation of the rectifier circuit and the control circuit according to the third embodiment of the present invention will be described with reference to FIG.

  However, the circuit operation of the N-channel FET Q5, which is the fifth semiconductor element constituting the rectifier current path in the rectifier circuit of FIG. 3 and the rectifier current path, the control circuit for controlling the FET Q5 (from the circuit surrounded by the broken line in FIG. The circuit operation of (1), (2) and (3) means the circuit excluding each element.) Is the same as the operation of the control circuit shown in FIG. 2, which is the second embodiment. The description of the circuit operation in FIG. 2 is used to omit the overlapping circuit operation description, and the circuit operation added by the above (1), (2), and (3) will be sequentially described.

(3-2-1) The circuit operation capacitor C1 to which each element of the above (1) is added has the potential applied to the terminal T3 as a current path of the resistance element R1, the capacitor C1, the diode D, the resistance element R3, and the terminal T1. It is charged with.
The potential polarity of the capacitor C1 is positive on the cathode side of the Zener diode Ze and negative on the anode side of the Zener diode Ze.

When there is a demand for rapidly switching the FET Q5 to the non-conductive state with the FET Q5 conducting, when the terminal T4 is connected to the terminal T1, the terminal T4 side, which is the charge potential polarity of the capacitor C1, is the positive potential, and the FET Q5 Since the gate G side has a negative potential, the charge accumulated in the gate G of the FET Q5 is rapidly discharged by the potential polarity of the capacitor C1 rather than simply connecting the gate G, which is the fifth control terminal of the FET Q5, directly to the terminal T1. The FET Q5 rapidly changes from the conductive state to the non-conductive state.

This demand is simpler than the FET control circuit used in the rectifier circuit as a diode for a switching power supply, etc., and is suitable as a diode for a switching power supply, etc., and a control circuit that can control the FET Q5 from conduction to non-conduction at high frequency. realizable.
When used as an ORingFET diode, when there is no demand for high-speed switching, such as when rectifying low-frequency alternating current, the additional circuit of (1) is not particularly required.

The voltage across the capacitor C1 can be charged up to the Zener voltage of the Zener diode. The Zener diode Ze applies the potential applied to the terminal T3 to the gate G of the FET Q5.
The Zener voltage of the Zener diode Ze is set so that the gate potential of the FET Q5 becomes a potential at which the FET Q5 becomes conductive. That is, the Zener voltage is smaller than the gate threshold voltage for allowing the FET Q5 to be completely conducted and is set so as to sufficiently satisfy the gate potential of the FET Q5, or is related to the potential of the terminal T3. Is set to an optimum value potential related to the gate threshold potential and the Zener voltage of the FET Q5.

(3-2-2) Circuit operation with the addition of the element of (2) Since both ends of the capacitor C2 are connected between the emitter E and the collector C of the NPN bipolar transistor Q2, the emitter E of the NPN bipolar transistor Q1 The potential can be rapidly made the potential of the terminal T1. That is, bypassing between the emitter E and the collector C of the bipolar transistor Q2 does not require time for the bipolar transistor Q2 to transition from the non-conductive state to the conductive state.

Suitable when NPN bipolar transistor Q1 and NPN bipolar transistor Q2 are in a conducting state, the collector C potential of NPN bipolar transistor Q1 is approximately 0 V, the gate potential of FET Q5 is lowered, and FET Q5 is rapidly transitioned to a non-conducting state. is there.

Even when the element (2) is used, combining with the circuit elements (1) described above is more preferable because the FET Q5 can be changed from a conductive state to a non-conductive state at a higher speed.

(3-2-3) Circuit operation in which each element of (3) is added Both ends of the current path of the bipolar transistor Q6, which is the sixth semiconductor element, are connected between the terminal T4 and the terminal T1. That is, one end and the other end of the bipolar transistor Q6 are connected between the collector C of the bipolar transistor Q1 and the collector C of the bipolar transistor Q2.
The resistance element R4, which is the fourth resistance element, is a base ground resistance of the bipolar transistor Q6, and the resistance element R5, which is the fifth resistance element, is a base current limiting resistance of the bipolar transistor Q6.

When a positive potential is applied to the terminal T5, a forward bias current flows through the base B which is the sixth control end of the bipolar transistor Q6, and the collector C and the emitter E of the bipolar transistor Q6 are conducted. The positive potential applied to the terminal T5 is 0.6V or more.

Connecting the terminal T4 to the terminal T1 (short-circuiting the terminal T4 between the terminals T1) means applying a 0 V potential to the terminal T4, and applying a positive potential to the terminal T5 means that the terminal T4 and the terminal T1 are applied. Is connected.

Therefore, when the clock pulse signal of the external control circuit, for example, the switching power supply uses 0V potential as the standard output, this output potential is applied to the terminal T4 of the circuit of FIG. 3 to discharge the capacitor C1.
As a result, the gate potential of the FET Q5 is set to a negative potential, and the FET Q5 is transitioned from the conductive state to the non-conductive state.
When an external control circuit (similarly, for example, a circuit that outputs a clock pulse signal of a switching power supply) uses a positive potential as a standard output, this output potential is applied to the terminal T5 of the circuit of FIG. When a forward bias potential is applied to the base B of the transistor Q6, the bipolar transistor Q6 is changed from a non-conductive state to a conductive state, the gate potential of the FET Q5 is changed to a negative potential, and the FET Q5 is changed from a conductive state to a non-conductive state.
Both of them have the same effect of transitioning the FET Q5 from the conductive state to the non-conductive state.

  Therefore, the terminal T4 and the terminal T5 can be used properly according to the polarity of the control output potential of the external control circuit.

(4) Fourth Embodiment (4-1) Circuit Configuration Although the fourth embodiment is not shown, the bipolar transistor Q1, the bipolar transistor Q2, and the bipolar of the control circuit of FIG. 3 in the third embodiment. The circuit configuration is such that the transistor Q3 and the bipolar transistor Q4 are replaced by FETQ1, FETQ2, FETQ3, and FETQ4, respectively.

Therefore, the additional elements (1), (2), (3) of the control circuit for the rectifier circuit in FIG. 3 according to the third embodiment are added to the control circuit for the rectifier circuit in FIG. 1 according to the first embodiment. ) Is selectively added.

Therefore, in the circuit description of the fourth embodiment, the circuit description of FIG. 1 of the first embodiment and the circuit description of FIG. 3 of the third embodiment are used, and redundant description is omitted.

(4) Fourth Embodiment (4-2) Circuit Operation The circuit operation description of FIG. 1 which is the first embodiment has already been described, and the circuit operation of FIG. 3 which is the third embodiment. The explanation has already been explained.

Therefore, although not shown in the fourth embodiment, the description of the additional elements (1), (2), and (3) in FIGS. 1 and 3 is used, and the redundant description is omitted.

(Supplementary item 1)
The N-channel FETQ1 to FETQ5 of FIG. 1 which is the first embodiment can be replaced with a P-channel FET.
At this time, the potential of the terminal T3 becomes a negative potential. The current of the FET Q5 becomes a rectified current path that flows from the drain D to the source S. That is, the drain D is an anode and the source S is a cathode.

Even if a P-channel FET is used, the operation principle of the control circuit of FIG. 1 using an N-channel FET is the same.
In all, only the potential polarity of each element is inverted.

(Supplementary item 2)
The NPN bipolar transistors Q1 to Q4 in FIG. 2, which is the second embodiment, can be replaced with PNP bipolar transistors.
At this time, the potential of the terminal T3 becomes a negative potential. Further, the FET Q5 uses a P-channel FET. The current of the FET Q5 becomes a rectified current path that flows from the drain D to the source S. That is, the drain D is an anode and the source S is a cathode.

Even if a PNP bipolar transistor is used in the control circuit of FIG. 2, it is the same as the operation principle of the control circuit of FIG. 2 using an NPN bipolar transistor.
In all, only the potential polarity of each element is inverted.

(Supplementary note 3)
3 of the third embodiment is also the same as the explanation of the FET Q5, in which the NPN bipolar transistor is replaced with the PNP bipolar transistor in (Supplementary Item 2). The polarities of the anode and cathode of the Zener diode Ze and the anode and cathode of the diode D are also reversed.
The bipolar transistor Q6 is also a PNP bipolar transistor. Therefore, a negative potential is applied to the terminal T5, and the same operation as the control circuit of FIG. 3 of the third embodiment is performed.
In all, only the potential polarity of each element is inverted.

(Supplementary item 4)
Also in the fourth embodiment, the explanations of (Supplementary matter 1) to (Supplementary matter 3) are used, all FETs are P-channel FETs, and all the potential polarities of the respective elements are inverted.

Q1-Q6 Semiconductor element R1-R5 Resistance element Ze Constant voltage element D Rectifier element C1, C2 Capacitance element T1-T5 terminal

Claims (16)

A first semiconductor element having a first control end and having one end and the other end of a current path;
A second semiconductor element having a second control end and having one end and the other end of a current path;
A third semiconductor element having a third control end and having one end and the other end of a current path;
A fourth semiconductor element having a fourth control end and having one end and the other end of a current path;
A fifth semiconductor element having a fifth control end and having one end and the other end of a current path;
A first resistance element and a second resistance element;
An external bias potential is applied to the first control end, the second control end, the third control end, and the fourth control end via the second resistance element,
The one end of the current path of the first semiconductor element is configured to flow a current supplied from an external DC power source through the first resistance element,
The other end of the current path of the second semiconductor element is configured such that a current supplied from an external DC power source flows through the other end of the first semiconductor element.
The one end of the current path of the third semiconductor element is configured to flow a current supplied from an external DC power source through the second resistance element,
The other end of the current path of the fourth semiconductor element is configured so that a current supplied from an external DC power source flows through the other end of the third semiconductor element.
A potential at one end of the current path of the second semiconductor element is configured to be transmitted to one end of the current path of the fifth semiconductor element;
The potential of one end of the current path of the fourth semiconductor element is configured to be transmitted to the other end of the current path of the fifth semiconductor element,
When the potential of one end of the current path of the fourth semiconductor element is equal to or exceeds the potential of one end of the current path of the second semiconductor element, the current paths of the first semiconductor element and the second semiconductor element are conductive, The potential of the fifth control terminal to which the potential of one end of the current path of the first semiconductor element is transmitted decreases, and the current path of the fifth semiconductor element is non-conductive,
When the potential of one end of the current path of the fourth semiconductor element is less than the potential of one end of the current path of the second semiconductor element, the current path of the first semiconductor element is non-conductive, and the current of the first semiconductor element The potential of the fifth control terminal to which the potential of one end of the path is transmitted rises, and the one end of the current path of the fifth semiconductor element and the current path of the fifth semiconductor element in which the current path of the fifth semiconductor element is conducted The other end of the rectifier is a rectifying current path. A parallel connection circuit of a constant voltage element and a first capacitor element is inserted between one end of the first semiconductor element and the fifth control end, the connection portion of the parallel connection circuit and the fifth control end, A series connection circuit of a rectifying element and a third resistance element is inserted between one end of the second semiconductor element, and the constant voltage element is in a direction opposite to the potential polarity supplied by the first resistance element, The rectifier circuit according to claim 1, wherein the element is in a forward direction with respect to a potential polarity supplied by the first resistance element. The rectifier circuit according to claim 1, wherein a second capacitive element is inserted between one end and the other end of the current path of the second semiconductor element. And a sixth semiconductor element having a sixth control end and having one end and the other end of a current path, wherein the sixth semiconductor element is provided between one end of the first semiconductor element and one end of the second semiconductor element. One end of the second semiconductor element and the other end of the sixth semiconductor element are inserted, and a potential is applied to the sixth control terminal to make the sixth semiconductor element conductive or non-conductive. The rectifier circuit according to any one of the above. A first semiconductor element having a first control end and having one end and the other end of a current path;
A second semiconductor element having a second control end and having one end and the other end of a current path;
A third semiconductor element having a third control end and having one end and the other end of a current path;
A fourth semiconductor element having a fourth control end and having one end and the other end of a current path;
A first resistance element and a second resistance element;
An external bias potential is applied to the first control end, the second control end, the third control end, and the fourth control end via the second resistance element,
The one end of the current path of the first semiconductor element is configured to flow a current supplied from an external DC power source through the first resistance element,
The other end of the current path of the second semiconductor element is configured such that a current supplied from an external DC power source flows through the other end of the first semiconductor element.
The one end of the current path of the third semiconductor element is configured to flow a current supplied from an external DC power source through the second resistance element,
The other end of the current path of the fourth semiconductor element is configured so that a current supplied from an external DC power source flows through the other end of the third semiconductor element.
The potential of one end of the current path of the second semiconductor element is configured to be transmitted to one end of the current path of the fifth semiconductor element existing outside,
The potential of one end of the current path of the fourth semiconductor element is configured to be transmitted to the other end of the current path of the fifth semiconductor element existing outside,
When the potential of one end of the current path of the fourth semiconductor element is equal to or exceeds the potential of one end of the current path of the second semiconductor element, the current paths of the first semiconductor element and the second semiconductor element are conductive, The electric potential at one end of the current path of the first semiconductor element is transmitted, the electric potential at the fifth control terminal of the fifth semiconductor element existing outside is lowered, and the electric current path of the fifth semiconductor element existing outside is not Continuity,
When the potential of one end of the current path of the fourth semiconductor element is less than the potential of one end of the current path of the second semiconductor element, the current path of the first semiconductor element is non-conductive, and the current of the first semiconductor element The potential of the fifth control terminal of the fifth semiconductor element existing outside to which the potential of one end of the path is transmitted rises, and the current path of the fifth semiconductor element existing outside the second semiconductor element existing outside the conductor is conducted. 5. A control circuit comprising: controlling one end of a current path of a fifth semiconductor element and the other end of a current path of a fifth semiconductor element existing outside as a rectifying action current path. A parallel connection circuit of a constant voltage element and a first capacitance element is inserted between one end of the first semiconductor element and a fifth control terminal of the fifth semiconductor element existing outside, and the parallel connection circuit and the first 5 A series connection circuit of a rectifying element and a third resistance element is inserted between the connection portion of the control end and one end of the second semiconductor element, and the constant voltage element is a potential supplied by the first resistance element. The control circuit according to claim 5, wherein the control circuit has a reverse direction to the polarity, and the rectifying element is in a forward direction with respect to a potential polarity supplied by the first resistance element. 7. The control circuit according to claim 5, wherein a second capacitive element is inserted between one end and the other end of the current path of the second semiconductor element. And a sixth semiconductor element having a sixth control end and having one end and the other end of a current path, wherein the sixth semiconductor element is provided between one end of the first semiconductor element and one end of the second semiconductor element. 8 and the other end of the sixth semiconductor element are inserted, and a potential is applied to the sixth control end to make the sixth semiconductor element conductive or non-conductive. The control circuit according to any one of the above. The first semiconductor element, the second semiconductor element, the third semiconductor element, the fourth semiconductor element, and the fifth semiconductor element are N-channel FETs,
One end of the current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a drain, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is a source,
One end of the current path of the fifth semiconductor element is a source and the other end is a drain;
When the sixth semiconductor element is included, the sixth semiconductor element is an N-channel FET, and one end of a current path of the sixth semiconductor element is a drain and the other end is a source. The rectifier circuit in any one of 1-4. The first semiconductor element, the second semiconductor element, the third semiconductor element, the fourth semiconductor element, and an NPN bipolar transistor;
One end of a current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a collector, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is an emitter,
The fifth semiconductor element is an N-channel FET, and one end of the fifth semiconductor element current path is a source and the other end is a drain.
2. When the sixth semiconductor element is included, the sixth semiconductor element is an NPN bipolar transistor, and one end of a current path of the sixth semiconductor element is a collector and the other end is an emitter. The rectifier circuit in any one of -4. The first semiconductor element, the second semiconductor element, the third semiconductor element, the fourth semiconductor element, and the fifth semiconductor element are P-channel FETs;
One end of the current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a drain, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is a source,
One end of the current path of the fifth semiconductor element is a source and the other end is a drain;
2. When the sixth semiconductor element is included, the sixth semiconductor element is a P-channel FET, and one end of the current path of the sixth semiconductor element is a drain and the other end is a source. The rectifier circuit in any one of -4. The first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element are PNP-type bipolar transistors,
One end of a current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a collector, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is an emitter,
The fifth semiconductor element is a P-channel FET;
One end of the current path of the fifth semiconductor element is a source and the other end is a drain;
2. When the sixth semiconductor element is included, the sixth semiconductor element is a PNP-type bipolar transistor, and one end of a current path of the sixth semiconductor element is a collector and the other end is an emitter. The rectifier circuit in any one of -4. The first semiconductor element, the second semiconductor element, the third semiconductor element, the fourth semiconductor element, and the fifth semiconductor element existing outside are N-channel FETs,
One end of the current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a drain, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is a source,
One end of the current path of the fifth semiconductor element existing outside is a source and the other end is a drain,
When the sixth semiconductor element is included, the sixth semiconductor element is an N-channel FET, and one end of a current path of the sixth semiconductor element is a drain and the other end is a source. The control circuit according to any one of 5 to 8. The first semiconductor element, the second semiconductor element, the third semiconductor element, the fourth semiconductor element, and an NPN bipolar transistor;
One end of a current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a collector, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is an emitter,
The fifth semiconductor element existing outside is an N-channel FET, one end of the fifth semiconductor element current path is a source, and the other end is a drain.
6. When the sixth semiconductor element is included, the sixth semiconductor element is an NPN bipolar transistor, and one end of the current path of the sixth semiconductor element is a collector and the other end is an emitter. The control circuit in any one of -8. The first semiconductor element, the second semiconductor element, the third semiconductor element, the fourth semiconductor element, and the fifth semiconductor element existing outside are P-channel FETs,
One end of the current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a drain, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is a source,
One end of the current path of the fifth semiconductor element existing outside is a source and the other end is a drain,
6. When the sixth semiconductor element is included, the sixth semiconductor element is a P-channel FET, and one end of a current path of the sixth semiconductor element is a drain and the other end is a source. The control circuit in any one of -8. The first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element are PNP-type bipolar transistors,
One end of a current path of the first semiconductor element, the second semiconductor element, the third semiconductor element, and the fourth semiconductor element is a collector, and the first semiconductor element, the second semiconductor element, and the third semiconductor element And the other end of the current path of the fourth semiconductor element is an emitter,
The fifth semiconductor element present outside is a P-channel FET,
One end of the current path of the fifth semiconductor element existing outside is a source and the other end is a drain,
6. When the sixth semiconductor element is included, the sixth semiconductor element is a PNP-type bipolar transistor, and one end of the current path of the sixth semiconductor element is a collector and the other end is an emitter. The control circuit in any one of -8.

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