JP2011249983A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an overcurrent of an output transistor by a simplified circuit configuration.SOLUTION: An overcurrent protection circuit 30 of a semiconductor integrated circuit device 70 includes an overcurrent detector 1 and an overcurrent controller 2. The overcurrent detector 1 includes current sources 11 through 13 and NPN transistors Q1 through Q3. The NPN transistor Q1 and the NPN transistor Q2 constitute a first current mirror circuit, and output an overcurrent detection signal Skk from the collector side of the NPN transistor Q2. The NPN transistor Q1 and the NPN transistor Q3 constitute a second current mirror circuit, and output an overcurrent control signal Sks from the collector side of the NPN transistor Q3 to the overcurrent controller 2. The overcurrent protection circuit 30 detects an overcurrent flowing into an output transistor MDT1 in between the source of the output transistor MDT1 and a resistor R1, and then suppresses the overcurrent.

Description

  The present invention relates to a semiconductor integrated circuit device.

  An open drain type or open collector type output transistor provided in a semiconductor integrated circuit device is provided with an overcurrent protection circuit that detects an overcurrent and suppresses the overcurrent (see, for example, Patent Document 1).

  The overcurrent protection circuit described in Patent Document 1 has a problem that the number of elements forming the circuit is large. When the number of elements is large, the chip area increases and the cost of the semiconductor integrated circuit device increases.

JP-A-2-285932

  An object of the present invention is to provide a semiconductor integrated circuit device that suppresses an overcurrent of an output transistor with a simple circuit configuration.

  The semiconductor integrated circuit device according to one embodiment of the present invention includes an output transistor that outputs an output current from the first terminal to the output terminal, and a second transistor side that is opposite to each other by flowing the first current on the first transistor side. And a first current mirror circuit for supplying a second current n times (where n> 1) the first current, and a third current that is opposite to the first current on the first transistor side. A second current mirror circuit for flowing a third current (n + m) times (where (n + m)> n) of the first current on the transistor side of the first transistor, and the first current of the second transistor An overcurrent detection signal is detected from a terminal, an overcurrent control signal is detected from a first terminal of the third transistor, and a second terminal of the second and third transistors is a second terminal of the output transistor. The overcurrent detector connected to the An overcurrent control unit that receives an overcurrent control signal and controls a signal level of a control signal supplied to a control terminal of the output transistor based on the overcurrent control signal to suppress the overcurrent. Features.

  Furthermore, a semiconductor integrated circuit device according to another aspect of the present invention includes an Nch MOS transistor that outputs an output current from the drain to an output terminal, a resistor provided between the source of the Nch MOS transistor and a low-potential side power supply, A first current is caused to flow on the NPN transistor side of the first NPN transistor, and a second current is caused to flow on the second NPN transistor side having an emitter area n times (where n> 1) that of the opposing first NPN transistor. 1 current mirror circuit and a first current flowing on the first NPN transistor side, and has an emitter area that is (n + m) times (where (n + m)> n) the first NPN transistor facing each other. A second current mirror circuit for passing a third current on the third NPN transistor side; a high-potential side power supply; and a collector of the first to third NPN transistors. First to third current sources provided between the first and second current sources, detecting an overcurrent detection signal from the collector of the second NPN transistor, and receiving an overcurrent control signal from the collector of the third NPN transistor. Detecting, an overcurrent detection unit in which the emitters of the second and third NPN transistors are connected between the source of the Nch MOS transistor and the resistor, and the overcurrent control signal is input, and the overcurrent control signal And an overcurrent control unit that controls the signal level of the control signal supplied to the gate of the Nch MOS transistor to suppress overcurrent.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device that suppresses an overcurrent of an output transistor with a simple circuit configuration.

1 is a circuit diagram showing a semiconductor integrated circuit device according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a semiconductor integrated circuit device of a comparative example in Example 1 of the present invention. FIG. 3A is a diagram illustrating the relationship between the current flowing through the output transistor and the detection voltage, and FIG. 3B is the current flowing through the output transistor. The figure which shows the relationship of an output voltage. FIG. 6 is a circuit diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 6 is a circuit diagram showing a semiconductor integrated circuit device according to a third embodiment of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor integrated circuit device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device, and FIG. 2 is a circuit diagram showing a semiconductor integrated circuit device of a comparative example. In this embodiment, an overcurrent of the output transistor is detected by using a current mirror circuit to suppress the overcurrent.

  As shown in FIG. 1, the semiconductor integrated circuit device 70 is provided with a control unit 3, an overcurrent protection circuit 30, a buffer BF11, a buffer BF1n, a diode D1, an output transistor MDT1, an output terminal PVo, and a resistor R1. The semiconductor integrated circuit device 70 is an open drain type output driver, and is often used for consumer electronic devices and industrial electronic devices.

  The output transistor MDT1 has a drain (first terminal) connected to the node N5 and the output terminal Pvo, a gate (control terminal) that receives a control signal output from the overcurrent protection circuit 30, and a source (second terminal). ) Is connected to the node N4, and the output signal Sout is output from the drain (first terminal) to the output terminal Pvo. The output transistor MDT1 is an open drain Nch (N channel) DMOS transistor. The output transistor MDT1 includes a diode DN1 whose cathode is connected to the drain of the output transistor MDT1, and whose anode is connected to the source of the output transistor MDT1.

  A diode D1 is provided between the high potential side power supply Vcc and the node N5. The diode D1 is a protective diode having a cathode connected to the high potential side power supply Vcc and an anode connected to the node N5. The resistor R1 has one end connected to the node N4 and the other end connected to the low potential side power supply (ground potential) Vss.

  The overcurrent protection circuit 30 includes an overcurrent detection unit 1 and an overcurrent control unit 2. The overcurrent protection circuit 30 detects an overcurrent flowing through the output transistor MDT1 and suppresses the overcurrent.

  The overcurrent detection unit 1 includes current sources 11 to 13 and NPN transistors Q1 to Q3. The overcurrent detection unit 1 detects an overcurrent flowing through the output transistor MDT1 on the source side (node N4) of the output transistor MDT1, and generates an overcurrent detection signal Skk and an overcurrent control signal Sks.

  The current source 11 is provided between the high-potential-side power supply Vdd and the node N1, and flows a first current to the node N1 side. The current source 12 is provided between the high potential side power source Vdd and the node N2, and allows a second current to flow to the node N2 side. The current source 13 is provided between the high potential side power source Vdd and the node N3, and allows a third current to flow to the node N3 side.

  The NPN transistor Q1 has a collector (first terminal) and a base (control terminal) connected to the node N1, an emitter (second terminal) connected to a low potential power supply (ground potential) Vss, and a low potential power supply. (Ground potential) A first current is supplied to the Vss side. The NPN transistor Q2 has a collector (first terminal) connected to the node N2, a base (control terminal) connected to the base (control terminal) and the node N1 of the NPN transistor Q1, and an emitter (second terminal) connected to the node. A second current is passed through the emitter connected to N4. The NPN transistor Q3 has a collector (first terminal) connected to the node N3, a base (control terminal) connected to the base (control terminal) and the node N1 of the NPN transistor Q1, and an emitter (second terminal) connected to the node. A third current is supplied to the emitter side connected to N4.

  NPN transistor Q2 has an emitter size set to n times (where n> 1) than NPN transistor Q1. NPN transistor Q3 has an emitter size set to (n + m) times (where (n + m)> n) than NPN transistor Q1. As a result, the second current is n times larger than the first current. The third current is (n + m) times larger than the first current.

  The NPN transistor Q1 and the NPN transistor Q2 constitute a first current mirror circuit. The NPN transistor Q1 and the NPN transistor Q3 constitute a second current mirror circuit. The first current mirror circuit detects an overcurrent flowing through the output transistor MDT1 at the node N4 and outputs an overcurrent detection signal Skk from the node N2. The second current mirror circuit detects an overcurrent flowing through the output transistor MDT1 at the node N4 and outputs an overcurrent control signal Sks from the node N3. Since the third current flowing through the NPN transistor Q3 is larger than the second current flowing through the NPN transistor Q2, the rising of the overcurrent control signal Sks is delayed from the rising of the overcurrent detection signal Skk.

  The overcurrent detection signal Skk output from the node N2 is amplified by n cascaded buffers (buffer BF11,..., Buffer BF1n) and then input to the control unit 3. The control part 3 consists of CPU (central processing unit), for example. The overcurrent control signal Sks output from the node N3 is output to the overcurrent control unit 2.

  The overcurrent control unit 2 is provided with a power supply 21, a buffer BF1, and a variable resistor KR1. The negative side of the power source 21 is connected to the low potential side power source (ground potential) Vss. One end of the variable resistor KR1 is connected to the positive side of the power source 21, changes the voltage Vb1 of the power source 21 based on the overcurrent control signal Sks, and supplies the changed voltage of the power source 21 to the buffer BF1.

  The buffer BF1 is provided between the changed voltage of the power supply 21 and the low-potential-side power supply (ground potential) Vss, and receives an input signal Sin for controlling on / off of the output transistor MDT1. The buffer BF1 outputs a control signal obtained by level-shifting the signal level of the input signal Sin to the gate (control terminal) of the output transistor MDT1 based on the changed voltage of the power supply 21. The buffer BF1 functions as a level shift circuit. An overcurrent flowing through the output transistor MDT1 is suppressed by the control signal output from the buffer BF1.

  As shown in FIG. 2, the semiconductor integrated circuit device 80 of the comparative example includes a control unit 3, an overcurrent protection circuit 40, a buffer BF11, a buffer BF1n, a diode D1, an output transistor MDT1, an output terminal PVo, and a resistor R1. It is done. The semiconductor integrated circuit device 80 is an open drain type output driver. In the semiconductor integrated circuit device 80 of the comparative example, the description of the same components as those of the semiconductor integrated circuit device 70 of the present embodiment is omitted, and only different portions are described.

  The overcurrent protection circuit 40 is provided with an overcurrent detection unit 4 and an overcurrent control unit 2. The overcurrent protection circuit 40 detects an overcurrent flowing through the output transistor MDT1 and suppresses the overcurrent.

  The overcurrent detection unit 4 is provided with a comparator 14, a comparator 15, a power supply 22, and a power supply 23. The overcurrent detection unit 4 detects an overcurrent flowing through the output transistor MDT1 on the source side (node N4) of the output transistor MDT1, and generates an overcurrent detection signal Skk and an overcurrent control signal Sks. The overcurrent detector 4 operates in the same manner as the overcurrent detector 1 of the semiconductor integrated circuit device 70 of this embodiment.

  The power source 22 has a negative side connected to a low potential side power source (ground potential) Vss, and outputs a voltage Vb2 from the positive side. The power source 23 has a negative side connected to a low potential side power source (ground potential) Vss, and outputs a voltage Vb3 higher than the voltage Vb2 from the positive side.

  The comparator 14 has a positive port on the input side connected to the node N4, a voltage Vb2 is applied to the negative port on the input side, and a signal that is compared and amplified when the voltage at the node N4 is greater than the voltage Vb2 is an overcurrent detection signal Skk. Is output to the buffer BF11. The comparator 15 has a positive port on the input side connected to the node N4, a voltage Vb3 is applied to the negative port on the input side, and a signal amplified and compared when the voltage at the node N4 is higher than the voltage Vb3. Is output to the overcurrent control unit 2 as follows.

  That is, when the overcurrent flowing through the output transistor MDT1 exceeds a predetermined value and the voltage at the node N4 becomes higher than the voltage Vb2, the comparator 14 outputs the overcurrent detection signal Skk that is comparatively amplified. Thereafter, when the overcurrent flowing through the output transistor MDT1 further increases and the voltage at the node N4 becomes higher than the voltage Vb3, the comparator 15 outputs the overcurrent control signal Sks which is compared and amplified.

  Here, for example, when the number of elements of the comparator 14 and the comparator 15 is 8 and the number of elements of the power supply 22 and the power supply 23 is 2, respectively, the number of elements of the overcurrent detection unit 4 of the semiconductor integrated circuit device 80 of the comparative example. Becomes 20, which is 3.3 times larger than the number of elements 6 in the overcurrent detection unit 2 of the semiconductor integrated circuit device 70 of this embodiment. The number of elements 8 of the comparator 14 and the comparator 15 includes, for example, two transistors of a differential pair, two resistors as a high-potential side current source, and a current mirror circuit (two Transistor) and two transistors on the output side. The contents of the number of elements 2 of the power supply 22 and the power supply 23 are, for example, to generate the voltage Vb2 and the voltage Vb3 using a resistance of 2 (resistance division). The current sources 11 to 13 use resistors.

  Next, suppression of overcurrent of the output transistor will be described with reference to FIG. 3 is a diagram for explaining the operation of overcurrent protection, FIG. 3A is a diagram showing the relationship between the current flowing through the output transistor and the detection voltage, and FIG. 3B is the diagram showing the relationship between the current flowing through the output transistor and the output voltage. FIG.

  As shown in FIG. 3A, in the semiconductor integrated circuit device 70 of the present embodiment, the current flowing through the output transistor MDT1 increases. For example, when the overcurrent detection value (42 mA) is exceeded, the node that is the overcurrent detection signal Skk The voltage Vn2 of N2 starts to rise from 0 (zero). Thereafter, the current flowing through the output transistor MDT1 further increases. For example, when the current value (44 mA) is exceeded, the voltage Vn3 of the node N3, which is the overcurrent control signal Sks, starts to rise from 0 (zero).

  As shown in FIG. 3B, in the semiconductor integrated circuit device 70 of this embodiment, the current flowing through the output transistor MDT1 from 0 (zero) until the voltage Vn3 of the node N3 that is the overcurrent control signal Sks rises. In the region, since the voltage output from the variable resistor KR1 supplied to the buffer BF1 is constant, the output voltage gradually increases.

  Next, when the voltage Vn3 of the node N3 that is the overcurrent control signal Sks rises, the voltage output from the variable resistor KR1 supplied to the buffer BF1 increases, and the control signal level output from the buffer BF1 increases. The output voltage rises.

  Subsequently, when the current flowing through the output transistor MDT1 becomes, for example, the output limit current value (45 mA) or more, the value of the variable resistor KR1 is changed based on the voltage Vn3 of the node N3 that is the overcurrent control signal Sks, and the buffer BF1 An increase in the output control signal level is suppressed, and the current of the output transistor MDT1 is limited (overcurrent suppression). For this reason, an increase in output voltage is suppressed.

  Here, the area ratio of the NPN transistors Q1 to Q3 is set so that the overcurrent detection is 42 mA and the output limiting current is 45 mA. For this reason, for example, even if element variations (ΔVbe (base-emitter voltage variation) or the like) occur in the NPN transistors Q1 to Q3, the overcurrent detection value and the output limit current value do not reverse.

  On the other hand, in the semiconductor integrated circuit device 80 of the comparative example, since the comparator 14 and the comparator 15 are used, there is a possibility that the overcurrent detection value and the output limit current value are reversed when element variation occurs.

  As described above, in the semiconductor integrated circuit device of this embodiment, the control unit 3, the overcurrent protection circuit 30, the buffer BF11, the buffer BF1n, the diode D1, the output transistor MDT1, the output terminal PVo, and the resistor R1 are provided. The overcurrent protection circuit 30 includes an overcurrent detection unit 1 and an overcurrent control unit 2. The overcurrent detection unit 1 includes current sources 11 to 13 and NPN transistors Q1 to Q3. The NPN transistor Q1 and the NPN transistor Q2 constitute a first current mirror circuit, and output an overcurrent detection signal Skk from the collector side of the NPN transistor Q2. The NPN transistor Q1 and the NPN transistor Q3 constitute a second current mirror circuit, and output an overcurrent control signal Sks from the collector side of the NPN transistor Q3 to the overcurrent control unit 2. The overcurrent protection circuit 30 detects an overcurrent flowing through the output transistor MDT1 between the source of the output transistor MDT1 and the resistor R1, and suppresses the overcurrent.

  For this reason, the number of elements constituting the overcurrent protection circuit 30 of the semiconductor integrated circuit device 70 can be reduced as compared with the prior art. Therefore, the chip area of the semiconductor integrated circuit device 70 can be reduced, and the cost can be reduced. Further, even if the elements vary, the overcurrent detection value and the output limit current value do not reverse.

  In this embodiment, an NPN transistor is used for the current mirror circuit, but an Nch MOS transistor or the like may be used instead.

  Next, a semiconductor integrated circuit device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram showing a semiconductor integrated circuit device. In this embodiment, the output current is higher than that in the first embodiment, and the overcurrent is detected at a location different from the output transistor through which the output current flows, and the overcurrent of the output transistor is suppressed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 4, the semiconductor integrated circuit device 71 includes a control unit 3, an overcurrent protection circuit 30, a buffer BF11, a buffer BF1n, a diode D1, an output transistor MDT1, an output transistor MDT11, an output terminal PVo, and a resistor R1. Provided. The semiconductor integrated circuit device 71 is an open drain type output driver having an output current capacity larger than that of the first embodiment, and is frequently used for consumer and industrial electronic devices.

  The output transistor MDT11 has a drain (first terminal) connected to the node N5 and the output terminal Pvo, a gate (control terminal) that receives a control signal output from the overcurrent protection circuit 30, and a source (second terminal). ) Is connected to the low potential side power supply (ground potential) Vss, and the output signal Sout is output from the drain (first terminal) to the output terminal Pvo. The output transistor MDT11 is an open drain Nch (N channel) DMOS transistor. The output transistor MDT11 includes a diode DN11 whose cathode is connected to the drain of the output transistor MDT11 and whose anode is connected to the source of the output transistor MDT11.

  The output transistor MDT11 has a transistor shape larger than that of the output transistor MDT1 and is not provided with a resistor on the source side, so that a voltage drop hardly occurs and an output current capacity can be increased. For example, while the output current capacity of the output transistor MDT1 is 100 mA, the output current capacity of the output transistor MDT11 can be set to 10A. When an overcurrent occurs, the output transistor MDT11 detects an overcurrent of the output transistor MDT1, and a control signal output from the overcurrent protection circuit 30 that suppresses the overcurrent is input to the gate (control terminal). Based on this, overcurrent is suppressed.

  As described above, in the semiconductor integrated circuit device of this embodiment, the control unit 3, the overcurrent protection circuit 30, the buffer BF11, the buffer BF1n, the diode D1, the output transistor MDT1, the output transistor MDT11, the output terminal PVo, and the resistor R1. Provided. The overcurrent detection unit 1 includes current sources 11 to 13 and NPN transistors Q1 to Q3. The NPN transistor Q1 and the NPN transistor Q2 constitute a first current mirror circuit, and output an overcurrent detection signal Skk from the collector side of the NPN transistor Q2. The NPN transistor Q1 and the NPN transistor Q3 constitute a second current mirror circuit, and output an overcurrent control signal Sks from the collector side of the NPN transistor Q3 to the overcurrent control unit 2. The overcurrent protection circuit 30 detects an overcurrent flowing through the output transistor MDT1 between the source of the output transistor MDT1 and the resistor R1, and suppresses the overcurrent flowing through the output transistor MDT11.

  For this reason, the number of elements constituting the overcurrent protection circuit 30 of the semiconductor integrated circuit device 71 can be reduced as compared with the prior art. Therefore, the chip area of the semiconductor integrated circuit device 71 can be reduced, and the cost can be reduced. Further, even if the elements vary, the overcurrent detection value and the output limit current value do not reverse.

  Next, a semiconductor integrated circuit device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 5 is a circuit diagram showing a semiconductor integrated circuit device. In this embodiment, the configuration of the overcurrent detection unit is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 5, the semiconductor integrated circuit device 72 includes a control unit 3, an overcurrent protection circuit 31, a buffer BF11, a buffer BF1n, a diode D1, an output transistor MDT1, an output terminal PVo, and a resistor R1. The semiconductor integrated circuit device 72 is an open drain type output driver, and is often used for consumer and industrial electronic devices.

  The overcurrent protection circuit 31 includes an overcurrent detection unit 5 and an overcurrent control unit 2. The overcurrent protection circuit 31 detects an overcurrent flowing through the output transistor MDT1 and suppresses the overcurrent.

  The overcurrent detection unit 5 includes current sources 11 to 13 and Nch (N channel) MOS transistors MNT1 to MNT4. The overcurrent detection unit 5 detects an overcurrent flowing through the output transistor MDT1 on the source side (node N4) of the output transistor MDT1, and generates an overcurrent detection signal Skk and an overcurrent control signal Sks. The overcurrent detection unit 5 operates in the same manner as the overcurrent detection unit 1 of the first embodiment.

  The Nch MOS transistor MNT1 has a drain (first terminal) connected to the other end of the current source 11, a gate (control terminal) connected to the node N12 and the node N13, and a source (second terminal) connected to the node N11. Connected. In the Nch MOS transistor MNT2, the drain (first terminal) is connected to the gate (control terminal) and the node N11, and the source (second terminal) is connected to the low potential side power supply (ground potential) Vss. In the Nch MOS transistor MNT1 and the Nch MOS transistor MNT2, a first current flows on the low potential side power supply (ground potential) Vss side.

  The Nch MOS transistor MNT3 has a drain (first terminal) connected to the other end of the current source 12 and the node N12, a gate (control terminal) connected to the gate (control terminal) of the Nch MOS transistor MNT2, and a source (first terminal). 2 terminal) is connected to the node N4. A second current flows through the Nch MOS transistor MNT3 on the low potential side power supply (ground potential) Vss side.

  The Nch MOS transistor MNT4 has a drain (first terminal) connected to the other end of the current source 13 and the node N13, a gate (control terminal) connected to the gate (control terminal) of the Nch MOS transistor MNT2, and a source (first terminal). 2 terminal) is connected to the node N4. In the Nch MOS transistor MNT4, a third current flows on the low potential side power supply (ground potential) Vss side.

  The Nch MOS transistors MNT1 to MNT3 constitute a first Wilson type current mirror circuit. Nch MOS transistor MNT3 has a β (gate width Wg / gate length Lg) n times larger than that of Nch MOS transistor MNT1 and Nch MOS transistor MNT2 (mirror ratio n). Overcurrent detection signal Skk is output to buffer BF11 from the drain side (node N12) of Nch MOS transistor MNT3.

  Nch MOS transistor MNT1, Nch MOS transistor MNT2, and Nch MOS transistor MNT4 constitute a second Wilson current mirror circuit. Nch MOS transistor MNT4 has (n + m) times larger (mirror ratio (n + m)) β (gate width Wg / gate length Lg) than Nch MOS transistor MNT1 and Nch MOS transistor MNT2. An overcurrent control signal Sks is output to the overcurrent control unit 2 from the drain side (node N13) of the Nch MOS transistor MNT4. As a result, the second current is n times larger than the first current. The third current is (n + m) times larger than the first current.

  Since the Wilson type current mirror circuit is not easily affected by the Early effect of the Nch MOS transistors MNT1 to MNT4, the characteristics are hardly deteriorated even at a low threshold voltage (Low Vth) as compared with a normal current mirror circuit.

  As described above, in the semiconductor integrated circuit device of this embodiment, the control unit 3, the overcurrent protection circuit 31, the buffer BF11, the buffer BF1n, the diode D1, the output transistor MDT1, the output terminal PVo, and the resistor R1 are provided. The overcurrent protection circuit 31 includes an overcurrent detection unit 5 and an overcurrent control unit 2. The overcurrent detection unit 5 is provided with current sources 11 to 13 and Nch MOS transistors MNT1 to MNT4. The Nch MOS transistors MNT1 to MNT3 constitute a first Wilson current mirror circuit, and output an overcurrent detection signal Skk from the drain side of the Nch MOS transistor NMT3. The Nch MOS transistor MNT1, the Nch MOS transistor MNT2, and the Nch MOS transistor MNT4 form a second Wilson current mirror circuit, and output an overcurrent control signal Sks from the drain side of the Nch MOS transistor MNT4 to the overcurrent control unit 2. . The overcurrent protection circuit 31 detects an overcurrent flowing through the output transistor MDT1 between the source of the output transistor MDT1 and the resistor R1, and suppresses the overcurrent.

  For this reason, the number of elements constituting the overcurrent protection circuit 31 of the semiconductor integrated circuit device 72 can be reduced as compared with the prior art. Therefore, the chip area of the semiconductor integrated circuit device 72 can be reduced, and the cost can be reduced. Further, even if the elements vary, the overcurrent detection value and the output limit current value do not reverse.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  In the embodiment, an Nch DMOS transistor is used as the output transistor. Instead, an Nch MOS transistor, an Nch trench power MOS transistor, an IGBT (insulated gate bipolar transistor), an NPN transistor, or the like that operates at a lower voltage than the Nch DMOS transistor is used. It may be used. Although the Wilson current mirror circuit is used in the second embodiment, a cascode current mirror circuit or the like may be used instead.

The present invention can be configured as described in the following supplementary notes.
(Supplementary note 1) A first output transistor that outputs an output current from the first terminal to the output terminal, a resistor provided between the second terminal of the output transistor and the low-potential side power supply, and an output to the output terminal A current is output from the first terminal, the second terminal is connected to the low-potential-side power supply, and the first current is allowed to flow on the first transistor side, and the second A first current mirror circuit for flowing a second current n times (where n> 1) of the first current on the transistor side and a first current on the first transistor side are opposed to each other. A second current mirror circuit for flowing a third current of (n + m) times (where (n + m)> n) of the first current on the third transistor side, a high-potential-side power supply, and the first to third Provided between the first terminals of the transistors of FIG. And detecting an overcurrent detection signal from the first terminal of the second transistor and detecting an overcurrent control signal from the first terminal of the third transistor. An overcurrent detection unit in which the second terminals of the second and third transistors are connected between the second terminal of the output transistor and the resistor; and the overcurrent control signal is input, and the overcurrent control is performed. A semiconductor integrated circuit comprising: an overcurrent control unit configured to control an overcurrent by controlling a signal level of a control signal supplied to control terminals of the first and second output transistors based on a signal; apparatus.

(Supplementary note 2) The semiconductor integrated circuit device according to supplementary note 1, wherein the first and second output transistors are an Nch MOS transistor, an Nch DMOS transistor, an Nch trench gate MOS transistor, an IGBT, or an NPN transistor.

(Supplementary Note 3) The semiconductor integrated circuit device according to Supplementary Note 1 or 2, wherein the first to third transistors are Nch MOS transistors or NPN transistors.

(Supplementary note 4) The semiconductor integrated circuit device according to any one of supplementary notes 1 to 3, wherein the first and second current mirror circuits are Wilson type current mirror circuits or cascode type current mirror circuits.

DESCRIPTION OF SYMBOLS 1, 4, 5 Overcurrent detection part 2 Overcurrent control part 3 Control part 11-13 Current source 14, 15 Comparator 21-23 Power supply 30, 31, 40 Overcurrent protection circuit 70-72, 80 Semiconductor integrated circuit device BF1, BF11, BF1n Buffer D1, DN1, DN11 Diode KR1 Variable resistor MDT1, MDT11 Output transistors MNT1-MNT4 Nch MOS transistors N1-N5, N11-N13 Node PVO Output terminals Q1-Q3 NPN transistor R1 Resistor Sin Input signal Skk Overcurrent detection signal Ssk Overcurrent control signal Sout Output signals Vb1 to Vb3 Voltage Vcc, Vdd High potential side power supply Vss Low potential side power supply (ground potential)

Claims (5)

An output transistor for outputting an output current from the first terminal to the output terminal;
A first current mirror circuit that causes a first current to flow on the first transistor side and a second current that is n times (where n> 1) the first current flows on the opposite second transistor side A first current is caused to flow on the first transistor side, and a third current that is (n + m) times (n + m)> n) of the first current on the opposite third transistor side. A second current mirror circuit for flowing, detecting an overcurrent detection signal from the first terminal of the second transistor, detecting an overcurrent control signal from the first terminal of the third transistor, An overcurrent detection unit in which second terminals of the second and third transistors are connected to a second terminal of the output transistor;
An overcurrent control unit that receives the overcurrent control signal and controls a signal level of a control signal supplied to a control terminal of the output transistor based on the overcurrent control signal to suppress overcurrent;
A semiconductor integrated circuit device comprising:   The overcurrent control unit includes a power source whose negative side is connected to a low potential side power source, one end connected to the positive side of the power source, and a voltage obtained by changing the voltage of the power source based on the overcurrent control signal at the other end A variable resistor that outputs from the side and a buffer that is supplied with the changed power supply voltage, changes the input signal level according to the changed power supply voltage, and outputs the changed input signal to the control terminal of the output transistor The semiconductor integrated circuit device according to claim 1, comprising:   3. The semiconductor integrated circuit device according to claim 1, wherein a current source is provided between a high-potential-side power source and the first terminals of the first to third transistors.   A resistor is provided between the second terminal of the output transistor and a low-potential side power supply, and the second terminals of the second and third transistors are connected between the second terminal of the output transistor and the resistor. The semiconductor integrated circuit device according to claim 1 or 3. An Nch MOS transistor for outputting an output current from the drain to the output terminal;
A resistor provided between the source of the Nch MOS transistor and a low-potential side power supply;
A first current is allowed to flow on the first NPN transistor side, and a second current is applied to the second NPN transistor side having an emitter area n times (where n> 1) that of the opposing first NPN transistor. The first current mirror circuit that flows and the emitter area of (n + m) times (where (n + m)> n) of the first NPN transistor facing each other by passing a first current on the first NPN transistor side A second current mirror circuit for flowing a third current on the third NPN transistor side, and a first to third current provided between a high-potential-side power supply and the collectors of the first to third NPN transistors, respectively. And detecting an overcurrent detection signal from the collector of the second NPN transistor, detecting an overcurrent control signal from the collector of the third NPN transistor, An overcurrent detector serial emitter of the second and third NPN transistor is connected between the resistor and the source of the Nch MOS transistor,
An overcurrent control unit that receives the overcurrent control signal and controls a signal level of a control signal supplied to a gate of the Nch MOS transistor based on the overcurrent control signal to suppress overcurrent;
A semiconductor integrated circuit device comprising:

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