JP2011249481A - Method of manufacturing wiring substrate, and method of manufacturing semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring substrate capable of forming a required-shaped resist pattern at a recessed portion including an inclined surface, and a method of manufacturing a semiconductor package mounting a semiconductor element in the recessed portion of the wiring substrate.SOLUTION: The method of manufacturing a wiring substrate comprises a first step of forming a recessed portion 14 having an inner bottom surface 14a and an inner surface 14b inclining to the inner bottom surface 14b, on one surface of a substrate body 11; a second step of forming a resist pattern at a part including the inner bottom surface and the inner surface on the one surface; and a third step of forming a wiring pattern corresponding to the resist pattern, at the part including the inner bottom surface and the inner surface on the one surface. The second step includes a step of forming a first resist pattern 21 for forming the wiring pattern on the inner surface, and a step of forming a second resist pattern 24 for forming the wiring pattern on the inner bottom surface.

Description

  The present invention relates to a method for manufacturing a wiring board having a recess including an inclined surface, and a method for manufacturing a semiconductor package in which a semiconductor element is mounted in the recess of the wiring board.

  Conventionally, a wiring board having a recess for mounting a semiconductor element on one surface has been known. The recess has, for example, an inner bottom surface that is substantially parallel to one surface of the wiring board and an inner side surface that is inclined with respect to the inner bottom surface (hereinafter referred to as an inclined surface). It is a shape that forms a large opening.

  An example of a method of forming a pattern in a recess in a wiring board having such a recess is as follows. That is, a resist is applied on a substrate having a copper foil formed on the entire surface having the recesses to cover the copper foil. Then, the resist is exposed and developed to pattern the resist so that only the portion of the copper foil wiring pattern is covered with the resist. And after removing only the copper foil of the part which is not covered with the resist by an etching etc., the resist which covered the copper foil is removed further, and a wiring pattern is formed on a board | substrate.

  As a method of exposing the resist, for example, a method of exposing through a mask on which a mask pattern corresponding to a wiring pattern is formed is known. In addition, as a method of exposing without using a mask, a method of directly drawing and exposing a laser beam corresponding to a wiring pattern by a method of controlling reflection of laser beam using a micromirror or the like is also known. Yes.

JP 2009-94409 A

  However, when the inclined surface is exposed through the mask, the exposure light is reflected by the inclined surface, and the reflected light may expose a portion that should not be exposed (for example, the inner bottom surface). There was a problem that it was difficult to pattern.

  In addition, in order to expose the inclined surface by directly drawing the laser beam, it is necessary to draw while tilting the substrate on which the resist is formed, but when the size of the substrate is relatively large, drawing is performed while tilting the substrate. This makes it difficult to pattern the resist into a desired shape.

  The present invention has been made in view of the above points, and a method of manufacturing a wiring board capable of forming a resist pattern having a desired shape in a recess including an inclined surface, and mounting a semiconductor element in the recess of the wiring board It is an object of the present invention to provide a method for manufacturing a semiconductor package.

  The method for manufacturing the wiring board includes a first step of forming a recess having an inner bottom surface and an inner surface inclined with respect to the inner bottom surface on one surface of the substrate body, the inner bottom surface of the one surface, and the A second step of forming a resist pattern on the portion including the inner surface; a third step of forming a wiring pattern corresponding to the resist pattern on the portion including the inner bottom surface and the inner surface of the one surface; And the second step includes a step of forming a first resist pattern for forming the wiring pattern on the inner side surface, and a second resist pattern for forming the wiring pattern on the inner bottom surface. And a step of forming the step.

  The manufacturing method of the present semiconductor package is required to include a step of mounting a semiconductor element in the concave portion of the wiring substrate manufactured by the manufacturing method of the wiring substrate according to the present invention.

  According to the disclosed technique, it is possible to provide a method for manufacturing a wiring board capable of forming a resist pattern having a desired shape in a recess including an inclined surface, and a method for manufacturing a semiconductor package in which a semiconductor element is mounted in the recess of the wiring board. .

It is sectional drawing which illustrates the wiring board which concerns on 1st Embodiment. FIG. 3 is a diagram (part 1) illustrating a manufacturing process of the wiring board according to the first embodiment; FIG. 6 is a diagram (part 2) illustrating the manufacturing process of the wiring board according to the first embodiment; FIG. 6 is a diagram (part 3) illustrating the manufacturing process of the wiring board according to the first embodiment; FIG. 9 is a diagram (No. 4) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a diagram (No. 5) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a diagram (No. 6) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 14 is a view (No. 7) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a diagram (No. 8) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a diagram (No. 9) for exemplifying the manufacturing process for the wiring board according to the first embodiment; FIG. 10 is a view (No. 10) illustrating the manufacturing step of the wiring board according to the first embodiment; FIG. 11 is a diagram (No. 11) illustrating the manufacturing process of the wiring substrate according to the first embodiment; FIG. 12 is a view (No. 12) illustrating the manufacturing step of the wiring board according to the first embodiment; It is FIG. (The 1) which illustrates the manufacturing process of the wiring board which concerns on a 1st comparative example. FIG. 10 is a second diagram illustrating a manufacturing process of a wiring board according to the first comparative example; It is FIG. (The 1) which illustrates the manufacturing process of the wiring board which concerns on a 2nd comparative example. It is FIG. (The 2) which illustrates the manufacturing process of the wiring board which concerns on a 2nd comparative example. It is FIG. (The 1) which illustrates the manufacturing process of the wiring board which concerns on the modification 1 of 1st Embodiment. FIG. 11 is a diagram (No. 2) for exemplifying the manufacturing process of the wiring board according to the first modification of the first embodiment; 6 is a cross-sectional view illustrating a semiconductor package according to a second embodiment; FIG. It is FIG. (The 1) which illustrates the manufacturing process of the semiconductor package which concerns on 2nd Embodiment. FIG. 9 is a second diagram illustrating a manufacturing process of a semiconductor package according to the second embodiment;

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description may be omitted.

<First Embodiment>
[Structure of Wiring Board According to First Embodiment]
FIG. 1 is a cross-sectional view illustrating a wiring board according to the first embodiment. Referring to FIG. 1, the wiring substrate 10 includes a substrate body 11, an insulating layer 12, and a wiring pattern 13.

  In the wiring substrate 10, the substrate body 11 is a member that forms the insulating layer 12 and the wiring pattern 13, and has a recess 14. The insulating layer 12 is formed on the surfaces 11 a and 11 b of the substrate body 11. The wiring pattern 13 includes conductive layers 13a and 13b. The wiring pattern 13 is formed on a planar portion (including an inner bottom surface 14a described later) and an inclined surface portion (including an inclined surface 14b described later) on the insulating layer 12.

  The recess 14 is formed on the surface 11 a of the substrate body 11. The recess 14 has an inner bottom surface 14a substantially parallel to the surface 11a and an inclined surface 14b that is an inner surface inclined with respect to the inner bottom surface 14a. The inclined surface 14b is formed so that the opening side of the recess 14 is wider than the inner bottom surface 14a. Note that a semiconductor element including a light emitting element and a light receiving element can be mounted in the recess 14.

  Various modifications can be made to the wiring board 10. For example, a solder resist layer may be provided in a predetermined portion on the wiring pattern 13, or a wiring pattern may be provided on the insulating layer 12 on the surface 11 b, and the wiring pattern 13 may be formed by via wiring penetrating the substrate body 11 and the insulating layer 12. You can connect. Further, three or more wiring patterns may be formed.

[Method for Manufacturing Wiring Board According to First Embodiment]
Next, a method for manufacturing a wiring board according to the first embodiment will be described. 2 to 13 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment.

  First, in the process shown in FIG. 2, the substrate body 11 is prepared. As a material of the substrate body 11, for example, silicon, ceramics, glass, or the like can be used. The planar shape of the substrate body 11 is not particularly limited, but may be, for example, a circle or a rectangle. In the present embodiment, the following description will be given taking as an example the case where a silicon wafer is used as the substrate body 11.

  As the substrate body 11, for example, a silicon wafer of 6 inches (about 150 mm), 8 inches (about 200 mm), 12 inches (about 300 mm) or the like can be used. The thickness of the substrate body 11 can be, for example, 0.625 mm (in the case of 6 inches), 0.725 mm (in the case of 8 inches), 0.775 mm (in the case of 12 inches), or the like. The substrate body 11 may be thinned using a backside grinder or the like.

  Next, in the steps shown in FIGS. 3 and 4, a recess 14 is formed in the surface 11 a of the substrate body 11 (FIG. 3 is a cross-sectional view of the substrate body 11, and FIG. 4 is a plan view of the substrate body 11). Specifically, for example, a resist having an opening corresponding to the position where the recess 14 is formed is formed on the surface 11 a of the substrate body 11. Then, the substrate body 11 exposed in the opening is subjected to anisotropic etching and isotropic etching using the resist as a mask. Thereby, the recessed part 14 which has the inclined surface 14b which is an inner surface which inclines with respect to the inner bottom face 14a and the inner bottom face 14a substantially parallel to the surface 11a is formed. The depth of the recess 14 may be appropriately set according to the thickness of the semiconductor element to be mounted in the recess, but may be about 100 to 500 μm, for example. The planar shape of the recess 14 is not limited to a quadrangle, and may be a circle or an ellipse.

Note that wet etching may be performed instead of anisotropic etching and isotropic etching. In this case, for example, an SiO ₂ film having an opening corresponding to the position where the recess 14 is formed is formed on the surface 11 a of the substrate body 11, and the substrate body 11 exposed in the opening of the SiO ₂ film is an aqueous potassium hydroxide solution. Etch wet etching or the like. Thereby, the recessed part 14 which has the inclined surface 14b which is the inner side face inclined to the inner bottom face 14a and the inner bottom face 14a substantially parallel to the surface 11a is formed.

Next, in the process shown in FIG. 5, the insulating layer 12 is formed on the surface of the substrate body 11. The insulating layer 12 is a film for insulating between the substrate body 11 and a wiring pattern 13 formed in a process to be described later, but also has a function of ensuring the stability and durability of the substrate body 11 over time. . As the insulating layer 12, for example, a thermal oxide film (SiO ₂ ) can be used. The insulating layer 12 can be formed by, for example, thermal oxidation using a wet thermal oxidation method in which the temperature near the surface of the substrate body 11 is 1000 ° C. or higher. The thickness of the insulating layer 12 can be about 1 to 2 μm, for example.

  The insulating layer 12 may be formed by forming benzocyclobutene (BCB) or the like on the surface of the substrate body 11 by a spin coating method or the like. The insulating layer 12 formed by spin coating or the like can be made thicker than the insulating layer 12 formed by thermal oxidation. By increasing the thickness of the insulating layer 12, it is possible to improve the insulation properties between the substrate body 11 and the wiring pattern 13 formed in the process described later.

  Next, in the step shown in FIG. 6, the conductive layer 13 a is formed on the insulating layer 12 on one side including the inside of the recess 14. The conductive layer 13a can be formed by sputtering, for example. As the conductive layer 13a, for example, a Ti / Cu layer (a metal layer obtained by laminating a Ti layer and a Cu layer in this order) or a Cr / Cu layer (a metal layer obtained by laminating a Cr layer and a Cu layer in this order) is used. Can do. The thickness of each layer constituting the conductive layer 13a is, for example, about 0.1 to 0.2 μm for the Ti layer, about 0.05 to 0.1 μm for the Cr layer, and about 0.1 to 0.5 μm for the Cu layer. be able to.

  Next, in a step shown in FIG. 7, a positive resist layer 21 is formed on the conductive layer 13a. Specifically, a positive resist layer 21 is formed by applying a liquid or paste positive resist made of a photosensitive resin composition on the conductive layer 13a by a spin coating method, a printing method, or the like. Alternatively, a positive resist layer 21 is formed by laminating a film-like positive resist made of a photosensitive resin composition on the conductive layer 13a. The thickness of the positive resist layer 21 can be, for example, about 10 μm. As the material of the positive resist layer 21, a phenol-based, novolak-based, polyimide-based, or silicon-based resist material can be used.

  Next, in the step shown in FIG. 8, the positive resist layer 21 is exposed and developed to form an opening 21x. Specifically, the positive resist layer 21 is irradiated with the exposure light 23 through the light shielding portion 22a patterned in a desired shape provided on the mask 22. The exposure light 23 passes through a portion other than the light shielding portion 22a of the mask 22 and is irradiated onto the positive resist layer 21 so that a predetermined portion of the positive resist layer 21 is exposed. Then, the exposed portion of the positive resist layer 21 is removed by etching using an alkaline developer or the like to form the opening 21x.

  The positive resist layer 21 having the opening 21x is a typical example of the first resist pattern according to the present invention, and the process shown in FIG. 8 is a representative of the process of forming the first resist pattern according to the present invention. An example.

  In this step, the inclined surface 14b on which the positive resist layer 21 is formed is exposed through the mask 22 to form openings 21x corresponding to the arrangement of the wiring patterns 13 on the inclined surface 14b. Also, in this step, almost the entire area of the inner bottom surface 14 a on which the positive resist layer 21 is formed is exposed, and almost the entire area of the inner bottom surface 14 a is exposed in the opening 21 x regardless of the arrangement of the wiring pattern 13.

  Thus, in this embodiment, a positive resist is always used as a resist for forming a wiring pattern on the inclined surface (inner side surface). Further, when exposing a portion including an inclined surface, the inner bottom surface is always exposed regardless of the presence or absence of the wiring pattern. The reason for this will be described later.

  Next, in a step shown in FIG. 9, a negative resist layer 24 is formed on the conductive layer 13a and the positive resist layer 21 exposed in the opening 21x. Specifically, a liquid or paste negative resist made of a photosensitive resin composition is applied onto the conductive layer 13a and the positive resist layer 21 exposed in the opening 21x by a spin coating method, a printing method, or the like. Then, a negative resist layer 24 is formed. Alternatively, a negative resist layer 24 is formed by laminating a film-like negative resist made of a photosensitive resin composition on the conductive layer 13a and the positive resist layer 21 exposed in the opening 21x. The thickness of the negative resist layer 24 can be, for example, about 10 μm. As a material for the negative resist layer 24, a resist material such as phenol, novolac, polyimide, or silicon can be used.

  Next, in the step shown in FIG. 10, the negative resist layer 24 is exposed and developed to form openings 24x. Specifically, the negative resist layer 24 is irradiated with exposure light 26 through a light shielding portion 25a patterned in a desired shape provided on the mask 25. The exposure light 26 passes through a portion other than the light shielding portion 25a of the mask 25, and is irradiated onto the negative resist layer 24, whereby a predetermined portion of the negative resist layer 24 is exposed. Then, an unexposed portion of the negative resist layer 24 is removed by etching using a developer containing an organic solvent or the like to form an opening 24x.

  The negative resist layer 24 having the opening 24x is a typical example of the second resist pattern according to the present invention, and the process shown in FIG. 10 is a typical process for forming the second resist pattern according to the present invention. An example.

  In this step, the inner bottom surface 14a on which the negative resist layer 24 is formed is exposed through a mask 25 to form an opening 24x corresponding to the arrangement of the wiring pattern 13 on the inner bottom surface 14a. In this step, the negative resist layer 24 formed on the inclined surface 14b and the negative resist layer 24 formed on the portion other than the recess 14 are removed, and a positive resist is used in the step shown in FIG. The formed resist pattern is exposed. As shown in FIG. 10, a portion where a part of the positive resist layer 21 and a part of the negative resist layer 24 overlap may be generated.

  As a result, a resist pattern made of a positive resist corresponding to the arrangement of the wiring pattern 13 is formed on a portion other than the inclined surface 14b and the concave portion 14, and a negative type corresponding to the arrangement of the wiring pattern 13 is formed on the inner bottom surface 14a. A resist pattern composed of the resist layer 24 was formed.

  However, a resist pattern made of a positive resist must always be formed on the inclined surface 14b, and a resist pattern made of a negative resist must be formed on the inner bottom surface 14a. A resist pattern made of a resist may not be formed, and a resist pattern made of a negative resist may be formed.

  In this step, the reason why only the inner bottom surface is exposed regardless of the presence or absence of the wiring pattern will be described later.

  Next, in the step shown in FIG. 11, the conductive layer 13b is formed on the conductive layer 13a exposed in the openings 21x and 24x. The conductive layer 13b can be formed by, for example, an electrolytic plating method using the conductive layer 13a as a power feeding layer. For example, a Cu layer or the like can be used as the conductive layer 13b.

  After the conductive layer 13b is formed on the conductive layer 13a, an Au layer, a Ni / Au layer (a metal layer obtained by laminating a Ni layer and an Au layer in this order), a Ni / Pd / Au layer is further formed on the conductive layer 13b. (A metal layer in which a Ni layer, a Pd layer, and an Au layer are stacked in this order) may be formed. The thickness of the metal layer formed on the conductive layer 13b can be, for example, about 0.5 to 5 μm. The metal layer formed on the conductive layer 13b is provided to improve connection reliability when the wiring pattern 13 is connected to a semiconductor element.

  Next, in the step shown in FIG. 12, the resist layers 21 and 24 shown in FIG. 11 are removed. The resist layers 21 and 24 can be removed with a stripping solution. As an example of the stripping solution, ethanolamine amines such as monoethanolamine, diethanolamine, and triethanolamine can be used. Moreover, you may use the liquid mixture of ethanolamine amine, and polar solvents, such as DMF (dimethylformamide), DMSO (dimethylsulfoxide), and NMP (N-methyl-2 pyrrolidone).

  Next, in the step shown in FIG. 13, using the conductive layer 13b as a mask, the portion of the conductive layer 13a not covered with the conductive layer 13b is removed by etching. Thereby, the wiring pattern 13 including the conductive layer 13a and the conductive layer 13b is formed. Thereafter, the wiring substrate 10 shown in FIG. 1 is completed by dividing into pieces at predetermined positions.

  In the first embodiment, the example in which the wiring pattern 13 is formed by the semi-additive method is shown. However, the wiring pattern 13 can be formed using various wiring forming methods such as a subtractive method, a lift-off method, and an aerosol deposition method in addition to the semi-additive method.

  Here, in order to form the wiring pattern on the inclined surface (inner side surface) in the step shown in FIG. 8 of the first embodiment with reference to the manufacturing method of the wiring board according to the first and second comparative examples. The positive resist is always used as the resist, the inclined surface is exposed and the inner bottom is always exposed, and in the process shown in FIG. 10, the negative resist is used as the resist for forming the wiring pattern on the inner bottom. The reason for exposing only the light will be described.

  14 and 15 are diagrams illustrating the manufacturing process of the wiring board according to the first comparative example. In the manufacturing process of the wiring substrate according to the first embodiment, a resist pattern corresponding to the wiring pattern 13 was formed using the positive resist layer 21 and the negative resist layer 24 in the exposure and development processes. On the other hand, in the manufacturing process of the wiring board according to the first comparative example, an attempt is made to form a resist pattern corresponding to the wiring pattern 13 using only the positive resist layer 21 in the exposure and development processes. is there.

  First, steps similar to those in FIGS. 2 to 7 of the manufacturing process of the wiring board according to the first embodiment are performed. In the step shown in FIG. 14, the positive resist layer 21 formed in the step shown in FIG. 7 is exposed and developed to form the opening 21x. The light shielding part 22b of the mask 22 used in the process shown in FIG. 14 is different in the patterned shape from the light shielding part 22a of the mask 22 used in the process of FIG. Specifically, the light shielding portion 22b has a pattern in which positions corresponding to all the wiring patterns 13 including the inner bottom surface 14a and the inner side surface 14b are exposed.

  However, the exposure light 23 applied to the inclined surface 14b through the light shielding portion 22b provided on the mask 22 is reflected by the inclined surface 14b and applied to a part of the inner bottom surface 14a. As a result, a part of the positive resist layer 21 covering the inner bottom surface 14a that should not be exposed is exposed. Thereafter, as shown in the lower diagram of FIG. 14, when the positive resist layer 21 is developed, the broken line portion 21 y of the positive resist layer 21 that should originally exist is removed. As a result, when the same processes as those in FIGS. 11 to 13 of the manufacturing process of the wiring board according to the first embodiment are performed, an unnecessary wiring pattern 13y is formed as shown in FIG. The wiring pattern 13 (see FIG. 13) cannot be formed.

  Thus, when manufacturing a wiring board in which the wiring pattern 13 is formed in a portion including the inclined surface 14b, only the positive resist layer 21 is used in the exposure and development processes, and the resist pattern is formed only in one exposure / development process. When the pattern is formed, a resist pattern corresponding to the wiring pattern 13 cannot be formed. As a result, the wiring pattern 13 having a desired shape cannot be obtained.

  Next, the manufacturing process of the wiring board according to the second comparative example will be described. 16 and 17 are diagrams illustrating the manufacturing process of the wiring board according to the second comparative example. In the manufacturing process of the wiring substrate according to the first embodiment, a resist pattern corresponding to the wiring pattern 13 was formed using the positive resist layer 21 and the negative resist layer 24 in the exposure and development processes. On the other hand, in the manufacturing process of the wiring substrate according to the second comparative example, an attempt is made to form a resist pattern corresponding to the wiring pattern 13 using only the negative resist layer 24 in the exposure and development processes. is there.

  First, the same processes as those in FIGS. 2 to 6 of the manufacturing process of the wiring board according to the first embodiment are performed. In the step shown in FIG. 16, after forming the negative resist layer 24 on the conductive layer 13a, the negative resist layer 24 is exposed and developed to form the opening 24x. The light shielding part 22c of the mask 22 used in the process shown in FIG. 16 is different in the patterned shape from the light shielding part 22a of the mask 22 used in the process of FIG. Specifically, the light shielding portion 22c has a pattern in which positions corresponding to all the wiring patterns 13 including the inner bottom surface 14a and the inner side surface 14b are not exposed.

  However, the exposure light 23 applied to the inclined surface 14b through the light shielding portion 22c provided on the mask 22 is reflected by the inclined surface 14b and applied to a part of the inner bottom surface 14a. As a result, a part of the negative resist layer 24 covering the inner bottom surface 14a that should not be exposed is exposed. Thereafter, as shown in the lower diagram of FIG. 16, when the negative resist layer 24 is developed, the broken line portion 24y of the negative resist layer 24 that should be removed is not removed. As a result, when the same steps as those in FIGS. 11 to 13 of the manufacturing process of the wiring board according to the first embodiment are performed, the necessary wiring pattern 13z is not formed as shown in FIG. The power wiring pattern 13 (see FIG. 13) cannot be formed.

  Thus, when manufacturing a wiring board in which the wiring pattern 13 is formed in a portion including the inclined surface 14b, only the negative resist layer 24 is used in the exposure and development processes, and the resist pattern is formed only in one exposure / development process. When the pattern is formed, a resist pattern corresponding to the wiring pattern 13 cannot be formed. As a result, the wiring pattern 13 having a desired shape cannot be obtained.

  Therefore, in the first embodiment, a resist pattern forming step includes a step of forming a resist pattern for forming a wiring pattern on an inclined surface (inner side surface) using a positive resist, and a negative resist. This is divided into the steps of forming a resist pattern for forming a wiring pattern on the inner bottom surface. That is, in the step shown in FIG. 8, the positive resist is used to expose the portion including the inclined surface and the inner bottom surface is always exposed, and in the step shown in FIG. 10, only the inner bottom surface is exposed using the negative resist. . However, either the inclined surface (inner surface) or the inner bottom surface (flat surface) may be exposed first.

  For the same reason as in Comparative Examples 1 and 2, a negative resist is used as a resist for forming a wiring pattern on the inclined surface (inner side surface), and a positive resist is used as a resist for forming the wiring pattern on the inner bottom surface. When is used, the wiring pattern 13 having a desired shape cannot be obtained.

  In this way, the resist pattern forming step is performed by using a positive resist to form a resist pattern for forming a wiring pattern on the inclined surface (inner side surface) and using a negative resist on the inner bottom surface. By dividing the process into a resist pattern for forming a pattern, even when manufacturing a wiring board on which a wiring pattern is formed on a portion including an inclined surface, the influence of exposure light reflection by the inclined surface should be ignored. Can do. As a result, even when manufacturing a wiring board in which a wiring pattern is formed on a portion including an inclined surface, a resist pattern corresponding to the wiring pattern can be formed, and a desired wiring pattern can be formed.

  In addition, since a wiring pattern can be formed on an inclined surface in a wiring substrate including an inclined surface, the degree of freedom in designing the wiring pattern on the wiring substrate can be improved.

<Variation 1 of the first embodiment>
In the first embodiment, an example in which the portion including the inclined surface is first exposed in the step shown in FIG. 8, and then only the inner bottom surface is exposed in the step shown in FIG. The first modification of the first embodiment shows an example in which the order of the steps is changed, only the inner bottom surface is exposed first, and then the portion including the inclined surface is exposed. In Modification 1 of the first embodiment, the steps other than the exposure and development steps are the same as those in the first embodiment, and thus the description thereof is omitted.

  18 and 19 are diagrams illustrating the manufacturing process of the wiring board according to the first modification of the first embodiment. First, in the step shown in FIG. 18, after forming a negative resist layer 24 on the conductive layer 13a, the negative resist layer 24 is exposed and developed to form an opening 24x. Specifically, the negative resist layer 24 is irradiated with exposure light 26 through a light shielding portion 25a patterned in a desired shape provided on the mask 25. The exposure light 26 passes through a portion other than the light shielding portion 25a of the mask 25, and is irradiated onto the negative resist layer 24, whereby a predetermined portion of the negative resist layer 24 is exposed. Then, an unexposed portion of the negative resist layer 24 is removed by etching using a developer containing an organic solvent or the like to form an opening 24x.

  The opening 24x is formed at a position corresponding to the wiring pattern 13 on the inner bottom surface 14a. Further, the opening 24x is not formed in a portion other than the inner bottom surface 14a regardless of the presence or absence of the wiring pattern 13. Thus, in this step, a negative resist is used and only the inner bottom surface is exposed.

  The negative resist layer 24 having the opening 24x is a typical example of the second resist pattern according to the present invention, and the process shown in FIG. 18 is a typical process for forming the second resist pattern according to the present invention. An example.

  Next, in the step shown in FIG. 19, after forming the positive resist layer 21 on the conductive layer 13a and the negative resist layer 24 exposed in the opening 24x, the positive resist layer 21 is exposed and developed to open the opening. Part 21x is formed. Specifically, the positive resist layer 21 is irradiated with the exposure light 23 through the light shielding portion 22a patterned in a desired shape provided on the mask 22. The exposure light 23 passes through a portion other than the light shielding portion 22a of the mask 22 and is irradiated onto the positive resist layer 21 so that a predetermined portion of the positive resist layer 21 is exposed. Then, the exposed portion of the positive resist layer 21 is removed by etching using an alkaline developer or the like to form the opening 21x.

  The positive resist layer 21 having the opening 21x is a typical example of the first resist pattern according to the present invention, and the process shown in FIG. 19 is a typical process for forming the first resist pattern according to the present invention. An example.

  As shown in FIG. 19, a portion where a part of the negative resist layer 24 and a part of the positive resist layer 21 overlap may be generated.

  The opening 21x is formed at a position corresponding to the wiring pattern 13 except for the inner bottom surface 14a. The opening 21x is formed on the inner bottom surface 14a regardless of the presence or absence of the wiring pattern 13. That is, the inner bottom surface 14a is necessarily exposed by the opening 21x, but the inner bottom surface 14a has an opening 24x formed at a position corresponding to the wiring pattern 13 in the step shown in FIG. Eventually, an opening 21x is formed at a position corresponding to the wiring pattern 13 in a portion other than the inner bottom surface 14a, and an opening 24x is formed at a position corresponding to the wiring pattern 13 in the inner bottom surface 14a.

  That is, at this stage, a resist pattern corresponding to the wiring pattern 13 is formed by the openings 21x and 24x. Thus, a resist pattern corresponding to the wiring pattern 13 was formed by the positive resist layer 21 and the negative resist layer 24.

  In this way, after using negative resist to expose only the inner bottom surface regardless of the presence or absence of the wiring pattern, the positive resist is used to expose the portion including the inclined surface and whether or not the wiring pattern exists. Even in the step of always exposing the bottom surface, the same effects as those of the first embodiment can be obtained.

<Modification 2 of the first embodiment>
In the first embodiment, the negative resist layer 24 is formed on the positive resist layer 21 in the step shown in FIG. In this case, depending on the combination of the materials of the positive resist layer 21 and the negative resist layer 24, the positive resist layer 21 previously resist-patterned may be dissolved by forming the negative resist layer 24. In that case, before the negative resist layer 24 is formed, if the positive resist layer 21 previously resist-patterned is cured and thermally cured, the positive resist layer 21 is formed by forming the negative resist layer 24. It is preferable because dissolution can be prevented.

  The curing is preferably performed in a vacuum atmosphere or a nitrogen atmosphere. This is to prevent damage to the conductive layer exposed from the resist layer. At this time, the curing temperature and the curing time can be appropriately determined according to the material used for the resist layer.

  In Modification 1 of the first embodiment, since the positive resist layer 21 is formed on the negative resist layer 24, the negative resist layer 24 previously resist-patterned is cured and thermally cured. The dissolution of the negative resist layer 24 by forming the positive resist layer 21 is preferable.

  In the first embodiment and the first modification thereof, the positive resist layer 21 or the negative resist layer 24 may be cured by irradiating light stronger than the exposure light instead of curing.

  Note that a resist layer cured by curing or the like is less likely to be peeled than a resist layer that is not cured. The resist layer cured by curing or the like can be peeled off using the stripping solution described in the step shown in FIG. 12, but it is preferable to use a stronger stripping solution. For example, it is preferable to use a mixed solution of an ethanolamine amine and a polar solvent of DMSO (dimethyl sulfoxide).

  In addition, when one of the positive resist layer 21 and the negative resist layer 24 is more difficult to be peeled when cured by curing or the like than the other, it has a property to be difficult to peel when cured by curing or the like. It is preferable to form the weaker resist layer first. This is because the resist layer to be formed later does not need to be cured by curing or the like. Therefore, in such a case, the process order of the first embodiment and the process order of the first modification of the first embodiment may be appropriately selected. Note that the negative resist layer has a stronger material than the positive resist layer in that it is difficult to peel off when cured by curing or the like.

  As is clear from the steps shown in FIGS. 10 and 19, the negative resist layer 24 has a smaller area after exposure and development than the positive resist layer 21. Therefore, if the properties of the positive resist layer 21 and the negative resist layer 24 that are difficult to peel off by curing are equal, the negative resist layer 24 is first resist-patterned and cured by curing or the like. It is preferable to form the positive resist layer 21 after the etching. This is because the amount of the resist layer that has been hardened by curing or the like and difficult to peel off can be reduced with a stripping solution.

  In this manner, by dissolving another resist layer after curing the resist layer previously resist-patterned, dissolution of the resist layer previously resist-patterned can be prevented.

<Modification 3 of the first embodiment>
In the first embodiment, in the step shown in FIG. 8, the portion of the positive resist layer 21 where the concave portion 14 of the substrate body 11 is not formed, the inclined surface 14 b, and the inner bottom surface 14 a are interposed via one mask 22. Were simultaneously exposed and then developed to form openings 21x in each. At this time, the portion where the concave portion 14 is not formed, the inclined surface 14b, and the inner bottom surface 14a are different in distance from the light source that emits the exposure light. Further, since the exposure light 23 is not completely parallel light, it is necessary to focus on one of them. In the process shown in FIG. 8, for example, all the portions can be exposed at the same time while focusing on the inclined surface 14b.

  However, in order to form the opening 21x with higher accuracy, exposure may be performed a plurality of times. For example, three masks each having a predetermined light-shielding part are prepared, and the exposure light 23 is first focused on the part where the concave part 14 is not formed, and then only the part where the concave part 14 is not formed is exposed. The exposure light 23 is focused on the inclined surface 14b to expose only the inclined surface 14b, and the exposure light 23 is focused on the inner bottom surface 14a to expose only the inner bottom surface 14a.

  In this way, in the resist layer, when exposing portions where the distance from the light source that emits the exposure light to the resist layer is different, the resist layer is exposed after focusing on each exposed portion in multiple steps. Can be formed with higher accuracy.

<Second Embodiment>
[Structure of Semiconductor Package According to Second Embodiment]
FIG. 20 is a cross-sectional view illustrating a semiconductor package according to the second embodiment. Referring to FIG. 20, the semiconductor package 50 includes the wiring substrate 10 shown in FIG. 1, a semiconductor element 51, and solder bumps 55. The semiconductor element 51 is mounted (flip chip connection) in the recess 14 of the wiring board 10.

  The semiconductor element 51 is a light emitting element such as a laser diode, for example, and includes a semiconductor substrate 52 and an electrode pad 53. The semiconductor substrate 52 is obtained by forming a semiconductor integrated circuit (not shown) on a substrate made of, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. The semiconductor element 51 has, for example, a function of irradiating light laterally (in the planar direction of the semiconductor package 50), and the light emitted laterally from the semiconductor element 51 is the wiring pattern 13 formed on the inclined surface 14b. And proceed in the direction of the arrow (direction perpendicular to the planar direction of the semiconductor package 50). In order to improve the reflection characteristics of the light emitted from the semiconductor element 51, a resin film or the like having a high reflectance may be formed on the wiring pattern 13 formed on the inclined surface 14b.

  The electrode pad 53 is formed on one side of the semiconductor substrate 52 and is electrically connected to a semiconductor integrated circuit (not shown). As a material of the electrode pad 53, for example, aluminum (Al) or the like can be used. As the material of the electrode pad 53, a material obtained by laminating copper (Cu) and aluminum (Al) in this order, a material obtained by laminating copper (Cu), aluminum (Al), and silicon (Si) in this order may be used. I do not care.

  The solder bump 55 electrically connects the wiring pattern 13 formed on the inner bottom surface 14 a of the recess 14 of the wiring substrate 10 and the electrode pad 53 of the semiconductor element 51. As a material of the solder bump 55, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used. An underfill resin may be filled in the peripheral portion of the solder bump 55 (excluding the light emitting portion of the semiconductor element 51).

[Method of Manufacturing Semiconductor Package According to Second Embodiment]
Next, a method for manufacturing a semiconductor package according to the second embodiment will be described. 21 and 22 are views illustrating the manufacturing process of the semiconductor package according to the second embodiment.

  First, in the step shown in FIG. 21, the wiring board 10 before separation is prepared, and the pre-solder 58 is formed on the wiring pattern 13 formed on the inner bottom surface 14 a of the recess 14 of the wiring board 10. Further, the semiconductor element 51 is prepared, and the pre-solder 59 is formed on the electrode pad 53. The pre-solders 58 and 59 apply a solder paste made of, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu on the wiring pattern 13 and the electrode pad 53. It can be formed by performing reflow.

  Next, in the step shown in FIG. 22, the pre-solders 58 and 59 are arranged at the corresponding positions with the concave portion 14 side of the wiring substrate 10 and the electrode pad 53 side of the semiconductor element 51 facing each other. Then, by heating the pre-solders 58 and 59 to, for example, 230 ° C., the pre-solders 58 and 59 are melted into one alloy, and the solder bumps 55 are formed. Further, after the solder bumps 55 are formed, the semiconductor package 50 shown in FIG. 20 is completed by dividing into pieces using a dicing blade or the like.

  As described above, a semiconductor package in which a semiconductor element is mounted on the wiring board according to the first embodiment can be manufactured. The semiconductor element mounting method is not limited to flip-chip connection, and connection using wire bonding may be used. Alternatively, a separated wiring board may be prepared and a semiconductor element may be mounted.

  The preferred embodiment and its modification have been described in detail above, but the present invention is not limited to the above-described embodiment and its modification, and the above-described implementation is performed without departing from the scope described in the claims. Various modifications and substitutions can be added to the embodiment and its modifications.

  For example, in the steps shown in FIGS. 10 and 19, the opening on the inclined surface of the substrate body must be formed with a positive resist, and the opening on the inner bottom surface of the substrate body must be formed with a negative resist. However, the openings other than the recesses (other than the inclined surface and the inner bottom surface) of the substrate body may be formed of a negative resist instead of a positive resist.

DESCRIPTION OF SYMBOLS 10 Wiring board 11 Substrate body 11a, 11b surface 12 Insulating layer 13 Wiring pattern 13a, 13b Conductive layer 13y, 13z Unnecessary wiring pattern 14 Recess 14a Inner bottom surface 14b Inclined surface 21 Positive resist layer 21x, 24x Opening 21y, 24y Broken line Part 22, 25 Mask 22a, 22b, 22c, 25a Light-shielding part 23, 26 Exposure light 24 Negative resist layer 50 Semiconductor package 51 Semiconductor element 52 Semiconductor substrate 53 Electrode pad 55 Solder bump 58, 59 Pre-solder

Claims (10)

A first step of forming a recess having an inner bottom surface and an inner surface inclined with respect to the inner bottom surface on one surface of the substrate body;
A second step of forming a resist pattern on a portion including the inner bottom surface and the inner side surface of the one surface;
A third step of forming a wiring pattern corresponding to the resist pattern in a portion including the inner bottom surface and the inner side surface of the one surface;
The second step includes
Forming a first resist pattern for forming the wiring pattern on the inner surface;
Forming a second resist pattern for forming the wiring pattern on the inner bottom surface. In the second step,
The method for manufacturing a wiring board according to claim 1, wherein the first resist pattern is formed using a positive resist. In the second step,
3. The method of manufacturing a wiring board according to claim 1, wherein, of the first resist pattern and the second resist pattern, the resist pattern formed first is cured, and then the other resist pattern is formed. 4. In the second step,
The method for manufacturing a wiring board according to claim 3, wherein the previously formed resist pattern is cured by heating. In the second step,
The method for manufacturing a wiring board according to claim 3, wherein the resist pattern formed earlier is cured by irradiating light stronger than exposure light.   The wiring according to any one of claims 3 to 5, wherein the previously formed resist pattern is formed by using a resist having a weaker property that is difficult to be peeled off when cured, of a positive resist and a negative resist. A method for manufacturing a substrate.   If the previously formed resist pattern has the same property that the positive resist and the negative resist are difficult to peel off when cured, the negative resist is reduced in area after exposure and development. The method for manufacturing a wiring board according to claim 3, wherein the wiring board is formed by using the wiring board.   The wiring board according to any one of claims 1 to 7, wherein a plurality of exposures are performed in one or both of the step of forming the first resist pattern and the step of forming the second resist pattern. Manufacturing method. Either or both of the step of forming the first resist pattern and the step of forming the second resist pattern are:
At least two of the step of focusing the exposure light on the inner bottom surface, the step of focusing the exposure light on the inner side surface, and the step of focusing the exposure light on a portion other than the inner bottom surface and the inner side surface. The manufacturing method of the wiring board of Claim 8 containing.   A method for manufacturing a semiconductor package, comprising: mounting a semiconductor element in the recess of the wiring substrate manufactured by the method for manufacturing a wiring substrate according to claim 1.

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