JP2011248603A - Ic chip, ic card, and operation method of ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IC chip, an IC card, and an operation method of the IC chip that can avoid a stop of a CPU operation even when an internal oscillator provided on the IC chip has a fault.SOLUTION: A CPU of the IC chip according to the present invention reads an identifier from a non-volatile memory when timing of switching from an external clock signal to an internal clock signal arrives, performs an operation for executing a processing instruction using the external clock signal if the read identifier is a first identifier indicating inoperability by the internal clock signal, and performs the operation for executing the processing instruction by switching from the external clock signal to the internal clock signal if the read identifier is a second identifier indicating operability by the internal clock signal.

Description

  The present invention relates to the field of technology for improving the reliability of an IC chip mounted on an IC card.

  Conventionally, IC cards have been widely used in various fields such as finance, communication, and transportation. An IC chip (for example, a one-chip microcomputer) mounted on an IC card includes a type in which a CPU is operated by a clock signal (hereinafter referred to as “external clock”) generated by an external device such as a reader / writer, and an IC chip. Can be broadly classified into those that operate the CPU by a clock signal (hereinafter referred to as “internal clock”) generated by an internal oscillator (oscillator) included in the CPU. Since the internal oscillator is an analog element, it is difficult to reduce the size of the internal oscillator. For applications such as smart cards defined in ISO / IEC7816, an operation method using an external clock tends to be adopted.

  On the other hand, conventionally, there has been proposed a technique for preventing processing contents and confidential information in an IC chip from being estimated and improving security. For example, in the technique disclosed in Patent Document 1, the content of encryption processing and the decryption of the encryption key can be prevented by changing the timing of an appropriate data processing operation according to the data processing procedure.

  In addition, in order to improve security, an IC chip that employs a method of performing data communication with an external device using an external clock generated by the external device and operating the CPU using the internal clock generated by the internal oscillator has been adopted. It was. According to such an IC chip, since the external clock and the internal clock are not synchronized, it is possible to effectively avoid an attack technique in which the processing content of the IC chip is estimated and asset information such as an encryption key is leaked.

JP 2000-259799 A

  By the way, in the case of an IC chip that communicates data with an external device using an external clock and operates the CPU using an internal clock, the internal clock frequency is higher than the external clock frequency. However, it becomes possible to speed up the processing. For this reason, it is desirable to operate the CPU with an internal clock from the initial state, for example, at the time of IC chip operation check.

  However, the internal oscillator provided in the IC chip is an analog element, which is more likely to vary depending on the manufacturing lot than the digital element, and when there is a malfunction (failure, etc.) in the internal oscillator, the external clock is switched to the internal clock. There is a problem that the operation of the CPU sometimes stops.

  Therefore, the present invention has been made in view of such problems and the like, and an IC chip capable of avoiding the stop of the operation of the CPU even if the internal oscillator provided in the IC chip has a problem. Another object is to provide a method for operating an IC card and an IC chip.

  In order to solve the above-mentioned problem, the invention according to claim 1 is an IC chip capable of transmitting / receiving a signal to / from an external device, and an input means for inputting an external clock signal from the external device. And an internal clock signal generating means for generating an internal clock signal, a read-only memory for storing a program for defining a plurality of processing instructions, and an operation for executing the processing instructions by the external clock signal or the internal clock signal A non-volatile memory for storing an arithmetic processing means and a first identifier representing inoperability by the internal clock signal, and the first identifier can be rewritten from the outside to a second identifier representing operation by the internal clock signal A nonvolatile memory, and the arithmetic processing means switches from the external clock signal to the internal clock signal. When the imming arrives, the identifier is read from the nonvolatile memory, and when the read identifier is the first identifier, an operation of executing the processing instruction is performed by the external clock signal, When the read identifier is the second identifier, an operation of executing the processing instruction by switching from the external clock signal to the internal clock signal is performed.

  According to a second aspect of the present invention, in the IC chip according to the first aspect, the first identifier is stored in the nonvolatile memory in an initial state before the operation check inspection of the IC chip. Features.

  According to a third aspect of the present invention, the IC card according to the first or second aspect is mounted.

  According to a fourth aspect of the present invention, there is provided input means for inputting an external clock signal from an external device, internal clock signal generation means for generating an internal clock signal, and a read-only memory for storing a program for defining a plurality of processing instructions. A non-volatile memory for storing an arithmetic processing means for performing an operation of executing the processing instruction by the external clock signal or the internal clock signal, and a first identifier representing an inoperability by the internal clock signal. A non-volatile memory that is rewritable from the outside to a second identifier indicating that the identifier can be operated by an internal clock signal, wherein the arithmetic processing means is configured to transmit the internal clock signal to the internal clock signal. Read the identifier from the non-volatile memory when the timing to switch to the clock signal arrives And when the read identifier is the first identifier, the arithmetic processing means performs an operation of executing the processing instruction by the external clock signal, and the read identifier Is the second identifier, the arithmetic processing means includes a step of switching the external clock signal to the internal clock signal and executing the processing instruction.

  According to the present invention, the processing speed can be increased, and even if the internal oscillator provided in the IC chip has a problem, the operation of the CPU as the arithmetic processing means can be prevented from stopping. .

It is a block diagram which shows the example of a schematic structure of the IC chip mounted in an IC card. (A) is a conceptual diagram showing an example of stored contents in the EEPROM 17, and (B) is a conceptual diagram showing an example of set contents in the internal oscillator control register 14. FIG. 4 is a diagram showing a part of processing instructions stored in a ROM 15. It is a flowchart which shows the operation example of CPU18.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiment described below is an embodiment when the present invention is applied to an IC card.

  First, the configuration and functional outline of an IC chip (microcomputer) according to the present embodiment will be described with reference to FIG. The IC chip according to the present embodiment can transmit and receive signals to and from an external device such as a reader / writer.

  FIG. 1 is a block diagram illustrating a schematic configuration example of an IC chip mounted on an IC card. As shown in FIG. 1, an IC chip 1 includes an I / O port 11, an internal oscillator (oscillator) 12, a clock divider / multiplier circuit 13, an internal oscillator control register 14, a ROM (Read Only Memory) 15, a RAM (Random An access memory 16, an EEPROM (Electrical Erasable Programmable Read Only Memory) 17, a CPU (Central Processing Unit) 18, and the like are included. The IC chip 1 includes a power supply terminal Vcc, a power supply reference potential terminal Vss, a reset input terminal RES bar, a clock terminal CLK, a data terminal I / O-1 / IRQ bar, and a data terminal I / O-2 / IRQ bar. Etc. are provided. The clock terminal CLK is an example of input means for inputting an external clock (for example, an external clock having a clock frequency of about 3.5 MHz) from an external device.

  The I / O port 11 receives (inputs) a data signal from an external device or transmits (outputs) a data signal to the external device.

  The internal oscillator 12 is an example of an internal clock signal generating unit that includes, for example, a crystal oscillator and generates an internal clock (for example, an internal clock having a clock frequency of 20 MHz to 30 MHz).

  The clock divider / multiplier circuit 13 includes a multiplier circuit, a divider circuit, a selector, and the like. The clock divider / multiplier circuit 13 receives an external clock input from an external device via the clock terminal CLK, and forms a system clock synchronized with the external clock. Supply to the address bus. The clock divider / multiplier circuit 13 receives the internal clock generated by the internal oscillator 12, forms a system clock synchronized with the internal clock, and supplies it to the address bus. Note that the external clock and the internal clock are asynchronous.

  The internal oscillator control register 14 is an 8-bit register, for example, and the stop or use of the internal oscillator 12 can be controlled by a state (0 or 1) of a predetermined bit (for example, the first 7 bits). For example, when the state of the predetermined bit of the internal oscillator control register 14 is “1”, the internal oscillator 12 is in a use state, and the internal clock generated by the internal oscillator 12 is supplied to the CPU 18 via the address bus as a system clock. It becomes possible.

  The ROM 15 is a read-only memory that retains stored information even when power supply is stopped, and stores a program that defines a plurality of processing instructions (for example, data reception such as signal reception and decryption). .

  The EEPROM 17 is a non-volatile memory in which stored information can be rewritten, and once written information is retained even when power supply is stopped. The EEPROM 17 may be a flash memory. The EEPROM 17 stores an identifier representing the operation mode. This operation mode includes an internal clock operation enable mode (operation by an internal clock) and an internal clock operation lock mode (inability to operate by an internal clock), and identifiers representing the respective modes are different from each other.

  FIG. 2A is a conceptual diagram showing an example of the contents stored in the EEPROM 17, and FIG. 2B is a conceptual diagram showing an example of the setting contents in the internal oscillator control register 14. In an initial state before the operation check inspection of the IC chip 1, as shown in FIG. 2, the EEPROM 17 stores an identifier (first identifier) indicating the internal clock operation lock mode. In this case, the leading seventh bit of the internal oscillator control register 14 is set to “0”. On the other hand, when an identifier representing the internal clock operable mode (second identifier) is stored in the EEPROM 17, the first 7 bits of the internal oscillator control register 14 are set to “1”.

  The rewriting of the operation mode stored in the EEPROM 17 is performed by a rewrite instruction signal input to the IC chip 1 from an external device, for example, by the operation check inspector of the IC chip 1.

  The CPU 18 is an example of arithmetic processing means for performing an operation (reading a processing instruction stored in the ROM 15 and an operation corresponding to the instruction) to execute the processing instruction using an external clock or an internal clock. That is, the CPU 18 receives a system clock (formed by an external clock or an internal clock) supplied from the clock divider / multiplier circuit 13 via the address bus, and operates at an operation timing and period determined by the system clock. In addition, the CPU 18 performs transmission / reception control of data signals via the I / O port 11 and control of data writing and reading operations to the RAM 16 and the EEPROM 17.

  Next, an operation example of the IC chip 1 according to the present embodiment will be described with reference to FIGS.

  FIG. 3 is a diagram showing a part of the processing instructions stored in the ROM 15. FIG. 4 is a flowchart illustrating an operation example of the CPU 18.

  The operation shown in FIG. 4 is performed when the CPU 18 performs, for example, a signal reception processing instruction (stored in the address “10000000” in the example of FIG. 3) using an external clock, and then the switching timing from the external clock to the internal clock. It starts when the address (10000001) in the example of FIG. 3 arrives. In the following operation example, the predetermined bit of the internal oscillator control register 14 is set to “0” indicating the initial state.

  In the operation shown in FIG. 4, the CPU 18 reads the identifier from the EEPROM 17 (step S1), and determines whether or not the read identifier is an identifier representing the internal clock operation lock mode (step S2).

  When the CPU 18 determines that the identifier represents the internal clock operation lock mode (before the operation check test of the IC chip 1) (step S2: YES), the predetermined bit of the internal oscillator control register 14 is set to “0”. The processing instruction (data analysis in the example shown in FIG. 3) following the above determination is executed by the external clock without switching from the external clock to the internal clock (step S3).

  On the other hand, for example, when the IC chip 1 is received from a semiconductor manufacturer and it is confirmed by the operation check inspector that the internal oscillator 12 is not defective by the operation check inspection of the IC chip 1, the external operation is performed by the operation check inspector. By the rewrite instruction signal input to the IC chip 1 from the device, the identifier representing the internal clock operation lock mode stored in the EEPROM 17 is rewritten to the identifier representing the internal clock operable mode. In this case, the CPU 18 determines in step S2 that the identifier is not an identifier representing the internal clock operation lock mode (step S2: NO), and the predetermined bit of the internal oscillator control register 14 is changed from “0” representing the initial state to the internal state. The setting is changed to “1” indicating the usage state of the oscillator 12, the external clock is switched to the internal clock, and the operation instruction (data analysis in the example shown in FIG. 3) following the above determination is executed by the internal clock ( Step S4).

  As described above, according to the above-described embodiment, the CPU 18 reads the identifier stored in the EEPROM 17 when the switching timing from the external clock to the internal clock arrives, and the read identifier is used as the internal clock operation. If the identifier represents a lock mode, the processing instruction is executed by an external clock. If the read identifier is an identifier representing an internal clock operable mode, the external clock is switched to the internal clock. In addition, since the operation for executing the processing instruction is performed by the internal clock, the processing speed can be increased, and even if the internal oscillator 12 provided in the IC chip 1 has a problem, the operation of the CPU 18 can be improved. Can be avoided.

  In the above-described embodiment, the case where the IC chip 1 is a contact type in which signals are transmitted to and received from the external device via a terminal has been described as an example. However, the IC chip 1 is not contacted with the external device (antenna The above embodiment can be applied even in the case of a non-contact type in which signals are transmitted and received (via).

1 IC chip 11 I / O port 12 Internal oscillator 13 Clock division / multiplication circuit 14 Internal oscillator control register 15 ROM
16 RAM
17 EEPROM
18 CPU

Claims (4)

An IC chip capable of transmitting and receiving signals to and from an external device,
Input means for inputting an external clock signal from the external device;
Internal clock signal generating means for generating an internal clock signal;
A read only memory for storing a program defining a plurality of processing instructions;
Arithmetic processing means for performing an operation of executing the processing instruction by the external clock signal or the internal clock signal;
A non-volatile memory for storing a first identifier representing inoperability by the internal clock signal, wherein the first identifier can be rewritten from the outside to a second identifier representing operation by the internal clock signal; ,
With
The arithmetic processing means reads the identifier from the nonvolatile memory when the switching timing from the external clock signal to the internal clock signal arrives, and when the read identifier is the first identifier Performs an operation of executing the processing instruction by the external clock signal, and when the read identifier is the second identifier, the processing instruction is switched from the external clock signal to the internal clock signal. An IC chip characterized by performing an operation to be executed. The IC chip according to claim 1,
The IC chip, wherein the first identifier is stored in the nonvolatile memory in an initial state before an operation check test of the IC chip.   An IC card on which the IC chip according to claim 1 is mounted. Input means for inputting an external clock signal from an external device;
Internal clock signal generating means for generating an internal clock signal;
A read only memory for storing a program defining a plurality of processing instructions;
Arithmetic processing means for performing an operation of executing the processing instruction by the external clock signal or the internal clock signal;
A non-volatile memory for storing a first identifier representing inoperability by the internal clock signal, wherein the first identifier can be rewritten from the outside to a second identifier representing operation by the internal clock signal; ,
A method of operating an IC chip comprising:
The arithmetic processing means reads the identifier from the non-volatile memory when the switching timing from the external clock signal to the internal clock signal arrives;
When the read identifier is the first identifier, the arithmetic processing means performs an operation of executing the processing instruction by the external clock signal;
When the read identifier is the second identifier, the arithmetic processing means performs an operation of switching the external clock signal to an internal clock signal and executing the processing instruction;
A method for operating an IC chip, comprising: