JP2011238655A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a variation in a threshold voltage Vt in a wafer surface of a semiconductor device using a cap material.SOLUTION: A high dielectric constant gate insulating film 1006 and a first cap film 1008 are sequentially formed on a semiconductor substrate 1001. Next, a first metal in the first cap film 1008 is diffused into the high dielectric constant gate insulating film 1006 by heat treatment. Subsequently, the first cap film 1008 that did not diffuse into the high dielectric constant gate insulating film 1006 and remained on the high dielectric constant gate insulating film 1006 is removed, and a metal electrode 1010 is formed on the high dielectric constant gate insulating film 1006A with the first metal diffused.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

In recent years, semiconductor devices are required to have low power consumption and high speed operation. In order to realize a high speed semiconductor device, a method of increasing a drive current by increasing a gate capacity of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is employed. In order to increase the gate capacitance of the MISFET, it is necessary to reduce the distance between the electrodes (distance between the substrate and the gate electrode) by reducing the thickness of the gate insulating film. In order to meet this requirement, the physical film thickness of the gate insulating film of MISFET is currently reduced to about 2 nm when a SiON (silicon oxynitride) film is used as the gate insulating film. However, as the gate insulating film becomes thinner, an increase in gate leakage current has become a big problem. In order to suppress the gate leakage current while reducing the thickness of the gate insulating film, a material having a high dielectric constant (high dielectric constant) such as an oxide containing Hf is used as the gate insulating film instead of a silicon oxide (SiO ₂ ) -based material. The use of body materials) is being considered.

In addition, in the gate electrode made of polycrystalline silicon, as the gate insulating film is made thinner, the gate electrode is depleted and the gate capacity is lowered. When the amount of decrease in gate capacitance due to depletion of the gate electrode is converted into the thickness of a gate insulating film made of, for example, silicon oxide (SiO ₂ ), the amount of decrease increases the thickness of the gate insulating film by about 0.5 nm. It corresponds to that. If depletion of the gate electrode can be suppressed, the effective thickness of the gate insulating film can be reduced without increasing the gate leakage current. In the case where the gate insulating film is a SiO ₂ film, when the thickness of the gate insulating film is reduced by 0.1 nm, the gate leakage current increases by 10 times or more compared to before the thinning of the gate insulating film. For this reason, the effect of reducing the thickness of the effective gate insulating film by suppressing the depletion of the gate electrode is very large.

  In order to avoid depletion of the gate electrode, studies have been made to replace the material of the gate electrode from polycrystalline silicon to a metal that does not cause depletion. When polycrystalline silicon is used as the material of the gate electrode, it is possible to form impurity levels by implanting impurities, so that the gate electrode for p-MISFET and the gate electrode for n-MISFET can be formed separately. it can. On the other hand, when a metal is used as the material of the gate electrode, the p-MISFET gate electrode and the n-MISFET gate electrode cannot be separately formed by impurity implantation. Therefore, a metal having a WF value substantially corresponding to the center of the WF (work function) value in the p-side region and the WF value in the n-side region is a common material for the gate electrode for p-MISFET and the gate electrode for n-MISFET. As a result, the p-MISFET and the n-MISFET are designed to have the same threshold voltage Vt.

  In recent years, semiconductor devices are required to operate at higher speeds, and thus lowering the threshold voltage is indispensable. Therefore, it has become necessary that each of the gate electrode for p-MISFET and the gate electrode for n-MISFET has a work function (WF) value close to the band edge of silicon. Here, the band edge means a high WF near the work function value (about 5.2 eV) of the upper part (top edge) of the valence band of silicon in the p-side region, and the n-side region means the conduction of silicon. This means a low WF close to the work function value (about 4.1 eV) at the bottom (bottom edge) of the band. Therefore, a semiconductor device in which a metal having a WF value substantially corresponding to the center of the WF value in the p-side region and the WF value in the n-side region is used as a common material for the gate electrode for p-MISFET and the gate electrode for n-MISFET. Is becoming impractical.

  Currently, a search for metal materials that can be used as materials for the gate electrodes of p-MISFETs and n-MISFETs has been actively conducted. However, it has become clear that even if a material exhibits an appropriate WF at room temperature, the WF fluctuates after a high temperature treatment such as activation of the source / drain. Recently, a cap material for controlling an effective work function (eWF (effective eork function)) is deposited between the high dielectric film and the gate electrode, and in the gate insulating film and at the interface between the high dielectric film and the metal. Studies have been made to control eWF by forming a dipole (see, for example, Non-Patent Document 1). Lanthanum oxide (hereinafter sometimes referred to as “LaO”) is known to have an effect of reducing eWF, and lanthanum oxide is expected as a cap material for forming a gate electrode of an n-MISFET. (For example, refer nonpatent literature 2.). Also, aluminum oxide (hereinafter sometimes referred to as “AlO”) is known to have an effect of increasing eWF, and aluminum oxide is expected as a cap material for forming a gate electrode of p-MISFET. . As disclosed in Patent Document 1, a complementary metal-oxide semiconductor (CMOS) using both LaO and AlO is currently being developed.

JP 2009-194352 A

S. Kubicek et al, "IEDM Tech Dig.", 2007, p. 49 P.D.Kirsch, "IEDM", 2006, p. 629

However, when an ultra-thin film having a thickness of sub-nano order is used as a cap material, eWF shifts by half (about 500 meV) of the silicon band gap. As described above, since the cap film (film made of a cap material) has a very large shift amount of eWF with respect to the film thickness, there is a problem that the variation in the threshold voltage Vt of the transistor due to the variation in the film thickness of the cap film is very large. Occurs. In addition to the cap film thickness, the eWF shift amount due to the cap material is not limited to the thickness of the base gate insulating film, and the composition of the material of the high dielectric constant gate insulating film (for example, the Hf composition in the HfSiO film). Also, it varies greatly depending on the annealing conditions in the subsequent process and the film quality of the electrode metal. As a result, the variation of the threshold voltage Vt increases. The factor that the eWF shift effect due to the cap material varies depending on other than the film thickness of the cap film is due to the eWF shift generation mechanism due to the cap material. (P. Sivasubramani et al VLSI2007)
The cap material such as LaO or AlO has an interface with SiO ₂ that diffuses in the high dielectric constant gate insulating film (for example, HfSiO) and is used as the base film (interface between the high dielectric constant gate insulating film and the base film). A dipole is formed on the substrate to generate an eWF shift. When the film thickness or Hf composition of the high dielectric constant gate insulating film changes, the amount of the cap material that diffuses to the interface between the high dielectric constant gate insulating film and the base film changes, and accordingly, the shift amount of eWF varies. Further, since the diffusion of the cap material is promoted by the post-process annealing treatment, the influence of the in-plane distribution of the annealing temperature is greatly affected.

  For the above reasons, the variation of the threshold voltage Vt in the wafer surface of the semiconductor device using the cap material is very large, which greatly hinders practical use.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems and to suppress a variation in threshold voltage Vt in a wafer surface of a semiconductor device using a cap material, and to realize a semiconductor device with high accuracy and yield. .

  According to a first method of manufacturing a semiconductor device of the present invention, a step (a) of forming a gate insulating film on a semiconductor substrate, and forming a first cap film containing a first metal on the gate insulating film. The step (b), the step (c) of diffusing the first metal into the gate insulating film by heat treatment, and the step of remaining the first metal remaining on the gate insulating film without diffusing into the gate insulating film after the step (c). A step (d) of removing the cap film 1 and a step (e) of forming a metal electrode on the gate insulating film in which the first metal is diffused.

  In the first method for manufacturing a semiconductor device according to the present invention, the cap material (first metal) existing in the gate insulating film is removed in order to remove the first cap film remaining without being diffused in the gate insulating film. The amount of can be controlled by heat treatment. Therefore, the influence due to the film thickness variation of the cap film can be substantially avoided. It is relatively easy to control the heat treatment temperature as compared with the case where the thickness of the cap film is controlled in the sub-nano order, and therefore, it is possible to form a semiconductor device with higher accuracy and less variation in threshold voltage Vt. It becomes possible. At this time, if the film thickness of the cap film is increased and the heat treatment temperature is set low, the amount of the cap material present in the gate insulating film becomes diffusion-controlled. Therefore, it is possible to further reduce the influence of the variation in the threshold voltage Vt due to the variation in the film thickness of the cap film.

  In the first method for manufacturing a semiconductor device of the present invention, the gate insulating film preferably contains hafnium, silicon, and oxygen, and the first metal is preferably hafnium.

  In the first method for manufacturing a semiconductor device of the present invention, the first element may be lanthanum, dysprosium, scandium, or magnesium.

  In the first method for manufacturing a semiconductor device according to the present invention, the first metal in the gate insulating film after the heat treatment is preferably 5 atomic% or more and 30 atomic% or less.

  In the first manufacturing method of the semiconductor device of the present invention, in the step (c), the in-plane distribution of the film thickness of the gate insulating film, the in-plane distribution of the composition ratio of the contained element in the gate insulating film, The in-plane distribution of the film thickness of the cap film, the in-plane distribution of the composition ratio of the contained elements in the first cap film, the in-plane distribution of the film thickness of the metal electrode, and the composition ratio of the contained elements in the metal electrode The distribution of the heat treatment temperature in the semiconductor substrate may be changed in accordance with at least one in-plane distribution of the inner distributions. Thereby, the first metal can be uniformly diffused into the gate insulating film. For example, in the step (c), the annealing temperature at the peripheral portion of the semiconductor substrate may be set higher than the annealing temperature at a portion other than the peripheral portion of the semiconductor substrate.

  A second method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device comprising a first transistor of a first conductivity type and a second transistor of a second conductivity type. Specifically, a step (a) of forming a gate insulating film on the semiconductor substrate, a step (b) of forming an electrode film on the second active region with the gate insulating film interposed therebetween, A step (c) of forming a first cap film containing a metal over the entire upper surface of the semiconductor substrate and a heat treatment diffuse the first metal into a portion of the gate insulating film formed on the first active region. A step (d), a step (e) of removing the first cap film remaining on the gate insulating film without diffusing into the gate insulating film, and a metal electrode film and a polysilicon film over the entire upper surface of the semiconductor substrate. Etching the gate insulating film, the metal electrode film, and the polysilicon film to form a first gate insulating film containing the first metal on the first active region, and a metal An electrode film and a first gate electrode having a polysilicon film are sequentially formed Is, on the second active region includes a second gate insulating film, and a step (g) to a second gate electrode having a metal electrode film and a polysilicon film are sequentially formed.

  In the second manufacturing method of the semiconductor device according to the present invention, the influence due to the film thickness variation of the cap film can be substantially avoided, so that the influence of the variation of the threshold voltage Vt due to the film thickness variation of the cap film can be reduced. .

  In the second method for manufacturing a semiconductor device of the present invention, in step (d), the first metal diffuses also into the electrode film, while the portion formed on the second active region in the gate insulating film. It is preferable not to diffuse. In the step (e), the electrode film is also preferably removed. Thereby, it is possible to prevent the first metal from diffusing into the second gate insulating film.

  In the second manufacturing method of the semiconductor device of the present invention, in the step (d), the in-plane distribution of the film thickness of the gate insulating film, the in-plane distribution of the composition ratio of the contained elements in the gate insulating film, The in-plane distribution of the film thickness of the cap film, the in-plane distribution of the composition ratio of the contained elements in the first cap film, the in-plane distribution of the film thickness of the metal electrode, and the composition ratio of the contained elements in the metal electrode The distribution of the heat treatment temperature in the semiconductor substrate may be changed in accordance with at least one in-plane distribution of the inner distributions. Thereby, the first metal can be uniformly diffused into the gate insulating film. For example, in the step (d), the annealing temperature at the peripheral portion of the semiconductor substrate may be set higher than the annealing temperature at a portion other than the peripheral portion of the semiconductor substrate.

  In the first and second manufacturing methods of the semiconductor device according to the present invention, if the cap material is diffused to the interface between the gate insulating film and the base film by heat treatment, the cap is formed at the interface in annealing or the like when activating the impurity. It can prevent that material exists unevenly.

As the high dielectric constant gate insulating film, an HfSiO film, an HFSiON film, or an HfO ₂ film is preferably used, but an oxide film such as Zr or Ta or an oxynitride film may be used.

  As a cap material for the n-type MISFET, an oxide of a lanthanoid element such as LaO is preferably used, but MgO or the like may be used. Moreover, although it is preferable to use AlO as the cap material for the p-type MISFET, TaO or the like may be used.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to realize a semiconductor device with high accuracy and high yield with little variation in the threshold voltage Vt even when a cap material is used.

(A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A)-(c) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A) And (b) is a graph for demonstrating the improvement of the in-plane distribution of the wafer of the threshold voltage Vt. (A)-(e) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. It is sectional drawing which shows the semiconductor device which concerns on the 2nd Embodiment of this invention.

  Embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited to embodiment shown below. Moreover, below, the same code | symbol may be attached | subjected with respect to the same member.

(First embodiment)
A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1A to FIG. 2C are cross-sectional views showing a method for manufacturing a semiconductor device according to this embodiment in the order of steps. FIGS. 3A and 3B are graphs for explaining the improvement of the in-plane distribution of the wafer with the threshold voltage Vt.

First, as shown in FIG. 1A, a p-type active region 1003 isolated by an element isolation region 1002 is formed on a semiconductor substrate 1001 such as a Si substrate. Thereafter, a base film 1005 made of SiO ₂ having a thickness of about 1 nm is formed on the entire top surface of the semiconductor substrate 1001. The base film 1005 may be formed by rapid thermal oxidation (RTO (Rapid Thermal Oxidation)) using oxygen gas, or may be formed by RTO using a gas species other than oxygen gas, or a heating furnace. It may be formed by thermal oxidation using. Further, the base film 1005 may be a silicon oxynitride (SiON) film or a chemical oxide film.

Next, a high dielectric constant gate insulating film 1006 is deposited on the base film 1005 (step (a)). Here, the high dielectric constant gate insulating film 1006 may be an HfSiO film having a Hf / (Hf + Si) composition of about 60% or an HfO ₂ film. Further, the Hf / (Hf + Si) composition in the high dielectric constant gate insulating film 1006 is not limited to 60%. The film thickness of the high dielectric constant gate insulating film 1006 may be 1.7 nm, for example, but may be changed depending on the use of the semiconductor device or the capability required for the semiconductor device. The high dielectric constant gate insulating film 1006 may be a high dielectric constant film (for example, a Zr oxide film, a Zr oxynitride film, a Ta oxide film, or a Ta oxynitride film) using an element other than Hf such as Zr.

  Next, the HfSiO film is nitrided using plasma, and then annealed at 1000 ° C. in a nitrogen atmosphere for baking. In this case, the nitriding treatment may be a treatment in which about 4 atomic% of nitrogen enters the film, but the nitrogen concentration may be changed according to the purpose or use of the semiconductor device. Further, the nitriding treatment may be performed immediately before the electrode is deposited. The annealing temperature for baking may be changed to a range of 800 to 1100 ° C., and the annealing treatment atmosphere may be changed from a nitrogen atmosphere.

  Next, as shown in FIG. 1B, a LaO film (first cap film) 1008 is deposited on the high dielectric constant gate insulating film 1006 (step (b)). The LaO film 1008 may be deposited using a PVD method (physical vapor deposition), or may be deposited using an ALD method (atomic layer deposition) or a CVD method (chemical vapor deposition). The thickness of the LaO film 1008 may be 2 nm, for example, but may be changed according to the purpose or application of the semiconductor device.

  Next, as shown in FIG. 1C, annealing is performed to diffuse La (first metal) in the LaO film 1008 into the high dielectric constant gate insulating film 1006 (step (c)). Thus, a high dielectric constant gate insulating film (hereinafter referred to as “first high dielectric constant gate insulating film”) 1006A in which La is diffused is formed on the base film 1005.

  In this annealing treatment, La is preferably diffused to the interface between the base film 1005 and the high dielectric constant gate insulating film 1006. Accordingly, it is possible to prevent the amount of La at the interface between the base film 1005 and the high dielectric constant gate insulating film 1006 from becoming non-uniform in a heat treatment step (step of activating impurities in the source / drain regions) in a later step. . For example, the annealing temperature may be 700 ° C.

  Further, in this annealing treatment, the heater temperature for annealing the peripheral portion of the semiconductor substrate 1001 is set higher than the heater temperature for annealing the central portion of the semiconductor substrate 1001, specifically 5-10 ° C. higher. Thereby, the diffusion of La in the peripheral portion of the semiconductor substrate 1001 is promoted, and the decrease in La diffusion due to the thin LaO film 1008 in the peripheral portion of the semiconductor substrate 1001 can be compensated. Even if the Hf composition of HfSiO is high at the peripheral edge of the semiconductor substrate 1001, even if the composition of the electrode (first electrode film 1010 described later) in the semiconductor substrate 1001 has an in-plane distribution. Even when the oxygen concentration in the electrode (first electrode film 1010 described later) in the semiconductor substrate 1001 has an in-plane distribution, eWF can be made uniform by using this method.

  Specifically, if there is an in-plane distribution in the film thickness of the high dielectric constant gate insulating film or the composition of the high dielectric constant gate insulating film in the semiconductor substrate, the cap material is difficult to diffuse uniformly in the high dielectric constant gate insulating film. As a result, a threshold voltage Vt may increase at the peripheral edge of the semiconductor substrate as shown in FIG. 3A (threshold voltage Vt variation). However, when the annealing temperature at the peripheral portion of the semiconductor substrate is made higher than the annealing temperature at the central portion of the semiconductor substrate as in this embodiment, the oxygen concentration in the high dielectric constant gate insulating film is increased only at the peripheral portion of the semiconductor substrate. Therefore, the cap material can be uniformly diffused in the high dielectric constant gate insulating film, and thus variation in the threshold voltage Vt can be prevented as shown in FIG.

  Subsequently, as shown in FIG. 1D, the excess LaO film 1008 that has not diffused into the high dielectric constant gate insulating film 1006 in the annealing process shown in FIG. 1C is removed (step (d)). . Any method may be used to remove the excess LaO film 1008. For example, hydrochloric acid (the concentration is preferably 37% by mass, for example) is diluted with diluted hydrochloric acid (dilute HCl) diluted 1000 times. Washing may be performed for 10 seconds. The dilution ratio of hydrochloric acid and the cleaning time with dilute hydrochloric acid may be appropriately changed according to the film thickness of the excess LaO film 1008 or the heat treatment time in the annealing treatment shown in FIG.

  The amount of La existing in the first high dielectric constant gate insulating film 1006A after removing the excess LaO film 1008 may be 5 atomic% or more and 30 atomic% or less, and is 0 in terms of the thickness of the LaO film. About 6 nm is sufficient. This amount of La (the amount of La present in the first high dielectric constant gate insulating film 1006A) can be controlled by the thickness of the LaO film 1008 and the annealing temperature shown in FIG. When the thickness of the LaO film 1008 is increased and the annealing temperature shown in FIG. 1C is lowered, the La amount becomes closer to the diffusion rate. Therefore, the diffusion of La is hardly affected by the film thickness distribution of the LaO film 1008. Therefore, it is possible to realize a distribution in which La is diffused relatively uniformly.

  Next, as shown in FIG. 2A, a first electrode film (metal electrode, metal electrode film) 1010 made of, for example, TiN is formed on the first high dielectric constant gate insulating film 1006A (step (e) 2), a second electrode film 1012 made of, for example, polysilicon is formed on the first electrode film 1010 as shown in FIG. Subsequently, an impurity is implanted into the second electrode film 1012. At this time, instead of implanting impurities into the second electrode film 1012, a polysilicon film doped with impurities may be deposited.

  The material of the first electrode film 1010 only needs to obtain an appropriate eWF in combination with the cap material, and may be, for example, tantalum nitride (TaN). The second electrode film 1012 may have a metal-inserted polysilicon stack (MIPS) as described above, or a full metal gate electrode (material of the second electrode film 1012). May be a metal). Further, the second electrode film 1012 is not necessarily provided.

  Next, as shown in FIG. 2C, the underlying film 1005, the first high dielectric constant gate insulating film 1006A, and the first film are formed by using a lithography method and a reactive ion etching (RIE) method. The electrode film 1010 and the second electrode film 1012 are selectively etched. Thus, on the p-type active region 1003, a gate insulating film made of the base film 1005 and the first high dielectric constant gate insulating film 1006A, and a gate electrode made of the first electrode film 1010 and the second electrode film 1012. Are formed in order.

  Next, an n-type impurity is implanted to the side of the gate electrode in the p-type active region 1003 to form an n-type extension region 1013, a sidewall 1014 is formed on the side surface of the gate electrode, and the p-type active region 1003 is formed. An n-type impurity is implanted below the side wall 1014 to form an n-type source / drain region 1015, and the n-type impurity implanted in each of the n-type extension region 1013 and the n-type source / drain region 1015 is activated. Make it.

  At this time, if La is diffused to the interface between the base film 1005 and the high dielectric constant gate insulating film 1006 in the annealing process shown in FIG. 1C, the n-type impurity implanted into the n-type extension region 1013 or the like is removed. When activated, La can be prevented from further diffusing. Therefore, it is possible to prevent the threshold voltage Vt of the semiconductor device from fluctuating. Further, it is possible to prevent a decrease in reliability of the transistor due to excessive La reaching the interface oxide film.

  As described above, in the method of manufacturing a semiconductor device according to the present embodiment, the threshold voltage Vt of the semiconductor device is set by avoiding the influence of the uniform film thickness of the cap film or the film formation state of the film other than the cap film. It can be made uniform and stabilized. Therefore, in the manufactured semiconductor device, the threshold voltage Vt can be made uniform and stable.

  In this embodiment, after the n-type impurity is activated, the upper surface of the second electrode film 1012 and the upper surface of the n-type source / drain region 1015 may be silicided.

(Second Embodiment)
The second embodiment of the present invention will be described below with reference to the drawings. FIG. 4A to FIG. 5D are cross-sectional views showing the manufacturing method of the semiconductor device according to this embodiment in the order of steps, and FIG. 6 is a cross-sectional view of the semiconductor device according to this embodiment. 4A to 6, the same members as those shown in FIGS. 1A to 2C are denoted by the same reference numerals.

  As shown in FIG. 6, the semiconductor device of this embodiment is a complementary MIS (CMIS, Complementary Metal Insulator Semiconductor) including an n-MISFET and a p-MISFET.

  A semiconductor substrate 1001 such as a Si substrate is formed with a p-type active region 1003 and an n-type active region 1004 that are separated from each other by an element isolation region 1002 made of STI (Shallow Trench Isolation).

On the p-type active region 1003, a first gate insulating film having a base film 1005 made of SiO ₂ or the like and a first high dielectric constant gate insulating film 1006A, and a first gate electrode (described later) are sequentially formed. Is formed. A sidewall 1014 is formed on the side surface of the first gate electrode.

  An n-type extension region 1013A is formed below the first gate electrode in the p-type active region 1003, and an n-type source / drain region 1015A is formed outside the n-type extension region 1013A.

On the n-type active region 1004, a _second gate insulating film having a base film 1005 made of SiO ₂ or the like, a second high dielectric constant gate insulating film 1006B, and an AlO film (p-type MISFET cap film) 1011; A second gate electrode (described later) is sequentially formed. A sidewall 1014 is formed on the side surface of the second gate electrode.

  A p-type extension region 1013B is formed below the second gate electrode in the n-type active region 1004, and a p-type source / drain region 1015B is formed outside the p-type extension region 1013B.

  The first gate electrode has a first electrode film 1010 made of TiN or the like, and a second electrode film 1012 made of polysilicon or the like formed on the first electrode film 1010. The second gate electrode includes an intermediate electrode film (electrode film) 1007 made of TiN or the like, a first electrode film 1010 made of TiN formed on the intermediate electrode film 1007, and an upper surface of the first electrode film 1010. And a second electrode film 1012 which is a polysilicon film formed on the substrate. In this manner, the first gate electrode does not have the intermediate electrode film 1007, but the second gate electrode has the intermediate electrode film 1007. Therefore, the thickness of the second gate electrode is the same as that of the first gate electrode. Greater than thickness.

  The first high dielectric constant gate insulating film 1006A and the second high dielectric constant gate insulating film 1006B are hafnium oxide (HfO) -based high dielectric films containing HfSiO or HfSiON. The first high dielectric constant gate insulating film 1006A contains La (cap material for n-type MISFET, first metal), but the second high dielectric constant gate insulating film 1006B does not contain La or the pole. It contains only a small amount of La.

  The method for manufacturing the semiconductor device according to the present embodiment will be described below with reference to the drawings.

First, as shown in FIG. 4A, a p-type active region 1003 and an n-type active region 1004 separated by an element isolation region 1002 are formed in a semiconductor substrate 1001 such as a Si substrate. Thereafter, a base film 1005 made of SiO ₂ having a thickness of about 1 nm is formed on the entire surface of the semiconductor substrate 1001. The base film 1005 may be formed by RTO using oxygen gas or the like, may be formed by RTO using a gas species other than oxygen gas, or may be formed by thermal oxidation using a heating furnace. good. Further, the base film 1005 may be a SiON film, a chemical oxide film, or the like.

Next, a high dielectric constant gate insulating film 1006 is deposited on the base film 1005 (step (a)). Here, as the high dielectric constant gate insulating film 1006, an HfSiO film having an Hf / (Hf + Si) composition of about 60% may be used, or an HfO ₂ film may be used. Further, the Hf / (Hf + Si) composition in the high dielectric constant gate insulating film 1006 is not limited to 60%. The film thickness of the high dielectric constant gate insulating film 1006 may be 1.7 nm, for example, but may be changed depending on the use of the semiconductor device or the capability required for the semiconductor device. The high dielectric constant gate insulating film 1006 may be a high dielectric constant film containing an element other than Hf, for example, a Zr oxide film, a Zr oxynitride film, a Ta oxide film, or a Ta oxynitride film.

  Next, the HfSiO film is nitrided using plasma, and then annealed at 1000 ° C. in a nitrogen atmosphere for baking. In this case, the nitriding may be a process in which about 4 atomic% of nitrogen enters the film, but the nitrogen concentration may be changed according to the purpose or use of the semiconductor device. Further, the nitriding treatment may be performed immediately before the electrode is deposited. The annealing temperature for baking may be changed to a range of 800 to 1100 ° C., and the annealing treatment atmosphere may be changed from a nitrogen atmosphere.

  Next, an AlO film 1011 serving as a p-type MISFET cap film is deposited on the high dielectric constant gate insulating film 1006. The film thickness of the AlO film 1011 may be 0.7 nm, for example, and can be changed according to the performance required for the semiconductor device.

  Next, an intermediate electrode film (electrode film) 1007 made of a TiN film having a thickness of about 5 nm is formed on the AlO film 1011 (step (b)).

  Next, as shown in FIG. 4B, a resist film 1009 is formed to cover the n-type active region 1004. Thereafter, as shown in FIG. 4C, using the resist film 1009 as a mask, portions of the intermediate electrode film 1007 and the AlO film 1011 formed on the p-type active region 1003 are removed.

  Next, as shown in FIG. 4D, after removing the resist film 1009 by thinner cleaning, a LaO film 1008 is deposited on the entire surface of the semiconductor substrate 1001 (step (c)). The LaO film may be deposited using a PVD method, or may be deposited using an ALD method or a CVD method. In this case, the thickness of the LaO film 1008 may be 2 nm, for example, but may be changed according to the use of the semiconductor device.

  Next, as shown in FIG. 4E, annealing is performed to diffuse La in the LaO film 1008 into the high dielectric constant gate insulating film 1006 (step (d)). Thus, a high dielectric constant gate insulating film (first high dielectric constant gate insulating film) 1006A in which La is diffused is formed on the base film 1005.

  In this annealing treatment, La is preferably diffused to the interface between the base film 1005 and the high dielectric constant gate insulating film 1006. Accordingly, it is possible to prevent the amount of La at the interface between the base film 1005 and the high dielectric constant gate insulating film 1006 from becoming non-uniform in a heat treatment step (step of activating impurities in the source / drain regions) in a later step. . For example, the annealing temperature may be 700 ° C.

  Further, in this annealing treatment, the heater temperature for annealing the peripheral portion of the semiconductor substrate 1001 is set higher than the heater temperature for annealing the central portion of the semiconductor substrate 1001, specifically 5-10 ° C. higher. Thereby, the diffusion of La in the peripheral portion of the semiconductor substrate 1001 is promoted, and the decrease in La diffusion due to the thin LaO film 1008 in the peripheral portion of the semiconductor substrate 1001 can be compensated. This method is used even when the Hf composition of HfSiO is high at the peripheral edge of the semiconductor substrate 1001, the electrode composition is fluctuating, or the oxygen concentration in the electrode is changing. EWF can be made uniform. The details are as described in the first embodiment.

  Subsequently, as shown in FIG. 5A, the excess LaO film 1008 that has not diffused into the high dielectric constant gate insulating film 1006 in the annealing process shown in FIG. 4E is removed (step (e)). . Any method may be used to remove the excess LaO film 1008. For example, cleaning is performed for 10 seconds with dilute hydrochloric acid obtained by diluting hydrochloric acid (the concentration is preferably 37% by mass, for example) 1000 times. Just do it. The dilution ratio of hydrochloric acid and the cleaning time with dilute hydrochloric acid may be appropriately changed according to the thickness of the excess LaO film 1008 or the heat treatment time in the annealing process shown in FIG.

  The amount of La existing in the first high dielectric constant gate insulating film 1006A after removing the excess LaO film 1008 may be 5 atomic% or more and 30 atomic% or less, and is 0 in terms of the thickness of the LaO film. About 6 nm is sufficient. This amount of La (the amount of La present in the first high dielectric constant gate insulating film 1006A) can be controlled by the film thickness of the LaO film 1008 and the annealing temperature shown in FIG. When the thickness of the LaO film 1008 is increased and the annealing temperature shown in FIG. 4E is lowered, the La amount becomes closer to the diffusion rate. Therefore, the diffusion of La is hardly affected by the film thickness distribution of the LaO film 1008. Therefore, it is possible to realize a distribution in which La is diffused relatively uniformly.

  On the other hand, on the n-type active region 1004, La in the LaO film 1008 is diffused only above the intermediate electrode film 1007 by the annealing shown in FIG. 4E, and the high dielectric constant gate insulating film 1006 and AlO It hardly diffuses into the film 1011. Therefore, on the n-type active region 1004, La is not diffused or only a very small amount of La is diffused (second dielectric constant gate insulating film). 1006B is formed. The temperature and time of the annealing process shown in FIG. 4E are appropriately changed depending on the required eWF value, the composition and film thickness of the high dielectric constant gate insulating film 1006, the composition and film thickness of the AlO film 1011, and the like. do it.

In this way, on the n-type active region 1004, La in the LaO film 1008 diffuses to the upper part of the intermediate electrode film 1007. Therefore, it is preferable to remove the upper part of the intermediate electrode film 1007 as shown in FIG. As a method of removing the upper portion of the intermediate electrode film 1007, any method may be used as long as the region where the cap material is diffused can be removed without deteriorating the high dielectric constant gate insulating film 1006. When the intermediate electrode film 1007 is a TiN film and the first cap film 1008 is a LaO film, the upper portion of the intermediate electrode film 1007 may be removed using hydrogen peroxide water (H ₂ O ₂ ). Even if the upper portion of the intermediate electrode film 1007 is removed by using sulfuric acid-hydrogen peroxide solution (SPM) or ammonia-hydrogen peroxide-mixture (APM). good.

  Next, as shown in FIG. 5C, a first electrode film 1010 made of TiN and a second electrode film 1012 made of polysilicon are sequentially deposited on the entire surface of the semiconductor substrate 1001 (step (f)). . Subsequently, an impurity is implanted into the second electrode film 1012. Note that a polysilicon film doped with impurities may be deposited instead of implanting impurities into the second electrode film 1012.

  Next, as shown in FIG. 5D, by using a lithography method and a reactive ion etching (RIE) method, in the p-type active region 1003, a base film 1005, a first high dielectric constant gate insulating film 1006A, The first electrode film 1010 and the second electrode film 1012 are selectively etched to form a base film 1005, a second high dielectric constant gate insulating film 1006B, an AlO film 1011, and an intermediate electrode film 1007 in the n-type active region 1004. The first electrode film 1010 and the second electrode film 1012 are selectively etched. Thus, on the p-type active region 1003, the first gate insulating film having the base film 1005 and the first high dielectric constant gate insulating film 1006A, the first electrode film 1010 made of TiN, and the polysilicon are formed. The first gate electrode having the second electrode film 1012 is formed. Further, on the n-type active region 1004, a base film 1005, a second gate insulating film having a second high dielectric constant gate insulating film 1006B and an AlO film 1011, an intermediate electrode film 1007 made of TiN, and TiN A second gate electrode having the first electrode film 1010 and the second electrode film 1012 made of polysilicon is formed (step (g)).

  Next, an n-type impurity is implanted below the first gate electrode in the p-type active region 1003 to form an n-type extension region 1013A, and the second lower side of the second gate electrode in the n-type active region 1004 is formed. A p-type impurity is implanted to form a p-type extension region 1013B. Thereafter, sidewalls 1014 (see FIG. 6) are formed on the side surfaces of the first gate electrode and the second gate electrode. Thereafter, an n-type impurity is implanted under the sidewall 1014 in the p-type active region 1003 to form an n-type source / drain region 1015A, and a p-type impurity is formed under the sidewall 1014 in the n-type active region 1004. Is implanted to form a p-type source / drain region 1015B. Thereafter, the n-type impurity implanted in each of the n-type extension region 1013A and the n-type source / drain region 1015A is activated, and the p-type implanted in each of the p-type extension region 1013B and the p-type source / drain region 1015B. Activate the impurities. As a result, as shown in FIG. 6, an n-MISFET is formed in the p-type active region 1003, and a p-MISFET is formed in the n-type active region 1004.

  At this time, if La is diffused to the interface between the base film 1005 and the high dielectric constant gate insulating film 1006 in the annealing process shown in FIG. 4E, the n-type impurity implanted into the n-type extension region 1013 or the like is removed. When activated, La can be prevented from further diffusing. Therefore, it is possible to prevent the threshold voltage Vt of the semiconductor device from fluctuating. Further, it is possible to prevent a decrease in reliability of the transistor due to excessive La reaching the interface oxide film.

  In the present embodiment, the first gate electrode and the second gate electrode are stacked films of a TiN film and a polysilicon film. In this case, at least a part of the polysilicon film may be silicided. Thereby, the resistance of the first gate electrode and the second gate electrode can be reduced. The second electrode film 1012 may be replaced with another metal film instead of the polysilicon film, and the second electrode film 1012 may not be provided.

  The first electrode film 1010 and the intermediate electrode film 1007 are not limited to TiN films, but are preferably metal films containing Ti or Ta, and may be TaN films, TaC films, TaCN films, or the like. A film having another metal material (metal other than Ti and Ta) may be used as long as an appropriate eWF is obtained when combined with a cap material.

  The thicknesses of the first electrode film 1010 and the intermediate electrode film 1007 may be appropriately changed according to the material and the manufacturing process. However, when both the first electrode film 1010 and the intermediate electrode film 1007 are TiN films, in order to obtain an appropriate eWF value in the p-MISFET, the film of the first electrode film 1010 and the intermediate electrode film 1007 is used. The sum of the thickness is preferably 15 nm or more.

  Further, a cap material having an effect of increasing eWF such as Al may be diffused in the second high dielectric constant gate insulating film 1006B of the p-MISFET.

  In this embodiment, after the cap material is diffused, the second gate electrode has a stacked film of the first electrode film 1010 and the intermediate electrode film 1007 by leaving a part of the intermediate electrode film 1007. It is configured. However, the intermediate electrode film 1007 may be completely removed after the cap material is diffused. In this case, the n-MISFET and the p-MISFET have the same height of the gate electrode, so that there is an advantage that the subsequent process becomes easy. Further, when the intermediate electrode film 1007 is left in the n-type active region 1004, a thin insulating film is formed at the interface between the intermediate electrode film 1007 and the first electrode film 1010. As a result, the gate resistance increases. There is a case. However, when the intermediate electrode film 1007 is completely removed in the n-type active region 1004, an increase in gate resistance can be prevented.

  In the first and second embodiments, an example in which a LaO film is used as a cap film for an n-type MISFET has been described. However, this cap film may be an insulating film having an effect of reducing the eWF of the electrode, and dysprosium oxide An oxide of a lanthanoid element such as (DyO) may be used, or scandium oxide (ScO) or magnesium oxide (MgO) may be used.

  In the second embodiment, the example in which the AlO film is used as the cap film for the p-type MISFET has been described. However, the cap film may be a TaO film or the like.

The high dielectric constant gate insulating film may be formed by using an ALD method, a metal organic chemical vapor deposition (MOCVD) method, a chemical vapor deposition (CVD) method, or a physical method. You may form using vapor phase deposition (PVD: Physical Vapor Deposition) method. In the case of the MOCVD method, a film having a high Hf composition and a film having a low Hf composition can be easily formed by changing the film formation temperature and the gas flow rate ratio. In the first and second embodiments, plasma nitridation is performed to change the HfSiO ₂ film into an HfSiON film, but annealing in an ammonia atmosphere may be used instead of plasma nitridation. Further, depending on the dielectric constant of the gate insulating film and the EOT (capacitance equivalent to the silicon oxide film) of the gate insulating film, the nitriding treatment of the HfSiO ₂ film may be omitted.

  Although an example in which an Hf-based film is used as the high dielectric constant gate insulating film is shown, a film containing aluminum, zircon, or the like may be used instead of Hf. Also in this case, the diffusibility of the cap material can be controlled by changing the composition of the high dielectric constant gate insulating film.

  In the first and second embodiments, the case where there is an in-plane distribution in the film thickness or composition of the high dielectric constant gate insulating film in the semiconductor substrate is described. However, in the semiconductor substrate, when the film thickness of the LaO film has an in-plane distribution, when the composition ratio of the contained elements in the LaO film has an in-plane distribution, the film thickness of the first electrode film has an in-plane distribution. In some cases, or even when the composition ratio of the contained elements in the first electrode film has an in-plane distribution, the threshold voltage Vt of the semiconductor device may vary. Therefore, even in these cases, it is preferable to change the distribution of the heat treatment temperature when La is diffused.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, a high-performance CMOS device having a high dielectric constant gate insulating film and a metal electrode can be realized with high accuracy and high yield.

1001 Semiconductor substrate
1002 Element isolation region
1003 p-type active region
1004 n-type active region
1005 Underlayer film
1006 High dielectric constant gate insulating film
1006A First high dielectric constant gate insulating film
1006B Second high dielectric constant gate insulating film
1007 Intermediate electrode film (electrode film)
1008 LaO film (first cap film)
1010 First electrode film (metal electrode, metal electrode film)
1011 AlO film
1012 Second electrode film
1013 n-type extension region
1013A n-type extension region
1013B p-type extension region
1014 sidewall
1015 n-type source / drain region
1015A n-type source / drain region
1015B p-type source / drain region

Claims (10)

Forming a gate insulating film on the semiconductor substrate (a);
A step (b) of forming a first cap film containing a first metal on the gate insulating film;
A step (c) of diffusing the first metal into the gate insulating film by heat treatment;
A step (d) of removing the first cap film remaining on the gate insulating film without diffusing into the gate insulating film after the step (c);
And (e) forming a metal electrode on the gate insulating film in which the first metal has been diffused. The gate insulating film contains hafnium, silicon and oxygen,
The method for manufacturing a semiconductor device according to claim 1, wherein the first metal is lanthanum.   The method for manufacturing a semiconductor device according to claim 1, wherein the first element is lanthanum, dysprosium, scandium, or magnesium.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal in the gate insulating film after the heat treatment is 5 atomic% or more and 30 atomic% or less. 5.   In the step (c), the in-plane distribution of the film thickness of the gate insulating film, the in-plane distribution of the composition ratio of the elements contained in the gate insulating film, and the film thickness of the first cap film in the semiconductor substrate. Of the in-plane distribution, the in-plane distribution of the composition ratio of the contained elements in the first cap film, the in-plane distribution of the film thickness of the metal electrode, and the in-plane distribution of the composition ratio of the contained elements in the metal electrode The method for manufacturing a semiconductor device according to claim 1, wherein the distribution of the heat treatment temperature in the semiconductor substrate is changed according to at least one in-plane distribution.   6. The manufacturing method of a semiconductor device according to claim 5, wherein in the step (c), an annealing temperature at a peripheral portion of the semiconductor substrate is set higher than an annealing temperature at a portion other than the peripheral portion of the semiconductor substrate. Method. A first transistor of a first conductivity type provided on a first active region in a semiconductor substrate and a second active region in the semiconductor substrate separated from the first active region by an element isolation region A method for manufacturing a semiconductor device comprising a second transistor of the second conductivity type provided,
Forming a gate insulating film on the semiconductor substrate;
Forming an electrode film on the second active region across the gate insulating film;
Forming a first cap film containing a first metal on the entire top surface of the semiconductor substrate;
Diffusing the first metal into a portion of the gate insulating film formed on the first active region by heat treatment (d);
Removing the first cap film remaining on the gate insulating film without diffusing into the gate insulating film (e);
Forming a metal electrode film and a polysilicon film over the entire top surface of the semiconductor substrate (f);
The gate insulating film, the metal electrode film, and the polysilicon film are etched to form a first gate insulating film containing the first metal on the first active region, the metal electrode film, and A first gate electrode having the polysilicon film is formed in order, and a second gate insulating film, a second electrode having the metal electrode film and the polysilicon film are formed on the second active region. A method for manufacturing a semiconductor device, comprising: a step (g) in which a gate electrode is sequentially formed. In the step (d), the first metal diffuses into the electrode film, but does not diffuse into a portion of the gate insulating film formed on the second active region,
The method for manufacturing a semiconductor device according to claim 7, wherein in the step (e), the electrode film is also removed.   In the step (d), the in-plane distribution of the film thickness of the gate insulating film, the in-plane distribution of the composition ratio of the elements contained in the gate insulating film, and the film thickness of the first cap film in the semiconductor substrate. Of the in-plane distribution, the in-plane distribution of the composition ratio of the contained elements in the first cap film, the in-plane distribution of the film thickness of the metal electrode, and the in-plane distribution of the composition ratio of the contained elements in the metal electrode 9. The method of manufacturing a semiconductor device according to claim 7, wherein the distribution of the heat treatment temperature in the semiconductor substrate is changed according to at least one in-plane distribution.   10. The method of manufacturing a semiconductor device according to claim 9, wherein, in the step (d), an annealing temperature at a peripheral portion of the semiconductor substrate is set higher than an annealing temperature at a portion other than the peripheral portion of the semiconductor substrate.

Images